./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu1.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 12:05:11,224 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 12:05:11,228 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 12:05:11,281 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 12:05:11,281 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 12:05:11,282 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 12:05:11,284 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 12:05:11,287 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 12:05:11,294 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 12:05:11,302 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 12:05:11,303 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 12:05:11,307 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 12:05:11,308 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 12:05:11,310 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 12:05:11,314 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 12:05:11,316 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 12:05:11,318 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 12:05:11,319 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 12:05:11,324 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 12:05:11,330 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 12:05:11,331 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 12:05:11,333 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 12:05:11,337 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 12:05:11,338 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 12:05:11,350 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 12:05:11,350 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 12:05:11,351 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 12:05:11,352 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 12:05:11,352 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 12:05:11,353 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 12:05:11,353 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 12:05:11,354 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 12:05:11,355 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 12:05:11,356 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 12:05:11,357 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 12:05:11,357 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 12:05:11,358 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 12:05:11,361 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 12:05:11,363 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 12:05:11,364 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 12:05:11,365 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 12:05:11,366 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 12:05:11,413 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 12:05:11,413 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 12:05:11,414 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 12:05:11,414 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 12:05:11,415 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 12:05:11,416 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 12:05:11,416 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 12:05:11,416 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 12:05:11,417 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 12:05:11,417 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 12:05:11,418 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 12:05:11,419 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 12:05:11,419 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 12:05:11,419 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 12:05:11,419 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 12:05:11,420 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 12:05:11,420 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 12:05:11,420 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 12:05:11,420 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 12:05:11,421 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 12:05:11,421 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 12:05:11,421 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 12:05:11,421 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 12:05:11,422 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 12:05:11,422 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 12:05:11,422 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 12:05:11,422 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 12:05:11,423 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 12:05:11,423 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 12:05:11,424 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 12:05:11,424 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 12:05:11,426 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 12:05:11,426 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7 [2022-11-16 12:05:11,818 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 12:05:11,858 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 12:05:11,861 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 12:05:11,863 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 12:05:11,864 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 12:05:11,865 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/kundu1.cil.c [2022-11-16 12:05:11,964 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/data/73a26e631/67924cef0c6743e0a3ce6f254f1a2beb/FLAG429fcbc04 [2022-11-16 12:05:12,529 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 12:05:12,530 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/sv-benchmarks/c/systemc/kundu1.cil.c [2022-11-16 12:05:12,552 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/data/73a26e631/67924cef0c6743e0a3ce6f254f1a2beb/FLAG429fcbc04 [2022-11-16 12:05:12,837 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/data/73a26e631/67924cef0c6743e0a3ce6f254f1a2beb [2022-11-16 12:05:12,840 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 12:05:12,842 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 12:05:12,844 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 12:05:12,845 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 12:05:12,853 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 12:05:12,854 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:05:12" (1/1) ... [2022-11-16 12:05:12,856 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@330b095e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:12, skipping insertion in model container [2022-11-16 12:05:12,857 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:05:12" (1/1) ... [2022-11-16 12:05:12,866 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 12:05:12,933 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 12:05:13,171 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/sv-benchmarks/c/systemc/kundu1.cil.c[636,649] [2022-11-16 12:05:13,242 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:05:13,254 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 12:05:13,267 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/sv-benchmarks/c/systemc/kundu1.cil.c[636,649] [2022-11-16 12:05:13,297 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:05:13,317 INFO L208 MainTranslator]: Completed translation [2022-11-16 12:05:13,318 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13 WrapperNode [2022-11-16 12:05:13,318 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 12:05:13,319 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 12:05:13,320 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 12:05:13,320 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 12:05:13,332 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,342 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,381 INFO L138 Inliner]: procedures = 32, calls = 36, calls flagged for inlining = 31, calls inlined = 34, statements flattened = 371 [2022-11-16 12:05:13,382 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 12:05:13,382 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 12:05:13,383 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 12:05:13,383 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 12:05:13,398 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,399 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,408 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,409 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,416 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,444 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,447 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,449 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,466 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 12:05:13,467 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 12:05:13,468 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 12:05:13,468 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 12:05:13,469 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (1/1) ... [2022-11-16 12:05:13,480 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 12:05:13,494 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:05:13,511 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 12:05:13,513 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 12:05:13,569 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 12:05:13,569 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 12:05:13,570 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 12:05:13,570 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 12:05:13,716 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 12:05:13,719 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 12:05:14,351 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 12:05:14,363 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 12:05:14,364 INFO L300 CfgBuilder]: Removed 4 assume(true) statements. [2022-11-16 12:05:14,367 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:05:14 BoogieIcfgContainer [2022-11-16 12:05:14,367 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 12:05:14,368 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 12:05:14,369 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 12:05:14,384 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 12:05:14,385 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:05:14,385 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 12:05:12" (1/3) ... [2022-11-16 12:05:14,386 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f788f20 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:05:14, skipping insertion in model container [2022-11-16 12:05:14,387 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:05:14,387 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:05:13" (2/3) ... [2022-11-16 12:05:14,388 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f788f20 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:05:14, skipping insertion in model container [2022-11-16 12:05:14,388 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:05:14,388 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:05:14" (3/3) ... [2022-11-16 12:05:14,390 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu1.cil.c [2022-11-16 12:05:14,462 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 12:05:14,462 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 12:05:14,462 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 12:05:14,462 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 12:05:14,463 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 12:05:14,463 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 12:05:14,463 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 12:05:14,464 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 12:05:14,470 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 125 states, 124 states have (on average 1.4919354838709677) internal successors, (185), 124 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:14,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 96 [2022-11-16 12:05:14,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:05:14,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:05:14,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:14,527 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:14,527 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 12:05:14,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 125 states, 124 states have (on average 1.4919354838709677) internal successors, (185), 124 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:14,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 96 [2022-11-16 12:05:14,537 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:05:14,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:05:14,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:14,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:14,550 INFO L748 eck$LassoCheckResult]: Stem: 115#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~C_1_i~0 := 0;~e~0 := 0;~P_1_pc~0 := 0;~num~0 := 0;~P_1_st~0 := 0;~i~0 := 0;~data_0~0 := 0;~C_1_pr~0 := 0;~C_1_st~0 := 0;~data_1~0 := 0;~max_loop~0 := 0;~timer~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_ev~0 := 0;~P_1_i~0 := 0; 45#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 78#L496true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122#L229true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64#L236true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 63#L236-2true assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 121#L241-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14#L331true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 7#L117true assume !(1 == ~P_1_pc~0); 25#L117-2true is_P_1_triggered_~__retres1~0#1 := 0; 57#L128true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 107#L129true activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 55#L383true assume !(0 != activate_threads_~tmp~1#1); 26#L383-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 54#L199true assume 1 == ~C_1_pc~0; 98#L200true assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 68#L220true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 80#L221true activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 79#L391true assume !(0 != activate_threads_~tmp___1~1#1); 4#L391-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119#L339true assume { :end_inline_reset_delta_events } true; 81#L445-2true [2022-11-16 12:05:14,551 INFO L750 eck$LassoCheckResult]: Loop: 81#L445-2true assume !false; 101#L446true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 93#L304true assume false; 77#L320true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65#L229-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30#L331-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 5#L117-3true assume !(1 == ~P_1_pc~0); 75#L117-5true is_P_1_triggered_~__retres1~0#1 := 0; 83#L128-1true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 48#L129-1true activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 39#L383-3true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 18#L383-5true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 118#L199-3true assume 1 == ~C_1_pc~0; 23#L200-1true assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 104#L220-1true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 60#L221-1true activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 126#L391-3true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 41#L391-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111#L339-1true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13#L254-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 44#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 71#L268-1true start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 102#L464true assume !(0 == start_simulation_~tmp~3#1); 27#L464-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 31#L254-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 84#L267-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 95#L268-2true stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 6#L419true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 109#L426true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86#L427true start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 32#L477true assume !(0 != start_simulation_~tmp___0~2#1); 81#L445-2true [2022-11-16 12:05:14,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:14,559 INFO L85 PathProgramCache]: Analyzing trace with hash -1103808071, now seen corresponding path program 1 times [2022-11-16 12:05:14,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:14,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882435919] [2022-11-16 12:05:14,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:14,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:14,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:05:14,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:05:14,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:05:14,796 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882435919] [2022-11-16 12:05:14,797 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1882435919] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:05:14,797 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:05:14,798 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:05:14,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343962031] [2022-11-16 12:05:14,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:05:14,807 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:05:14,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:14,808 INFO L85 PathProgramCache]: Analyzing trace with hash -436523117, now seen corresponding path program 1 times [2022-11-16 12:05:14,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:14,809 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737767654] [2022-11-16 12:05:14,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:14,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:14,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:05:14,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:05:14,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:05:14,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737767654] [2022-11-16 12:05:14,842 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737767654] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:05:14,843 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:05:14,843 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:05:14,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [146961286] [2022-11-16 12:05:14,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:05:14,845 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:05:14,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:05:14,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:05:14,890 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:05:14,893 INFO L87 Difference]: Start difference. First operand has 125 states, 124 states have (on average 1.4919354838709677) internal successors, (185), 124 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:14,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:05:14,933 INFO L93 Difference]: Finished difference Result 122 states and 172 transitions. [2022-11-16 12:05:14,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 172 transitions. [2022-11-16 12:05:14,940 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 90 [2022-11-16 12:05:14,946 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 115 states and 165 transitions. [2022-11-16 12:05:14,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2022-11-16 12:05:14,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2022-11-16 12:05:14,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 165 transitions. [2022-11-16 12:05:14,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:05:14,951 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 165 transitions. [2022-11-16 12:05:14,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 165 transitions. [2022-11-16 12:05:14,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2022-11-16 12:05:14,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.434782608695652) internal successors, (165), 114 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:14,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 165 transitions. [2022-11-16 12:05:14,997 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 165 transitions. [2022-11-16 12:05:14,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:05:15,004 INFO L428 stractBuchiCegarLoop]: Abstraction has 115 states and 165 transitions. [2022-11-16 12:05:15,004 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 12:05:15,004 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 165 transitions. [2022-11-16 12:05:15,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 90 [2022-11-16 12:05:15,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:05:15,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:05:15,009 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:15,009 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:15,010 INFO L748 eck$LassoCheckResult]: Stem: 370#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~C_1_i~0 := 0;~e~0 := 0;~P_1_pc~0 := 0;~num~0 := 0;~P_1_st~0 := 0;~i~0 := 0;~data_0~0 := 0;~C_1_pr~0 := 0;~C_1_st~0 := 0;~data_1~0 := 0;~max_loop~0 := 0;~timer~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_ev~0 := 0;~P_1_i~0 := 0; 326#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 327#L496 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 359#L229 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 352#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 350#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 351#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 282#L331 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 266#L117 assume !(1 == ~P_1_pc~0); 267#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 299#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 345#L129 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 343#L383 assume !(0 != activate_threads_~tmp~1#1); 300#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 301#L199 assume 1 == ~C_1_pc~0; 341#L200 assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 278#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 356#L221 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 360#L391 assume !(0 != activate_threads_~tmp___1~1#1); 259#L391-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260#L339 assume { :end_inline_reset_delta_events } true; 310#L445-2 [2022-11-16 12:05:15,011 INFO L750 eck$LassoCheckResult]: Loop: 310#L445-2 assume !false; 361#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 284#L304 assume !false; 365#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 344#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 303#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 297#L268 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 298#L284 assume !(0 != eval_~tmp___2~0#1); 355#L320 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 353#L229-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 306#L331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 261#L117-3 assume 1 == ~P_1_pc~0; 262#L118-1 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 346#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 331#L129-1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 317#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 288#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 289#L199-3 assume 1 == ~C_1_pc~0; 294#L200-1 assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1; 296#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 347#L221-1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 348#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 319#L391-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 320#L339-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 279#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 280#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 325#L268-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 357#L464 assume !(0 == start_simulation_~tmp~3#1); 275#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 302#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 308#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 362#L268-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 264#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 265#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 363#L427 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 309#L477 assume !(0 != start_simulation_~tmp___0~2#1); 310#L445-2 [2022-11-16 12:05:15,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:15,012 INFO L85 PathProgramCache]: Analyzing trace with hash 484539831, now seen corresponding path program 1 times [2022-11-16 12:05:15,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:15,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492180207] [2022-11-16 12:05:15,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:15,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:15,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:05:15,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:05:15,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:05:15,225 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [492180207] [2022-11-16 12:05:15,225 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [492180207] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:05:15,225 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:05:15,226 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 12:05:15,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [727643990] [2022-11-16 12:05:15,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:05:15,227 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:05:15,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:15,228 INFO L85 PathProgramCache]: Analyzing trace with hash -745860796, now seen corresponding path program 1 times [2022-11-16 12:05:15,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:15,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228032228] [2022-11-16 12:05:15,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:15,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:15,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:05:15,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:05:15,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:05:15,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228032228] [2022-11-16 12:05:15,326 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [228032228] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:05:15,326 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:05:15,326 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:05:15,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389620696] [2022-11-16 12:05:15,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:05:15,328 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:05:15,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:05:15,329 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:05:15,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:05:15,329 INFO L87 Difference]: Start difference. First operand 115 states and 165 transitions. cyclomatic complexity: 51 Second operand has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:15,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:05:15,555 INFO L93 Difference]: Finished difference Result 281 states and 389 transitions. [2022-11-16 12:05:15,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281 states and 389 transitions. [2022-11-16 12:05:15,561 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 246 [2022-11-16 12:05:15,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281 states to 281 states and 389 transitions. [2022-11-16 12:05:15,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2022-11-16 12:05:15,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2022-11-16 12:05:15,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281 states and 389 transitions. [2022-11-16 12:05:15,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:05:15,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281 states and 389 transitions. [2022-11-16 12:05:15,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states and 389 transitions. [2022-11-16 12:05:15,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 262. [2022-11-16 12:05:15,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 262 states, 262 states have (on average 1.3969465648854962) internal successors, (366), 261 states have internal predecessors, (366), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:15,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 366 transitions. [2022-11-16 12:05:15,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 262 states and 366 transitions. [2022-11-16 12:05:15,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:05:15,618 INFO L428 stractBuchiCegarLoop]: Abstraction has 262 states and 366 transitions. [2022-11-16 12:05:15,619 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 12:05:15,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 262 states and 366 transitions. [2022-11-16 12:05:15,622 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 239 [2022-11-16 12:05:15,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:05:15,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:05:15,629 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:15,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:15,633 INFO L748 eck$LassoCheckResult]: Stem: 797#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~C_1_i~0 := 0;~e~0 := 0;~P_1_pc~0 := 0;~num~0 := 0;~P_1_st~0 := 0;~i~0 := 0;~data_0~0 := 0;~C_1_pr~0 := 0;~C_1_st~0 := 0;~data_1~0 := 0;~max_loop~0 := 0;~timer~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_ev~0 := 0;~P_1_i~0 := 0; 734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 735#L496 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 778#L229 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 769#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 765#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 766#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 689#L331 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 674#L117 assume !(1 == ~P_1_pc~0); 675#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 706#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 758#L129 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 753#L383 assume !(0 != activate_threads_~tmp~1#1); 709#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 710#L199 assume !(1 == ~C_1_pc~0); 752#L199-2 assume !(2 == ~C_1_pc~0); 687#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 688#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 774#L221 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 779#L391 assume !(0 != activate_threads_~tmp___1~1#1); 670#L391-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 671#L339 assume { :end_inline_reset_delta_events } true; 798#L445-2 [2022-11-16 12:05:15,634 INFO L750 eck$LassoCheckResult]: Loop: 798#L445-2 assume !false; 865#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 860#L304 assume !false; 859#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 857#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 854#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 852#L268 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 849#L284 assume !(0 != eval_~tmp___2~0#1); 847#L320 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 844#L229-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 714#L331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 668#L117-3 assume !(1 == ~P_1_pc~0); 669#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 776#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 739#L129-1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 726#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 695#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 696#L199-3 assume !(1 == ~C_1_pc~0); 795#L199-5 assume 2 == ~C_1_pc~0; 720#L210-1 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1; 721#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 762#L221-1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 763#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 727#L391-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728#L339-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 683#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 684#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 733#L268-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 775#L464 assume !(0 == start_simulation_~tmp~3#1); 794#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 880#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 877#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 876#L268-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 875#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 873#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 871#L427 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 869#L477 assume !(0 != start_simulation_~tmp___0~2#1); 798#L445-2 [2022-11-16 12:05:15,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:15,635 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 1 times [2022-11-16 12:05:15,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:15,638 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530431129] [2022-11-16 12:05:15,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:15,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:15,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:15,667 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:15,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:15,726 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:05:15,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:15,728 INFO L85 PathProgramCache]: Analyzing trace with hash -1174958789, now seen corresponding path program 1 times [2022-11-16 12:05:15,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:15,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436327292] [2022-11-16 12:05:15,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:15,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:15,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:05:15,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:05:15,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:05:15,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436327292] [2022-11-16 12:05:15,928 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436327292] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:05:15,929 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:05:15,929 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:05:15,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69947185] [2022-11-16 12:05:15,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:05:15,930 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:05:15,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:05:15,930 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:05:15,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:05:15,931 INFO L87 Difference]: Start difference. First operand 262 states and 366 transitions. cyclomatic complexity: 106 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:16,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:05:16,064 INFO L93 Difference]: Finished difference Result 451 states and 622 transitions. [2022-11-16 12:05:16,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 622 transitions. [2022-11-16 12:05:16,069 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 428 [2022-11-16 12:05:16,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 622 transitions. [2022-11-16 12:05:16,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2022-11-16 12:05:16,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2022-11-16 12:05:16,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 622 transitions. [2022-11-16 12:05:16,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:05:16,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 622 transitions. [2022-11-16 12:05:16,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 622 transitions. [2022-11-16 12:05:16,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 271. [2022-11-16 12:05:16,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.3837638376383763) internal successors, (375), 270 states have internal predecessors, (375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:16,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 375 transitions. [2022-11-16 12:05:16,098 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 375 transitions. [2022-11-16 12:05:16,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 12:05:16,100 INFO L428 stractBuchiCegarLoop]: Abstraction has 271 states and 375 transitions. [2022-11-16 12:05:16,100 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 12:05:16,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 375 transitions. [2022-11-16 12:05:16,105 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 248 [2022-11-16 12:05:16,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:05:16,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:05:16,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:16,114 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:16,114 INFO L748 eck$LassoCheckResult]: Stem: 1535#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~C_1_i~0 := 0;~e~0 := 0;~P_1_pc~0 := 0;~num~0 := 0;~P_1_st~0 := 0;~i~0 := 0;~data_0~0 := 0;~C_1_pr~0 := 0;~C_1_st~0 := 0;~data_1~0 := 0;~max_loop~0 := 0;~timer~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_ev~0 := 0;~P_1_i~0 := 0; 1469#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 1470#L496 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1511#L229 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1503#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1498#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1499#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1418#L331 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1403#L117 assume !(1 == ~P_1_pc~0); 1404#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1435#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1491#L129 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1486#L383 assume !(0 != activate_threads_~tmp~1#1); 1438#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 1439#L199 assume !(1 == ~C_1_pc~0); 1485#L199-2 assume !(2 == ~C_1_pc~0); 1416#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 1417#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 1506#L221 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1512#L391 assume !(0 != activate_threads_~tmp___1~1#1); 1399#L391-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1400#L339 assume { :end_inline_reset_delta_events } true; 1540#L445-2 [2022-11-16 12:05:16,115 INFO L750 eck$LassoCheckResult]: Loop: 1540#L445-2 assume !false; 1648#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1420#L304 assume !false; 1597#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1594#L254 assume !(0 == ~P_1_st~0); 1591#L258 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 1590#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1589#L268 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1588#L284 assume !(0 != eval_~tmp___2~0#1); 1510#L320 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1500#L229-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1443#L331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1397#L117-3 assume !(1 == ~P_1_pc~0); 1398#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 1515#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1474#L129-1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1475#L383-3 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1424#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 1425#L199-3 assume !(1 == ~C_1_pc~0); 1530#L199-5 assume 2 == ~C_1_pc~0; 1531#L210-1 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1; 1528#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 1529#L221-1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1542#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1543#L391-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1619#L339-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1412#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1413#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1468#L268-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1507#L464 assume !(0 == start_simulation_~tmp~3#1); 1436#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1437#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1657#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1655#L268-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 1653#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1652#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1650#L427 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1649#L477 assume !(0 != start_simulation_~tmp___0~2#1); 1540#L445-2 [2022-11-16 12:05:16,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:16,116 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 2 times [2022-11-16 12:05:16,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:16,116 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [289007418] [2022-11-16 12:05:16,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:16,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:16,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:16,129 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:16,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:16,144 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:05:16,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:16,145 INFO L85 PathProgramCache]: Analyzing trace with hash 1740811999, now seen corresponding path program 1 times [2022-11-16 12:05:16,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:16,146 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610038792] [2022-11-16 12:05:16,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:16,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:16,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:05:16,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:05:16,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:05:16,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610038792] [2022-11-16 12:05:16,335 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610038792] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:05:16,335 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:05:16,335 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:05:16,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703800203] [2022-11-16 12:05:16,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:05:16,336 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:05:16,337 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:05:16,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:05:16,338 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:05:16,338 INFO L87 Difference]: Start difference. First operand 271 states and 375 transitions. cyclomatic complexity: 106 Second operand has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:16,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:05:16,449 INFO L93 Difference]: Finished difference Result 577 states and 796 transitions. [2022-11-16 12:05:16,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 577 states and 796 transitions. [2022-11-16 12:05:16,454 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 554 [2022-11-16 12:05:16,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 577 states to 577 states and 796 transitions. [2022-11-16 12:05:16,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 577 [2022-11-16 12:05:16,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 577 [2022-11-16 12:05:16,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 577 states and 796 transitions. [2022-11-16 12:05:16,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:05:16,463 INFO L218 hiAutomatonCegarLoop]: Abstraction has 577 states and 796 transitions. [2022-11-16 12:05:16,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577 states and 796 transitions. [2022-11-16 12:05:16,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577 to 283. [2022-11-16 12:05:16,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 283 states, 283 states have (on average 1.3568904593639577) internal successors, (384), 282 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:16,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 283 states to 283 states and 384 transitions. [2022-11-16 12:05:16,494 INFO L240 hiAutomatonCegarLoop]: Abstraction has 283 states and 384 transitions. [2022-11-16 12:05:16,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 12:05:16,507 INFO L428 stractBuchiCegarLoop]: Abstraction has 283 states and 384 transitions. [2022-11-16 12:05:16,507 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 12:05:16,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 283 states and 384 transitions. [2022-11-16 12:05:16,509 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 260 [2022-11-16 12:05:16,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:05:16,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:05:16,511 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:16,512 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:16,513 INFO L748 eck$LassoCheckResult]: Stem: 2381#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~C_1_i~0 := 0;~e~0 := 0;~P_1_pc~0 := 0;~num~0 := 0;~P_1_st~0 := 0;~i~0 := 0;~data_0~0 := 0;~C_1_pr~0 := 0;~C_1_st~0 := 0;~data_1~0 := 0;~max_loop~0 := 0;~timer~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_ev~0 := 0;~P_1_i~0 := 0; 2325#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 2326#L496 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2365#L229 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2358#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2354#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2355#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2279#L331 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2264#L117 assume !(1 == ~P_1_pc~0); 2265#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 2296#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2345#L129 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2343#L383 assume !(0 != activate_threads_~tmp~1#1); 2297#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 2298#L199 assume !(1 == ~C_1_pc~0); 2342#L199-2 assume !(2 == ~C_1_pc~0); 2274#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 2275#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 2359#L221 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2366#L391 assume !(0 != activate_threads_~tmp___1~1#1); 2258#L391-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2259#L339 assume { :end_inline_reset_delta_events } true; 2382#L445-2 [2022-11-16 12:05:16,514 INFO L750 eck$LassoCheckResult]: Loop: 2382#L445-2 assume !false; 2406#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2401#L304 assume !false; 2400#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2399#L254 assume !(0 == ~P_1_st~0); 2397#L258 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2396#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2395#L268 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2393#L284 assume !(0 != eval_~tmp___2~0#1); 2392#L320 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2391#L229-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2390#L331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2260#L117-3 assume !(1 == ~P_1_pc~0); 2261#L117-5 is_P_1_triggered_~__retres1~0#1 := 0; 2460#L128-1 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2459#L129-1 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2458#L383-3 assume !(0 != activate_threads_~tmp~1#1); 2456#L383-5 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 2454#L199-3 assume !(1 == ~C_1_pc~0); 2452#L199-5 assume 2 == ~C_1_pc~0; 2449#L210-1 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1; 2447#L220-1 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 2445#L221-1 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2442#L391-3 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2440#L391-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2438#L339-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2435#L254-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2433#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2431#L268-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2429#L464 assume !(0 == start_simulation_~tmp~3#1); 2427#L464-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2426#L254-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2424#L267-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2423#L268-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 2422#L419 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2421#L426 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2419#L427 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2414#L477 assume !(0 != start_simulation_~tmp___0~2#1); 2382#L445-2 [2022-11-16 12:05:16,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:16,515 INFO L85 PathProgramCache]: Analyzing trace with hash 1818999495, now seen corresponding path program 3 times [2022-11-16 12:05:16,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:16,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481808321] [2022-11-16 12:05:16,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:16,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:16,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:16,526 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:16,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:16,539 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:05:16,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:16,540 INFO L85 PathProgramCache]: Analyzing trace with hash 1959666717, now seen corresponding path program 1 times [2022-11-16 12:05:16,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:16,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932436845] [2022-11-16 12:05:16,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:16,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:16,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:05:16,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:05:16,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:05:16,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932436845] [2022-11-16 12:05:16,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932436845] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:05:16,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:05:16,615 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:05:16,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [235213241] [2022-11-16 12:05:16,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:05:16,616 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:05:16,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:05:16,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:05:16,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:05:16,617 INFO L87 Difference]: Start difference. First operand 283 states and 384 transitions. cyclomatic complexity: 103 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:16,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:05:16,674 INFO L93 Difference]: Finished difference Result 427 states and 570 transitions. [2022-11-16 12:05:16,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 427 states and 570 transitions. [2022-11-16 12:05:16,680 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 397 [2022-11-16 12:05:16,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 427 states to 427 states and 570 transitions. [2022-11-16 12:05:16,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 427 [2022-11-16 12:05:16,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 427 [2022-11-16 12:05:16,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 427 states and 570 transitions. [2022-11-16 12:05:16,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:05:16,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 427 states and 570 transitions. [2022-11-16 12:05:16,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 427 states and 570 transitions. [2022-11-16 12:05:16,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 427 to 427. [2022-11-16 12:05:16,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 427 states, 427 states have (on average 1.334894613583138) internal successors, (570), 426 states have internal predecessors, (570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:16,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 570 transitions. [2022-11-16 12:05:16,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 427 states and 570 transitions. [2022-11-16 12:05:16,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:05:16,722 INFO L428 stractBuchiCegarLoop]: Abstraction has 427 states and 570 transitions. [2022-11-16 12:05:16,723 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 12:05:16,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 427 states and 570 transitions. [2022-11-16 12:05:16,726 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 397 [2022-11-16 12:05:16,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:05:16,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:05:16,727 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:16,727 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:16,727 INFO L748 eck$LassoCheckResult]: Stem: 3103#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~C_1_i~0 := 0;~e~0 := 0;~P_1_pc~0 := 0;~num~0 := 0;~P_1_st~0 := 0;~i~0 := 0;~data_0~0 := 0;~C_1_pr~0 := 0;~C_1_st~0 := 0;~data_1~0 := 0;~max_loop~0 := 0;~timer~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_ev~0 := 0;~P_1_i~0 := 0; 3042#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 3043#L496 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3083#L229 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3072#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3070#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3071#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2994#L331 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2980#L117 assume !(1 == ~P_1_pc~0); 2981#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 3013#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3061#L129 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3059#L383 assume !(0 != activate_threads_~tmp~1#1); 3014#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 3015#L199 assume !(1 == ~C_1_pc~0); 3058#L199-2 assume !(2 == ~C_1_pc~0); 2990#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 2991#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 3075#L221 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3084#L391 assume !(0 != activate_threads_~tmp___1~1#1); 2974#L391-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2975#L339 assume { :end_inline_reset_delta_events } true; 3105#L445-2 assume !false; 3397#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2996#L304 [2022-11-16 12:05:16,728 INFO L750 eck$LassoCheckResult]: Loop: 2996#L304 assume !false; 3395#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3394#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3393#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3392#L268 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3391#L284 assume 0 != eval_~tmp___2~0#1; 3390#L284-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 3102#L293 assume !(0 != eval_~tmp~0#1); 3034#L289 assume !(0 == ~C_1_st~0); 2996#L304 [2022-11-16 12:05:16,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:16,729 INFO L85 PathProgramCache]: Analyzing trace with hash 6828137, now seen corresponding path program 1 times [2022-11-16 12:05:16,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:16,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899292997] [2022-11-16 12:05:16,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:16,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:16,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:16,739 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:16,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:16,752 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:05:16,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:16,753 INFO L85 PathProgramCache]: Analyzing trace with hash 602708997, now seen corresponding path program 1 times [2022-11-16 12:05:16,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:16,753 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396918546] [2022-11-16 12:05:16,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:16,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:16,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:16,759 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:16,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:16,764 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:05:16,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:16,765 INFO L85 PathProgramCache]: Analyzing trace with hash 462446749, now seen corresponding path program 1 times [2022-11-16 12:05:16,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:16,766 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768809999] [2022-11-16 12:05:16,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:16,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:16,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:05:16,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:05:16,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:05:16,805 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768809999] [2022-11-16 12:05:16,806 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768809999] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:05:16,806 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:05:16,806 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:05:16,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1541358998] [2022-11-16 12:05:16,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:05:16,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:05:16,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:05:16,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:05:16,889 INFO L87 Difference]: Start difference. First operand 427 states and 570 transitions. cyclomatic complexity: 146 Second operand has 3 states, 2 states have (on average 16.5) internal successors, (33), 3 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:16,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:05:16,935 INFO L93 Difference]: Finished difference Result 706 states and 924 transitions. [2022-11-16 12:05:16,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 706 states and 924 transitions. [2022-11-16 12:05:16,941 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2022-11-16 12:05:16,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 706 states to 706 states and 924 transitions. [2022-11-16 12:05:16,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 706 [2022-11-16 12:05:16,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 706 [2022-11-16 12:05:16,947 INFO L73 IsDeterministic]: Start isDeterministic. Operand 706 states and 924 transitions. [2022-11-16 12:05:16,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:05:16,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 706 states and 924 transitions. [2022-11-16 12:05:16,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 706 states and 924 transitions. [2022-11-16 12:05:16,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 706 to 706. [2022-11-16 12:05:16,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 706 states, 706 states have (on average 1.3087818696883853) internal successors, (924), 705 states have internal predecessors, (924), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:16,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 706 states to 706 states and 924 transitions. [2022-11-16 12:05:16,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 706 states and 924 transitions. [2022-11-16 12:05:16,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:05:16,965 INFO L428 stractBuchiCegarLoop]: Abstraction has 706 states and 924 transitions. [2022-11-16 12:05:16,965 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 12:05:16,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 706 states and 924 transitions. [2022-11-16 12:05:16,969 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2022-11-16 12:05:16,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:05:16,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:05:16,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:16,971 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:16,971 INFO L748 eck$LassoCheckResult]: Stem: 4245#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~C_1_i~0 := 0;~e~0 := 0;~P_1_pc~0 := 0;~num~0 := 0;~P_1_st~0 := 0;~i~0 := 0;~data_0~0 := 0;~C_1_pr~0 := 0;~C_1_st~0 := 0;~data_1~0 := 0;~max_loop~0 := 0;~timer~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_ev~0 := 0;~P_1_i~0 := 0; 4179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 4180#L496 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4222#L229 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4210#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 4207#L236-2 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 4208#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4546#L331 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4545#L117 assume !(1 == ~P_1_pc~0); 4544#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 4543#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4542#L129 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4541#L383 assume !(0 != activate_threads_~tmp~1#1); 4540#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 4539#L199 assume !(1 == ~C_1_pc~0); 4538#L199-2 assume !(2 == ~C_1_pc~0); 4536#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 4535#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 4534#L221 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4533#L391 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4115#L391-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4116#L339 assume { :end_inline_reset_delta_events } true; 4246#L445-2 assume !false; 4563#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 4551#L304 [2022-11-16 12:05:16,972 INFO L750 eck$LassoCheckResult]: Loop: 4551#L304 assume !false; 4562#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4560#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4559#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4558#L268 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4557#L284 assume 0 != eval_~tmp___2~0#1; 4555#L284-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4553#L293 assume !(0 != eval_~tmp~0#1); 4552#L289 assume 0 == ~C_1_st~0;eval_~tmp___1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4550#L308 assume !(0 != eval_~tmp___1~0#1); 4551#L304 [2022-11-16 12:05:16,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:16,972 INFO L85 PathProgramCache]: Analyzing trace with hash -1683962647, now seen corresponding path program 1 times [2022-11-16 12:05:16,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:16,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513339075] [2022-11-16 12:05:16,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:16,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:16,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:05:17,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:05:17,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:05:17,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513339075] [2022-11-16 12:05:17,008 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [513339075] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:05:17,008 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:05:17,008 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:05:17,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326767428] [2022-11-16 12:05:17,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:05:17,009 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:05:17,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:17,010 INFO L85 PathProgramCache]: Analyzing trace with hash 1504107565, now seen corresponding path program 1 times [2022-11-16 12:05:17,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:17,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985246088] [2022-11-16 12:05:17,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:17,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:17,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:17,016 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:17,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:17,022 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:05:17,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:05:17,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:05:17,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:05:17,141 INFO L87 Difference]: Start difference. First operand 706 states and 924 transitions. cyclomatic complexity: 221 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:17,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:05:17,151 INFO L93 Difference]: Finished difference Result 687 states and 901 transitions. [2022-11-16 12:05:17,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 687 states and 901 transitions. [2022-11-16 12:05:17,156 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2022-11-16 12:05:17,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 687 states to 687 states and 901 transitions. [2022-11-16 12:05:17,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 687 [2022-11-16 12:05:17,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 687 [2022-11-16 12:05:17,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 687 states and 901 transitions. [2022-11-16 12:05:17,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:05:17,164 INFO L218 hiAutomatonCegarLoop]: Abstraction has 687 states and 901 transitions. [2022-11-16 12:05:17,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 687 states and 901 transitions. [2022-11-16 12:05:17,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 687 to 687. [2022-11-16 12:05:17,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 687 states, 687 states have (on average 1.3114992721979621) internal successors, (901), 686 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:05:17,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 687 states to 687 states and 901 transitions. [2022-11-16 12:05:17,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 687 states and 901 transitions. [2022-11-16 12:05:17,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:05:17,180 INFO L428 stractBuchiCegarLoop]: Abstraction has 687 states and 901 transitions. [2022-11-16 12:05:17,180 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 12:05:17,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 687 states and 901 transitions. [2022-11-16 12:05:17,184 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 652 [2022-11-16 12:05:17,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:05:17,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:05:17,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:17,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:05:17,186 INFO L748 eck$LassoCheckResult]: Stem: 5640#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~C_1_i~0 := 0;~e~0 := 0;~P_1_pc~0 := 0;~num~0 := 0;~P_1_st~0 := 0;~i~0 := 0;~data_0~0 := 0;~C_1_pr~0 := 0;~C_1_st~0 := 0;~data_1~0 := 0;~max_loop~0 := 0;~timer~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_ev~0 := 0;~P_1_i~0 := 0; 5580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1; 5581#L496 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5621#L229 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5608#L236 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 5605#L236-2 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 5606#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5534#L331 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 5520#L117 assume !(1 == ~P_1_pc~0); 5521#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 5552#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 5597#L129 activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5595#L383 assume !(0 != activate_threads_~tmp~1#1); 5554#L383-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1; 5555#L199 assume !(1 == ~C_1_pc~0); 5594#L199-2 assume !(2 == ~C_1_pc~0); 5532#L209-1 is_C_1_triggered_~__retres1~1#1 := 0; 5533#L220 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1; 5611#L221 activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5622#L391 assume !(0 != activate_threads_~tmp___1~1#1); 5514#L391-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5515#L339 assume { :end_inline_reset_delta_events } true; 5642#L445-2 assume !false; 5940#L446 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 5923#L304 [2022-11-16 12:05:17,186 INFO L750 eck$LassoCheckResult]: Loop: 5923#L304 assume !false; 5939#L280 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5937#L254 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5935#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5934#L268 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5932#L284 assume 0 != eval_~tmp___2~0#1; 5930#L284-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5927#L293 assume !(0 != eval_~tmp~0#1); 5925#L289 assume 0 == ~C_1_st~0;eval_~tmp___1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5791#L308 assume !(0 != eval_~tmp___1~0#1); 5923#L304 [2022-11-16 12:05:17,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:17,187 INFO L85 PathProgramCache]: Analyzing trace with hash 6828137, now seen corresponding path program 2 times [2022-11-16 12:05:17,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:17,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878142210] [2022-11-16 12:05:17,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:17,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:17,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:17,196 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:17,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:17,207 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:05:17,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:17,208 INFO L85 PathProgramCache]: Analyzing trace with hash 1504107565, now seen corresponding path program 2 times [2022-11-16 12:05:17,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:17,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162899965] [2022-11-16 12:05:17,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:17,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:17,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:17,214 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:17,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:17,219 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:05:17,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:05:17,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1450945173, now seen corresponding path program 1 times [2022-11-16 12:05:17,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:05:17,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176947816] [2022-11-16 12:05:17,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:05:17,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:05:17,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:17,235 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:17,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:17,255 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:05:18,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:18,359 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:05:18,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:05:18,515 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.11 12:05:18 BoogieIcfgContainer [2022-11-16 12:05:18,525 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-16 12:05:18,526 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-16 12:05:18,526 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-16 12:05:18,526 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-16 12:05:18,527 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:05:14" (3/4) ... [2022-11-16 12:05:18,530 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-16 12:05:18,660 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/witness.graphml [2022-11-16 12:05:18,661 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-16 12:05:18,666 INFO L158 Benchmark]: Toolchain (without parser) took 5823.09ms. Allocated memory was 159.4MB in the beginning and 197.1MB in the end (delta: 37.7MB). Free memory was 123.8MB in the beginning and 169.2MB in the end (delta: -45.4MB). Peak memory consumption was 81.3MB. Max. memory is 16.1GB. [2022-11-16 12:05:18,666 INFO L158 Benchmark]: CDTParser took 0.73ms. Allocated memory is still 90.2MB. Free memory was 61.2MB in the beginning and 61.1MB in the end (delta: 27.2kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-16 12:05:18,671 INFO L158 Benchmark]: CACSL2BoogieTranslator took 474.15ms. Allocated memory is still 159.4MB. Free memory was 123.8MB in the beginning and 133.8MB in the end (delta: -10.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-16 12:05:18,671 INFO L158 Benchmark]: Boogie Procedure Inliner took 62.31ms. Allocated memory is still 159.4MB. Free memory was 133.8MB in the beginning and 131.2MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-16 12:05:18,672 INFO L158 Benchmark]: Boogie Preprocessor took 84.20ms. Allocated memory is still 159.4MB. Free memory was 131.2MB in the beginning and 129.6MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-16 12:05:18,673 INFO L158 Benchmark]: RCFGBuilder took 899.82ms. Allocated memory is still 159.4MB. Free memory was 129.1MB in the beginning and 109.3MB in the end (delta: 19.7MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2022-11-16 12:05:18,675 INFO L158 Benchmark]: BuchiAutomizer took 4157.11ms. Allocated memory is still 159.4MB. Free memory was 108.8MB in the beginning and 49.1MB in the end (delta: 59.6MB). Peak memory consumption was 61.6MB. Max. memory is 16.1GB. [2022-11-16 12:05:18,675 INFO L158 Benchmark]: Witness Printer took 138.56ms. Allocated memory was 159.4MB in the beginning and 197.1MB in the end (delta: 37.7MB). Free memory was 49.1MB in the beginning and 169.2MB in the end (delta: -120.0MB). Peak memory consumption was 7.9MB. Max. memory is 16.1GB. [2022-11-16 12:05:18,678 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.73ms. Allocated memory is still 90.2MB. Free memory was 61.2MB in the beginning and 61.1MB in the end (delta: 27.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 474.15ms. Allocated memory is still 159.4MB. Free memory was 123.8MB in the beginning and 133.8MB in the end (delta: -10.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 62.31ms. Allocated memory is still 159.4MB. Free memory was 133.8MB in the beginning and 131.2MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 84.20ms. Allocated memory is still 159.4MB. Free memory was 131.2MB in the beginning and 129.6MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 899.82ms. Allocated memory is still 159.4MB. Free memory was 129.1MB in the beginning and 109.3MB in the end (delta: 19.7MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 4157.11ms. Allocated memory is still 159.4MB. Free memory was 108.8MB in the beginning and 49.1MB in the end (delta: 59.6MB). Peak memory consumption was 61.6MB. Max. memory is 16.1GB. * Witness Printer took 138.56ms. Allocated memory was 159.4MB in the beginning and 197.1MB in the end (delta: 37.7MB). Free memory was 49.1MB in the beginning and 169.2MB in the end (delta: -120.0MB). Peak memory consumption was 7.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 7 terminating modules (7 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.7 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 687 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.9s and 8 iterations. TraceHistogramMax:1. Analysis of lassos took 2.7s. Construction of modules took 0.3s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 7. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 7 MinimizatonAttempts, 493 StatesRemovedByMinimization, 3 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1602 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1602 mSDsluCounter, 2755 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1615 mSDsCounter, 60 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 169 IncrementalHoareTripleChecker+Invalid, 229 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 60 mSolverCounterUnsat, 1140 mSDtfsCounter, 169 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN1 SILU0 SILI2 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 279]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L134] int C_1_i ; [L28] int e ; [L74] int P_1_pc; [L26] int num ; [L75] int P_1_st ; [L27] int i ; [L30] char data_0 ; [L136] int C_1_pr ; [L133] int C_1_st ; [L31] char data_1 ; [L25] int max_loop ; [L29] int timer ; [L77] int P_1_ev ; [L132] int C_1_pc ; [L135] int C_1_ev ; [L76] int P_1_i ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L500] int count ; [L501] int __retres2 ; [L505] num = 0 [L506] i = 0 [L507] max_loop = 2 [L509] timer = 0 [L510] P_1_pc = 0 [L511] C_1_pc = 0 [L513] count = 0 [L514] CALL init_model() [L493] P_1_i = 1 [L494] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L514] RET init_model() [L515] CALL start_simulation() [L431] int kernel_st ; [L432] int tmp ; [L433] int tmp___0 ; [L437] kernel_st = 0 [L438] FCALL update_channels() [L439] CALL init_threads() [L236] COND TRUE (int )P_1_i == 1 [L237] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] COND TRUE (int )C_1_i == 1 [L242] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L439] RET init_threads() [L440] FCALL fire_delta_events() [L441] CALL activate_threads() [L375] int tmp ; [L376] int tmp___0 ; [L377] int tmp___1 ; [L381] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L127] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L129] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L381] RET, EXPR is_P_1_triggered() [L381] tmp = is_P_1_triggered() [L383] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L389] CALL, EXPR is_C_1_triggered() [L196] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L219] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L221] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L389] RET, EXPR is_C_1_triggered() [L389] tmp___1 = is_C_1_triggered() [L391] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=0] [L441] RET activate_threads() [L442] FCALL reset_delta_events() [L445] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L448] kernel_st = 1 [L449] CALL eval() [L272] int tmp ; [L273] int tmp___0 ; [L274] int tmp___1 ; [L275] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] Loop: [L279] COND TRUE 1 [L282] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE (int )P_1_st == 0 [L255] __retres1 = 1 [L268] return (__retres1); [L282] RET, EXPR exists_runnable_thread() [L282] tmp___2 = exists_runnable_thread() [L284] COND TRUE \read(tmp___2) [L289] COND TRUE (int )P_1_st == 0 [L291] tmp = __VERIFIER_nondet_int() [L293] COND FALSE !(\read(tmp)) [L304] COND TRUE (int )C_1_st == 0 [L306] tmp___1 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 279]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L134] int C_1_i ; [L28] int e ; [L74] int P_1_pc; [L26] int num ; [L75] int P_1_st ; [L27] int i ; [L30] char data_0 ; [L136] int C_1_pr ; [L133] int C_1_st ; [L31] char data_1 ; [L25] int max_loop ; [L29] int timer ; [L77] int P_1_ev ; [L132] int C_1_pc ; [L135] int C_1_ev ; [L76] int P_1_i ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L500] int count ; [L501] int __retres2 ; [L505] num = 0 [L506] i = 0 [L507] max_loop = 2 [L509] timer = 0 [L510] P_1_pc = 0 [L511] C_1_pc = 0 [L513] count = 0 [L514] CALL init_model() [L493] P_1_i = 1 [L494] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L514] RET init_model() [L515] CALL start_simulation() [L431] int kernel_st ; [L432] int tmp ; [L433] int tmp___0 ; [L437] kernel_st = 0 [L438] FCALL update_channels() [L439] CALL init_threads() [L236] COND TRUE (int )P_1_i == 1 [L237] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] COND TRUE (int )C_1_i == 1 [L242] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L439] RET init_threads() [L440] FCALL fire_delta_events() [L441] CALL activate_threads() [L375] int tmp ; [L376] int tmp___0 ; [L377] int tmp___1 ; [L381] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L127] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L129] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L381] RET, EXPR is_P_1_triggered() [L381] tmp = is_P_1_triggered() [L383] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0] [L389] CALL, EXPR is_C_1_triggered() [L196] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L219] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L221] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L389] RET, EXPR is_C_1_triggered() [L389] tmp___1 = is_C_1_triggered() [L391] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0, tmp=0, tmp___1=0] [L441] RET activate_threads() [L442] FCALL reset_delta_events() [L445] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L448] kernel_st = 1 [L449] CALL eval() [L272] int tmp ; [L273] int tmp___0 ; [L274] int tmp___1 ; [L275] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] Loop: [L279] COND TRUE 1 [L282] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE (int )P_1_st == 0 [L255] __retres1 = 1 [L268] return (__retres1); [L282] RET, EXPR exists_runnable_thread() [L282] tmp___2 = exists_runnable_thread() [L284] COND TRUE \read(tmp___2) [L289] COND TRUE (int )P_1_st == 0 [L291] tmp = __VERIFIER_nondet_int() [L293] COND FALSE !(\read(tmp)) [L304] COND TRUE (int )C_1_st == 0 [L306] tmp___1 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-16 12:05:18,752 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d1eb0a11-2d52-46ca-91b2-83c46a3c85d7/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)