./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 12:02:01,682 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 12:02:01,684 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 12:02:01,704 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 12:02:01,705 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 12:02:01,706 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 12:02:01,708 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 12:02:01,710 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 12:02:01,712 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 12:02:01,713 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 12:02:01,714 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 12:02:01,715 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 12:02:01,716 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 12:02:01,717 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 12:02:01,718 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 12:02:01,720 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 12:02:01,721 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 12:02:01,722 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 12:02:01,724 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 12:02:01,726 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 12:02:01,728 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 12:02:01,729 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 12:02:01,730 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 12:02:01,731 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 12:02:01,735 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 12:02:01,736 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 12:02:01,736 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 12:02:01,737 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 12:02:01,738 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 12:02:01,739 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 12:02:01,740 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 12:02:01,740 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 12:02:01,741 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 12:02:01,742 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 12:02:01,744 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 12:02:01,744 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 12:02:01,745 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 12:02:01,745 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 12:02:01,745 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 12:02:01,746 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 12:02:01,747 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 12:02:01,748 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 12:02:01,771 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 12:02:01,771 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 12:02:01,772 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 12:02:01,772 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 12:02:01,773 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 12:02:01,773 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 12:02:01,774 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 12:02:01,774 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 12:02:01,774 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 12:02:01,774 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 12:02:01,775 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 12:02:01,775 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 12:02:01,775 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 12:02:01,775 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 12:02:01,776 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 12:02:01,776 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 12:02:01,776 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 12:02:01,776 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 12:02:01,777 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 12:02:01,777 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 12:02:01,777 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 12:02:01,777 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 12:02:01,778 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 12:02:01,778 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 12:02:01,778 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 12:02:01,778 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 12:02:01,779 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 12:02:01,779 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 12:02:01,779 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 12:02:01,780 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 12:02:01,780 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 12:02:01,781 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 12:02:01,781 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 [2022-11-16 12:02:02,014 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 12:02:02,040 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 12:02:02,044 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 12:02:02,045 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 12:02:02,046 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 12:02:02,047 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2022-11-16 12:02:02,127 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/data/600bf31b6/c83148de6f6d45db97593355f96951bc/FLAGbb53cfa65 [2022-11-16 12:02:02,769 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 12:02:02,770 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2022-11-16 12:02:02,790 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/data/600bf31b6/c83148de6f6d45db97593355f96951bc/FLAGbb53cfa65 [2022-11-16 12:02:03,106 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/data/600bf31b6/c83148de6f6d45db97593355f96951bc [2022-11-16 12:02:03,108 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 12:02:03,110 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 12:02:03,112 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 12:02:03,112 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 12:02:03,125 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 12:02:03,126 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,127 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@69b72203 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03, skipping insertion in model container [2022-11-16 12:02:03,128 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,136 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 12:02:03,164 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 12:02:03,356 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[671,684] [2022-11-16 12:02:03,416 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:02:03,426 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 12:02:03,438 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[671,684] [2022-11-16 12:02:03,470 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:02:03,486 INFO L208 MainTranslator]: Completed translation [2022-11-16 12:02:03,486 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03 WrapperNode [2022-11-16 12:02:03,487 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 12:02:03,488 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 12:02:03,488 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 12:02:03,488 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 12:02:03,496 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,510 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,560 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 63, statements flattened = 825 [2022-11-16 12:02:03,560 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 12:02:03,561 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 12:02:03,561 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 12:02:03,561 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 12:02:03,573 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,574 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,578 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,578 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,589 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,599 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,603 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,605 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,611 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 12:02:03,612 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 12:02:03,612 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 12:02:03,612 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 12:02:03,613 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (1/1) ... [2022-11-16 12:02:03,629 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 12:02:03,642 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:02:03,684 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 12:02:03,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 12:02:03,733 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 12:02:03,734 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 12:02:03,734 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 12:02:03,734 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 12:02:03,853 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 12:02:03,856 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 12:02:04,909 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 12:02:04,926 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 12:02:04,926 INFO L300 CfgBuilder]: Removed 6 assume(true) statements. [2022-11-16 12:02:04,929 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:02:04 BoogieIcfgContainer [2022-11-16 12:02:04,929 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 12:02:04,930 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 12:02:04,930 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 12:02:04,936 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 12:02:04,937 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:02:04,937 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 12:02:03" (1/3) ... [2022-11-16 12:02:04,937 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4e5f3034 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:02:04, skipping insertion in model container [2022-11-16 12:02:04,938 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:02:04,938 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:02:03" (2/3) ... [2022-11-16 12:02:04,938 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4e5f3034 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:02:04, skipping insertion in model container [2022-11-16 12:02:04,938 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:02:04,938 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:02:04" (3/3) ... [2022-11-16 12:02:04,940 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2022-11-16 12:02:04,999 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 12:02:04,999 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 12:02:04,999 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 12:02:04,999 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 12:02:05,000 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 12:02:05,000 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 12:02:05,000 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 12:02:05,000 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 12:02:05,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:05,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2022-11-16 12:02:05,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:05,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:05,053 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:05,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:05,053 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 12:02:05,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:05,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2022-11-16 12:02:05,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:05,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:05,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:05,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:05,080 INFO L748 eck$LassoCheckResult]: Stem: 310#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 216#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 64#L653true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46#L297true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 281#L304true assume !(1 == ~m_i~0);~m_st~0 := 2; 122#L304-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 24#L309-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 234#L314-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 137#L319-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30#L441true assume !(0 == ~M_E~0); 119#L441-2true assume !(0 == ~T1_E~0); 252#L446-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 95#L451-1true assume !(0 == ~T3_E~0); 274#L456-1true assume !(0 == ~E_M~0); 225#L461-1true assume !(0 == ~E_1~0); 247#L466-1true assume !(0 == ~E_2~0); 293#L471-1true assume !(0 == ~E_3~0); 50#L476-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87#L220true assume 1 == ~m_pc~0; 263#L221true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 104#L231true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178#L232true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67#L543true assume !(0 != activate_threads_~tmp~1#1); 322#L543-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 202#L239true assume !(1 == ~t1_pc~0); 222#L239-2true is_transmit1_triggered_~__retres1~1#1 := 0; 270#L250true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260#L251true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 207#L551true assume !(0 != activate_threads_~tmp___0~0#1); 326#L551-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 208#L258true assume 1 == ~t2_pc~0; 245#L259true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86#L269true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11#L270true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 220#L559true assume !(0 != activate_threads_~tmp___1~0#1); 129#L559-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169#L277true assume !(1 == ~t3_pc~0); 323#L277-2true is_transmit3_triggered_~__retres1~3#1 := 0; 38#L288true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 213#L289true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63#L567true assume !(0 != activate_threads_~tmp___2~0#1); 92#L567-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 303#L489true assume !(1 == ~M_E~0); 223#L489-2true assume !(1 == ~T1_E~0); 149#L494-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 58#L499-1true assume !(1 == ~T3_E~0); 123#L504-1true assume !(1 == ~E_M~0); 262#L509-1true assume !(1 == ~E_1~0); 51#L514-1true assume !(1 == ~E_2~0); 177#L519-1true assume !(1 == ~E_3~0); 56#L524-1true assume { :end_inline_reset_delta_events } true; 37#L690-2true [2022-11-16 12:02:05,082 INFO L750 eck$LassoCheckResult]: Loop: 37#L690-2true assume !false; 52#L691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21#L416true assume false; 320#L431true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 209#L297-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 194#L441-3true assume 0 == ~M_E~0;~M_E~0 := 1; 8#L441-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 254#L446-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 190#L451-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 35#L456-3true assume 0 == ~E_M~0;~E_M~0 := 1; 72#L461-3true assume 0 == ~E_1~0;~E_1~0 := 1; 153#L466-3true assume 0 == ~E_2~0;~E_2~0 := 1; 257#L471-3true assume !(0 == ~E_3~0); 65#L476-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105#L220-15true assume !(1 == ~m_pc~0); 159#L220-17true is_master_triggered_~__retres1~0#1 := 0; 206#L231-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27#L232-5true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 218#L543-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 130#L543-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 120#L239-15true assume 1 == ~t1_pc~0; 267#L240-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 280#L250-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 330#L251-5true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25#L551-15true assume !(0 != activate_threads_~tmp___0~0#1); 315#L551-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 314#L258-15true assume 1 == ~t2_pc~0; 152#L259-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 278#L269-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121#L270-5true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 331#L559-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 227#L559-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 299#L277-15true assume !(1 == ~t3_pc~0); 13#L277-17true is_transmit3_triggered_~__retres1~3#1 := 0; 324#L288-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241#L289-5true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 269#L567-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33#L567-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26#L489-3true assume 1 == ~M_E~0;~M_E~0 := 2; 173#L489-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 219#L494-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 297#L499-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 106#L504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 15#L509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 295#L514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 164#L519-3true assume !(1 == ~E_3~0); 45#L524-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53#L332-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57#L354-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 332#L355-1true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 150#L709true assume !(0 == start_simulation_~tmp~3#1); 7#L709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 115#L332-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 55#L354-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 112#L355-2true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 54#L664true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 154#L671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 141#L672true start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 85#L722true assume !(0 != start_simulation_~tmp___0~1#1); 37#L690-2true [2022-11-16 12:02:05,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:05,088 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2022-11-16 12:02:05,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:05,098 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909826019] [2022-11-16 12:02:05,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:05,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:05,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:05,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:05,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:05,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909826019] [2022-11-16 12:02:05,304 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909826019] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:05,304 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:05,305 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:05,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113221726] [2022-11-16 12:02:05,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:05,312 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:02:05,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:05,313 INFO L85 PathProgramCache]: Analyzing trace with hash 266127093, now seen corresponding path program 1 times [2022-11-16 12:02:05,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:05,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784768493] [2022-11-16 12:02:05,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:05,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:05,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:05,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:05,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:05,354 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784768493] [2022-11-16 12:02:05,354 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784768493] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:05,354 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:05,354 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:02:05,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436619021] [2022-11-16 12:02:05,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:05,356 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:05,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:05,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:05,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:05,394 INFO L87 Difference]: Start difference. First operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:05,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:05,453 INFO L93 Difference]: Finished difference Result 329 states and 491 transitions. [2022-11-16 12:02:05,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 491 transitions. [2022-11-16 12:02:05,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-11-16 12:02:05,477 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 323 states and 485 transitions. [2022-11-16 12:02:05,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2022-11-16 12:02:05,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2022-11-16 12:02:05,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 485 transitions. [2022-11-16 12:02:05,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:05,493 INFO L218 hiAutomatonCegarLoop]: Abstraction has 323 states and 485 transitions. [2022-11-16 12:02:05,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 485 transitions. [2022-11-16 12:02:05,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2022-11-16 12:02:05,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.501547987616099) internal successors, (485), 322 states have internal predecessors, (485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:05,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 485 transitions. [2022-11-16 12:02:05,559 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 485 transitions. [2022-11-16 12:02:05,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:05,574 INFO L428 stractBuchiCegarLoop]: Abstraction has 323 states and 485 transitions. [2022-11-16 12:02:05,574 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 12:02:05,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 485 transitions. [2022-11-16 12:02:05,580 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-11-16 12:02:05,580 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:05,580 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:05,586 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:05,586 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:05,587 INFO L748 eck$LassoCheckResult]: Stem: 989#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 955#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 795#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 762#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 763#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 869#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 721#L309-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 722#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 888#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 732#L441 assume !(0 == ~M_E~0); 733#L441-2 assume !(0 == ~T1_E~0); 863#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 836#L451-1 assume !(0 == ~T3_E~0); 837#L456-1 assume !(0 == ~E_M~0); 958#L461-1 assume !(0 == ~E_1~0); 959#L466-1 assume !(0 == ~E_2~0); 971#L471-1 assume !(0 == ~E_3~0); 770#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 771#L220 assume 1 == ~m_pc~0; 829#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 804#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 851#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 799#L543 assume !(0 != activate_threads_~tmp~1#1); 800#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 942#L239 assume !(1 == ~t1_pc~0); 940#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 941#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 974#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 944#L551 assume !(0 != activate_threads_~tmp___0~0#1); 945#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 946#L258 assume 1 == ~t2_pc~0; 947#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 828#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 690#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 691#L559 assume !(0 != activate_threads_~tmp___1~0#1); 875#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 876#L277 assume !(1 == ~t3_pc~0); 915#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 746#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 747#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 793#L567 assume !(0 != activate_threads_~tmp___2~0#1); 794#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 833#L489 assume !(1 == ~M_E~0); 957#L489-2 assume !(1 == ~T1_E~0); 902#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 784#L499-1 assume !(1 == ~T3_E~0); 785#L504-1 assume !(1 == ~E_M~0); 870#L509-1 assume !(1 == ~E_1~0); 772#L514-1 assume !(1 == ~E_2~0); 773#L519-1 assume !(1 == ~E_3~0); 780#L524-1 assume { :end_inline_reset_delta_events } true; 744#L690-2 [2022-11-16 12:02:05,587 INFO L750 eck$LassoCheckResult]: Loop: 744#L690-2 assume !false; 745#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 674#L416 assume !false; 713#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 809#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 757#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 951#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 952#L369 assume !(0 != eval_~tmp~0#1); 954#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 949#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 936#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 683#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 684#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 930#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 741#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 742#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 808#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 904#L471-3 assume !(0 == ~E_3~0); 797#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 798#L220-15 assume !(1 == ~m_pc~0); 689#L220-17 is_master_triggered_~__retres1~0#1 := 0; 688#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 727#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 728#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 877#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 864#L239-15 assume !(1 == ~t1_pc~0); 865#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 973#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 984#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 719#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 720#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 991#L258-15 assume !(1 == ~t2_pc~0); 834#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 835#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 867#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 868#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 960#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 961#L277-15 assume !(1 == ~t3_pc~0); 695#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 696#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 967#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 968#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 738#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 723#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 724#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 919#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 956#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 850#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 700#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 701#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 909#L519-3 assume !(1 == ~E_3~0); 760#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 761#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 774#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 781#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 901#L709 assume !(0 == start_simulation_~tmp~3#1); 681#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 682#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 778#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 779#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 776#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 777#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 892#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 826#L722 assume !(0 != start_simulation_~tmp___0~1#1); 744#L690-2 [2022-11-16 12:02:05,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:05,588 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2022-11-16 12:02:05,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:05,589 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943833283] [2022-11-16 12:02:05,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:05,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:05,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:05,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:05,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:05,695 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943833283] [2022-11-16 12:02:05,695 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943833283] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:05,695 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:05,696 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:05,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393565044] [2022-11-16 12:02:05,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:05,697 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:02:05,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:05,697 INFO L85 PathProgramCache]: Analyzing trace with hash -639658428, now seen corresponding path program 1 times [2022-11-16 12:02:05,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:05,698 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112457166] [2022-11-16 12:02:05,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:05,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:05,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:05,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:05,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:05,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112457166] [2022-11-16 12:02:05,833 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2112457166] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:05,833 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:05,833 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:05,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1510415456] [2022-11-16 12:02:05,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:05,834 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:05,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:05,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:05,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:05,837 INFO L87 Difference]: Start difference. First operand 323 states and 485 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:05,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:05,869 INFO L93 Difference]: Finished difference Result 323 states and 484 transitions. [2022-11-16 12:02:05,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 484 transitions. [2022-11-16 12:02:05,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-11-16 12:02:05,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 323 states and 484 transitions. [2022-11-16 12:02:05,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2022-11-16 12:02:05,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2022-11-16 12:02:05,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 484 transitions. [2022-11-16 12:02:05,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:05,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 323 states and 484 transitions. [2022-11-16 12:02:05,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 484 transitions. [2022-11-16 12:02:05,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2022-11-16 12:02:05,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.498452012383901) internal successors, (484), 322 states have internal predecessors, (484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:05,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 484 transitions. [2022-11-16 12:02:05,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 484 transitions. [2022-11-16 12:02:05,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:05,910 INFO L428 stractBuchiCegarLoop]: Abstraction has 323 states and 484 transitions. [2022-11-16 12:02:05,911 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 12:02:05,911 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 484 transitions. [2022-11-16 12:02:05,914 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-11-16 12:02:05,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:05,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:05,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:05,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:05,918 INFO L748 eck$LassoCheckResult]: Stem: 1644#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 1610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1450#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1417#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1418#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 1525#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1376#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1377#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1543#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1389#L441 assume !(0 == ~M_E~0); 1390#L441-2 assume !(0 == ~T1_E~0); 1518#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1491#L451-1 assume !(0 == ~T3_E~0); 1492#L456-1 assume !(0 == ~E_M~0); 1613#L461-1 assume !(0 == ~E_1~0); 1614#L466-1 assume !(0 == ~E_2~0); 1626#L471-1 assume !(0 == ~E_3~0); 1425#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1426#L220 assume 1 == ~m_pc~0; 1486#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1459#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1506#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1454#L543 assume !(0 != activate_threads_~tmp~1#1); 1455#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1597#L239 assume !(1 == ~t1_pc~0); 1595#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1596#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1628#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1599#L551 assume !(0 != activate_threads_~tmp___0~0#1); 1600#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1601#L258 assume 1 == ~t2_pc~0; 1602#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1483#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1345#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1346#L559 assume !(0 != activate_threads_~tmp___1~0#1); 1530#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1531#L277 assume !(1 == ~t3_pc~0); 1569#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1401#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1402#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1448#L567 assume !(0 != activate_threads_~tmp___2~0#1); 1449#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1488#L489 assume !(1 == ~M_E~0); 1612#L489-2 assume !(1 == ~T1_E~0); 1556#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1437#L499-1 assume !(1 == ~T3_E~0); 1438#L504-1 assume !(1 == ~E_M~0); 1524#L509-1 assume !(1 == ~E_1~0); 1427#L514-1 assume !(1 == ~E_2~0); 1428#L519-1 assume !(1 == ~E_3~0); 1435#L524-1 assume { :end_inline_reset_delta_events } true; 1399#L690-2 [2022-11-16 12:02:05,919 INFO L750 eck$LassoCheckResult]: Loop: 1399#L690-2 assume !false; 1400#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1329#L416 assume !false; 1368#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1464#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1411#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1606#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1607#L369 assume !(0 != eval_~tmp~0#1); 1609#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1604#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1589#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1338#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1339#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1585#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1396#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1397#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1463#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1559#L471-3 assume !(0 == ~E_3~0); 1452#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1453#L220-15 assume !(1 == ~m_pc~0); 1344#L220-17 is_master_triggered_~__retres1~0#1 := 0; 1343#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1380#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1381#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1532#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1519#L239-15 assume !(1 == ~t1_pc~0); 1520#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1629#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1639#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1374#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 1375#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1646#L258-15 assume !(1 == ~t2_pc~0); 1489#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 1490#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1522#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1523#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1615#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1616#L277-15 assume !(1 == ~t3_pc~0); 1350#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1351#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1622#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1623#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1393#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1378#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1379#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1574#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1611#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1505#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1355#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1356#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1564#L519-3 assume !(1 == ~E_3~0); 1415#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1416#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1429#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1436#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1557#L709 assume !(0 == start_simulation_~tmp~3#1); 1336#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1337#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1433#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1434#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1431#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1432#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1547#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1482#L722 assume !(0 != start_simulation_~tmp___0~1#1); 1399#L690-2 [2022-11-16 12:02:05,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:05,924 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2022-11-16 12:02:05,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:05,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771708457] [2022-11-16 12:02:05,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:05,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:05,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:06,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:06,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:06,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771708457] [2022-11-16 12:02:06,020 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771708457] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:06,020 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:06,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:06,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121221527] [2022-11-16 12:02:06,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:06,021 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:02:06,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:06,022 INFO L85 PathProgramCache]: Analyzing trace with hash -639658428, now seen corresponding path program 2 times [2022-11-16 12:02:06,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:06,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624899164] [2022-11-16 12:02:06,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:06,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:06,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:06,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:06,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:06,174 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624899164] [2022-11-16 12:02:06,174 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624899164] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:06,174 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:06,174 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:06,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382045203] [2022-11-16 12:02:06,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:06,175 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:06,176 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:06,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:06,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:06,176 INFO L87 Difference]: Start difference. First operand 323 states and 484 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:06,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:06,200 INFO L93 Difference]: Finished difference Result 323 states and 483 transitions. [2022-11-16 12:02:06,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 483 transitions. [2022-11-16 12:02:06,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-11-16 12:02:06,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 323 states and 483 transitions. [2022-11-16 12:02:06,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2022-11-16 12:02:06,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2022-11-16 12:02:06,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 483 transitions. [2022-11-16 12:02:06,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:06,209 INFO L218 hiAutomatonCegarLoop]: Abstraction has 323 states and 483 transitions. [2022-11-16 12:02:06,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 483 transitions. [2022-11-16 12:02:06,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2022-11-16 12:02:06,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.4953560371517027) internal successors, (483), 322 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:06,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 483 transitions. [2022-11-16 12:02:06,245 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 483 transitions. [2022-11-16 12:02:06,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:06,255 INFO L428 stractBuchiCegarLoop]: Abstraction has 323 states and 483 transitions. [2022-11-16 12:02:06,255 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 12:02:06,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 483 transitions. [2022-11-16 12:02:06,257 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2022-11-16 12:02:06,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:06,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:06,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:06,259 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:06,260 INFO L748 eck$LassoCheckResult]: Stem: 2299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 2265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2105#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2072#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2073#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 2179#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2029#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2030#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2198#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2042#L441 assume !(0 == ~M_E~0); 2043#L441-2 assume !(0 == ~T1_E~0); 2173#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2146#L451-1 assume !(0 == ~T3_E~0); 2147#L456-1 assume !(0 == ~E_M~0); 2268#L461-1 assume !(0 == ~E_1~0); 2269#L466-1 assume !(0 == ~E_2~0); 2281#L471-1 assume !(0 == ~E_3~0); 2080#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2081#L220 assume 1 == ~m_pc~0; 2139#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2114#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2160#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2109#L543 assume !(0 != activate_threads_~tmp~1#1); 2110#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2252#L239 assume !(1 == ~t1_pc~0); 2250#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2251#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2283#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2254#L551 assume !(0 != activate_threads_~tmp___0~0#1); 2255#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2256#L258 assume 1 == ~t2_pc~0; 2257#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2138#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2000#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2001#L559 assume !(0 != activate_threads_~tmp___1~0#1); 2185#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2186#L277 assume !(1 == ~t3_pc~0); 2224#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2056#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2057#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2103#L567 assume !(0 != activate_threads_~tmp___2~0#1); 2104#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2143#L489 assume !(1 == ~M_E~0); 2267#L489-2 assume !(1 == ~T1_E~0); 2211#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2092#L499-1 assume !(1 == ~T3_E~0); 2093#L504-1 assume !(1 == ~E_M~0); 2180#L509-1 assume !(1 == ~E_1~0); 2082#L514-1 assume !(1 == ~E_2~0); 2083#L519-1 assume !(1 == ~E_3~0); 2090#L524-1 assume { :end_inline_reset_delta_events } true; 2054#L690-2 [2022-11-16 12:02:06,262 INFO L750 eck$LassoCheckResult]: Loop: 2054#L690-2 assume !false; 2055#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1984#L416 assume !false; 2023#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2119#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2066#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2261#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2262#L369 assume !(0 != eval_~tmp~0#1); 2264#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2259#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2244#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1993#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1994#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2240#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2051#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2052#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2118#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2214#L471-3 assume !(0 == ~E_3~0); 2107#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2108#L220-15 assume 1 == ~m_pc~0; 1997#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1998#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2035#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2036#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2187#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2174#L239-15 assume 1 == ~t1_pc~0; 2176#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2284#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2294#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2031#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 2032#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2301#L258-15 assume !(1 == ~t2_pc~0); 2144#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 2145#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2177#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2178#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2270#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2271#L277-15 assume !(1 == ~t3_pc~0); 2005#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2006#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2277#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2278#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2048#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2033#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2034#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2229#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2266#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2161#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2010#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2011#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2219#L519-3 assume !(1 == ~E_3~0); 2070#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2071#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2084#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2091#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2212#L709 assume !(0 == start_simulation_~tmp~3#1); 1991#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1992#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2088#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2089#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2086#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2087#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2202#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2137#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2054#L690-2 [2022-11-16 12:02:06,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:06,264 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2022-11-16 12:02:06,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:06,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863214354] [2022-11-16 12:02:06,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:06,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:06,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:06,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:06,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:06,425 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863214354] [2022-11-16 12:02:06,426 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863214354] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:06,426 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:06,426 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:06,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [354320257] [2022-11-16 12:02:06,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:06,427 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:02:06,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:06,428 INFO L85 PathProgramCache]: Analyzing trace with hash 1190747650, now seen corresponding path program 1 times [2022-11-16 12:02:06,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:06,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333835563] [2022-11-16 12:02:06,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:06,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:06,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:06,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:06,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:06,514 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333835563] [2022-11-16 12:02:06,514 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333835563] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:06,514 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:06,515 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:06,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275933193] [2022-11-16 12:02:06,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:06,516 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:06,516 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:06,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:02:06,517 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:02:06,517 INFO L87 Difference]: Start difference. First operand 323 states and 483 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:06,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:06,627 INFO L93 Difference]: Finished difference Result 561 states and 834 transitions. [2022-11-16 12:02:06,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 561 states and 834 transitions. [2022-11-16 12:02:06,631 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 498 [2022-11-16 12:02:06,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 561 states to 561 states and 834 transitions. [2022-11-16 12:02:06,634 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 561 [2022-11-16 12:02:06,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 561 [2022-11-16 12:02:06,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 561 states and 834 transitions. [2022-11-16 12:02:06,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:06,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 561 states and 834 transitions. [2022-11-16 12:02:06,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states and 834 transitions. [2022-11-16 12:02:06,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 561. [2022-11-16 12:02:06,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 561 states, 561 states have (on average 1.4866310160427807) internal successors, (834), 560 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:06,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 561 states to 561 states and 834 transitions. [2022-11-16 12:02:06,657 INFO L240 hiAutomatonCegarLoop]: Abstraction has 561 states and 834 transitions. [2022-11-16 12:02:06,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:02:06,658 INFO L428 stractBuchiCegarLoop]: Abstraction has 561 states and 834 transitions. [2022-11-16 12:02:06,658 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 12:02:06,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 561 states and 834 transitions. [2022-11-16 12:02:06,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 498 [2022-11-16 12:02:06,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:06,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:06,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:06,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:06,663 INFO L748 eck$LassoCheckResult]: Stem: 3234#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 3183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3003#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2970#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2971#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 3080#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2926#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2927#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3099#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2940#L441 assume !(0 == ~M_E~0); 2941#L441-2 assume !(0 == ~T1_E~0); 3074#L446-1 assume !(0 == ~T2_E~0); 3045#L451-1 assume !(0 == ~T3_E~0); 3046#L456-1 assume !(0 == ~E_M~0); 3189#L461-1 assume !(0 == ~E_1~0); 3190#L466-1 assume !(0 == ~E_2~0); 3210#L471-1 assume !(0 == ~E_3~0); 2978#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2979#L220 assume 1 == ~m_pc~0; 3038#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3012#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3059#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3007#L543 assume !(0 != activate_threads_~tmp~1#1); 3008#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3164#L239 assume !(1 == ~t1_pc~0); 3162#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3163#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3214#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3168#L551 assume !(0 != activate_threads_~tmp___0~0#1); 3169#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3170#L258 assume 1 == ~t2_pc~0; 3171#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3037#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2896#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2897#L559 assume !(0 != activate_threads_~tmp___1~0#1); 3086#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3087#L277 assume !(1 == ~t3_pc~0); 3127#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2954#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2955#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3001#L567 assume !(0 != activate_threads_~tmp___2~0#1); 3002#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3042#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 3186#L489-2 assume !(1 == ~T1_E~0); 3187#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2990#L499-1 assume !(1 == ~T3_E~0); 2991#L504-1 assume !(1 == ~E_M~0); 3081#L509-1 assume !(1 == ~E_1~0); 2980#L514-1 assume !(1 == ~E_2~0); 2981#L519-1 assume !(1 == ~E_3~0); 3137#L524-1 assume { :end_inline_reset_delta_events } true; 3249#L690-2 [2022-11-16 12:02:06,664 INFO L750 eck$LassoCheckResult]: Loop: 3249#L690-2 assume !false; 3248#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2919#L416 assume !false; 2920#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3165#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2964#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3178#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3179#L369 assume !(0 != eval_~tmp~0#1); 3241#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3173#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3174#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3240#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3343#L446-3 assume !(0 == ~T2_E~0); 3342#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3341#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3340#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3339#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3338#L471-3 assume !(0 == ~E_3~0); 3337#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3336#L220-15 assume !(1 == ~m_pc~0); 3334#L220-17 is_master_triggered_~__retres1~0#1 := 0; 3333#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3332#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3331#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3330#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3329#L239-15 assume !(1 == ~t1_pc~0); 3328#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3326#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3325#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3324#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 3323#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3322#L258-15 assume 1 == ~t2_pc~0; 3320#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3319#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3318#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3317#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3316#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3315#L277-15 assume !(1 == ~t3_pc~0); 3313#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 3312#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3311#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3310#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3309#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3308#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2931#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3307#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3184#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3306#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3305#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3304#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3303#L519-3 assume !(1 == ~E_3~0); 3302#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3300#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3297#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3296#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3295#L709 assume !(0 == start_simulation_~tmp~3#1); 3136#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3068#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2986#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2987#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2984#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2985#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3103#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3104#L722 assume !(0 != start_simulation_~tmp___0~1#1); 3249#L690-2 [2022-11-16 12:02:06,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:06,665 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2022-11-16 12:02:06,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:06,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449581074] [2022-11-16 12:02:06,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:06,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:06,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:06,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:06,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:06,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449581074] [2022-11-16 12:02:06,703 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [449581074] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:06,703 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:06,704 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:02:06,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244743169] [2022-11-16 12:02:06,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:06,705 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:02:06,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:06,705 INFO L85 PathProgramCache]: Analyzing trace with hash -1819727935, now seen corresponding path program 1 times [2022-11-16 12:02:06,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:06,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51285652] [2022-11-16 12:02:06,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:06,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:06,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:06,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:06,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:06,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51285652] [2022-11-16 12:02:06,759 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51285652] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:06,759 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:06,759 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:06,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976521803] [2022-11-16 12:02:06,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:06,760 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:06,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:06,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:06,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:06,762 INFO L87 Difference]: Start difference. First operand 561 states and 834 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:06,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:06,812 INFO L93 Difference]: Finished difference Result 1031 states and 1507 transitions. [2022-11-16 12:02:06,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1031 states and 1507 transitions. [2022-11-16 12:02:06,819 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 967 [2022-11-16 12:02:06,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1031 states to 1031 states and 1507 transitions. [2022-11-16 12:02:06,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1031 [2022-11-16 12:02:06,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1031 [2022-11-16 12:02:06,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1031 states and 1507 transitions. [2022-11-16 12:02:06,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:06,828 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1031 states and 1507 transitions. [2022-11-16 12:02:06,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1031 states and 1507 transitions. [2022-11-16 12:02:06,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1031 to 977. [2022-11-16 12:02:06,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 977 states, 977 states have (on average 1.4667349027635619) internal successors, (1433), 976 states have internal predecessors, (1433), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:06,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 977 states to 977 states and 1433 transitions. [2022-11-16 12:02:06,849 INFO L240 hiAutomatonCegarLoop]: Abstraction has 977 states and 1433 transitions. [2022-11-16 12:02:06,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:06,850 INFO L428 stractBuchiCegarLoop]: Abstraction has 977 states and 1433 transitions. [2022-11-16 12:02:06,850 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 12:02:06,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 977 states and 1433 transitions. [2022-11-16 12:02:06,855 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 913 [2022-11-16 12:02:06,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:06,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:06,857 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:06,857 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:06,857 INFO L748 eck$LassoCheckResult]: Stem: 4830#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 4778#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4603#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4570#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4571#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 4680#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4528#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4529#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4701#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4540#L441 assume !(0 == ~M_E~0); 4541#L441-2 assume !(0 == ~T1_E~0); 4674#L446-1 assume !(0 == ~T2_E~0); 4646#L451-1 assume !(0 == ~T3_E~0); 4647#L456-1 assume !(0 == ~E_M~0); 4786#L461-1 assume !(0 == ~E_1~0); 4787#L466-1 assume !(0 == ~E_2~0); 4803#L471-1 assume !(0 == ~E_3~0); 4578#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4579#L220 assume !(1 == ~m_pc~0); 4611#L220-2 is_master_triggered_~__retres1~0#1 := 0; 4612#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4662#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4607#L543 assume !(0 != activate_threads_~tmp~1#1); 4608#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4765#L239 assume !(1 == ~t1_pc~0); 4763#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4764#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4807#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4767#L551 assume !(0 != activate_threads_~tmp___0~0#1); 4768#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4769#L258 assume 1 == ~t2_pc~0; 4770#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4639#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4497#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4498#L559 assume !(0 != activate_threads_~tmp___1~0#1); 4688#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4689#L277 assume !(1 == ~t3_pc~0); 4737#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4554#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4555#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4601#L567 assume !(0 != activate_threads_~tmp___2~0#1); 4602#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4643#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 4783#L489-2 assume !(1 == ~T1_E~0); 4784#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4721#L499-1 assume !(1 == ~T3_E~0); 5048#L504-1 assume !(1 == ~E_M~0); 5043#L509-1 assume !(1 == ~E_1~0); 5033#L514-1 assume !(1 == ~E_2~0); 5029#L519-1 assume !(1 == ~E_3~0); 5019#L524-1 assume { :end_inline_reset_delta_events } true; 5012#L690-2 [2022-11-16 12:02:06,858 INFO L750 eck$LassoCheckResult]: Loop: 5012#L690-2 assume !false; 5006#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5001#L416 assume !false; 5000#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4998#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4995#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4994#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4992#L369 assume !(0 != eval_~tmp~0#1); 4991#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4989#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4986#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4987#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5187#L446-3 assume !(0 == ~T2_E~0); 5186#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5185#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5184#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5183#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5182#L471-3 assume !(0 == ~E_3~0); 5181#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5180#L220-15 assume !(1 == ~m_pc~0); 5179#L220-17 is_master_triggered_~__retres1~0#1 := 0; 5178#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5177#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5176#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5175#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4959#L239-15 assume 1 == ~t1_pc~0; 4955#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4953#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4951#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4949#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 4946#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4947#L258-15 assume 1 == ~t2_pc~0; 4941#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4940#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4937#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4935#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4932#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4933#L277-15 assume !(1 == ~t3_pc~0); 4925#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 4923#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4920#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4917#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4918#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4911#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4912#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5156#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4903#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4904#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4897#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4898#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4887#L519-3 assume !(1 == ~E_3~0); 4888#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4879#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4877#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4861#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4862#L709 assume !(0 == start_simulation_~tmp~3#1); 5074#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5069#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5063#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5057#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5053#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5047#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5034#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5020#L722 assume !(0 != start_simulation_~tmp___0~1#1); 5012#L690-2 [2022-11-16 12:02:06,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:06,858 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2022-11-16 12:02:06,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:06,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [191376527] [2022-11-16 12:02:06,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:06,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:06,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:06,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:06,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:06,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [191376527] [2022-11-16 12:02:06,924 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [191376527] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:06,924 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:06,924 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:06,925 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427909990] [2022-11-16 12:02:06,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:06,925 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:02:06,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:06,926 INFO L85 PathProgramCache]: Analyzing trace with hash -862799552, now seen corresponding path program 1 times [2022-11-16 12:02:06,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:06,927 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983053672] [2022-11-16 12:02:06,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:06,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:06,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:07,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:07,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:07,034 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983053672] [2022-11-16 12:02:07,040 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983053672] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:07,041 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:07,041 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:07,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36666257] [2022-11-16 12:02:07,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:07,042 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:07,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:07,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:02:07,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:02:07,044 INFO L87 Difference]: Start difference. First operand 977 states and 1433 transitions. cyclomatic complexity: 460 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:07,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:07,219 INFO L93 Difference]: Finished difference Result 2207 states and 3186 transitions. [2022-11-16 12:02:07,219 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2207 states and 3186 transitions. [2022-11-16 12:02:07,233 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2074 [2022-11-16 12:02:07,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2207 states to 2207 states and 3186 transitions. [2022-11-16 12:02:07,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2207 [2022-11-16 12:02:07,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2207 [2022-11-16 12:02:07,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2207 states and 3186 transitions. [2022-11-16 12:02:07,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:07,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2207 states and 3186 transitions. [2022-11-16 12:02:07,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2207 states and 3186 transitions. [2022-11-16 12:02:07,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2207 to 1745. [2022-11-16 12:02:07,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1745 states, 1745 states have (on average 1.4573065902578797) internal successors, (2543), 1744 states have internal predecessors, (2543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:07,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1745 states to 1745 states and 2543 transitions. [2022-11-16 12:02:07,288 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1745 states and 2543 transitions. [2022-11-16 12:02:07,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:02:07,291 INFO L428 stractBuchiCegarLoop]: Abstraction has 1745 states and 2543 transitions. [2022-11-16 12:02:07,291 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 12:02:07,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1745 states and 2543 transitions. [2022-11-16 12:02:07,301 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1680 [2022-11-16 12:02:07,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:07,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:07,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:07,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:07,303 INFO L748 eck$LassoCheckResult]: Stem: 8054#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 7990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7798#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7765#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7766#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 7881#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7721#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7722#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7904#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7735#L441 assume !(0 == ~M_E~0); 7736#L441-2 assume !(0 == ~T1_E~0); 7875#L446-1 assume !(0 == ~T2_E~0); 7844#L451-1 assume !(0 == ~T3_E~0); 7845#L456-1 assume !(0 == ~E_M~0); 7997#L461-1 assume !(0 == ~E_1~0); 7998#L466-1 assume !(0 == ~E_2~0); 8017#L471-1 assume !(0 == ~E_3~0); 7773#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7774#L220 assume !(1 == ~m_pc~0); 7806#L220-2 is_master_triggered_~__retres1~0#1 := 0; 7807#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7859#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7802#L543 assume !(0 != activate_threads_~tmp~1#1); 7803#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7976#L239 assume !(1 == ~t1_pc~0); 7974#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7975#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8021#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7979#L551 assume !(0 != activate_threads_~tmp___0~0#1); 7980#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7981#L258 assume !(1 == ~t2_pc~0); 7982#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7835#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7693#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7694#L559 assume !(0 != activate_threads_~tmp___1~0#1); 7890#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7891#L277 assume !(1 == ~t3_pc~0); 7941#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7749#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7750#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7796#L567 assume !(0 != activate_threads_~tmp___2~0#1); 7797#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7841#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 7994#L489-2 assume !(1 == ~T1_E~0); 7995#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7785#L499-1 assume !(1 == ~T3_E~0); 7786#L504-1 assume !(1 == ~E_M~0); 8023#L509-1 assume !(1 == ~E_1~0); 8024#L514-1 assume !(1 == ~E_2~0); 7953#L519-1 assume !(1 == ~E_3~0); 7954#L524-1 assume { :end_inline_reset_delta_events } true; 9210#L690-2 [2022-11-16 12:02:07,303 INFO L750 eck$LassoCheckResult]: Loop: 9210#L690-2 assume !false; 9207#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9201#L416 assume !false; 9200#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9197#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8007#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7985#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7986#L369 assume !(0 != eval_~tmp~0#1); 9190#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9313#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9312#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9311#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9309#L446-3 assume !(0 == ~T2_E~0); 9307#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9305#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9303#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9301#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9299#L471-3 assume !(0 == ~E_3~0); 9297#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9294#L220-15 assume !(1 == ~m_pc~0); 9292#L220-17 is_master_triggered_~__retres1~0#1 := 0; 9290#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9288#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9286#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9284#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9283#L239-15 assume 1 == ~t1_pc~0; 9280#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9278#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9276#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9274#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 9272#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9269#L258-15 assume !(1 == ~t2_pc~0); 8660#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 9267#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9266#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9265#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9264#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9263#L277-15 assume !(1 == ~t3_pc~0); 9261#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 9260#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9259#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9258#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9257#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9256#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7726#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9255#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7991#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9254#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9253#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9251#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9249#L519-3 assume !(1 == ~E_3~0); 9247#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9243#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9239#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9237#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 9234#L709 assume !(0 == start_simulation_~tmp~3#1); 7952#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9229#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9225#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9223#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 9222#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9219#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9217#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 9213#L722 assume !(0 != start_simulation_~tmp___0~1#1); 9210#L690-2 [2022-11-16 12:02:07,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:07,303 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2022-11-16 12:02:07,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:07,304 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14758415] [2022-11-16 12:02:07,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:07,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:07,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:07,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:07,363 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:07,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14758415] [2022-11-16 12:02:07,363 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [14758415] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:07,364 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:07,364 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:02:07,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139389280] [2022-11-16 12:02:07,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:07,364 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:02:07,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:07,365 INFO L85 PathProgramCache]: Analyzing trace with hash 1855609985, now seen corresponding path program 1 times [2022-11-16 12:02:07,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:07,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800145327] [2022-11-16 12:02:07,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:07,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:07,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:07,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:07,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:07,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800145327] [2022-11-16 12:02:07,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800145327] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:07,428 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:07,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:07,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101509066] [2022-11-16 12:02:07,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:07,429 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:07,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:07,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:07,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:07,430 INFO L87 Difference]: Start difference. First operand 1745 states and 2543 transitions. cyclomatic complexity: 802 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:07,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:07,489 INFO L93 Difference]: Finished difference Result 2543 states and 3704 transitions. [2022-11-16 12:02:07,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2543 states and 3704 transitions. [2022-11-16 12:02:07,515 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2478 [2022-11-16 12:02:07,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2543 states to 2543 states and 3704 transitions. [2022-11-16 12:02:07,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2543 [2022-11-16 12:02:07,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2543 [2022-11-16 12:02:07,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2543 states and 3704 transitions. [2022-11-16 12:02:07,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:07,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2543 states and 3704 transitions. [2022-11-16 12:02:07,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2543 states and 3704 transitions. [2022-11-16 12:02:07,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2543 to 1769. [2022-11-16 12:02:07,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1769 states, 1769 states have (on average 1.4601469756924816) internal successors, (2583), 1768 states have internal predecessors, (2583), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:07,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1769 states to 1769 states and 2583 transitions. [2022-11-16 12:02:07,597 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1769 states and 2583 transitions. [2022-11-16 12:02:07,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:07,599 INFO L428 stractBuchiCegarLoop]: Abstraction has 1769 states and 2583 transitions. [2022-11-16 12:02:07,599 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 12:02:07,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1769 states and 2583 transitions. [2022-11-16 12:02:07,608 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1712 [2022-11-16 12:02:07,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:07,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:07,613 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:07,613 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:07,614 INFO L748 eck$LassoCheckResult]: Stem: 12340#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 12276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12095#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12061#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12062#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 12173#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12018#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12019#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12194#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12031#L441 assume !(0 == ~M_E~0); 12032#L441-2 assume !(0 == ~T1_E~0); 12167#L446-1 assume !(0 == ~T2_E~0); 12135#L451-1 assume !(0 == ~T3_E~0); 12136#L456-1 assume !(0 == ~E_M~0); 12280#L461-1 assume !(0 == ~E_1~0); 12281#L466-1 assume !(0 == ~E_2~0); 12299#L471-1 assume !(0 == ~E_3~0); 12069#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12070#L220 assume !(1 == ~m_pc~0); 12103#L220-2 is_master_triggered_~__retres1~0#1 := 0; 12104#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12152#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12099#L543 assume !(0 != activate_threads_~tmp~1#1); 12100#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12260#L239 assume !(1 == ~t1_pc~0); 12258#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12259#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12304#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12264#L551 assume !(0 != activate_threads_~tmp___0~0#1); 12265#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12266#L258 assume !(1 == ~t2_pc~0); 12267#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12128#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11990#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11991#L559 assume !(0 != activate_threads_~tmp___1~0#1); 12179#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12180#L277 assume !(1 == ~t3_pc~0); 12228#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12045#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12046#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12093#L567 assume !(0 != activate_threads_~tmp___2~0#1); 12094#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12132#L489 assume !(1 == ~M_E~0); 12279#L489-2 assume !(1 == ~T1_E~0); 12209#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12082#L499-1 assume !(1 == ~T3_E~0); 12083#L504-1 assume !(1 == ~E_M~0); 12174#L509-1 assume !(1 == ~E_1~0); 12071#L514-1 assume !(1 == ~E_2~0); 12072#L519-1 assume !(1 == ~E_3~0); 12079#L524-1 assume { :end_inline_reset_delta_events } true; 12080#L690-2 [2022-11-16 12:02:07,614 INFO L750 eck$LassoCheckResult]: Loop: 12080#L690-2 assume !false; 13594#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13587#L416 assume !false; 13582#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13580#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13577#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13575#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13572#L369 assume !(0 != eval_~tmp~0#1); 13573#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13728#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13727#L441-3 assume !(0 == ~M_E~0); 13726#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13725#L446-3 assume !(0 == ~T2_E~0); 13724#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13720#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12108#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12109#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12216#L471-3 assume !(0 == ~E_3~0); 12097#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12098#L220-15 assume !(1 == ~m_pc~0); 12153#L220-17 is_master_triggered_~__retres1~0#1 := 0; 13723#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13722#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13721#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12181#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12168#L239-15 assume !(1 == ~t1_pc~0); 12169#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 12305#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13628#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13545#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 12345#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12346#L258-15 assume !(1 == ~t2_pc~0); 12474#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 12471#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12468#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12465#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12462#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12458#L277-15 assume !(1 == ~t3_pc~0); 12453#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 12450#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12447#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12444#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12441#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12427#L489-3 assume !(1 == ~M_E~0); 12423#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12421#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12419#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12417#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12415#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12413#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12408#L519-3 assume !(1 == ~E_3~0); 12403#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12391#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12382#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12379#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 12374#L709 assume !(0 == start_simulation_~tmp~3#1); 12375#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13615#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13612#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13611#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 13610#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13608#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13606#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 13601#L722 assume !(0 != start_simulation_~tmp___0~1#1); 12080#L690-2 [2022-11-16 12:02:07,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:07,614 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2022-11-16 12:02:07,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:07,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217278678] [2022-11-16 12:02:07,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:07,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:07,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:07,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:07,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:07,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217278678] [2022-11-16 12:02:07,671 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217278678] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:07,674 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:07,674 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:07,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485023227] [2022-11-16 12:02:07,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:07,675 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:02:07,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:07,676 INFO L85 PathProgramCache]: Analyzing trace with hash -2097564862, now seen corresponding path program 1 times [2022-11-16 12:02:07,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:07,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083722699] [2022-11-16 12:02:07,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:07,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:07,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:07,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:07,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:07,735 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083722699] [2022-11-16 12:02:07,738 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083722699] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:07,738 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:07,738 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:07,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475000833] [2022-11-16 12:02:07,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:07,740 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:07,740 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:07,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:02:07,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:02:07,741 INFO L87 Difference]: Start difference. First operand 1769 states and 2583 transitions. cyclomatic complexity: 816 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:07,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:07,795 INFO L93 Difference]: Finished difference Result 2537 states and 3672 transitions. [2022-11-16 12:02:07,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2537 states and 3672 transitions. [2022-11-16 12:02:07,811 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2478 [2022-11-16 12:02:07,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2537 states to 2537 states and 3672 transitions. [2022-11-16 12:02:07,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2537 [2022-11-16 12:02:07,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2537 [2022-11-16 12:02:07,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2537 states and 3672 transitions. [2022-11-16 12:02:07,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:07,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2537 states and 3672 transitions. [2022-11-16 12:02:07,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2537 states and 3672 transitions. [2022-11-16 12:02:07,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2537 to 1769. [2022-11-16 12:02:07,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1769 states, 1769 states have (on average 1.4505370265686828) internal successors, (2566), 1768 states have internal predecessors, (2566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:07,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1769 states to 1769 states and 2566 transitions. [2022-11-16 12:02:07,870 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1769 states and 2566 transitions. [2022-11-16 12:02:07,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:02:07,874 INFO L428 stractBuchiCegarLoop]: Abstraction has 1769 states and 2566 transitions. [2022-11-16 12:02:07,874 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 12:02:07,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1769 states and 2566 transitions. [2022-11-16 12:02:07,885 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1712 [2022-11-16 12:02:07,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:07,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:07,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:07,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:07,887 INFO L748 eck$LassoCheckResult]: Stem: 16647#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 16594#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16414#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16380#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16381#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 16494#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16336#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16337#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16516#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16349#L441 assume !(0 == ~M_E~0); 16350#L441-2 assume !(0 == ~T1_E~0); 16488#L446-1 assume !(0 == ~T2_E~0); 16459#L451-1 assume !(0 == ~T3_E~0); 16460#L456-1 assume !(0 == ~E_M~0); 16597#L461-1 assume !(0 == ~E_1~0); 16598#L466-1 assume !(0 == ~E_2~0); 16617#L471-1 assume !(0 == ~E_3~0); 16389#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16390#L220 assume !(1 == ~m_pc~0); 16422#L220-2 is_master_triggered_~__retres1~0#1 := 0; 16423#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16474#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16418#L543 assume !(0 != activate_threads_~tmp~1#1); 16419#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16581#L239 assume !(1 == ~t1_pc~0); 16579#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16580#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16621#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16583#L551 assume !(0 != activate_threads_~tmp___0~0#1); 16584#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16585#L258 assume !(1 == ~t2_pc~0); 16586#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16450#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16308#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16309#L559 assume !(0 != activate_threads_~tmp___1~0#1); 16501#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16502#L277 assume !(1 == ~t3_pc~0); 16553#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16364#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16365#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16412#L567 assume !(0 != activate_threads_~tmp___2~0#1); 16413#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16456#L489 assume !(1 == ~M_E~0); 16596#L489-2 assume !(1 == ~T1_E~0); 16532#L494-1 assume !(1 == ~T2_E~0); 16401#L499-1 assume !(1 == ~T3_E~0); 16402#L504-1 assume !(1 == ~E_M~0); 16495#L509-1 assume !(1 == ~E_1~0); 16391#L514-1 assume !(1 == ~E_2~0); 16392#L519-1 assume !(1 == ~E_3~0); 16399#L524-1 assume { :end_inline_reset_delta_events } true; 16362#L690-2 [2022-11-16 12:02:07,887 INFO L750 eck$LassoCheckResult]: Loop: 16362#L690-2 assume !false; 16363#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16292#L416 assume !false; 16330#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16428#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16374#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16590#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16591#L369 assume !(0 != eval_~tmp~0#1); 16593#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16587#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16573#L441-3 assume !(0 == ~M_E~0); 16301#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16302#L446-3 assume !(0 == ~T2_E~0); 16569#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16359#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16360#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16427#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16539#L471-3 assume !(0 == ~E_3~0); 16416#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16417#L220-15 assume !(1 == ~m_pc~0); 16475#L220-17 is_master_triggered_~__retres1~0#1 := 0; 16544#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16342#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16343#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16503#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16489#L239-15 assume !(1 == ~t1_pc~0); 16490#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 16622#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16636#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16654#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 18014#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17837#L258-15 assume !(1 == ~t2_pc~0); 17835#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 17833#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17828#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17825#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17822#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17818#L277-15 assume !(1 == ~t3_pc~0); 17812#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 17810#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17806#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17803#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17798#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17707#L489-3 assume !(1 == ~M_E~0); 17137#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17705#L494-3 assume !(1 == ~T2_E~0); 17704#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17703#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17702#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17701#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17700#L519-3 assume !(1 == ~E_3~0); 17699#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17697#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17694#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17693#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 16533#L709 assume !(0 == start_simulation_~tmp~3#1); 16534#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 18005#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17941#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17940#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 17939#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17938#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17937#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 17936#L722 assume !(0 != start_simulation_~tmp___0~1#1); 16362#L690-2 [2022-11-16 12:02:07,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:07,888 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2022-11-16 12:02:07,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:07,888 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088979819] [2022-11-16 12:02:07,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:07,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:07,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:07,897 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:07,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:07,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:07,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:07,946 INFO L85 PathProgramCache]: Analyzing trace with hash 508458692, now seen corresponding path program 1 times [2022-11-16 12:02:07,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:07,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1603840161] [2022-11-16 12:02:07,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:07,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:07,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:07,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:07,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:07,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1603840161] [2022-11-16 12:02:07,997 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1603840161] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:07,997 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:07,997 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:07,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047370243] [2022-11-16 12:02:07,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:07,998 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:07,998 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:07,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:02:07,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:02:07,999 INFO L87 Difference]: Start difference. First operand 1769 states and 2566 transitions. cyclomatic complexity: 799 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:08,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:08,152 INFO L93 Difference]: Finished difference Result 3093 states and 4410 transitions. [2022-11-16 12:02:08,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3093 states and 4410 transitions. [2022-11-16 12:02:08,170 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3032 [2022-11-16 12:02:08,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3093 states to 3093 states and 4410 transitions. [2022-11-16 12:02:08,186 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3093 [2022-11-16 12:02:08,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3093 [2022-11-16 12:02:08,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3093 states and 4410 transitions. [2022-11-16 12:02:08,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:08,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3093 states and 4410 transitions. [2022-11-16 12:02:08,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3093 states and 4410 transitions. [2022-11-16 12:02:08,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3093 to 1793. [2022-11-16 12:02:08,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1793 states, 1793 states have (on average 1.4445064138315673) internal successors, (2590), 1792 states have internal predecessors, (2590), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:08,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1793 states to 1793 states and 2590 transitions. [2022-11-16 12:02:08,232 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1793 states and 2590 transitions. [2022-11-16 12:02:08,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 12:02:08,233 INFO L428 stractBuchiCegarLoop]: Abstraction has 1793 states and 2590 transitions. [2022-11-16 12:02:08,233 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 12:02:08,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1793 states and 2590 transitions. [2022-11-16 12:02:08,240 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1736 [2022-11-16 12:02:08,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:08,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:08,242 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:08,242 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:08,242 INFO L748 eck$LassoCheckResult]: Stem: 21522#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 21469#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21293#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21258#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21259#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 21375#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21214#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21215#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21396#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21227#L441 assume !(0 == ~M_E~0); 21228#L441-2 assume !(0 == ~T1_E~0); 21369#L446-1 assume !(0 == ~T2_E~0); 21338#L451-1 assume !(0 == ~T3_E~0); 21339#L456-1 assume !(0 == ~E_M~0); 21474#L461-1 assume !(0 == ~E_1~0); 21475#L466-1 assume !(0 == ~E_2~0); 21492#L471-1 assume !(0 == ~E_3~0); 21266#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21267#L220 assume !(1 == ~m_pc~0); 21301#L220-2 is_master_triggered_~__retres1~0#1 := 0; 21302#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21352#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21297#L543 assume !(0 != activate_threads_~tmp~1#1); 21298#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21457#L239 assume !(1 == ~t1_pc~0); 21455#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21456#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21495#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21460#L551 assume !(0 != activate_threads_~tmp___0~0#1); 21461#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21462#L258 assume !(1 == ~t2_pc~0); 21463#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21329#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21186#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21187#L559 assume !(0 != activate_threads_~tmp___1~0#1); 21381#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21382#L277 assume !(1 == ~t3_pc~0); 21426#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21241#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21242#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21291#L567 assume !(0 != activate_threads_~tmp___2~0#1); 21292#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21335#L489 assume !(1 == ~M_E~0); 21473#L489-2 assume !(1 == ~T1_E~0); 21409#L494-1 assume !(1 == ~T2_E~0); 21280#L499-1 assume !(1 == ~T3_E~0); 21281#L504-1 assume !(1 == ~E_M~0); 21376#L509-1 assume !(1 == ~E_1~0); 21268#L514-1 assume !(1 == ~E_2~0); 21269#L519-1 assume !(1 == ~E_3~0); 21277#L524-1 assume { :end_inline_reset_delta_events } true; 21278#L690-2 [2022-11-16 12:02:08,242 INFO L750 eck$LassoCheckResult]: Loop: 21278#L690-2 assume !false; 22150#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22144#L416 assume !false; 22104#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22100#L332 assume !(0 == ~m_st~0); 22101#L336 assume !(0 == ~t1_st~0); 22098#L340 assume !(0 == ~t2_st~0); 22099#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 22096#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22019#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22020#L369 assume !(0 != eval_~tmp~0#1); 22087#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22085#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22082#L441-3 assume !(0 == ~M_E~0); 22083#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22071#L446-3 assume !(0 == ~T2_E~0); 22072#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21588#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21589#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21566#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21567#L471-3 assume !(0 == ~E_3~0); 21295#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21296#L220-15 assume !(1 == ~m_pc~0); 21353#L220-17 is_master_triggered_~__retres1~0#1 := 0; 21420#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21220#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21221#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21383#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21370#L239-15 assume !(1 == ~t1_pc~0); 21371#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 21496#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21511#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21216#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 21217#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21526#L258-15 assume !(1 == ~t2_pc~0); 21527#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 22308#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22306#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22304#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22302#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22300#L277-15 assume !(1 == ~t3_pc~0); 22297#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 22294#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22292#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22290#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22288#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22286#L489-3 assume !(1 == ~M_E~0); 22283#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22282#L494-3 assume !(1 == ~T2_E~0); 22281#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22280#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22279#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22278#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22277#L519-3 assume !(1 == ~E_3~0); 22276#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22274#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22270#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22268#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 22265#L709 assume !(0 == start_simulation_~tmp~3#1); 22264#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22262#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22258#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22256#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 22159#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 22157#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22155#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 22153#L722 assume !(0 != start_simulation_~tmp___0~1#1); 21278#L690-2 [2022-11-16 12:02:08,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:08,243 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2022-11-16 12:02:08,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:08,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063287777] [2022-11-16 12:02:08,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:08,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:08,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:08,251 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:08,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:08,268 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:08,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:08,270 INFO L85 PathProgramCache]: Analyzing trace with hash -2116089398, now seen corresponding path program 1 times [2022-11-16 12:02:08,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:08,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983964922] [2022-11-16 12:02:08,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:08,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:08,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:08,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:08,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:08,332 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983964922] [2022-11-16 12:02:08,332 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983964922] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:08,334 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:08,335 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:08,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456457876] [2022-11-16 12:02:08,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:08,335 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:08,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:08,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:02:08,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:02:08,336 INFO L87 Difference]: Start difference. First operand 1793 states and 2590 transitions. cyclomatic complexity: 799 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:08,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:08,487 INFO L93 Difference]: Finished difference Result 5813 states and 8306 transitions. [2022-11-16 12:02:08,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5813 states and 8306 transitions. [2022-11-16 12:02:08,545 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5744 [2022-11-16 12:02:08,582 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5813 states to 5813 states and 8306 transitions. [2022-11-16 12:02:08,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5813 [2022-11-16 12:02:08,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5813 [2022-11-16 12:02:08,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5813 states and 8306 transitions. [2022-11-16 12:02:08,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:08,597 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5813 states and 8306 transitions. [2022-11-16 12:02:08,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5813 states and 8306 transitions. [2022-11-16 12:02:08,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5813 to 1817. [2022-11-16 12:02:08,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1817 states, 1817 states have (on average 1.4386351128233352) internal successors, (2614), 1816 states have internal predecessors, (2614), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:08,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1817 states to 1817 states and 2614 transitions. [2022-11-16 12:02:08,664 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1817 states and 2614 transitions. [2022-11-16 12:02:08,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 12:02:08,665 INFO L428 stractBuchiCegarLoop]: Abstraction has 1817 states and 2614 transitions. [2022-11-16 12:02:08,665 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 12:02:08,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1817 states and 2614 transitions. [2022-11-16 12:02:08,673 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1760 [2022-11-16 12:02:08,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:08,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:08,675 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:08,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:08,675 INFO L748 eck$LassoCheckResult]: Stem: 29148#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 29094#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 28916#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28881#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28882#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 28994#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28839#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28840#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29016#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28852#L441 assume !(0 == ~M_E~0); 28853#L441-2 assume !(0 == ~T1_E~0); 28988#L446-1 assume !(0 == ~T2_E~0); 28959#L451-1 assume !(0 == ~T3_E~0); 28960#L456-1 assume !(0 == ~E_M~0); 29097#L461-1 assume !(0 == ~E_1~0); 29098#L466-1 assume !(0 == ~E_2~0); 29114#L471-1 assume !(0 == ~E_3~0); 28889#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28890#L220 assume !(1 == ~m_pc~0); 28924#L220-2 is_master_triggered_~__retres1~0#1 := 0; 28925#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28975#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28922#L543 assume !(0 != activate_threads_~tmp~1#1); 28923#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29082#L239 assume !(1 == ~t1_pc~0); 29080#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29081#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29122#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29085#L551 assume !(0 != activate_threads_~tmp___0~0#1); 29086#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29087#L258 assume !(1 == ~t2_pc~0); 29088#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28952#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28809#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28810#L559 assume !(0 != activate_threads_~tmp___1~0#1); 29002#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29003#L277 assume !(1 == ~t3_pc~0); 29054#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28864#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28865#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28914#L567 assume !(0 != activate_threads_~tmp___2~0#1); 28915#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28956#L489 assume !(1 == ~M_E~0); 29096#L489-2 assume !(1 == ~T1_E~0); 29034#L494-1 assume !(1 == ~T2_E~0); 28905#L499-1 assume !(1 == ~T3_E~0); 28906#L504-1 assume !(1 == ~E_M~0); 28995#L509-1 assume !(1 == ~E_1~0); 28891#L514-1 assume !(1 == ~E_2~0); 28892#L519-1 assume !(1 == ~E_3~0); 28900#L524-1 assume { :end_inline_reset_delta_events } true; 28901#L690-2 [2022-11-16 12:02:08,676 INFO L750 eck$LassoCheckResult]: Loop: 28901#L690-2 assume !false; 29969#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29964#L416 assume !false; 29913#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 29911#L332 assume !(0 == ~m_st~0); 29912#L336 assume !(0 == ~t1_st~0); 29908#L340 assume !(0 == ~t2_st~0); 29910#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 29905#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 29901#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29902#L369 assume !(0 != eval_~tmp~0#1); 30029#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30366#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30365#L441-3 assume !(0 == ~M_E~0); 30364#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30363#L446-3 assume !(0 == ~T2_E~0); 30362#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28860#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28861#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30361#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30360#L471-3 assume !(0 == ~E_3~0); 30359#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30358#L220-15 assume !(1 == ~m_pc~0); 30357#L220-17 is_master_triggered_~__retres1~0#1 := 0; 30356#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30355#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30354#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30353#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30352#L239-15 assume 1 == ~t1_pc~0; 30349#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30346#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29155#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28837#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 28838#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29151#L258-15 assume !(1 == ~t2_pc~0); 29152#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 30341#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30339#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30337#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30335#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30333#L277-15 assume !(1 == ~t3_pc~0); 30330#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 30327#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30325#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30323#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30321#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30319#L489-3 assume !(1 == ~M_E~0); 30316#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30315#L494-3 assume !(1 == ~T2_E~0); 30314#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30313#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30312#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30311#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30310#L519-3 assume !(1 == ~E_3~0); 30309#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30307#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30289#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30282#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 30223#L709 assume !(0 == start_simulation_~tmp~3#1); 29983#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 29981#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 29978#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 29976#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 29974#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29972#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29971#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 29970#L722 assume !(0 != start_simulation_~tmp___0~1#1); 28901#L690-2 [2022-11-16 12:02:08,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:08,676 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2022-11-16 12:02:08,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:08,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127396639] [2022-11-16 12:02:08,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:08,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:08,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:08,689 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:08,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:08,713 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:08,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:08,714 INFO L85 PathProgramCache]: Analyzing trace with hash -1159220597, now seen corresponding path program 1 times [2022-11-16 12:02:08,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:08,714 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746043712] [2022-11-16 12:02:08,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:08,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:08,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:08,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:08,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:08,794 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746043712] [2022-11-16 12:02:08,794 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746043712] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:08,794 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:08,794 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:08,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896771248] [2022-11-16 12:02:08,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:08,795 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:08,795 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:08,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:02:08,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:02:08,796 INFO L87 Difference]: Start difference. First operand 1817 states and 2614 transitions. cyclomatic complexity: 799 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:08,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:08,956 INFO L93 Difference]: Finished difference Result 3499 states and 4974 transitions. [2022-11-16 12:02:08,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3499 states and 4974 transitions. [2022-11-16 12:02:08,976 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3412 [2022-11-16 12:02:08,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3499 states to 3499 states and 4974 transitions. [2022-11-16 12:02:08,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3499 [2022-11-16 12:02:08,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3499 [2022-11-16 12:02:08,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3499 states and 4974 transitions. [2022-11-16 12:02:08,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:08,997 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3499 states and 4974 transitions. [2022-11-16 12:02:09,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3499 states and 4974 transitions. [2022-11-16 12:02:09,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3499 to 1928. [2022-11-16 12:02:09,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4133817427385893) internal successors, (2725), 1927 states have internal predecessors, (2725), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:09,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2725 transitions. [2022-11-16 12:02:09,060 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2725 transitions. [2022-11-16 12:02:09,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-16 12:02:09,061 INFO L428 stractBuchiCegarLoop]: Abstraction has 1928 states and 2725 transitions. [2022-11-16 12:02:09,061 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 12:02:09,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2725 transitions. [2022-11-16 12:02:09,067 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1868 [2022-11-16 12:02:09,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:09,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:09,069 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:09,069 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:09,069 INFO L748 eck$LassoCheckResult]: Stem: 34509#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 34449#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 34247#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34213#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34214#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 34338#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34170#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34171#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34362#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34183#L441 assume !(0 == ~M_E~0); 34184#L441-2 assume !(0 == ~T1_E~0); 34330#L446-1 assume !(0 == ~T2_E~0); 34295#L451-1 assume !(0 == ~T3_E~0); 34296#L456-1 assume !(0 == ~E_M~0); 34454#L461-1 assume !(0 == ~E_1~0); 34455#L466-1 assume !(0 == ~E_2~0); 34472#L471-1 assume !(0 == ~E_3~0); 34221#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34222#L220 assume !(1 == ~m_pc~0); 34255#L220-2 is_master_triggered_~__retres1~0#1 := 0; 34256#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34312#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34253#L543 assume !(0 != activate_threads_~tmp~1#1); 34254#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34433#L239 assume !(1 == ~t1_pc~0); 34430#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34452#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34524#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34523#L551 assume !(0 != activate_threads_~tmp___0~0#1); 34439#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34440#L258 assume !(1 == ~t2_pc~0); 34441#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34284#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34139#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34140#L559 assume !(0 != activate_threads_~tmp___1~0#1); 34348#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34349#L277 assume !(1 == ~t3_pc~0); 34401#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34196#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34197#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34245#L567 assume !(0 != activate_threads_~tmp___2~0#1); 34246#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34290#L489 assume !(1 == ~M_E~0); 34453#L489-2 assume !(1 == ~T1_E~0); 34379#L494-1 assume !(1 == ~T2_E~0); 34234#L499-1 assume !(1 == ~T3_E~0); 34235#L504-1 assume !(1 == ~E_M~0); 34339#L509-1 assume !(1 == ~E_1~0); 34223#L514-1 assume !(1 == ~E_2~0); 34224#L519-1 assume !(1 == ~E_3~0); 34231#L524-1 assume { :end_inline_reset_delta_events } true; 34232#L690-2 [2022-11-16 12:02:09,069 INFO L750 eck$LassoCheckResult]: Loop: 34232#L690-2 assume !false; 35945#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34166#L416 assume !false; 34167#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 34261#L332 assume !(0 == ~m_st~0); 35941#L336 assume !(0 == ~t1_st~0); 35938#L340 assume !(0 == ~t2_st~0); 35939#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 35940#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 36005#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36002#L369 assume !(0 != eval_~tmp~0#1); 36003#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36045#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36044#L441-3 assume !(0 == ~M_E~0); 36043#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36042#L446-3 assume !(0 == ~T2_E~0); 36041#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36040#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36039#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36038#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36037#L471-3 assume !(0 == ~E_3~0); 36036#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34309#L220-15 assume !(1 == ~m_pc~0); 34310#L220-17 is_master_triggered_~__retres1~0#1 := 0; 34390#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36033#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36032#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36031#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34331#L239-15 assume !(1 == ~t1_pc~0); 34332#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 34496#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34497#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35942#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 34169#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34513#L258-15 assume !(1 == ~t2_pc~0); 34293#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 34294#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34334#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34335#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34456#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34457#L277-15 assume !(1 == ~t3_pc~0); 34144#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 34145#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34467#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34468#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34189#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34172#L489-3 assume !(1 == ~M_E~0); 34173#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36016#L494-3 assume !(1 == ~T2_E~0); 36015#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36014#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36013#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36012#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36011#L519-3 assume !(1 == ~E_3~0); 36010#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35996#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 35992#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 35990#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 35987#L709 assume !(0 == start_simulation_~tmp~3#1); 35982#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35975#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 34229#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34230#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 35964#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35960#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35958#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 35954#L722 assume !(0 != start_simulation_~tmp___0~1#1); 34232#L690-2 [2022-11-16 12:02:09,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:09,070 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2022-11-16 12:02:09,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:09,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895319803] [2022-11-16 12:02:09,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:09,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:09,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:09,078 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:09,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:09,090 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:09,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:09,091 INFO L85 PathProgramCache]: Analyzing trace with hash -2116148980, now seen corresponding path program 1 times [2022-11-16 12:02:09,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:09,091 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399478742] [2022-11-16 12:02:09,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:09,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:09,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:09,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:09,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:09,175 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399478742] [2022-11-16 12:02:09,175 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399478742] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:09,175 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:09,175 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:02:09,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575709511] [2022-11-16 12:02:09,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:09,175 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:09,176 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:09,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:02:09,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:02:09,176 INFO L87 Difference]: Start difference. First operand 1928 states and 2725 transitions. cyclomatic complexity: 799 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:09,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:09,341 INFO L93 Difference]: Finished difference Result 3806 states and 5342 transitions. [2022-11-16 12:02:09,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3806 states and 5342 transitions. [2022-11-16 12:02:09,358 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3746 [2022-11-16 12:02:09,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3806 states to 3806 states and 5342 transitions. [2022-11-16 12:02:09,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3806 [2022-11-16 12:02:09,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3806 [2022-11-16 12:02:09,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3806 states and 5342 transitions. [2022-11-16 12:02:09,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:09,381 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3806 states and 5342 transitions. [2022-11-16 12:02:09,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3806 states and 5342 transitions. [2022-11-16 12:02:09,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3806 to 1988. [2022-11-16 12:02:09,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1988 states, 1988 states have (on average 1.392354124748491) internal successors, (2768), 1987 states have internal predecessors, (2768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:09,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1988 states to 1988 states and 2768 transitions. [2022-11-16 12:02:09,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1988 states and 2768 transitions. [2022-11-16 12:02:09,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 12:02:09,427 INFO L428 stractBuchiCegarLoop]: Abstraction has 1988 states and 2768 transitions. [2022-11-16 12:02:09,427 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 12:02:09,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1988 states and 2768 transitions. [2022-11-16 12:02:09,433 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1928 [2022-11-16 12:02:09,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:09,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:09,434 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:09,434 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:09,435 INFO L748 eck$LassoCheckResult]: Stem: 40272#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 40200#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 39996#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39961#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39962#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 40083#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39915#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39916#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40106#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39928#L441 assume !(0 == ~M_E~0); 39929#L441-2 assume !(0 == ~T1_E~0); 40077#L446-1 assume !(0 == ~T2_E~0); 40042#L451-1 assume !(0 == ~T3_E~0); 40043#L456-1 assume !(0 == ~E_M~0); 40208#L461-1 assume !(0 == ~E_1~0); 40209#L466-1 assume !(0 == ~E_2~0); 40227#L471-1 assume !(0 == ~E_3~0); 39969#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39970#L220 assume !(1 == ~m_pc~0); 40004#L220-2 is_master_triggered_~__retres1~0#1 := 0; 40005#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40058#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40000#L543 assume !(0 != activate_threads_~tmp~1#1); 40001#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40183#L239 assume !(1 == ~t1_pc~0); 40180#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40205#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40286#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40285#L551 assume !(0 != activate_threads_~tmp___0~0#1); 40189#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40190#L258 assume !(1 == ~t2_pc~0); 40191#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40034#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39886#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39887#L559 assume !(0 != activate_threads_~tmp___1~0#1); 40091#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40092#L277 assume !(1 == ~t3_pc~0); 40145#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39943#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39944#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39994#L567 assume !(0 != activate_threads_~tmp___2~0#1); 39995#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40038#L489 assume !(1 == ~M_E~0); 40206#L489-2 assume !(1 == ~T1_E~0); 40122#L494-1 assume !(1 == ~T2_E~0); 39983#L499-1 assume !(1 == ~T3_E~0); 39984#L504-1 assume !(1 == ~E_M~0); 40084#L509-1 assume !(1 == ~E_1~0); 39971#L514-1 assume !(1 == ~E_2~0); 39972#L519-1 assume !(1 == ~E_3~0); 39979#L524-1 assume { :end_inline_reset_delta_events } true; 39980#L690-2 [2022-11-16 12:02:09,435 INFO L750 eck$LassoCheckResult]: Loop: 39980#L690-2 assume !false; 40492#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40486#L416 assume !false; 40484#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 40482#L332 assume !(0 == ~m_st~0); 40480#L336 assume !(0 == ~t1_st~0); 40476#L340 assume !(0 == ~t2_st~0); 40471#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 40473#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40663#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40461#L369 assume !(0 != eval_~tmp~0#1); 40459#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40457#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40455#L441-3 assume !(0 == ~M_E~0); 40453#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40452#L446-3 assume !(0 == ~T2_E~0); 40344#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40345#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40337#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40338#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40323#L471-3 assume !(0 == ~E_3~0); 40324#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40059#L220-15 assume !(1 == ~m_pc~0); 40060#L220-17 is_master_triggered_~__retres1~0#1 := 0; 40450#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40448#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40446#L543-15 assume !(0 != activate_threads_~tmp~1#1); 40444#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40442#L239-15 assume 1 == ~t1_pc~0; 40439#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40434#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40427#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40420#L551-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40419#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40410#L258-15 assume !(1 == ~t2_pc~0); 40408#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 40406#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40404#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40402#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40400#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40398#L277-15 assume !(1 == ~t3_pc~0); 40395#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 40392#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40390#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40388#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40386#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40384#L489-3 assume !(1 == ~M_E~0); 40383#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40378#L494-3 assume !(1 == ~T2_E~0); 40379#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40375#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40374#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40373#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40371#L519-3 assume !(1 == ~E_3~0); 40372#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 40367#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 40365#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40799#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 40796#L709 assume !(0 == start_simulation_~tmp~3#1); 40795#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 40792#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 40788#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40786#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 40784#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40781#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40779#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 40777#L722 assume !(0 != start_simulation_~tmp___0~1#1); 39980#L690-2 [2022-11-16 12:02:09,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:09,436 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 5 times [2022-11-16 12:02:09,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:09,436 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186691545] [2022-11-16 12:02:09,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:09,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:09,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:09,444 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:09,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:09,456 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:09,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:09,457 INFO L85 PathProgramCache]: Analyzing trace with hash 108431627, now seen corresponding path program 1 times [2022-11-16 12:02:09,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:09,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824824425] [2022-11-16 12:02:09,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:09,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:09,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:09,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:09,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:09,487 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824824425] [2022-11-16 12:02:09,487 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824824425] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:09,487 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:09,488 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:09,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089316689] [2022-11-16 12:02:09,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:09,488 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:02:09,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:09,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:09,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:09,489 INFO L87 Difference]: Start difference. First operand 1988 states and 2768 transitions. cyclomatic complexity: 782 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:09,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:09,557 INFO L93 Difference]: Finished difference Result 3054 states and 4184 transitions. [2022-11-16 12:02:09,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3054 states and 4184 transitions. [2022-11-16 12:02:09,569 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2994 [2022-11-16 12:02:09,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3054 states to 3054 states and 4184 transitions. [2022-11-16 12:02:09,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3054 [2022-11-16 12:02:09,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3054 [2022-11-16 12:02:09,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3054 states and 4184 transitions. [2022-11-16 12:02:09,584 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:09,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3054 states and 4184 transitions. [2022-11-16 12:02:09,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3054 states and 4184 transitions. [2022-11-16 12:02:09,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3054 to 2952. [2022-11-16 12:02:09,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2952 states, 2952 states have (on average 1.3719512195121952) internal successors, (4050), 2951 states have internal predecessors, (4050), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:09,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2952 states to 2952 states and 4050 transitions. [2022-11-16 12:02:09,631 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2952 states and 4050 transitions. [2022-11-16 12:02:09,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:09,632 INFO L428 stractBuchiCegarLoop]: Abstraction has 2952 states and 4050 transitions. [2022-11-16 12:02:09,632 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 12:02:09,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2952 states and 4050 transitions. [2022-11-16 12:02:09,642 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2892 [2022-11-16 12:02:09,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:09,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:09,643 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:09,643 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:09,643 INFO L748 eck$LassoCheckResult]: Stem: 45295#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 45237#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 45040#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45006#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45007#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 45125#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44962#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44963#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45148#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44975#L441 assume !(0 == ~M_E~0); 44976#L441-2 assume !(0 == ~T1_E~0); 45119#L446-1 assume !(0 == ~T2_E~0); 45083#L451-1 assume !(0 == ~T3_E~0); 45084#L456-1 assume !(0 == ~E_M~0); 45244#L461-1 assume !(0 == ~E_1~0); 45245#L466-1 assume !(0 == ~E_2~0); 45264#L471-1 assume !(0 == ~E_3~0); 45014#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45015#L220 assume !(1 == ~m_pc~0); 45048#L220-2 is_master_triggered_~__retres1~0#1 := 0; 45049#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45099#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45044#L543 assume !(0 != activate_threads_~tmp~1#1); 45045#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45222#L239 assume !(1 == ~t1_pc~0); 45219#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45240#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45304#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45303#L551 assume !(0 != activate_threads_~tmp___0~0#1); 45226#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45227#L258 assume !(1 == ~t2_pc~0); 45228#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45075#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44934#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44935#L559 assume !(0 != activate_threads_~tmp___1~0#1); 45133#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45134#L277 assume !(1 == ~t3_pc~0); 45186#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44989#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44990#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45038#L567 assume !(0 != activate_threads_~tmp___2~0#1); 45039#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45079#L489 assume !(1 == ~M_E~0); 45241#L489-2 assume !(1 == ~T1_E~0); 45166#L494-1 assume !(1 == ~T2_E~0); 45027#L499-1 assume !(1 == ~T3_E~0); 45028#L504-1 assume !(1 == ~E_M~0); 45126#L509-1 assume !(1 == ~E_1~0); 45016#L514-1 assume !(1 == ~E_2~0); 45017#L519-1 assume !(1 == ~E_3~0); 45023#L524-1 assume { :end_inline_reset_delta_events } true; 45024#L690-2 assume !false; 45947#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45943#L416 [2022-11-16 12:02:09,644 INFO L750 eck$LassoCheckResult]: Loop: 45943#L416 assume !false; 45937#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 45938#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 45997#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 45996#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 45994#L369 assume 0 != eval_~tmp~0#1; 45989#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 45987#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 45988#L374 assume !(0 == ~t1_st~0); 46003#L388 assume !(0 == ~t2_st~0); 45946#L402 assume !(0 == ~t3_st~0); 45943#L416 [2022-11-16 12:02:09,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:09,644 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2022-11-16 12:02:09,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:09,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175167537] [2022-11-16 12:02:09,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:09,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:09,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:09,652 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:09,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:09,664 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:09,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:09,665 INFO L85 PathProgramCache]: Analyzing trace with hash 258292880, now seen corresponding path program 1 times [2022-11-16 12:02:09,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:09,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142342] [2022-11-16 12:02:09,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:09,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:09,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:09,669 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:09,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:09,672 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:09,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:09,673 INFO L85 PathProgramCache]: Analyzing trace with hash 1139971210, now seen corresponding path program 1 times [2022-11-16 12:02:09,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:09,673 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31853284] [2022-11-16 12:02:09,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:09,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:09,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:09,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:09,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:09,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31853284] [2022-11-16 12:02:09,707 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [31853284] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:09,707 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:09,707 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:09,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500261670] [2022-11-16 12:02:09,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:09,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:09,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:09,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:09,790 INFO L87 Difference]: Start difference. First operand 2952 states and 4050 transitions. cyclomatic complexity: 1101 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:09,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:09,852 INFO L93 Difference]: Finished difference Result 5226 states and 7111 transitions. [2022-11-16 12:02:09,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5226 states and 7111 transitions. [2022-11-16 12:02:09,874 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5112 [2022-11-16 12:02:09,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5226 states to 5226 states and 7111 transitions. [2022-11-16 12:02:09,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5226 [2022-11-16 12:02:09,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5226 [2022-11-16 12:02:09,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5226 states and 7111 transitions. [2022-11-16 12:02:09,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:09,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5226 states and 7111 transitions. [2022-11-16 12:02:09,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5226 states and 7111 transitions. [2022-11-16 12:02:10,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5226 to 4885. [2022-11-16 12:02:10,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4885 states, 4885 states have (on average 1.3715455475946776) internal successors, (6700), 4884 states have internal predecessors, (6700), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:10,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4885 states to 4885 states and 6700 transitions. [2022-11-16 12:02:10,033 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4885 states and 6700 transitions. [2022-11-16 12:02:10,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:10,034 INFO L428 stractBuchiCegarLoop]: Abstraction has 4885 states and 6700 transitions. [2022-11-16 12:02:10,034 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 12:02:10,035 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4885 states and 6700 transitions. [2022-11-16 12:02:10,051 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4774 [2022-11-16 12:02:10,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:10,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:10,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:10,052 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:10,052 INFO L748 eck$LassoCheckResult]: Stem: 53554#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 53454#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 53227#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53193#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53194#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 53319#L304-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 53150#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53151#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53343#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53344#L441 assume !(0 == ~M_E~0); 53311#L441-2 assume !(0 == ~T1_E~0); 53312#L446-1 assume !(0 == ~T2_E~0); 53277#L451-1 assume !(0 == ~T3_E~0); 53278#L456-1 assume !(0 == ~E_M~0); 53467#L461-1 assume !(0 == ~E_1~0); 53468#L466-1 assume !(0 == ~E_2~0); 53540#L471-1 assume !(0 == ~E_3~0); 53541#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53267#L220 assume !(1 == ~m_pc~0); 53268#L220-2 is_master_triggered_~__retres1~0#1 := 0; 53294#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53295#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53233#L543 assume !(0 != activate_threads_~tmp~1#1); 53234#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53433#L239 assume !(1 == ~t1_pc~0); 53429#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53575#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53576#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53571#L551 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53440#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53441#L258 assume !(1 == ~t2_pc~0); 53442#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53495#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53120#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53121#L559 assume !(0 != activate_threads_~tmp___1~0#1); 53329#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53330#L277 assume !(1 == ~t3_pc~0); 53406#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53405#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53448#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53449#L567 assume !(0 != activate_threads_~tmp___2~0#1); 53272#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53273#L489 assume !(1 == ~M_E~0); 53463#L489-2 assume !(1 == ~T1_E~0); 53464#L494-1 assume !(1 == ~T2_E~0); 53216#L499-1 assume !(1 == ~T3_E~0); 53217#L504-1 assume !(1 == ~E_M~0); 53508#L509-1 assume !(1 == ~E_1~0); 53509#L514-1 assume !(1 == ~E_2~0); 53400#L519-1 assume !(1 == ~E_3~0); 53210#L524-1 assume { :end_inline_reset_delta_events } true; 53211#L690-2 assume !false; 56437#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56431#L416 [2022-11-16 12:02:10,053 INFO L750 eck$LassoCheckResult]: Loop: 56431#L416 assume !false; 56428#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 56424#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 56421#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 56419#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 56417#L369 assume 0 != eval_~tmp~0#1; 56414#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 56410#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 56411#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 56216#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 56445#L388 assume !(0 == ~t2_st~0); 56436#L402 assume !(0 == ~t3_st~0); 56431#L416 [2022-11-16 12:02:10,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:10,053 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2022-11-16 12:02:10,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:10,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178188527] [2022-11-16 12:02:10,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:10,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:10,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:10,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:10,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:10,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178188527] [2022-11-16 12:02:10,076 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178188527] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:10,076 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:10,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:10,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005953881] [2022-11-16 12:02:10,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:10,076 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:02:10,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:10,077 INFO L85 PathProgramCache]: Analyzing trace with hash -586893878, now seen corresponding path program 1 times [2022-11-16 12:02:10,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:10,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595884888] [2022-11-16 12:02:10,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:10,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:10,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:10,081 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:10,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:10,084 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:10,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:10,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:10,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:10,190 INFO L87 Difference]: Start difference. First operand 4885 states and 6700 transitions. cyclomatic complexity: 1818 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:10,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:10,211 INFO L93 Difference]: Finished difference Result 4836 states and 6631 transitions. [2022-11-16 12:02:10,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4836 states and 6631 transitions. [2022-11-16 12:02:10,231 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4774 [2022-11-16 12:02:10,247 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4836 states to 4836 states and 6631 transitions. [2022-11-16 12:02:10,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4836 [2022-11-16 12:02:10,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4836 [2022-11-16 12:02:10,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4836 states and 6631 transitions. [2022-11-16 12:02:10,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:10,255 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4836 states and 6631 transitions. [2022-11-16 12:02:10,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4836 states and 6631 transitions. [2022-11-16 12:02:10,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4836 to 4836. [2022-11-16 12:02:10,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4836 states, 4836 states have (on average 1.3711745244003308) internal successors, (6631), 4835 states have internal predecessors, (6631), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:10,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4836 states to 4836 states and 6631 transitions. [2022-11-16 12:02:10,383 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4836 states and 6631 transitions. [2022-11-16 12:02:10,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:10,384 INFO L428 stractBuchiCegarLoop]: Abstraction has 4836 states and 6631 transitions. [2022-11-16 12:02:10,384 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 12:02:10,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4836 states and 6631 transitions. [2022-11-16 12:02:10,403 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4774 [2022-11-16 12:02:10,403 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:10,403 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:10,404 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:10,404 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:10,405 INFO L748 eck$LassoCheckResult]: Stem: 63209#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 63150#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 62954#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62920#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62921#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 63044#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62876#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62877#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63067#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62889#L441 assume !(0 == ~M_E~0); 62890#L441-2 assume !(0 == ~T1_E~0); 63038#L446-1 assume !(0 == ~T2_E~0); 63003#L451-1 assume !(0 == ~T3_E~0); 63004#L456-1 assume !(0 == ~E_M~0); 63155#L461-1 assume !(0 == ~E_1~0); 63156#L466-1 assume !(0 == ~E_2~0); 63174#L471-1 assume !(0 == ~E_3~0); 62928#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62929#L220 assume !(1 == ~m_pc~0); 62962#L220-2 is_master_triggered_~__retres1~0#1 := 0; 62963#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63017#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 62958#L543 assume !(0 != activate_threads_~tmp~1#1); 62959#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63135#L239 assume !(1 == ~t1_pc~0); 63133#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63153#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63214#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 63213#L551 assume !(0 != activate_threads_~tmp___0~0#1); 63139#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63140#L258 assume !(1 == ~t2_pc~0); 63141#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62993#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62847#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 62848#L559 assume !(0 != activate_threads_~tmp___1~0#1); 63052#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63053#L277 assume !(1 == ~t3_pc~0); 63102#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62903#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62904#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 62952#L567 assume !(0 != activate_threads_~tmp___2~0#1); 62953#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62999#L489 assume !(1 == ~M_E~0); 63154#L489-2 assume !(1 == ~T1_E~0); 63084#L494-1 assume !(1 == ~T2_E~0); 62941#L499-1 assume !(1 == ~T3_E~0); 62942#L504-1 assume !(1 == ~E_M~0); 63045#L509-1 assume !(1 == ~E_1~0); 62930#L514-1 assume !(1 == ~E_2~0); 62931#L519-1 assume !(1 == ~E_3~0); 62937#L524-1 assume { :end_inline_reset_delta_events } true; 62938#L690-2 assume !false; 64710#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64705#L416 [2022-11-16 12:02:10,405 INFO L750 eck$LassoCheckResult]: Loop: 64705#L416 assume !false; 64703#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 64700#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 64698#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 64695#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 64693#L369 assume 0 != eval_~tmp~0#1; 64691#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 64689#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 64686#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 64253#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 64684#L388 assume !(0 == ~t2_st~0); 64682#L402 assume !(0 == ~t3_st~0); 64705#L416 [2022-11-16 12:02:10,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:10,406 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2022-11-16 12:02:10,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:10,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677931728] [2022-11-16 12:02:10,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:10,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:10,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:10,416 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:10,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:10,431 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:10,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:10,432 INFO L85 PathProgramCache]: Analyzing trace with hash -586893878, now seen corresponding path program 2 times [2022-11-16 12:02:10,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:10,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817018803] [2022-11-16 12:02:10,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:10,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:10,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:10,439 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:10,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:10,443 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:10,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:10,445 INFO L85 PathProgramCache]: Analyzing trace with hash 975330576, now seen corresponding path program 1 times [2022-11-16 12:02:10,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:10,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508940164] [2022-11-16 12:02:10,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:10,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:10,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:10,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:10,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:10,489 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508940164] [2022-11-16 12:02:10,489 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508940164] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:10,489 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:10,489 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:02:10,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197048736] [2022-11-16 12:02:10,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:10,606 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:10,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:10,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:10,607 INFO L87 Difference]: Start difference. First operand 4836 states and 6631 transitions. cyclomatic complexity: 1798 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:10,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:10,681 INFO L93 Difference]: Finished difference Result 8691 states and 11844 transitions. [2022-11-16 12:02:10,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8691 states and 11844 transitions. [2022-11-16 12:02:10,724 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8625 [2022-11-16 12:02:10,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8691 states to 8691 states and 11844 transitions. [2022-11-16 12:02:10,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8691 [2022-11-16 12:02:10,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8691 [2022-11-16 12:02:10,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8691 states and 11844 transitions. [2022-11-16 12:02:10,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:10,773 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8691 states and 11844 transitions. [2022-11-16 12:02:10,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8691 states and 11844 transitions. [2022-11-16 12:02:10,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8691 to 8537. [2022-11-16 12:02:10,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8537 states, 8537 states have (on average 1.3644137284760454) internal successors, (11648), 8536 states have internal predecessors, (11648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:11,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8537 states to 8537 states and 11648 transitions. [2022-11-16 12:02:11,014 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8537 states and 11648 transitions. [2022-11-16 12:02:11,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:11,015 INFO L428 stractBuchiCegarLoop]: Abstraction has 8537 states and 11648 transitions. [2022-11-16 12:02:11,015 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 12:02:11,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8537 states and 11648 transitions. [2022-11-16 12:02:11,042 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8471 [2022-11-16 12:02:11,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:11,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:11,043 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:11,043 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:11,043 INFO L748 eck$LassoCheckResult]: Stem: 76764#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 76690#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 76490#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76455#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76456#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 76578#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76411#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76412#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76601#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76423#L441 assume !(0 == ~M_E~0); 76424#L441-2 assume !(0 == ~T1_E~0); 76572#L446-1 assume !(0 == ~T2_E~0); 76536#L451-1 assume !(0 == ~T3_E~0); 76537#L456-1 assume !(0 == ~E_M~0); 76697#L461-1 assume !(0 == ~E_1~0); 76698#L466-1 assume !(0 == ~E_2~0); 76717#L471-1 assume !(0 == ~E_3~0); 76463#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76464#L220 assume !(1 == ~m_pc~0); 76498#L220-2 is_master_triggered_~__retres1~0#1 := 0; 76499#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76551#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 76494#L543 assume !(0 != activate_threads_~tmp~1#1); 76495#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76675#L239 assume !(1 == ~t1_pc~0); 76670#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76695#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76777#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 76776#L551 assume !(0 != activate_threads_~tmp___0~0#1); 76681#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76682#L258 assume !(1 == ~t2_pc~0); 76683#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76527#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76382#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76383#L559 assume !(0 != activate_threads_~tmp___1~0#1); 76586#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76587#L277 assume !(1 == ~t3_pc~0); 76639#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76438#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76439#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76488#L567 assume !(0 != activate_threads_~tmp___2~0#1); 76489#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76532#L489 assume !(1 == ~M_E~0); 76696#L489-2 assume !(1 == ~T1_E~0); 76620#L494-1 assume !(1 == ~T2_E~0); 76477#L499-1 assume !(1 == ~T3_E~0); 76478#L504-1 assume !(1 == ~E_M~0); 76579#L509-1 assume !(1 == ~E_1~0); 76465#L514-1 assume !(1 == ~E_2~0); 76466#L519-1 assume !(1 == ~E_3~0); 76473#L524-1 assume { :end_inline_reset_delta_events } true; 76474#L690-2 assume !false; 79209#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 79203#L416 [2022-11-16 12:02:11,044 INFO L750 eck$LassoCheckResult]: Loop: 79203#L416 assume !false; 79191#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 79185#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 79180#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 79154#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 79146#L369 assume 0 != eval_~tmp~0#1; 79138#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 79130#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 79122#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 79036#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 79037#L388 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 78898#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 79032#L402 assume !(0 == ~t3_st~0); 79203#L416 [2022-11-16 12:02:11,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:11,044 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2022-11-16 12:02:11,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:11,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162819766] [2022-11-16 12:02:11,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:11,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:11,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:11,053 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:11,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:11,066 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:11,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:11,067 INFO L85 PathProgramCache]: Analyzing trace with hash -1013970345, now seen corresponding path program 1 times [2022-11-16 12:02:11,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:11,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033915761] [2022-11-16 12:02:11,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:11,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:11,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:11,072 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:11,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:11,077 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:11,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:11,078 INFO L85 PathProgramCache]: Analyzing trace with hash 170347473, now seen corresponding path program 1 times [2022-11-16 12:02:11,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:11,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227344071] [2022-11-16 12:02:11,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:11,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:11,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:02:11,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:02:11,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:02:11,110 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227344071] [2022-11-16 12:02:11,110 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227344071] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:02:11,110 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:02:11,111 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:02:11,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666577169] [2022-11-16 12:02:11,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:02:11,322 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:02:11,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:02:11,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:02:11,323 INFO L87 Difference]: Start difference. First operand 8537 states and 11648 transitions. cyclomatic complexity: 3114 Second operand has 3 states, 2 states have (on average 33.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:11,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:02:11,407 INFO L93 Difference]: Finished difference Result 14244 states and 19347 transitions. [2022-11-16 12:02:11,407 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14244 states and 19347 transitions. [2022-11-16 12:02:11,468 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14170 [2022-11-16 12:02:11,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14244 states to 14244 states and 19347 transitions. [2022-11-16 12:02:11,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14244 [2022-11-16 12:02:11,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14244 [2022-11-16 12:02:11,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14244 states and 19347 transitions. [2022-11-16 12:02:11,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:02:11,544 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14244 states and 19347 transitions. [2022-11-16 12:02:11,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14244 states and 19347 transitions. [2022-11-16 12:02:11,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14244 to 14020. [2022-11-16 12:02:11,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14020 states, 14020 states have (on average 1.3639800285306705) internal successors, (19123), 14019 states have internal predecessors, (19123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:02:11,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14020 states to 14020 states and 19123 transitions. [2022-11-16 12:02:11,961 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14020 states and 19123 transitions. [2022-11-16 12:02:11,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:02:11,962 INFO L428 stractBuchiCegarLoop]: Abstraction has 14020 states and 19123 transitions. [2022-11-16 12:02:11,962 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 12:02:11,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14020 states and 19123 transitions. [2022-11-16 12:02:12,058 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13946 [2022-11-16 12:02:12,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:02:12,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:02:12,060 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:12,060 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:02:12,060 INFO L748 eck$LassoCheckResult]: Stem: 99549#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~token~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 99482#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 99278#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 99244#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 99245#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 99369#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 99201#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 99202#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 99393#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 99213#L441 assume !(0 == ~M_E~0); 99214#L441-2 assume !(0 == ~T1_E~0); 99363#L446-1 assume !(0 == ~T2_E~0); 99326#L451-1 assume !(0 == ~T3_E~0); 99327#L456-1 assume !(0 == ~E_M~0); 99486#L461-1 assume !(0 == ~E_1~0); 99487#L466-1 assume !(0 == ~E_2~0); 99507#L471-1 assume !(0 == ~E_3~0); 99252#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99253#L220 assume !(1 == ~m_pc~0); 99286#L220-2 is_master_triggered_~__retres1~0#1 := 0; 99287#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99341#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 99282#L543 assume !(0 != activate_threads_~tmp~1#1); 99283#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99465#L239 assume !(1 == ~t1_pc~0); 99461#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 99484#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99564#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 99563#L551 assume !(0 != activate_threads_~tmp___0~0#1); 99470#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99471#L258 assume !(1 == ~t2_pc~0); 99472#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 99317#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99172#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 99173#L559 assume !(0 != activate_threads_~tmp___1~0#1); 99378#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99379#L277 assume !(1 == ~t3_pc~0); 99430#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 99228#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99229#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 99276#L567 assume !(0 != activate_threads_~tmp___2~0#1); 99277#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99322#L489 assume !(1 == ~M_E~0); 99485#L489-2 assume !(1 == ~T1_E~0); 99411#L494-1 assume !(1 == ~T2_E~0); 99265#L499-1 assume !(1 == ~T3_E~0); 99266#L504-1 assume !(1 == ~E_M~0); 99370#L509-1 assume !(1 == ~E_1~0); 99254#L514-1 assume !(1 == ~E_2~0); 99255#L519-1 assume !(1 == ~E_3~0); 99261#L524-1 assume { :end_inline_reset_delta_events } true; 99262#L690-2 assume !false; 103236#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103233#L416 [2022-11-16 12:02:12,060 INFO L750 eck$LassoCheckResult]: Loop: 103233#L416 assume !false; 103231#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 103228#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 103226#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 103225#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 103223#L369 assume 0 != eval_~tmp~0#1; 103218#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 103213#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 103210#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 103195#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 103207#L388 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 102850#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 103238#L402 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 102857#L419 assume !(0 != eval_~tmp_ndt_4~0#1); 103233#L416 [2022-11-16 12:02:12,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:12,061 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2022-11-16 12:02:12,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:12,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320118372] [2022-11-16 12:02:12,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:12,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:12,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:12,078 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:12,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:12,093 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:12,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:12,095 INFO L85 PathProgramCache]: Analyzing trace with hash -1368312829, now seen corresponding path program 1 times [2022-11-16 12:02:12,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:12,095 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808271271] [2022-11-16 12:02:12,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:12,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:12,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:12,100 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:12,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:12,104 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:12,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:02:12,105 INFO L85 PathProgramCache]: Analyzing trace with hash 985801161, now seen corresponding path program 1 times [2022-11-16 12:02:12,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:02:12,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970907164] [2022-11-16 12:02:12,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:02:12,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:02:12,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:12,118 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:12,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:12,148 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:02:13,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:13,671 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:02:13,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:02:13,840 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.11 12:02:13 BoogieIcfgContainer [2022-11-16 12:02:13,843 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-16 12:02:13,844 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-16 12:02:13,844 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-16 12:02:13,844 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-16 12:02:13,845 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:02:04" (3/4) ... [2022-11-16 12:02:13,850 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-16 12:02:13,928 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/witness.graphml [2022-11-16 12:02:13,928 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-16 12:02:13,929 INFO L158 Benchmark]: Toolchain (without parser) took 10819.22ms. Allocated memory was 132.1MB in the beginning and 562.0MB in the end (delta: 429.9MB). Free memory was 103.8MB in the beginning and 369.4MB in the end (delta: -265.6MB). Peak memory consumption was 163.6MB. Max. memory is 16.1GB. [2022-11-16 12:02:13,930 INFO L158 Benchmark]: CDTParser took 0.30ms. Allocated memory is still 96.5MB. Free memory is still 53.3MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-16 12:02:13,930 INFO L158 Benchmark]: CACSL2BoogieTranslator took 375.31ms. Allocated memory is still 132.1MB. Free memory was 103.8MB in the beginning and 104.6MB in the end (delta: -792.0kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-16 12:02:13,931 INFO L158 Benchmark]: Boogie Procedure Inliner took 72.57ms. Allocated memory is still 132.1MB. Free memory was 104.6MB in the beginning and 100.8MB in the end (delta: 3.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-16 12:02:13,931 INFO L158 Benchmark]: Boogie Preprocessor took 50.57ms. Allocated memory is still 132.1MB. Free memory was 100.8MB in the beginning and 97.6MB in the end (delta: 3.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-16 12:02:13,931 INFO L158 Benchmark]: RCFGBuilder took 1317.28ms. Allocated memory is still 132.1MB. Free memory was 97.6MB in the beginning and 97.0MB in the end (delta: 556.6kB). Peak memory consumption was 36.0MB. Max. memory is 16.1GB. [2022-11-16 12:02:13,932 INFO L158 Benchmark]: BuchiAutomizer took 8912.91ms. Allocated memory was 132.1MB in the beginning and 562.0MB in the end (delta: 429.9MB). Free memory was 96.7MB in the beginning and 375.7MB in the end (delta: -279.0MB). Peak memory consumption was 151.9MB. Max. memory is 16.1GB. [2022-11-16 12:02:13,932 INFO L158 Benchmark]: Witness Printer took 85.02ms. Allocated memory is still 562.0MB. Free memory was 375.7MB in the beginning and 369.4MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-16 12:02:13,934 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30ms. Allocated memory is still 96.5MB. Free memory is still 53.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 375.31ms. Allocated memory is still 132.1MB. Free memory was 103.8MB in the beginning and 104.6MB in the end (delta: -792.0kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 72.57ms. Allocated memory is still 132.1MB. Free memory was 104.6MB in the beginning and 100.8MB in the end (delta: 3.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 50.57ms. Allocated memory is still 132.1MB. Free memory was 100.8MB in the beginning and 97.6MB in the end (delta: 3.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1317.28ms. Allocated memory is still 132.1MB. Free memory was 97.6MB in the beginning and 97.0MB in the end (delta: 556.6kB). Peak memory consumption was 36.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 8912.91ms. Allocated memory was 132.1MB in the beginning and 562.0MB in the end (delta: 429.9MB). Free memory was 96.7MB in the beginning and 375.7MB in the end (delta: -279.0MB). Peak memory consumption was 151.9MB. Max. memory is 16.1GB. * Witness Printer took 85.02ms. Allocated memory is still 562.0MB. Free memory was 375.7MB in the beginning and 369.4MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 14020 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.7s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 4.4s. Construction of modules took 0.6s. Büchi inclusion checks took 3.2s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 1.5s AutomataMinimizationTime, 17 MinimizatonAttempts, 11564 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.6s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 11794 SdHoareTripleChecker+Valid, 0.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 11794 mSDsluCounter, 20157 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 10920 mSDsCounter, 188 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 522 IncrementalHoareTripleChecker+Invalid, 710 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 188 mSolverCounterUnsat, 9237 mSDtfsCounter, 522 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L28] int m_st ; [L38] int T2_E = 2; [L39] int T3_E = 2; [L37] int T1_E = 2; [L27] int t3_pc = 0; [L26] int t2_pc = 0; [L51] int local ; [L25] int t1_pc = 0; [L49] int token ; [L33] int t1_i ; [L36] int M_E = 2; [L40] int E_M = 2; [L32] int m_i ; [L41] int E_1 = 2; [L24] int m_pc = 0; [L30] int t2_st ; [L43] int E_3 = 2; [L29] int t1_st ; [L42] int E_2 = 2; [L31] int t3_st ; [L35] int t3_i ; [L34] int t2_i ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 364]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L28] int m_st ; [L38] int T2_E = 2; [L39] int T3_E = 2; [L37] int T1_E = 2; [L27] int t3_pc = 0; [L26] int t2_pc = 0; [L51] int local ; [L25] int t1_pc = 0; [L49] int token ; [L33] int t1_i ; [L36] int M_E = 2; [L40] int E_M = 2; [L32] int m_i ; [L41] int E_1 = 2; [L24] int m_pc = 0; [L30] int t2_st ; [L43] int E_3 = 2; [L29] int t1_st ; [L42] int E_2 = 2; [L31] int t3_st ; [L35] int t3_i ; [L34] int t2_i ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, token=0] [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L446] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L451] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L456] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L461] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L466] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L471] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L476] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L230] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L232] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L249] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L251] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L268] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L270] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L287] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L289] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L494] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L499] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L504] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L509] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L514] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L519] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L524] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L687] RET reset_delta_events() [L690] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-16 12:02:14,025 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64f24b4a-0be2-4b1f-8234-0972a0508ed7/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)