./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:13:41,492 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:13:41,495 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:13:41,542 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:13:41,546 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:13:41,548 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:13:41,551 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:13:41,557 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:13:41,563 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:13:41,564 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:13:41,565 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:13:41,567 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:13:41,567 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:13:41,568 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:13:41,570 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:13:41,571 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:13:41,572 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:13:41,573 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:13:41,575 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:13:41,577 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:13:41,578 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:13:41,593 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:13:41,594 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:13:41,595 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:13:41,598 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:13:41,604 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:13:41,604 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:13:41,605 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:13:41,606 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:13:41,607 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:13:41,609 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:13:41,610 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:13:41,611 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:13:41,613 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:13:41,615 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:13:41,616 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:13:41,617 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:13:41,617 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:13:41,618 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:13:41,619 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:13:41,620 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:13:41,621 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 11:13:41,647 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:13:41,647 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:13:41,648 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:13:41,648 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:13:41,649 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:13:41,650 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:13:41,650 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:13:41,650 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 11:13:41,650 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 11:13:41,651 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 11:13:41,651 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 11:13:41,651 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 11:13:41,651 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 11:13:41,651 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:13:41,652 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 11:13:41,652 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 11:13:41,652 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:13:41,652 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 11:13:41,653 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:13:41,653 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 11:13:41,653 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 11:13:41,653 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 11:13:41,653 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 11:13:41,654 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:13:41,654 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 11:13:41,654 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:13:41,654 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 11:13:41,655 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:13:41,655 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:13:41,655 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:13:41,655 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:13:41,656 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 11:13:41,657 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 [2022-11-16 11:13:41,958 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:13:41,987 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:13:41,991 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:13:41,992 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:13:41,993 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:13:41,994 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2022-11-16 11:13:42,091 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/data/9faa64e94/c38b8a450ebd4dda940e4c31a392bf2d/FLAG208fa3878 [2022-11-16 11:13:42,728 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:13:42,732 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2022-11-16 11:13:42,747 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/data/9faa64e94/c38b8a450ebd4dda940e4c31a392bf2d/FLAG208fa3878 [2022-11-16 11:13:43,005 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/data/9faa64e94/c38b8a450ebd4dda940e4c31a392bf2d [2022-11-16 11:13:43,008 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:13:43,009 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:13:43,011 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:13:43,011 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:13:43,015 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:13:43,016 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,017 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2eab84f9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43, skipping insertion in model container [2022-11-16 11:13:43,018 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,025 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:13:43,070 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:13:43,258 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[671,684] [2022-11-16 11:13:43,358 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:13:43,369 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:13:43,382 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[671,684] [2022-11-16 11:13:43,445 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:13:43,461 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:13:43,461 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43 WrapperNode [2022-11-16 11:13:43,462 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:13:43,463 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:13:43,463 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:13:43,463 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:13:43,470 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,481 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,563 INFO L138 Inliner]: procedures = 38, calls = 46, calls flagged for inlining = 41, calls inlined = 94, statements flattened = 1341 [2022-11-16 11:13:43,563 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:13:43,564 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:13:43,564 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:13:43,564 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:13:43,575 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,575 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,583 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,591 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,618 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,641 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,645 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,649 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,668 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:13:43,677 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:13:43,678 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:13:43,678 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:13:43,691 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (1/1) ... [2022-11-16 11:13:43,699 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:13:43,717 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:13:43,740 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:13:43,768 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 11:13:43,804 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 11:13:43,805 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 11:13:43,805 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:13:43,805 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:13:43,936 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:13:43,938 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:13:45,178 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:13:45,198 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:13:45,200 INFO L300 CfgBuilder]: Removed 8 assume(true) statements. [2022-11-16 11:13:45,204 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:13:45 BoogieIcfgContainer [2022-11-16 11:13:45,204 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:13:45,206 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 11:13:45,206 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 11:13:45,210 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 11:13:45,211 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:13:45,211 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 11:13:43" (1/3) ... [2022-11-16 11:13:45,213 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@699f375b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:13:45, skipping insertion in model container [2022-11-16 11:13:45,214 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:13:45,214 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:13:43" (2/3) ... [2022-11-16 11:13:45,214 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@699f375b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:13:45, skipping insertion in model container [2022-11-16 11:13:45,215 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:13:45,215 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:13:45" (3/3) ... [2022-11-16 11:13:45,216 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2022-11-16 11:13:45,299 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 11:13:45,299 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 11:13:45,300 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 11:13:45,300 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 11:13:45,300 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 11:13:45,300 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 11:13:45,300 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 11:13:45,301 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 11:13:45,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 552 states, 551 states have (on average 1.528130671506352) internal successors, (842), 551 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:45,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 469 [2022-11-16 11:13:45,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:45,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:45,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:45,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:45,373 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 11:13:45,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 552 states, 551 states have (on average 1.528130671506352) internal successors, (842), 551 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:45,391 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 469 [2022-11-16 11:13:45,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:45,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:45,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:45,396 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:45,407 INFO L748 eck$LassoCheckResult]: Stem: 543#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 464#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 212#L891true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13#L407true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 546#L414true assume !(1 == ~m_i~0);~m_st~0 := 2; 222#L414-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 414#L419-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 413#L424-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 203#L429-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 406#L434-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 467#L439-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 201#L599true assume 0 == ~M_E~0;~M_E~0 := 1; 358#L599-2true assume !(0 == ~T1_E~0); 15#L604-1true assume !(0 == ~T2_E~0); 10#L609-1true assume !(0 == ~T3_E~0); 84#L614-1true assume !(0 == ~T4_E~0); 154#L619-1true assume !(0 == ~T5_E~0); 227#L624-1true assume !(0 == ~E_M~0); 504#L629-1true assume !(0 == ~E_1~0); 51#L634-1true assume 0 == ~E_2~0;~E_2~0 := 1; 325#L639-1true assume !(0 == ~E_3~0); 399#L644-1true assume !(0 == ~E_4~0); 348#L649-1true assume !(0 == ~E_5~0); 34#L654-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89#L292true assume !(1 == ~m_pc~0); 182#L292-2true is_master_triggered_~__retres1~0#1 := 0; 262#L303true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 523#L304true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 483#L743true assume !(0 != activate_threads_~tmp~1#1); 68#L743-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 324#L311true assume 1 == ~t1_pc~0; 138#L312true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 232#L322true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2#L323true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24#L751true assume !(0 != activate_threads_~tmp___0~0#1); 429#L751-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 327#L330true assume 1 == ~t2_pc~0; 157#L331true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 90#L341true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29#L342true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 458#L759true assume !(0 != activate_threads_~tmp___1~0#1); 468#L759-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85#L349true assume !(1 == ~t3_pc~0); 508#L349-2true is_transmit3_triggered_~__retres1~3#1 := 0; 295#L360true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 219#L361true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 530#L767true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 449#L767-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 531#L368true assume 1 == ~t4_pc~0; 460#L369true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 389#L379true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214#L380true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 439#L775true assume !(0 != activate_threads_~tmp___3~0#1); 16#L775-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 473#L387true assume !(1 == ~t5_pc~0); 243#L387-2true is_transmit5_triggered_~__retres1~5#1 := 0; 540#L398true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66#L399true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 74#L783true assume !(0 != activate_threads_~tmp___4~0#1); 120#L783-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178#L667true assume !(1 == ~M_E~0); 333#L667-2true assume !(1 == ~T1_E~0); 338#L672-1true assume !(1 == ~T2_E~0); 146#L677-1true assume !(1 == ~T3_E~0); 307#L682-1true assume !(1 == ~T4_E~0); 401#L687-1true assume !(1 == ~T5_E~0); 469#L692-1true assume !(1 == ~E_M~0); 294#L697-1true assume 1 == ~E_1~0;~E_1~0 := 2; 522#L702-1true assume !(1 == ~E_2~0); 347#L707-1true assume !(1 == ~E_3~0); 215#L712-1true assume !(1 == ~E_4~0); 332#L717-1true assume !(1 == ~E_5~0); 316#L722-1true assume { :end_inline_reset_delta_events } true; 21#L928-2true [2022-11-16 11:13:45,409 INFO L750 eck$LassoCheckResult]: Loop: 21#L928-2true assume !false; 218#L929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39#L574true assume !true; 159#L589true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 95#L407-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 259#L599-3true assume 0 == ~M_E~0;~M_E~0 := 1; 306#L599-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 189#L604-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 512#L609-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 247#L614-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 25#L619-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 257#L624-3true assume !(0 == ~E_M~0); 303#L629-3true assume 0 == ~E_1~0;~E_1~0 := 1; 397#L634-3true assume 0 == ~E_2~0;~E_2~0 := 1; 317#L639-3true assume 0 == ~E_3~0;~E_3~0 := 1; 452#L644-3true assume 0 == ~E_4~0;~E_4~0 := 1; 515#L649-3true assume 0 == ~E_5~0;~E_5~0 := 1; 195#L654-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293#L292-21true assume 1 == ~m_pc~0; 265#L293-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 59#L303-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 362#L304-7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 431#L743-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 185#L743-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 398#L311-21true assume !(1 == ~t1_pc~0); 134#L311-23true is_transmit1_triggered_~__retres1~1#1 := 0; 37#L322-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 200#L323-7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 465#L751-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88#L751-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282#L330-21true assume 1 == ~t2_pc~0; 477#L331-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 254#L341-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108#L342-7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 273#L759-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64#L759-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 211#L349-21true assume !(1 == ~t3_pc~0); 365#L349-23true is_transmit3_triggered_~__retres1~3#1 := 0; 386#L360-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 482#L361-7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 320#L767-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 456#L767-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99#L368-21true assume 1 == ~t4_pc~0; 45#L369-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 383#L379-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6#L380-7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 359#L775-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12#L775-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40#L387-21true assume !(1 == ~t5_pc~0); 538#L387-23true is_transmit5_triggered_~__retres1~5#1 := 0; 335#L398-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9#L399-7true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393#L783-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 61#L783-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184#L667-3true assume !(1 == ~M_E~0); 53#L667-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 329#L672-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 87#L677-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 548#L682-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 378#L687-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 112#L692-3true assume 1 == ~E_M~0;~E_M~0 := 2; 494#L697-3true assume 1 == ~E_1~0;~E_1~0 := 2; 166#L702-3true assume !(1 == ~E_2~0); 263#L707-3true assume 1 == ~E_3~0;~E_3~0 := 2; 291#L712-3true assume 1 == ~E_4~0;~E_4~0 := 2; 58#L717-3true assume 1 == ~E_5~0;~E_5~0 := 2; 286#L722-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 455#L452-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 388#L484-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 503#L485-1true start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 191#L947true assume !(0 == start_simulation_~tmp~3#1); 524#L947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 194#L452-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 321#L484-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 428#L485-2true stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 375#L902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 331#L909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 292#L910true start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 279#L960true assume !(0 != start_simulation_~tmp___0~1#1); 21#L928-2true [2022-11-16 11:13:45,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:45,416 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2022-11-16 11:13:45,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:45,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627508808] [2022-11-16 11:13:45,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:45,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:45,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:45,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:45,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:45,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627508808] [2022-11-16 11:13:45,787 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627508808] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:45,787 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:45,789 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:45,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954354219] [2022-11-16 11:13:45,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:45,798 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:45,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:45,801 INFO L85 PathProgramCache]: Analyzing trace with hash -870049925, now seen corresponding path program 1 times [2022-11-16 11:13:45,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:45,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197148533] [2022-11-16 11:13:45,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:45,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:45,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:45,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:45,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:45,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197148533] [2022-11-16 11:13:45,886 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197148533] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:45,887 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:45,887 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:13:45,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [861981273] [2022-11-16 11:13:45,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:45,888 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:45,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:45,944 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:45,944 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:45,948 INFO L87 Difference]: Start difference. First operand has 552 states, 551 states have (on average 1.528130671506352) internal successors, (842), 551 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:46,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:46,034 INFO L93 Difference]: Finished difference Result 551 states and 823 transitions. [2022-11-16 11:13:46,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 823 transitions. [2022-11-16 11:13:46,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:46,051 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 546 states and 818 transitions. [2022-11-16 11:13:46,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-11-16 11:13:46,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-11-16 11:13:46,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 818 transitions. [2022-11-16 11:13:46,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:46,057 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 818 transitions. [2022-11-16 11:13:46,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 818 transitions. [2022-11-16 11:13:46,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-11-16 11:13:46,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4981684981684982) internal successors, (818), 545 states have internal predecessors, (818), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:46,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 818 transitions. [2022-11-16 11:13:46,114 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 818 transitions. [2022-11-16 11:13:46,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:46,120 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 818 transitions. [2022-11-16 11:13:46,120 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 11:13:46,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 818 transitions. [2022-11-16 11:13:46,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:46,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:46,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:46,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:46,151 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:46,151 INFO L748 eck$LassoCheckResult]: Stem: 1657#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 1648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1477#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1133#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1134#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 1489#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1490#L419-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1628#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1467#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1468#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1624#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1465#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 1466#L599-2 assume !(0 == ~T1_E~0); 1137#L604-1 assume !(0 == ~T2_E~0); 1126#L609-1 assume !(0 == ~T3_E~0); 1127#L614-1 assume !(0 == ~T4_E~0); 1286#L619-1 assume !(0 == ~T5_E~0); 1405#L624-1 assume !(0 == ~E_M~0); 1494#L629-1 assume !(0 == ~E_1~0); 1214#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1215#L639-1 assume !(0 == ~E_3~0); 1586#L644-1 assume !(0 == ~E_4~0); 1598#L649-1 assume !(0 == ~E_5~0); 1177#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1178#L292 assume !(1 == ~m_pc~0); 1296#L292-2 is_master_triggered_~__retres1~0#1 := 0; 1437#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1535#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1650#L743 assume !(0 != activate_threads_~tmp~1#1); 1251#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1252#L311 assume 1 == ~t1_pc~0; 1374#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1375#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1112#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1113#L751 assume !(0 != activate_threads_~tmp___0~0#1); 1153#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1587#L330 assume 1 == ~t2_pc~0; 1407#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1298#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1165#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1166#L759 assume !(0 != activate_threads_~tmp___1~0#1); 1645#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1287#L349 assume !(1 == ~t3_pc~0); 1288#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1332#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1485#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1486#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1641#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1642#L368 assume 1 == ~t4_pc~0; 1646#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1363#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1478#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1479#L775 assume !(0 != activate_threads_~tmp___3~0#1); 1138#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1139#L387 assume !(1 == ~t5_pc~0); 1510#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1511#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1247#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1248#L783 assume !(0 != activate_threads_~tmp___4~0#1); 1264#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1351#L667 assume !(1 == ~M_E~0); 1431#L667-2 assume !(1 == ~T1_E~0); 1591#L672-1 assume !(1 == ~T2_E~0); 1390#L677-1 assume !(1 == ~T3_E~0); 1391#L682-1 assume !(1 == ~T4_E~0); 1567#L687-1 assume !(1 == ~T5_E~0); 1621#L692-1 assume !(1 == ~E_M~0); 1558#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1559#L702-1 assume !(1 == ~E_2~0); 1597#L707-1 assume !(1 == ~E_3~0); 1480#L712-1 assume !(1 == ~E_4~0); 1481#L717-1 assume !(1 == ~E_5~0); 1577#L722-1 assume { :end_inline_reset_delta_events } true; 1148#L928-2 [2022-11-16 11:13:46,152 INFO L750 eck$LassoCheckResult]: Loop: 1148#L928-2 assume !false; 1149#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1188#L574 assume !false; 1189#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1640#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1338#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1302#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1182#L499 assume !(0 != eval_~tmp~0#1); 1183#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1306#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1307#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1533#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1447#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1448#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1517#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1154#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1155#L624-3 assume !(0 == ~E_M~0); 1529#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1565#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1578#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1579#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1643#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1457#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1458#L292-21 assume 1 == ~m_pc~0; 1536#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1233#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1234#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1605#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1440#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1441#L311-21 assume 1 == ~t1_pc~0; 1620#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1184#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1185#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1461#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1294#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1295#L330-21 assume 1 == ~t2_pc~0; 1549#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1525#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1327#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1328#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1243#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1244#L349-21 assume !(1 == ~t3_pc~0); 1475#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 1607#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1616#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1581#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1582#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1312#L368-21 assume 1 == ~t4_pc~0; 1202#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1203#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1118#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1119#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1131#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1132#L387-21 assume 1 == ~t5_pc~0; 1190#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1509#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1124#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1125#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1235#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1236#L667-3 assume !(1 == ~M_E~0); 1221#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1222#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1292#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1293#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1614#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1333#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1334#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1414#L702-3 assume !(1 == ~E_2~0); 1415#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1534#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1227#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1228#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1553#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1160#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1618#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1450#L947 assume !(0 == start_simulation_~tmp~3#1); 1451#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1454#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1418#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1583#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 1613#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1589#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1555#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1545#L960 assume !(0 != start_simulation_~tmp___0~1#1); 1148#L928-2 [2022-11-16 11:13:46,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:46,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2022-11-16 11:13:46,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:46,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322711294] [2022-11-16 11:13:46,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:46,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:46,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:46,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:46,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:46,275 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322711294] [2022-11-16 11:13:46,276 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322711294] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:46,276 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:46,277 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:46,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425577826] [2022-11-16 11:13:46,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:46,280 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:46,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:46,282 INFO L85 PathProgramCache]: Analyzing trace with hash 354999345, now seen corresponding path program 1 times [2022-11-16 11:13:46,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:46,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935022770] [2022-11-16 11:13:46,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:46,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:46,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:46,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:46,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:46,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935022770] [2022-11-16 11:13:46,449 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1935022770] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:46,450 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:46,450 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:46,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611259866] [2022-11-16 11:13:46,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:46,452 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:46,453 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:46,454 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:46,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:46,454 INFO L87 Difference]: Start difference. First operand 546 states and 818 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:46,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:46,488 INFO L93 Difference]: Finished difference Result 546 states and 817 transitions. [2022-11-16 11:13:46,488 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 817 transitions. [2022-11-16 11:13:46,500 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:46,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 817 transitions. [2022-11-16 11:13:46,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-11-16 11:13:46,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-11-16 11:13:46,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 817 transitions. [2022-11-16 11:13:46,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:46,514 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 817 transitions. [2022-11-16 11:13:46,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 817 transitions. [2022-11-16 11:13:46,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-11-16 11:13:46,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4963369963369964) internal successors, (817), 545 states have internal predecessors, (817), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:46,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 817 transitions. [2022-11-16 11:13:46,554 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 817 transitions. [2022-11-16 11:13:46,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:46,555 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 817 transitions. [2022-11-16 11:13:46,556 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 11:13:46,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 817 transitions. [2022-11-16 11:13:46,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:46,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:46,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:46,564 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:46,564 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:46,564 INFO L748 eck$LassoCheckResult]: Stem: 2756#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 2747#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2576#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2232#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2233#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 2588#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2589#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2727#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2566#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2567#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2723#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2564#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 2565#L599-2 assume !(0 == ~T1_E~0); 2236#L604-1 assume !(0 == ~T2_E~0); 2225#L609-1 assume !(0 == ~T3_E~0); 2226#L614-1 assume !(0 == ~T4_E~0); 2385#L619-1 assume !(0 == ~T5_E~0); 2504#L624-1 assume !(0 == ~E_M~0); 2593#L629-1 assume !(0 == ~E_1~0); 2313#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2314#L639-1 assume !(0 == ~E_3~0); 2685#L644-1 assume !(0 == ~E_4~0); 2698#L649-1 assume !(0 == ~E_5~0); 2276#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2277#L292 assume !(1 == ~m_pc~0); 2395#L292-2 is_master_triggered_~__retres1~0#1 := 0; 2536#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2634#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2749#L743 assume !(0 != activate_threads_~tmp~1#1); 2350#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2351#L311 assume 1 == ~t1_pc~0; 2473#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2474#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2211#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2212#L751 assume !(0 != activate_threads_~tmp___0~0#1); 2252#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2686#L330 assume 1 == ~t2_pc~0; 2506#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2397#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2264#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2265#L759 assume !(0 != activate_threads_~tmp___1~0#1); 2744#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2386#L349 assume !(1 == ~t3_pc~0); 2387#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2433#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2584#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2585#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2740#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2741#L368 assume 1 == ~t4_pc~0; 2745#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2464#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2577#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2578#L775 assume !(0 != activate_threads_~tmp___3~0#1); 2237#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2238#L387 assume !(1 == ~t5_pc~0); 2609#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2610#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2348#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2349#L783 assume !(0 != activate_threads_~tmp___4~0#1); 2363#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2450#L667 assume !(1 == ~M_E~0); 2530#L667-2 assume !(1 == ~T1_E~0); 2690#L672-1 assume !(1 == ~T2_E~0); 2489#L677-1 assume !(1 == ~T3_E~0); 2490#L682-1 assume !(1 == ~T4_E~0); 2666#L687-1 assume !(1 == ~T5_E~0); 2720#L692-1 assume !(1 == ~E_M~0); 2657#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2658#L702-1 assume !(1 == ~E_2~0); 2696#L707-1 assume !(1 == ~E_3~0); 2579#L712-1 assume !(1 == ~E_4~0); 2580#L717-1 assume !(1 == ~E_5~0); 2676#L722-1 assume { :end_inline_reset_delta_events } true; 2247#L928-2 [2022-11-16 11:13:46,565 INFO L750 eck$LassoCheckResult]: Loop: 2247#L928-2 assume !false; 2248#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2287#L574 assume !false; 2288#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2739#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2437#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2401#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2281#L499 assume !(0 != eval_~tmp~0#1); 2282#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2406#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2407#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2632#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2546#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2547#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2616#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2253#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2254#L624-3 assume !(0 == ~E_M~0); 2628#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2664#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2677#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2678#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2742#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2556#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2557#L292-21 assume !(1 == ~m_pc~0); 2453#L292-23 is_master_triggered_~__retres1~0#1 := 0; 2332#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2333#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2704#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2539#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2540#L311-21 assume !(1 == ~t1_pc~0); 2467#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 2283#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2284#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2560#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2393#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2394#L330-21 assume 1 == ~t2_pc~0; 2648#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2624#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2426#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2427#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2344#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2345#L349-21 assume !(1 == ~t3_pc~0); 2574#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2706#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2715#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2680#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2681#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2411#L368-21 assume 1 == ~t4_pc~0; 2301#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2302#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2217#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2218#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2227#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2228#L387-21 assume 1 == ~t5_pc~0; 2289#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2607#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2221#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2222#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2334#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2335#L667-3 assume !(1 == ~M_E~0); 2315#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2316#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2391#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2392#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2713#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2431#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2432#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2513#L702-3 assume !(1 == ~E_2~0); 2514#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2633#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2328#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2329#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2652#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2259#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2717#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2549#L947 assume !(0 == start_simulation_~tmp~3#1); 2550#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2553#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2517#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2682#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 2712#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2688#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2654#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2644#L960 assume !(0 != start_simulation_~tmp___0~1#1); 2247#L928-2 [2022-11-16 11:13:46,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:46,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2022-11-16 11:13:46,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:46,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830561160] [2022-11-16 11:13:46,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:46,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:46,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:46,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:46,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:46,645 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830561160] [2022-11-16 11:13:46,645 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830561160] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:46,645 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:46,645 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:46,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032693164] [2022-11-16 11:13:46,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:46,647 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:46,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:46,648 INFO L85 PathProgramCache]: Analyzing trace with hash 275402867, now seen corresponding path program 1 times [2022-11-16 11:13:46,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:46,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158651768] [2022-11-16 11:13:46,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:46,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:46,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:46,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:46,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:46,751 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158651768] [2022-11-16 11:13:46,751 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158651768] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:46,751 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:46,751 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:46,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046397015] [2022-11-16 11:13:46,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:46,752 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:46,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:46,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:46,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:46,753 INFO L87 Difference]: Start difference. First operand 546 states and 817 transitions. cyclomatic complexity: 272 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:46,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:46,772 INFO L93 Difference]: Finished difference Result 546 states and 816 transitions. [2022-11-16 11:13:46,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 816 transitions. [2022-11-16 11:13:46,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:46,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 816 transitions. [2022-11-16 11:13:46,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-11-16 11:13:46,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-11-16 11:13:46,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 816 transitions. [2022-11-16 11:13:46,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:46,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 816 transitions. [2022-11-16 11:13:46,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 816 transitions. [2022-11-16 11:13:46,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-11-16 11:13:46,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4945054945054945) internal successors, (816), 545 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:46,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 816 transitions. [2022-11-16 11:13:46,802 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 816 transitions. [2022-11-16 11:13:46,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:46,805 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 816 transitions. [2022-11-16 11:13:46,805 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 11:13:46,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 816 transitions. [2022-11-16 11:13:46,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:46,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:46,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:46,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:46,819 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:46,820 INFO L748 eck$LassoCheckResult]: Stem: 3855#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 3846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3675#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3331#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3332#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 3687#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3688#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3826#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3667#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3668#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3822#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3663#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 3664#L599-2 assume !(0 == ~T1_E~0); 3335#L604-1 assume !(0 == ~T2_E~0); 3324#L609-1 assume !(0 == ~T3_E~0); 3325#L614-1 assume !(0 == ~T4_E~0); 3484#L619-1 assume !(0 == ~T5_E~0); 3603#L624-1 assume !(0 == ~E_M~0); 3692#L629-1 assume !(0 == ~E_1~0); 3412#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3413#L639-1 assume !(0 == ~E_3~0); 3784#L644-1 assume !(0 == ~E_4~0); 3797#L649-1 assume !(0 == ~E_5~0); 3375#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3376#L292 assume !(1 == ~m_pc~0); 3494#L292-2 is_master_triggered_~__retres1~0#1 := 0; 3635#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3733#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3848#L743 assume !(0 != activate_threads_~tmp~1#1); 3449#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3450#L311 assume 1 == ~t1_pc~0; 3572#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3573#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3310#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3311#L751 assume !(0 != activate_threads_~tmp___0~0#1); 3351#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3785#L330 assume 1 == ~t2_pc~0; 3605#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3496#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3365#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3366#L759 assume !(0 != activate_threads_~tmp___1~0#1); 3843#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3485#L349 assume !(1 == ~t3_pc~0); 3486#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3532#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3683#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3684#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3839#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3840#L368 assume 1 == ~t4_pc~0; 3844#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3563#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3676#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3677#L775 assume !(0 != activate_threads_~tmp___3~0#1); 3336#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3337#L387 assume !(1 == ~t5_pc~0); 3708#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3709#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3447#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3448#L783 assume !(0 != activate_threads_~tmp___4~0#1); 3465#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3551#L667 assume !(1 == ~M_E~0); 3629#L667-2 assume !(1 == ~T1_E~0); 3789#L672-1 assume !(1 == ~T2_E~0); 3588#L677-1 assume !(1 == ~T3_E~0); 3589#L682-1 assume !(1 == ~T4_E~0); 3765#L687-1 assume !(1 == ~T5_E~0); 3819#L692-1 assume !(1 == ~E_M~0); 3756#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3757#L702-1 assume !(1 == ~E_2~0); 3795#L707-1 assume !(1 == ~E_3~0); 3678#L712-1 assume !(1 == ~E_4~0); 3679#L717-1 assume !(1 == ~E_5~0); 3775#L722-1 assume { :end_inline_reset_delta_events } true; 3346#L928-2 [2022-11-16 11:13:46,820 INFO L750 eck$LassoCheckResult]: Loop: 3346#L928-2 assume !false; 3347#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3386#L574 assume !false; 3387#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3838#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3536#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3500#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3380#L499 assume !(0 != eval_~tmp~0#1); 3381#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3505#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3506#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3731#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3645#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3646#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3716#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3352#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3353#L624-3 assume !(0 == ~E_M~0); 3727#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3763#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3776#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3777#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3841#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3655#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3656#L292-21 assume !(1 == ~m_pc~0); 3552#L292-23 is_master_triggered_~__retres1~0#1 := 0; 3431#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3432#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3803#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3638#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3639#L311-21 assume 1 == ~t1_pc~0; 3818#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3382#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3383#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3659#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3492#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3493#L330-21 assume 1 == ~t2_pc~0; 3744#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3723#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3525#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3526#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3438#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3439#L349-21 assume !(1 == ~t3_pc~0); 3673#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3805#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3814#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3779#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3780#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3510#L368-21 assume 1 == ~t4_pc~0; 3400#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3401#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3316#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3317#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3329#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3330#L387-21 assume 1 == ~t5_pc~0; 3388#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3706#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3320#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3321#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3433#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3434#L667-3 assume !(1 == ~M_E~0); 3414#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3415#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3490#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3491#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3812#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3530#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3531#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3612#L702-3 assume !(1 == ~E_2~0); 3613#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3732#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3427#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3428#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3751#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3358#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3816#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3648#L947 assume !(0 == start_simulation_~tmp~3#1); 3649#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3652#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3616#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3781#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 3811#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3787#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3755#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3743#L960 assume !(0 != start_simulation_~tmp___0~1#1); 3346#L928-2 [2022-11-16 11:13:46,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:46,821 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2022-11-16 11:13:46,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:46,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702230273] [2022-11-16 11:13:46,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:46,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:46,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:46,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:46,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:46,904 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702230273] [2022-11-16 11:13:46,905 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702230273] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:46,905 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:46,905 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:46,905 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [242485554] [2022-11-16 11:13:46,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:46,906 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:46,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:46,907 INFO L85 PathProgramCache]: Analyzing trace with hash 1383531506, now seen corresponding path program 1 times [2022-11-16 11:13:46,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:46,908 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961784366] [2022-11-16 11:13:46,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:46,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:46,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:46,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:46,964 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:46,964 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961784366] [2022-11-16 11:13:46,964 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961784366] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:46,964 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:46,965 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:46,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342612390] [2022-11-16 11:13:46,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:46,966 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:46,966 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:46,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:46,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:46,967 INFO L87 Difference]: Start difference. First operand 546 states and 816 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:46,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:46,985 INFO L93 Difference]: Finished difference Result 546 states and 815 transitions. [2022-11-16 11:13:46,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 815 transitions. [2022-11-16 11:13:46,990 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:46,993 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 815 transitions. [2022-11-16 11:13:46,993 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-11-16 11:13:46,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-11-16 11:13:46,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 815 transitions. [2022-11-16 11:13:46,995 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:46,996 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 815 transitions. [2022-11-16 11:13:46,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 815 transitions. [2022-11-16 11:13:47,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-11-16 11:13:47,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4926739926739927) internal successors, (815), 545 states have internal predecessors, (815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:47,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 815 transitions. [2022-11-16 11:13:47,009 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 815 transitions. [2022-11-16 11:13:47,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:47,010 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 815 transitions. [2022-11-16 11:13:47,010 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 11:13:47,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 815 transitions. [2022-11-16 11:13:47,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:47,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:47,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:47,016 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:47,016 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:47,016 INFO L748 eck$LassoCheckResult]: Stem: 4954#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 4945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4774#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4430#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4431#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 4786#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4787#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4925#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4766#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4767#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4921#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4762#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 4763#L599-2 assume !(0 == ~T1_E~0); 4434#L604-1 assume !(0 == ~T2_E~0); 4423#L609-1 assume !(0 == ~T3_E~0); 4424#L614-1 assume !(0 == ~T4_E~0); 4583#L619-1 assume !(0 == ~T5_E~0); 4702#L624-1 assume !(0 == ~E_M~0); 4791#L629-1 assume !(0 == ~E_1~0); 4511#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4512#L639-1 assume !(0 == ~E_3~0); 4883#L644-1 assume !(0 == ~E_4~0); 4896#L649-1 assume !(0 == ~E_5~0); 4474#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4475#L292 assume !(1 == ~m_pc~0); 4593#L292-2 is_master_triggered_~__retres1~0#1 := 0; 4734#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4832#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4947#L743 assume !(0 != activate_threads_~tmp~1#1); 4548#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4549#L311 assume 1 == ~t1_pc~0; 4671#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4672#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4409#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4410#L751 assume !(0 != activate_threads_~tmp___0~0#1); 4450#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4884#L330 assume 1 == ~t2_pc~0; 4704#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4595#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4464#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4465#L759 assume !(0 != activate_threads_~tmp___1~0#1); 4942#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4584#L349 assume !(1 == ~t3_pc~0); 4585#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4631#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4782#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4783#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4938#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4939#L368 assume 1 == ~t4_pc~0; 4943#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4662#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4775#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4776#L775 assume !(0 != activate_threads_~tmp___3~0#1); 4435#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4436#L387 assume !(1 == ~t5_pc~0); 4807#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4808#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4546#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4547#L783 assume !(0 != activate_threads_~tmp___4~0#1); 4564#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4650#L667 assume !(1 == ~M_E~0); 4728#L667-2 assume !(1 == ~T1_E~0); 4888#L672-1 assume !(1 == ~T2_E~0); 4687#L677-1 assume !(1 == ~T3_E~0); 4688#L682-1 assume !(1 == ~T4_E~0); 4864#L687-1 assume !(1 == ~T5_E~0); 4918#L692-1 assume !(1 == ~E_M~0); 4855#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4856#L702-1 assume !(1 == ~E_2~0); 4894#L707-1 assume !(1 == ~E_3~0); 4777#L712-1 assume !(1 == ~E_4~0); 4778#L717-1 assume !(1 == ~E_5~0); 4874#L722-1 assume { :end_inline_reset_delta_events } true; 4445#L928-2 [2022-11-16 11:13:47,017 INFO L750 eck$LassoCheckResult]: Loop: 4445#L928-2 assume !false; 4446#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4485#L574 assume !false; 4486#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4937#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4635#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4599#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4479#L499 assume !(0 != eval_~tmp~0#1); 4480#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4604#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4605#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4830#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4744#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4745#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4815#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4451#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4452#L624-3 assume !(0 == ~E_M~0); 4826#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4862#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4875#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4876#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4940#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4754#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4755#L292-21 assume 1 == ~m_pc~0; 4833#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4530#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4531#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4902#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4737#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4738#L311-21 assume 1 == ~t1_pc~0; 4917#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4481#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4482#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4758#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4591#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4592#L330-21 assume 1 == ~t2_pc~0; 4844#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4822#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4624#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4625#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4537#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4538#L349-21 assume !(1 == ~t3_pc~0); 4772#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 4904#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4913#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4878#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4879#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4609#L368-21 assume 1 == ~t4_pc~0; 4499#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4500#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4415#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4416#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4428#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4429#L387-21 assume 1 == ~t5_pc~0; 4487#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4805#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4419#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4420#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4532#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4533#L667-3 assume !(1 == ~M_E~0); 4516#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4517#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4589#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4590#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4911#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4629#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4630#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4711#L702-3 assume !(1 == ~E_2~0); 4712#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4831#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4526#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4527#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4850#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4457#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4915#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4747#L947 assume !(0 == start_simulation_~tmp~3#1); 4748#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4751#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4716#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4880#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 4910#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4886#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4854#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4842#L960 assume !(0 != start_simulation_~tmp___0~1#1); 4445#L928-2 [2022-11-16 11:13:47,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:47,018 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2022-11-16 11:13:47,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:47,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210099090] [2022-11-16 11:13:47,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:47,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:47,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:47,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:47,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:47,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210099090] [2022-11-16 11:13:47,059 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210099090] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:47,059 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:47,059 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:47,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050790545] [2022-11-16 11:13:47,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:47,060 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:47,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:47,060 INFO L85 PathProgramCache]: Analyzing trace with hash 354999345, now seen corresponding path program 2 times [2022-11-16 11:13:47,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:47,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186810575] [2022-11-16 11:13:47,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:47,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:47,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:47,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:47,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:47,117 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [186810575] [2022-11-16 11:13:47,117 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [186810575] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:47,118 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:47,118 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:47,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443184922] [2022-11-16 11:13:47,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:47,119 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:47,119 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:47,119 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:47,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:47,120 INFO L87 Difference]: Start difference. First operand 546 states and 815 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:47,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:47,135 INFO L93 Difference]: Finished difference Result 546 states and 814 transitions. [2022-11-16 11:13:47,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 814 transitions. [2022-11-16 11:13:47,140 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:47,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 814 transitions. [2022-11-16 11:13:47,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2022-11-16 11:13:47,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2022-11-16 11:13:47,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 814 transitions. [2022-11-16 11:13:47,145 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:47,145 INFO L218 hiAutomatonCegarLoop]: Abstraction has 546 states and 814 transitions. [2022-11-16 11:13:47,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 814 transitions. [2022-11-16 11:13:47,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2022-11-16 11:13:47,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4908424908424909) internal successors, (814), 545 states have internal predecessors, (814), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:47,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 814 transitions. [2022-11-16 11:13:47,157 INFO L240 hiAutomatonCegarLoop]: Abstraction has 546 states and 814 transitions. [2022-11-16 11:13:47,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:47,160 INFO L428 stractBuchiCegarLoop]: Abstraction has 546 states and 814 transitions. [2022-11-16 11:13:47,161 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 11:13:47,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 814 transitions. [2022-11-16 11:13:47,164 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2022-11-16 11:13:47,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:47,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:47,166 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:47,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:47,167 INFO L748 eck$LassoCheckResult]: Stem: 6053#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 6044#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5873#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5529#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5530#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 5885#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5886#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6024#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5865#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5866#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6020#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5861#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 5862#L599-2 assume !(0 == ~T1_E~0); 5533#L604-1 assume !(0 == ~T2_E~0); 5522#L609-1 assume !(0 == ~T3_E~0); 5523#L614-1 assume !(0 == ~T4_E~0); 5682#L619-1 assume !(0 == ~T5_E~0); 5801#L624-1 assume !(0 == ~E_M~0); 5890#L629-1 assume !(0 == ~E_1~0); 5610#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5611#L639-1 assume !(0 == ~E_3~0); 5982#L644-1 assume !(0 == ~E_4~0); 5995#L649-1 assume !(0 == ~E_5~0); 5573#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5574#L292 assume !(1 == ~m_pc~0); 5692#L292-2 is_master_triggered_~__retres1~0#1 := 0; 5833#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5931#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6046#L743 assume !(0 != activate_threads_~tmp~1#1); 5647#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5648#L311 assume 1 == ~t1_pc~0; 5770#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5771#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5508#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5509#L751 assume !(0 != activate_threads_~tmp___0~0#1); 5549#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5983#L330 assume 1 == ~t2_pc~0; 5803#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5695#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5563#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5564#L759 assume !(0 != activate_threads_~tmp___1~0#1); 6041#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5683#L349 assume !(1 == ~t3_pc~0); 5684#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5730#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5881#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5882#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6037#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6038#L368 assume 1 == ~t4_pc~0; 6042#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5763#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5874#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5875#L775 assume !(0 != activate_threads_~tmp___3~0#1); 5534#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5535#L387 assume !(1 == ~t5_pc~0); 5906#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5907#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5645#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5646#L783 assume !(0 != activate_threads_~tmp___4~0#1); 5663#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5749#L667 assume !(1 == ~M_E~0); 5827#L667-2 assume !(1 == ~T1_E~0); 5987#L672-1 assume !(1 == ~T2_E~0); 5786#L677-1 assume !(1 == ~T3_E~0); 5787#L682-1 assume !(1 == ~T4_E~0); 5963#L687-1 assume !(1 == ~T5_E~0); 6017#L692-1 assume !(1 == ~E_M~0); 5954#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5955#L702-1 assume !(1 == ~E_2~0); 5993#L707-1 assume !(1 == ~E_3~0); 5876#L712-1 assume !(1 == ~E_4~0); 5877#L717-1 assume !(1 == ~E_5~0); 5973#L722-1 assume { :end_inline_reset_delta_events } true; 5544#L928-2 [2022-11-16 11:13:47,167 INFO L750 eck$LassoCheckResult]: Loop: 5544#L928-2 assume !false; 5545#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5584#L574 assume !false; 5585#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6036#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5734#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5698#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5578#L499 assume !(0 != eval_~tmp~0#1); 5579#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5703#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5704#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5929#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5844#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5845#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5914#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5550#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5551#L624-3 assume !(0 == ~E_M~0); 5925#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5961#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5974#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5975#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6039#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5853#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5854#L292-21 assume !(1 == ~m_pc~0); 5750#L292-23 is_master_triggered_~__retres1~0#1 := 0; 5629#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5630#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6001#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5836#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5837#L311-21 assume 1 == ~t1_pc~0; 6016#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5580#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5581#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5857#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5690#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5691#L330-21 assume 1 == ~t2_pc~0; 5943#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5921#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5723#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5724#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5636#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5637#L349-21 assume 1 == ~t3_pc~0; 5872#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6003#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6012#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5977#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5978#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5708#L368-21 assume !(1 == ~t4_pc~0); 5600#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5599#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5514#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5515#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5527#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5528#L387-21 assume 1 == ~t5_pc~0; 5586#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5904#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5520#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5521#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5631#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5632#L667-3 assume !(1 == ~M_E~0); 5615#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5616#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5688#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5689#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6010#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5728#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5729#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5810#L702-3 assume !(1 == ~E_2~0); 5811#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5930#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5625#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5626#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5949#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5556#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6014#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5846#L947 assume !(0 == start_simulation_~tmp~3#1); 5847#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5850#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5815#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5979#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 6009#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5985#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5953#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5941#L960 assume !(0 != start_simulation_~tmp___0~1#1); 5544#L928-2 [2022-11-16 11:13:47,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:47,168 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2022-11-16 11:13:47,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:47,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037525454] [2022-11-16 11:13:47,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:47,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:47,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:47,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:47,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:47,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037525454] [2022-11-16 11:13:47,242 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037525454] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:47,242 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:47,242 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:13:47,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996618215] [2022-11-16 11:13:47,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:47,249 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:47,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:47,253 INFO L85 PathProgramCache]: Analyzing trace with hash 610261170, now seen corresponding path program 1 times [2022-11-16 11:13:47,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:47,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702066014] [2022-11-16 11:13:47,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:47,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:47,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:47,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:47,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:47,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702066014] [2022-11-16 11:13:47,317 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702066014] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:47,318 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:47,318 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:47,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613067245] [2022-11-16 11:13:47,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:47,319 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:47,319 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:47,320 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:47,320 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:47,321 INFO L87 Difference]: Start difference. First operand 546 states and 814 transitions. cyclomatic complexity: 269 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:47,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:47,365 INFO L93 Difference]: Finished difference Result 969 states and 1439 transitions. [2022-11-16 11:13:47,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 969 states and 1439 transitions. [2022-11-16 11:13:47,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2022-11-16 11:13:47,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 969 states to 969 states and 1439 transitions. [2022-11-16 11:13:47,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 969 [2022-11-16 11:13:47,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 969 [2022-11-16 11:13:47,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 969 states and 1439 transitions. [2022-11-16 11:13:47,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:47,381 INFO L218 hiAutomatonCegarLoop]: Abstraction has 969 states and 1439 transitions. [2022-11-16 11:13:47,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 969 states and 1439 transitions. [2022-11-16 11:13:47,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 969 to 969. [2022-11-16 11:13:47,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.4850361197110422) internal successors, (1439), 968 states have internal predecessors, (1439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:47,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1439 transitions. [2022-11-16 11:13:47,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 969 states and 1439 transitions. [2022-11-16 11:13:47,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:47,407 INFO L428 stractBuchiCegarLoop]: Abstraction has 969 states and 1439 transitions. [2022-11-16 11:13:47,407 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 11:13:47,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1439 transitions. [2022-11-16 11:13:47,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2022-11-16 11:13:47,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:47,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:47,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:47,414 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:47,415 INFO L748 eck$LassoCheckResult]: Stem: 7605#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 7589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7400#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7051#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7052#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 7412#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7413#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7563#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7392#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7393#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7560#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7388#L599 assume !(0 == ~M_E~0); 7389#L599-2 assume !(0 == ~T1_E~0); 7055#L604-1 assume !(0 == ~T2_E~0); 7044#L609-1 assume !(0 == ~T3_E~0); 7045#L614-1 assume !(0 == ~T4_E~0); 7205#L619-1 assume !(0 == ~T5_E~0); 7324#L624-1 assume !(0 == ~E_M~0); 7418#L629-1 assume !(0 == ~E_1~0); 7133#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7134#L639-1 assume !(0 == ~E_3~0); 7513#L644-1 assume !(0 == ~E_4~0); 7527#L649-1 assume !(0 == ~E_5~0); 7095#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7096#L292 assume !(1 == ~m_pc~0); 7215#L292-2 is_master_triggered_~__retres1~0#1 := 0; 7359#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7459#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7592#L743 assume !(0 != activate_threads_~tmp~1#1); 7170#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7171#L311 assume 1 == ~t1_pc~0; 7293#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7294#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7030#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7031#L751 assume !(0 != activate_threads_~tmp___0~0#1); 7071#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7515#L330 assume 1 == ~t2_pc~0; 7326#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7218#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7085#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7086#L759 assume !(0 != activate_threads_~tmp___1~0#1); 7586#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7206#L349 assume !(1 == ~t3_pc~0); 7207#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7253#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7408#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7409#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7582#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7583#L368 assume 1 == ~t4_pc~0; 7587#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7286#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7401#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7402#L775 assume !(0 != activate_threads_~tmp___3~0#1); 7056#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7057#L387 assume !(1 == ~t5_pc~0); 7434#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7435#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7168#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7169#L783 assume !(0 != activate_threads_~tmp___4~0#1); 7186#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7272#L667 assume !(1 == ~M_E~0); 7353#L667-2 assume !(1 == ~T1_E~0); 7520#L672-1 assume !(1 == ~T2_E~0); 7309#L677-1 assume !(1 == ~T3_E~0); 7310#L682-1 assume !(1 == ~T4_E~0); 7492#L687-1 assume !(1 == ~T5_E~0); 7554#L692-1 assume !(1 == ~E_M~0); 7482#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7483#L702-1 assume !(1 == ~E_2~0); 7525#L707-1 assume !(1 == ~E_3~0); 7403#L712-1 assume !(1 == ~E_4~0); 7404#L717-1 assume !(1 == ~E_5~0); 7503#L722-1 assume { :end_inline_reset_delta_events } true; 7504#L928-2 [2022-11-16 11:13:47,415 INFO L750 eck$LassoCheckResult]: Loop: 7504#L928-2 assume !false; 7620#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7619#L574 assume !false; 7618#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7614#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7562#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7221#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7100#L499 assume !(0 != eval_~tmp~0#1); 7102#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7224#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7225#L599-3 assume !(0 == ~M_E~0); 7456#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7889#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7888#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7886#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7883#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7881#L624-3 assume !(0 == ~E_M~0); 7880#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7879#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7877#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7875#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7873#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7870#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7868#L292-21 assume 1 == ~m_pc~0; 7865#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7863#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7861#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7859#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7856#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7854#L311-21 assume !(1 == ~t1_pc~0); 7851#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 7849#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7847#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7845#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7842#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7840#L330-21 assume 1 == ~t2_pc~0; 7837#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7835#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7833#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7831#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7828#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7826#L349-21 assume 1 == ~t3_pc~0; 7824#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7821#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7819#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7817#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7814#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7812#L368-21 assume 1 == ~t4_pc~0; 7721#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7719#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7717#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7715#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7713#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7712#L387-21 assume !(1 == ~t5_pc~0); 7710#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 7709#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7706#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7704#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7702#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7701#L667-3 assume !(1 == ~M_E~0); 7362#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7516#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7211#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7212#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7546#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7251#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7252#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7335#L702-3 assume !(1 == ~E_2~0); 7336#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7458#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7148#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7149#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7477#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7078#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7551#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7373#L947 assume !(0 == start_simulation_~tmp~3#1); 7374#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7378#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7340#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7510#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 7544#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7545#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7633#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7627#L960 assume !(0 != start_simulation_~tmp___0~1#1); 7504#L928-2 [2022-11-16 11:13:47,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:47,416 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2022-11-16 11:13:47,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:47,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925064858] [2022-11-16 11:13:47,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:47,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:47,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:47,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:47,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:47,464 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925064858] [2022-11-16 11:13:47,464 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925064858] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:47,464 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:47,465 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:13:47,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302353442] [2022-11-16 11:13:47,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:47,465 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:47,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:47,466 INFO L85 PathProgramCache]: Analyzing trace with hash 759059568, now seen corresponding path program 1 times [2022-11-16 11:13:47,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:47,467 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842868892] [2022-11-16 11:13:47,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:47,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:47,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:47,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:47,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:47,517 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842868892] [2022-11-16 11:13:47,517 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842868892] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:47,518 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:47,518 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:47,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [551951455] [2022-11-16 11:13:47,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:47,519 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:47,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:47,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:47,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:47,520 INFO L87 Difference]: Start difference. First operand 969 states and 1439 transitions. cyclomatic complexity: 471 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:47,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:47,578 INFO L93 Difference]: Finished difference Result 969 states and 1417 transitions. [2022-11-16 11:13:47,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 969 states and 1417 transitions. [2022-11-16 11:13:47,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2022-11-16 11:13:47,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 969 states to 969 states and 1417 transitions. [2022-11-16 11:13:47,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 969 [2022-11-16 11:13:47,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 969 [2022-11-16 11:13:47,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 969 states and 1417 transitions. [2022-11-16 11:13:47,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:47,596 INFO L218 hiAutomatonCegarLoop]: Abstraction has 969 states and 1417 transitions. [2022-11-16 11:13:47,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 969 states and 1417 transitions. [2022-11-16 11:13:47,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 969 to 969. [2022-11-16 11:13:47,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.4623323013415892) internal successors, (1417), 968 states have internal predecessors, (1417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:47,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1417 transitions. [2022-11-16 11:13:47,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 969 states and 1417 transitions. [2022-11-16 11:13:47,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:47,624 INFO L428 stractBuchiCegarLoop]: Abstraction has 969 states and 1417 transitions. [2022-11-16 11:13:47,624 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 11:13:47,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1417 transitions. [2022-11-16 11:13:47,630 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2022-11-16 11:13:47,630 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:47,630 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:47,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:47,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:47,632 INFO L748 eck$LassoCheckResult]: Stem: 9540#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 9526#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9341#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8996#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8997#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 9353#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9354#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9500#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9333#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9334#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9497#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9329#L599 assume !(0 == ~M_E~0); 9330#L599-2 assume !(0 == ~T1_E~0); 9000#L604-1 assume !(0 == ~T2_E~0); 8989#L609-1 assume !(0 == ~T3_E~0); 8990#L614-1 assume !(0 == ~T4_E~0); 9149#L619-1 assume !(0 == ~T5_E~0); 9267#L624-1 assume !(0 == ~E_M~0); 9358#L629-1 assume !(0 == ~E_1~0); 9077#L634-1 assume !(0 == ~E_2~0); 9078#L639-1 assume !(0 == ~E_3~0); 9454#L644-1 assume !(0 == ~E_4~0); 9467#L649-1 assume !(0 == ~E_5~0); 9040#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9041#L292 assume !(1 == ~m_pc~0); 9159#L292-2 is_master_triggered_~__retres1~0#1 := 0; 9301#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9400#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9529#L743 assume !(0 != activate_threads_~tmp~1#1); 9114#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9115#L311 assume 1 == ~t1_pc~0; 9237#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9238#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8975#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8976#L751 assume !(0 != activate_threads_~tmp___0~0#1); 9016#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9456#L330 assume !(1 == ~t2_pc~0); 9270#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9162#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9030#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9031#L759 assume !(0 != activate_threads_~tmp___1~0#1); 9523#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9150#L349 assume !(1 == ~t3_pc~0); 9151#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9197#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9349#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9350#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9519#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9520#L368 assume 1 == ~t4_pc~0; 9524#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9230#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9342#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9343#L775 assume !(0 != activate_threads_~tmp___3~0#1); 9001#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9002#L387 assume !(1 == ~t5_pc~0); 9375#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9376#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9112#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9113#L783 assume !(0 != activate_threads_~tmp___4~0#1); 9130#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9216#L667 assume !(1 == ~M_E~0); 9295#L667-2 assume !(1 == ~T1_E~0); 9460#L672-1 assume !(1 == ~T2_E~0); 9252#L677-1 assume !(1 == ~T3_E~0); 9253#L682-1 assume !(1 == ~T4_E~0); 9434#L687-1 assume !(1 == ~T5_E~0); 9492#L692-1 assume !(1 == ~E_M~0); 9424#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9425#L702-1 assume !(1 == ~E_2~0); 9465#L707-1 assume !(1 == ~E_3~0); 9344#L712-1 assume !(1 == ~E_4~0); 9345#L717-1 assume !(1 == ~E_5~0); 9444#L722-1 assume { :end_inline_reset_delta_events } true; 9445#L928-2 [2022-11-16 11:13:47,633 INFO L750 eck$LassoCheckResult]: Loop: 9445#L928-2 assume !false; 9556#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9555#L574 assume !false; 9554#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9550#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9499#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9165#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9045#L499 assume !(0 != eval_~tmp~0#1); 9047#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9170#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9171#L599-3 assume !(0 == ~M_E~0); 9398#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9313#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9314#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9383#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9017#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9018#L624-3 assume !(0 == ~E_M~0); 9394#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9432#L634-3 assume !(0 == ~E_2~0); 9446#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9447#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9521#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9322#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9323#L292-21 assume !(1 == ~m_pc~0); 9217#L292-23 is_master_triggered_~__retres1~0#1 := 0; 9096#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9097#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9473#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9304#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9305#L311-21 assume 1 == ~t1_pc~0; 9491#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9048#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9049#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9326#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9157#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9158#L330-21 assume !(1 == ~t2_pc~0); 9413#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9390#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9190#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9191#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9103#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9104#L349-21 assume !(1 == ~t3_pc~0); 9339#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 9475#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9487#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9449#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9450#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9175#L368-21 assume 1 == ~t4_pc~0; 9065#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9066#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8981#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8982#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8994#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8995#L387-21 assume 1 == ~t5_pc~0; 9054#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9373#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8987#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8988#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9098#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9099#L667-3 assume !(1 == ~M_E~0); 9082#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9083#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9155#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9156#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9485#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9195#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9196#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9825#L702-3 assume !(1 == ~E_2~0); 9824#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9823#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9822#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9418#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9419#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9023#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9489#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9315#L947 assume !(0 == start_simulation_~tmp~3#1); 9316#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9319#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9283#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9451#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 9483#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9484#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9569#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9563#L960 assume !(0 != start_simulation_~tmp___0~1#1); 9445#L928-2 [2022-11-16 11:13:47,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:47,634 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2022-11-16 11:13:47,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:47,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268516717] [2022-11-16 11:13:47,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:47,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:47,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:47,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:47,710 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:47,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268516717] [2022-11-16 11:13:47,711 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268516717] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:47,711 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:47,711 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:47,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351196248] [2022-11-16 11:13:47,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:47,712 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:47,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:47,713 INFO L85 PathProgramCache]: Analyzing trace with hash -1287977041, now seen corresponding path program 1 times [2022-11-16 11:13:47,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:47,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584230163] [2022-11-16 11:13:47,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:47,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:47,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:47,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:47,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:47,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1584230163] [2022-11-16 11:13:47,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1584230163] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:47,781 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:47,782 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:13:47,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169169031] [2022-11-16 11:13:47,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:47,782 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:47,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:47,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:13:47,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:13:47,784 INFO L87 Difference]: Start difference. First operand 969 states and 1417 transitions. cyclomatic complexity: 449 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:48,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:48,035 INFO L93 Difference]: Finished difference Result 2592 states and 3726 transitions. [2022-11-16 11:13:48,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2592 states and 3726 transitions. [2022-11-16 11:13:48,052 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2417 [2022-11-16 11:13:48,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2592 states to 2592 states and 3726 transitions. [2022-11-16 11:13:48,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2592 [2022-11-16 11:13:48,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2592 [2022-11-16 11:13:48,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2592 states and 3726 transitions. [2022-11-16 11:13:48,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:48,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2592 states and 3726 transitions. [2022-11-16 11:13:48,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2592 states and 3726 transitions. [2022-11-16 11:13:48,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2592 to 2432. [2022-11-16 11:13:48,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2432 states, 2432 states have (on average 1.444078947368421) internal successors, (3512), 2431 states have internal predecessors, (3512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:48,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2432 states to 2432 states and 3512 transitions. [2022-11-16 11:13:48,115 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2432 states and 3512 transitions. [2022-11-16 11:13:48,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:13:48,116 INFO L428 stractBuchiCegarLoop]: Abstraction has 2432 states and 3512 transitions. [2022-11-16 11:13:48,116 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 11:13:48,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2432 states and 3512 transitions. [2022-11-16 11:13:48,128 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2345 [2022-11-16 11:13:48,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:48,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:48,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:48,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:48,130 INFO L748 eck$LassoCheckResult]: Stem: 13209#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 13173#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12935#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12569#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12570#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 12949#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12950#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13133#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12921#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12922#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13124#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12917#L599 assume !(0 == ~M_E~0); 12918#L599-2 assume !(0 == ~T1_E~0); 12573#L604-1 assume !(0 == ~T2_E~0); 12562#L609-1 assume !(0 == ~T3_E~0); 12563#L614-1 assume !(0 == ~T4_E~0); 12723#L619-1 assume !(0 == ~T5_E~0); 12849#L624-1 assume !(0 == ~E_M~0); 12954#L629-1 assume !(0 == ~E_1~0); 12650#L634-1 assume !(0 == ~E_2~0); 12651#L639-1 assume !(0 == ~E_3~0); 13065#L644-1 assume !(0 == ~E_4~0); 13081#L649-1 assume !(0 == ~E_5~0); 12613#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12614#L292 assume !(1 == ~m_pc~0); 12733#L292-2 is_master_triggered_~__retres1~0#1 := 0; 12887#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13001#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13179#L743 assume !(0 != activate_threads_~tmp~1#1); 12688#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12689#L311 assume !(1 == ~t1_pc~0); 13064#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12961#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12548#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12549#L751 assume !(0 != activate_threads_~tmp___0~0#1); 12589#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13066#L330 assume !(1 == ~t2_pc~0); 12853#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12734#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12603#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12604#L759 assume !(0 != activate_threads_~tmp___1~0#1); 13170#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12724#L349 assume !(1 == ~t3_pc~0); 12725#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12775#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12943#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12944#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13162#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13163#L368 assume 1 == ~t4_pc~0; 13171#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12808#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12936#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12937#L775 assume !(0 != activate_threads_~tmp___3~0#1); 12574#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12575#L387 assume !(1 == ~t5_pc~0); 12975#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12976#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12686#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12687#L783 assume !(0 != activate_threads_~tmp___4~0#1); 12702#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12795#L667 assume !(1 == ~M_E~0); 12881#L667-2 assume !(1 == ~T1_E~0); 13071#L672-1 assume !(1 == ~T2_E~0); 12834#L677-1 assume !(1 == ~T3_E~0); 12835#L682-1 assume !(1 == ~T4_E~0); 13044#L687-1 assume !(1 == ~T5_E~0); 13120#L692-1 assume !(1 == ~E_M~0); 13032#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13033#L702-1 assume !(1 == ~E_2~0); 13079#L707-1 assume !(1 == ~E_3~0); 12938#L712-1 assume !(1 == ~E_4~0); 12939#L717-1 assume !(1 == ~E_5~0); 13054#L722-1 assume { :end_inline_reset_delta_events } true; 13055#L928-2 [2022-11-16 11:13:48,130 INFO L750 eck$LassoCheckResult]: Loop: 13055#L928-2 assume !false; 14432#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14431#L574 assume !false; 14430#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14426#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13129#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12739#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12618#L499 assume !(0 != eval_~tmp~0#1); 12620#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14880#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14879#L599-3 assume !(0 == ~M_E~0); 13043#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12899#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12900#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12982#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12590#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12591#L624-3 assume !(0 == ~E_M~0); 13040#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13041#L634-3 assume !(0 == ~E_2~0); 13056#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13057#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14874#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12910#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12911#L292-21 assume !(1 == ~m_pc~0); 12796#L292-23 is_master_triggered_~__retres1~0#1 := 0; 12797#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13088#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13089#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12891#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12892#L311-21 assume !(1 == ~t1_pc~0); 14873#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 14872#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12915#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12916#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12731#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12732#L330-21 assume !(1 == ~t2_pc~0); 13021#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 14785#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14780#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14781#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12679#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12680#L349-21 assume !(1 == ~t3_pc~0); 13091#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 13092#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13177#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13178#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13168#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13169#L368-21 assume !(1 == ~t4_pc~0); 12641#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 12640#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12554#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12555#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12564#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12565#L387-21 assume 1 == ~t5_pc~0; 12627#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12973#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13070#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13112#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13113#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12888#L667-3 assume !(1 == ~M_E~0); 12652#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12653#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12729#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12730#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13102#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12773#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12774#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12860#L702-3 assume !(1 == ~E_2~0); 12861#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13000#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12663#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12664#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13026#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14502#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14500#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 14498#L947 assume !(0 == start_simulation_~tmp~3#1); 14494#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14489#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14483#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14481#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 14457#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14456#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14447#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 14441#L960 assume !(0 != start_simulation_~tmp___0~1#1); 13055#L928-2 [2022-11-16 11:13:48,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:48,131 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2022-11-16 11:13:48,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:48,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625623262] [2022-11-16 11:13:48,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:48,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:48,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:48,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:48,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:48,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625623262] [2022-11-16 11:13:48,183 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625623262] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:48,183 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:48,183 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:13:48,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864176748] [2022-11-16 11:13:48,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:48,184 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:48,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:48,185 INFO L85 PathProgramCache]: Analyzing trace with hash -1270845711, now seen corresponding path program 1 times [2022-11-16 11:13:48,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:48,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308712065] [2022-11-16 11:13:48,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:48,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:48,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:48,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:48,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:48,247 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308712065] [2022-11-16 11:13:48,248 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308712065] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:48,248 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:48,248 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:13:48,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81916496] [2022-11-16 11:13:48,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:48,249 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:48,249 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:48,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:13:48,250 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:13:48,250 INFO L87 Difference]: Start difference. First operand 2432 states and 3512 transitions. cyclomatic complexity: 1082 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:48,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:48,516 INFO L93 Difference]: Finished difference Result 6064 states and 8790 transitions. [2022-11-16 11:13:48,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6064 states and 8790 transitions. [2022-11-16 11:13:48,558 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5900 [2022-11-16 11:13:48,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6064 states to 6064 states and 8790 transitions. [2022-11-16 11:13:48,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6064 [2022-11-16 11:13:48,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6064 [2022-11-16 11:13:48,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6064 states and 8790 transitions. [2022-11-16 11:13:48,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:48,605 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6064 states and 8790 transitions. [2022-11-16 11:13:48,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6064 states and 8790 transitions. [2022-11-16 11:13:48,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6064 to 2552. [2022-11-16 11:13:48,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2552 states, 2552 states have (on average 1.4231974921630095) internal successors, (3632), 2551 states have internal predecessors, (3632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:48,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2552 states to 2552 states and 3632 transitions. [2022-11-16 11:13:48,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2552 states and 3632 transitions. [2022-11-16 11:13:48,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 11:13:48,684 INFO L428 stractBuchiCegarLoop]: Abstraction has 2552 states and 3632 transitions. [2022-11-16 11:13:48,684 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 11:13:48,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2552 states and 3632 transitions. [2022-11-16 11:13:48,695 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2462 [2022-11-16 11:13:48,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:48,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:48,696 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:48,696 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:48,696 INFO L748 eck$LassoCheckResult]: Stem: 21740#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 21692#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21435#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21080#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21081#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 21448#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21449#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21653#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21426#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21427#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21648#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21422#L599 assume !(0 == ~M_E~0); 21423#L599-2 assume !(0 == ~T1_E~0); 21084#L604-1 assume !(0 == ~T2_E~0); 21073#L609-1 assume !(0 == ~T3_E~0); 21074#L614-1 assume !(0 == ~T4_E~0); 21231#L619-1 assume !(0 == ~T5_E~0); 21353#L624-1 assume !(0 == ~E_M~0); 21453#L629-1 assume !(0 == ~E_1~0); 21160#L634-1 assume !(0 == ~E_2~0); 21161#L639-1 assume !(0 == ~E_3~0); 21581#L644-1 assume !(0 == ~E_4~0); 21600#L649-1 assume !(0 == ~E_5~0); 21125#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21126#L292 assume !(1 == ~m_pc~0); 21241#L292-2 is_master_triggered_~__retres1~0#1 := 0; 21392#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21510#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21703#L743 assume !(0 != activate_threads_~tmp~1#1); 21197#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21198#L311 assume !(1 == ~t1_pc~0); 21579#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21462#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21059#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21060#L751 assume !(0 != activate_threads_~tmp___0~0#1); 21101#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21583#L330 assume !(1 == ~t2_pc~0); 21357#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21243#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21115#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21116#L759 assume !(0 != activate_threads_~tmp___1~0#1); 21687#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21232#L349 assume !(1 == ~t3_pc~0); 21233#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21543#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21544#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21733#L767 assume !(0 != activate_threads_~tmp___2~0#1); 21681#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21682#L368 assume 1 == ~t4_pc~0; 21688#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21317#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21436#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21437#L775 assume !(0 != activate_threads_~tmp___3~0#1); 21085#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21086#L387 assume !(1 == ~t5_pc~0); 21481#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21482#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21195#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21196#L783 assume !(0 != activate_threads_~tmp___4~0#1); 21212#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21299#L667 assume !(1 == ~M_E~0); 21386#L667-2 assume !(1 == ~T1_E~0); 21587#L672-1 assume !(1 == ~T2_E~0); 21337#L677-1 assume !(1 == ~T3_E~0); 21338#L682-1 assume !(1 == ~T4_E~0); 21555#L687-1 assume !(1 == ~T5_E~0); 21640#L692-1 assume !(1 == ~E_M~0); 21541#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21542#L702-1 assume !(1 == ~E_2~0); 21598#L707-1 assume !(1 == ~E_3~0); 21438#L712-1 assume !(1 == ~E_4~0); 21439#L717-1 assume !(1 == ~E_5~0); 21566#L722-1 assume { :end_inline_reset_delta_events } true; 21567#L928-2 [2022-11-16 11:13:48,697 INFO L750 eck$LassoCheckResult]: Loop: 21567#L928-2 assume !false; 22854#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22853#L574 assume !false; 22852#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22822#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22819#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22818#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22816#L499 assume !(0 != eval_~tmp~0#1); 22817#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23127#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23125#L599-3 assume !(0 == ~M_E~0); 23123#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23121#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23119#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23117#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23116#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23115#L624-3 assume !(0 == ~E_M~0); 23114#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23113#L634-3 assume !(0 == ~E_2~0); 23112#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23111#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23110#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23109#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21539#L292-21 assume !(1 == ~m_pc~0); 21540#L292-23 is_master_triggered_~__retres1~0#1 := 0; 23191#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23190#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23189#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23188#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23187#L311-21 assume !(1 == ~t1_pc~0); 23186#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 23185#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23184#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23183#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23182#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23181#L330-21 assume !(1 == ~t2_pc~0); 23179#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 23178#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23177#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23176#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23175#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23174#L349-21 assume 1 == ~t3_pc~0; 23172#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23170#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23168#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23166#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23081#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23079#L368-21 assume 1 == ~t4_pc~0; 23076#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23073#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23071#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23069#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23067#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23065#L387-21 assume !(1 == ~t5_pc~0); 23062#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 23059#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23057#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23055#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23053#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23049#L667-3 assume !(1 == ~M_E~0); 23048#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23047#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23046#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23045#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23044#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23043#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23042#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23041#L702-3 assume !(1 == ~E_2~0); 23040#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23039#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23038#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23037#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 23035#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 23030#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 23029#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 23028#L947 assume !(0 == start_simulation_~tmp~3#1); 23026#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 23008#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 23002#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 23001#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 23000#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22999#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22998#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 22997#L960 assume !(0 != start_simulation_~tmp___0~1#1); 21567#L928-2 [2022-11-16 11:13:48,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:48,697 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2022-11-16 11:13:48,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:48,698 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323939306] [2022-11-16 11:13:48,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:48,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:48,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:48,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:48,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:48,767 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323939306] [2022-11-16 11:13:48,767 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323939306] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:48,767 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:48,767 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:13:48,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413525939] [2022-11-16 11:13:48,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:48,768 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:48,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:48,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1771139664, now seen corresponding path program 1 times [2022-11-16 11:13:48,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:48,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293251854] [2022-11-16 11:13:48,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:48,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:48,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:48,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:48,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:48,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293251854] [2022-11-16 11:13:48,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1293251854] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:48,823 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:48,823 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:13:48,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428409812] [2022-11-16 11:13:48,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:48,824 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:48,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:48,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:48,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:48,825 INFO L87 Difference]: Start difference. First operand 2552 states and 3632 transitions. cyclomatic complexity: 1082 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:48,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:48,946 INFO L93 Difference]: Finished difference Result 4708 states and 6670 transitions. [2022-11-16 11:13:48,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4708 states and 6670 transitions. [2022-11-16 11:13:48,975 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4597 [2022-11-16 11:13:49,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4708 states to 4708 states and 6670 transitions. [2022-11-16 11:13:49,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4708 [2022-11-16 11:13:49,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4708 [2022-11-16 11:13:49,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4708 states and 6670 transitions. [2022-11-16 11:13:49,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:49,032 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4708 states and 6670 transitions. [2022-11-16 11:13:49,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4708 states and 6670 transitions. [2022-11-16 11:13:49,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4708 to 4696. [2022-11-16 11:13:49,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4696 states, 4696 states have (on average 1.417802385008518) internal successors, (6658), 4695 states have internal predecessors, (6658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:49,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4696 states to 4696 states and 6658 transitions. [2022-11-16 11:13:49,133 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4696 states and 6658 transitions. [2022-11-16 11:13:49,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:49,134 INFO L428 stractBuchiCegarLoop]: Abstraction has 4696 states and 6658 transitions. [2022-11-16 11:13:49,134 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 11:13:49,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4696 states and 6658 transitions. [2022-11-16 11:13:49,158 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4585 [2022-11-16 11:13:49,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:49,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:49,160 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:49,160 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:49,160 INFO L748 eck$LassoCheckResult]: Stem: 28966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 28923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 28704#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28349#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28350#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 28716#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28717#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28894#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28694#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28695#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28888#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28690#L599 assume !(0 == ~M_E~0); 28691#L599-2 assume !(0 == ~T1_E~0); 28353#L604-1 assume !(0 == ~T2_E~0); 28342#L609-1 assume !(0 == ~T3_E~0); 28343#L614-1 assume !(0 == ~T4_E~0); 28498#L619-1 assume !(0 == ~T5_E~0); 28622#L624-1 assume !(0 == ~E_M~0); 28722#L629-1 assume !(0 == ~E_1~0); 28428#L634-1 assume !(0 == ~E_2~0); 28429#L639-1 assume !(0 == ~E_3~0); 28831#L644-1 assume !(0 == ~E_4~0); 28846#L649-1 assume !(0 == ~E_5~0); 28393#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28394#L292 assume !(1 == ~m_pc~0); 28508#L292-2 is_master_triggered_~__retres1~0#1 := 0; 28657#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28769#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28932#L743 assume !(0 != activate_threads_~tmp~1#1); 28465#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28466#L311 assume !(1 == ~t1_pc~0); 28830#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28730#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28328#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28329#L751 assume !(0 != activate_threads_~tmp___0~0#1); 28369#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28833#L330 assume !(1 == ~t2_pc~0); 28625#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28510#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28383#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28384#L759 assume !(0 != activate_threads_~tmp___1~0#1); 28920#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28499#L349 assume !(1 == ~t3_pc~0); 28500#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28797#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28798#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28959#L767 assume !(0 != activate_threads_~tmp___2~0#1); 28915#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28916#L368 assume !(1 == ~t4_pc~0); 28585#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28586#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28705#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28706#L775 assume !(0 != activate_threads_~tmp___3~0#1); 28354#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28355#L387 assume !(1 == ~t5_pc~0); 28742#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28743#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28463#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28464#L783 assume !(0 != activate_threads_~tmp___4~0#1); 28479#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28569#L667 assume !(1 == ~M_E~0); 28651#L667-2 assume !(1 == ~T1_E~0); 28837#L672-1 assume !(1 == ~T2_E~0); 28607#L677-1 assume !(1 == ~T3_E~0); 28608#L682-1 assume !(1 == ~T4_E~0); 28809#L687-1 assume !(1 == ~T5_E~0); 28882#L692-1 assume !(1 == ~E_M~0); 28795#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28796#L702-1 assume !(1 == ~E_2~0); 28844#L707-1 assume !(1 == ~E_3~0); 28707#L712-1 assume !(1 == ~E_4~0); 28708#L717-1 assume !(1 == ~E_5~0); 28820#L722-1 assume { :end_inline_reset_delta_events } true; 28821#L928-2 [2022-11-16 11:13:49,167 INFO L750 eck$LassoCheckResult]: Loop: 28821#L928-2 assume !false; 32147#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32146#L574 assume !false; 32145#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 28949#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 28553#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 28513#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28398#L499 assume !(0 != eval_~tmp~0#1); 28399#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28516#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28517#L599-3 assume !(0 == ~M_E~0); 28764#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28667#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28668#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28953#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28370#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28371#L624-3 assume !(0 == ~E_M~0); 28761#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28806#L634-3 assume !(0 == ~E_2~0); 28881#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32941#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32940#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28680#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28681#L292-21 assume !(1 == ~m_pc~0); 28571#L292-23 is_master_triggered_~__retres1~0#1 := 0; 28445#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28446#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28856#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28660#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28661#L311-21 assume !(1 == ~t1_pc~0); 28587#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 28400#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28401#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28687#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28506#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28507#L330-21 assume !(1 == ~t2_pc~0); 28784#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 28758#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28541#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28542#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28457#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28458#L349-21 assume !(1 == ~t3_pc~0); 28701#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 28859#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28872#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28825#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 28826#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28524#L368-21 assume !(1 == ~t4_pc~0); 28525#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 28852#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28334#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28335#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28344#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28345#L387-21 assume 1 == ~t5_pc~0; 28406#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28740#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28336#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28337#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28450#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28451#L667-3 assume !(1 == ~M_E~0); 28433#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28434#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28504#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28505#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28870#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28547#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28548#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28633#L702-3 assume !(1 == ~E_2~0); 28634#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28767#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28443#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28444#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 28790#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 28376#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 28874#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 30192#L947 assume !(0 == start_simulation_~tmp~3#1); 32368#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 32340#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 32333#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 32330#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 32327#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32324#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32321#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 32318#L960 assume !(0 != start_simulation_~tmp___0~1#1); 28821#L928-2 [2022-11-16 11:13:49,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:49,168 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2022-11-16 11:13:49,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:49,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861750330] [2022-11-16 11:13:49,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:49,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:49,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:49,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:49,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:49,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1861750330] [2022-11-16 11:13:49,249 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1861750330] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:49,249 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:49,249 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:49,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [311920906] [2022-11-16 11:13:49,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:49,250 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:49,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:49,250 INFO L85 PathProgramCache]: Analyzing trace with hash 1178754419, now seen corresponding path program 1 times [2022-11-16 11:13:49,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:49,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935979663] [2022-11-16 11:13:49,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:49,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:49,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:49,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:49,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:49,319 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935979663] [2022-11-16 11:13:49,319 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935979663] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:49,319 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:49,319 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:13:49,319 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145425884] [2022-11-16 11:13:49,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:49,320 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:49,320 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:49,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:13:49,321 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:13:49,321 INFO L87 Difference]: Start difference. First operand 4696 states and 6658 transitions. cyclomatic complexity: 1966 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:49,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:49,500 INFO L93 Difference]: Finished difference Result 7486 states and 10538 transitions. [2022-11-16 11:13:49,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7486 states and 10538 transitions. [2022-11-16 11:13:49,549 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7281 [2022-11-16 11:13:49,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7486 states to 7486 states and 10538 transitions. [2022-11-16 11:13:49,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7486 [2022-11-16 11:13:49,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7486 [2022-11-16 11:13:49,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7486 states and 10538 transitions. [2022-11-16 11:13:49,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:49,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7486 states and 10538 transitions. [2022-11-16 11:13:49,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7486 states and 10538 transitions. [2022-11-16 11:13:49,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7486 to 5425. [2022-11-16 11:13:49,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5425 states, 5425 states have (on average 1.4106912442396313) internal successors, (7653), 5424 states have internal predecessors, (7653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:49,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5425 states to 5425 states and 7653 transitions. [2022-11-16 11:13:49,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5425 states and 7653 transitions. [2022-11-16 11:13:49,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:13:49,710 INFO L428 stractBuchiCegarLoop]: Abstraction has 5425 states and 7653 transitions. [2022-11-16 11:13:49,710 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 11:13:49,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5425 states and 7653 transitions. [2022-11-16 11:13:49,733 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5259 [2022-11-16 11:13:49,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:49,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:49,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:49,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:49,735 INFO L748 eck$LassoCheckResult]: Stem: 41190#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 41140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 40889#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40543#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40544#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 40902#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40903#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41098#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40879#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40880#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41091#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40875#L599 assume !(0 == ~M_E~0); 40876#L599-2 assume !(0 == ~T1_E~0); 40547#L604-1 assume !(0 == ~T2_E~0); 40536#L609-1 assume !(0 == ~T3_E~0); 40537#L614-1 assume !(0 == ~T4_E~0); 40689#L619-1 assume !(0 == ~T5_E~0); 40809#L624-1 assume !(0 == ~E_M~0); 40909#L629-1 assume 0 == ~E_1~0;~E_1~0 := 1; 40623#L634-1 assume !(0 == ~E_2~0); 40624#L639-1 assume !(0 == ~E_3~0); 41085#L644-1 assume !(0 == ~E_4~0); 41086#L649-1 assume !(0 == ~E_5~0); 40588#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40589#L292 assume !(1 == ~m_pc~0); 40844#L292-2 is_master_triggered_~__retres1~0#1 := 0; 40845#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41177#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 41178#L743 assume !(0 != activate_threads_~tmp~1#1); 40659#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40660#L311 assume !(1 == ~t1_pc~0); 41067#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41068#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40522#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40523#L751 assume !(0 != activate_threads_~tmp___0~0#1); 41108#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41109#L330 assume !(1 == ~t2_pc~0); 40982#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40983#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40576#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40577#L759 assume !(0 != activate_threads_~tmp___1~0#1); 41142#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41143#L349 assume !(1 == ~t3_pc~0); 41220#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41219#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41215#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41213#L767 assume !(0 != activate_threads_~tmp___2~0#1); 41212#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41182#L368 assume !(1 == ~t4_pc~0); 41183#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41211#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41210#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41209#L775 assume !(0 != activate_threads_~tmp___3~0#1); 41208#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41207#L387 assume !(1 == ~t5_pc~0); 41205#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41186#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41187#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41204#L783 assume !(0 != activate_threads_~tmp___4~0#1); 41203#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41202#L667 assume !(1 == ~M_E~0); 41201#L667-2 assume !(1 == ~T1_E~0); 41200#L672-1 assume !(1 == ~T2_E~0); 41199#L677-1 assume !(1 == ~T3_E~0); 41198#L682-1 assume !(1 == ~T4_E~0); 41197#L687-1 assume !(1 == ~T5_E~0); 41196#L692-1 assume !(1 == ~E_M~0); 41195#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 40992#L702-1 assume !(1 == ~E_2~0); 41042#L707-1 assume !(1 == ~E_3~0); 40893#L712-1 assume !(1 == ~E_4~0); 40894#L717-1 assume !(1 == ~E_5~0); 41015#L722-1 assume { :end_inline_reset_delta_events } true; 41016#L928-2 [2022-11-16 11:13:49,735 INFO L750 eck$LassoCheckResult]: Loop: 41016#L928-2 assume !false; 44875#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44873#L574 assume !false; 44871#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 44864#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 44859#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 44857#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44851#L499 assume !(0 != eval_~tmp~0#1); 44848#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44844#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44840#L599-3 assume !(0 == ~M_E~0); 44836#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44835#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44834#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44833#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44831#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44830#L624-3 assume !(0 == ~E_M~0); 44828#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44827#L634-3 assume !(0 == ~E_2~0); 44826#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44825#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44824#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44823#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44822#L292-21 assume !(1 == ~m_pc~0); 44821#L292-23 is_master_triggered_~__retres1~0#1 := 0; 44820#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44819#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44818#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44817#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44816#L311-21 assume !(1 == ~t1_pc~0); 44815#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 44814#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44813#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44812#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44811#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44810#L330-21 assume !(1 == ~t2_pc~0); 44808#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 44807#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44806#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44805#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44804#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44803#L349-21 assume 1 == ~t3_pc~0; 44801#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44799#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44797#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44795#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44794#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44793#L368-21 assume !(1 == ~t4_pc~0); 44792#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 44791#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44790#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44789#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44788#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44787#L387-21 assume !(1 == ~t5_pc~0); 44785#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 44784#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44783#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44782#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44781#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44780#L667-3 assume !(1 == ~M_E~0); 44197#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44779#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44778#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44777#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44776#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44775#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44773#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44770#L702-3 assume !(1 == ~E_2~0); 44768#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44766#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44764#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44762#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 41330#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 41324#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 41319#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 41320#L947 assume !(0 == start_simulation_~tmp~3#1); 41770#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 44918#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 44912#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 44910#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 44908#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44906#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44905#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 44894#L960 assume !(0 != start_simulation_~tmp___0~1#1); 41016#L928-2 [2022-11-16 11:13:49,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:49,736 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2022-11-16 11:13:49,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:49,736 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751038943] [2022-11-16 11:13:49,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:49,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:49,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:49,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:49,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:49,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751038943] [2022-11-16 11:13:49,788 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751038943] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:49,788 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:49,789 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:49,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406360944] [2022-11-16 11:13:49,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:49,789 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:49,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:49,789 INFO L85 PathProgramCache]: Analyzing trace with hash -645879695, now seen corresponding path program 1 times [2022-11-16 11:13:49,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:49,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434135561] [2022-11-16 11:13:49,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:49,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:49,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:49,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:49,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:49,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [434135561] [2022-11-16 11:13:49,863 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [434135561] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:49,863 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:49,864 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:13:49,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1000280994] [2022-11-16 11:13:49,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:49,864 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:49,864 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:49,865 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:13:49,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:13:49,865 INFO L87 Difference]: Start difference. First operand 5425 states and 7653 transitions. cyclomatic complexity: 2232 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:49,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:49,966 INFO L93 Difference]: Finished difference Result 6610 states and 9281 transitions. [2022-11-16 11:13:49,966 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6610 states and 9281 transitions. [2022-11-16 11:13:49,998 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6465 [2022-11-16 11:13:50,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6610 states to 6610 states and 9281 transitions. [2022-11-16 11:13:50,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6610 [2022-11-16 11:13:50,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6610 [2022-11-16 11:13:50,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6610 states and 9281 transitions. [2022-11-16 11:13:50,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:50,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6610 states and 9281 transitions. [2022-11-16 11:13:50,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6610 states and 9281 transitions. [2022-11-16 11:13:50,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6610 to 4696. [2022-11-16 11:13:50,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4696 states, 4696 states have (on average 1.4045996592844974) internal successors, (6596), 4695 states have internal predecessors, (6596), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:50,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4696 states to 4696 states and 6596 transitions. [2022-11-16 11:13:50,147 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4696 states and 6596 transitions. [2022-11-16 11:13:50,148 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:13:50,148 INFO L428 stractBuchiCegarLoop]: Abstraction has 4696 states and 6596 transitions. [2022-11-16 11:13:50,149 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 11:13:50,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4696 states and 6596 transitions. [2022-11-16 11:13:50,165 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4585 [2022-11-16 11:13:50,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:50,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:50,166 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:50,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:50,167 INFO L748 eck$LassoCheckResult]: Stem: 53210#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 53169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 52945#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52590#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52591#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 52956#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52957#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53129#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52933#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52934#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53126#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52929#L599 assume !(0 == ~M_E~0); 52930#L599-2 assume !(0 == ~T1_E~0); 52594#L604-1 assume !(0 == ~T2_E~0); 52583#L609-1 assume !(0 == ~T3_E~0); 52584#L614-1 assume !(0 == ~T4_E~0); 52738#L619-1 assume !(0 == ~T5_E~0); 52861#L624-1 assume !(0 == ~E_M~0); 52962#L629-1 assume !(0 == ~E_1~0); 52670#L634-1 assume !(0 == ~E_2~0); 52671#L639-1 assume !(0 == ~E_3~0); 53073#L644-1 assume !(0 == ~E_4~0); 53089#L649-1 assume !(0 == ~E_5~0); 52634#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52635#L292 assume !(1 == ~m_pc~0); 52748#L292-2 is_master_triggered_~__retres1~0#1 := 0; 52894#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53011#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53179#L743 assume !(0 != activate_threads_~tmp~1#1); 52706#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52707#L311 assume !(1 == ~t1_pc~0); 53071#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52969#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52569#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 52570#L751 assume !(0 != activate_threads_~tmp___0~0#1); 52610#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53075#L330 assume !(1 == ~t2_pc~0); 52864#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 52751#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52624#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 52625#L759 assume !(0 != activate_threads_~tmp___1~0#1); 53164#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52739#L349 assume !(1 == ~t3_pc~0); 52740#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53038#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53039#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53207#L767 assume !(0 != activate_threads_~tmp___2~0#1); 53156#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53157#L368 assume !(1 == ~t4_pc~0); 52823#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 52824#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52946#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52947#L775 assume !(0 != activate_threads_~tmp___3~0#1); 52595#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52596#L387 assume !(1 == ~t5_pc~0); 52984#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52985#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52704#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52705#L783 assume !(0 != activate_threads_~tmp___4~0#1); 52721#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52808#L667 assume !(1 == ~M_E~0); 52889#L667-2 assume !(1 == ~T1_E~0); 53079#L672-1 assume !(1 == ~T2_E~0); 52846#L677-1 assume !(1 == ~T3_E~0); 52847#L682-1 assume !(1 == ~T4_E~0); 53048#L687-1 assume !(1 == ~T5_E~0); 53120#L692-1 assume !(1 == ~E_M~0); 53036#L697-1 assume !(1 == ~E_1~0); 53037#L702-1 assume !(1 == ~E_2~0); 53087#L707-1 assume !(1 == ~E_3~0); 52948#L712-1 assume !(1 == ~E_4~0); 52949#L717-1 assume !(1 == ~E_5~0); 53060#L722-1 assume { :end_inline_reset_delta_events } true; 53061#L928-2 [2022-11-16 11:13:50,167 INFO L750 eck$LassoCheckResult]: Loop: 53061#L928-2 assume !false; 54212#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54211#L574 assume !false; 54210#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54206#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54203#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54202#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54200#L499 assume !(0 != eval_~tmp~0#1); 54199#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54198#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54197#L599-3 assume !(0 == ~M_E~0); 54196#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54195#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54194#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54193#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54192#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54191#L624-3 assume !(0 == ~E_M~0); 54190#L629-3 assume !(0 == ~E_1~0); 54189#L634-3 assume !(0 == ~E_2~0); 54188#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54187#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54186#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54185#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54184#L292-21 assume !(1 == ~m_pc~0); 54183#L292-23 is_master_triggered_~__retres1~0#1 := 0; 54182#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54181#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54180#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 54179#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54178#L311-21 assume !(1 == ~t1_pc~0); 54177#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 54176#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54175#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54174#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54173#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54172#L330-21 assume !(1 == ~t2_pc~0); 54170#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 54169#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54168#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54167#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54166#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54165#L349-21 assume 1 == ~t3_pc~0; 54163#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54161#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54159#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54157#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54156#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54155#L368-21 assume !(1 == ~t4_pc~0); 54154#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 54153#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54152#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54151#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54150#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54149#L387-21 assume !(1 == ~t5_pc~0); 54147#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 54146#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54145#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54144#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54143#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53846#L667-3 assume !(1 == ~M_E~0); 53843#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53841#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53839#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53837#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53835#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53833#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53831#L697-3 assume !(1 == ~E_1~0); 53829#L702-3 assume !(1 == ~E_2~0); 53828#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53827#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53826#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53825#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 53823#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 53812#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 53810#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 53241#L947 assume !(0 == start_simulation_~tmp~3#1); 53242#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54262#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54254#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54248#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 54241#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54235#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54226#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 54220#L960 assume !(0 != start_simulation_~tmp___0~1#1); 53061#L928-2 [2022-11-16 11:13:50,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:50,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2022-11-16 11:13:50,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:50,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538563950] [2022-11-16 11:13:50,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:50,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:50,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:50,179 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:50,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:50,235 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:50,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:50,236 INFO L85 PathProgramCache]: Analyzing trace with hash 438789169, now seen corresponding path program 1 times [2022-11-16 11:13:50,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:50,237 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599767993] [2022-11-16 11:13:50,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:50,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:50,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:50,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:50,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:50,288 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599767993] [2022-11-16 11:13:50,288 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1599767993] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:50,289 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:50,289 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:13:50,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878026305] [2022-11-16 11:13:50,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:50,289 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:50,289 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:50,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:13:50,290 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:13:50,291 INFO L87 Difference]: Start difference. First operand 4696 states and 6596 transitions. cyclomatic complexity: 1904 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:50,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:50,450 INFO L93 Difference]: Finished difference Result 8383 states and 11605 transitions. [2022-11-16 11:13:50,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8383 states and 11605 transitions. [2022-11-16 11:13:50,489 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8240 [2022-11-16 11:13:50,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8383 states to 8383 states and 11605 transitions. [2022-11-16 11:13:50,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8383 [2022-11-16 11:13:50,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8383 [2022-11-16 11:13:50,522 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8383 states and 11605 transitions. [2022-11-16 11:13:50,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:50,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8383 states and 11605 transitions. [2022-11-16 11:13:50,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8383 states and 11605 transitions. [2022-11-16 11:13:50,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8383 to 4732. [2022-11-16 11:13:50,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4732 states, 4732 states have (on average 1.4015215553677092) internal successors, (6632), 4731 states have internal predecessors, (6632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:50,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4732 states to 4732 states and 6632 transitions. [2022-11-16 11:13:50,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4732 states and 6632 transitions. [2022-11-16 11:13:50,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 11:13:50,623 INFO L428 stractBuchiCegarLoop]: Abstraction has 4732 states and 6632 transitions. [2022-11-16 11:13:50,623 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 11:13:50,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4732 states and 6632 transitions. [2022-11-16 11:13:50,639 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4621 [2022-11-16 11:13:50,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:50,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:50,640 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:50,640 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:50,641 INFO L748 eck$LassoCheckResult]: Stem: 66291#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 66260#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 66031#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65685#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65686#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 66043#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66044#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66232#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66020#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66021#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66222#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66016#L599 assume !(0 == ~M_E~0); 66017#L599-2 assume !(0 == ~T1_E~0); 65689#L604-1 assume !(0 == ~T2_E~0); 65678#L609-1 assume !(0 == ~T3_E~0); 65679#L614-1 assume !(0 == ~T4_E~0); 65830#L619-1 assume !(0 == ~T5_E~0); 65950#L624-1 assume !(0 == ~E_M~0); 66049#L629-1 assume !(0 == ~E_1~0); 65764#L634-1 assume !(0 == ~E_2~0); 65765#L639-1 assume !(0 == ~E_3~0); 66164#L644-1 assume !(0 == ~E_4~0); 66184#L649-1 assume !(0 == ~E_5~0); 65729#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65730#L292 assume !(1 == ~m_pc~0); 65840#L292-2 is_master_triggered_~__retres1~0#1 := 0; 65986#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66099#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 66267#L743 assume !(0 != activate_threads_~tmp~1#1); 65800#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65801#L311 assume !(1 == ~t1_pc~0); 66163#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66056#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65664#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65665#L751 assume !(0 != activate_threads_~tmp___0~0#1); 65705#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66165#L330 assume !(1 == ~t2_pc~0); 65953#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65841#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65717#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 65718#L759 assume !(0 != activate_threads_~tmp___1~0#1); 66257#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65831#L349 assume !(1 == ~t3_pc~0); 65832#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 66128#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66129#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66285#L767 assume !(0 != activate_threads_~tmp___2~0#1); 66251#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66252#L368 assume !(1 == ~t4_pc~0); 65910#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 65911#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66033#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66034#L775 assume !(0 != activate_threads_~tmp___3~0#1); 65690#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65691#L387 assume !(1 == ~t5_pc~0); 66070#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 66071#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65796#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65797#L783 assume !(0 != activate_threads_~tmp___4~0#1); 65810#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65897#L667 assume !(1 == ~M_E~0); 65980#L667-2 assume !(1 == ~T1_E~0); 66171#L672-1 assume !(1 == ~T2_E~0); 65935#L677-1 assume !(1 == ~T3_E~0); 65936#L682-1 assume !(1 == ~T4_E~0); 66139#L687-1 assume !(1 == ~T5_E~0); 66218#L692-1 assume !(1 == ~E_M~0); 66126#L697-1 assume !(1 == ~E_1~0); 66127#L702-1 assume !(1 == ~E_2~0); 66183#L707-1 assume !(1 == ~E_3~0); 66035#L712-1 assume !(1 == ~E_4~0); 66036#L717-1 assume !(1 == ~E_5~0); 66152#L722-1 assume { :end_inline_reset_delta_events } true; 66153#L928-2 [2022-11-16 11:13:50,641 INFO L750 eck$LassoCheckResult]: Loop: 66153#L928-2 assume !false; 69284#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69281#L574 assume !false; 66248#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66249#L452 assume !(0 == ~m_st~0); 65883#L456 assume !(0 == ~t1_st~0); 65885#L460 assume !(0 == ~t2_st~0); 66172#L464 assume !(0 == ~t3_st~0); 66223#L468 assume !(0 == ~t4_st~0); 66224#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 66256#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 68471#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 68468#L499 assume !(0 != eval_~tmp~0#1); 68461#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68462#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66093#L599-3 assume !(0 == ~M_E~0); 66094#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 66138#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 69741#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69740#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65706#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65707#L624-3 assume !(0 == ~E_M~0); 66090#L629-3 assume !(0 == ~E_1~0); 66136#L634-3 assume !(0 == ~E_2~0); 66154#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66155#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 66282#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66007#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66008#L292-21 assume !(1 == ~m_pc~0); 65900#L292-23 is_master_triggered_~__retres1~0#1 := 0; 65901#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69732#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69731#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69730#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69729#L311-21 assume !(1 == ~t1_pc~0); 69728#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 69727#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69726#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69725#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69724#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69723#L330-21 assume !(1 == ~t2_pc~0); 69721#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 69720#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65872#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 65873#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65792#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65793#L349-21 assume !(1 == ~t3_pc~0); 69717#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 69715#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69713#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 69711#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 69709#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69708#L368-21 assume !(1 == ~t4_pc~0); 69707#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 69705#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69703#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 69701#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69699#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69697#L387-21 assume !(1 == ~t5_pc~0); 69693#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 69691#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69689#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69687#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 69685#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69682#L667-3 assume !(1 == ~M_E~0); 69681#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69680#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69679#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69678#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69677#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69676#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69675#L697-3 assume !(1 == ~E_1~0); 69674#L702-3 assume !(1 == ~E_2~0); 69673#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69672#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69671#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69670#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 69668#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 69662#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 69660#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 69658#L947 assume !(0 == start_simulation_~tmp~3#1); 69655#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 69653#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 69647#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 69645#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 69643#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69641#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69640#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 69639#L960 assume !(0 != start_simulation_~tmp___0~1#1); 66153#L928-2 [2022-11-16 11:13:50,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:50,642 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2022-11-16 11:13:50,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:50,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918001952] [2022-11-16 11:13:50,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:50,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:50,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:50,653 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:50,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:50,685 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:50,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:50,686 INFO L85 PathProgramCache]: Analyzing trace with hash 382844095, now seen corresponding path program 1 times [2022-11-16 11:13:50,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:50,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550209887] [2022-11-16 11:13:50,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:50,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:50,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:50,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:50,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:50,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550209887] [2022-11-16 11:13:50,798 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550209887] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:50,798 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:50,798 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:13:50,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625760057] [2022-11-16 11:13:50,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:50,799 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:50,799 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:50,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:13:50,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:13:50,800 INFO L87 Difference]: Start difference. First operand 4732 states and 6632 transitions. cyclomatic complexity: 1904 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:51,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:51,039 INFO L93 Difference]: Finished difference Result 10896 states and 15159 transitions. [2022-11-16 11:13:51,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10896 states and 15159 transitions. [2022-11-16 11:13:51,084 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10769 [2022-11-16 11:13:51,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10896 states to 10896 states and 15159 transitions. [2022-11-16 11:13:51,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10896 [2022-11-16 11:13:51,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10896 [2022-11-16 11:13:51,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10896 states and 15159 transitions. [2022-11-16 11:13:51,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:51,143 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10896 states and 15159 transitions. [2022-11-16 11:13:51,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10896 states and 15159 transitions. [2022-11-16 11:13:51,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10896 to 4888. [2022-11-16 11:13:51,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4888 states, 4888 states have (on average 1.3844108019639934) internal successors, (6767), 4887 states have internal predecessors, (6767), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:51,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4888 states to 4888 states and 6767 transitions. [2022-11-16 11:13:51,324 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4888 states and 6767 transitions. [2022-11-16 11:13:51,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 11:13:51,325 INFO L428 stractBuchiCegarLoop]: Abstraction has 4888 states and 6767 transitions. [2022-11-16 11:13:51,325 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 11:13:51,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4888 states and 6767 transitions. [2022-11-16 11:13:51,339 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4777 [2022-11-16 11:13:51,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:51,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:51,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:51,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:51,342 INFO L748 eck$LassoCheckResult]: Stem: 82011#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 81963#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 81691#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81326#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81327#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 81706#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81707#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81913#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81676#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81677#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81905#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81672#L599 assume !(0 == ~M_E~0); 81673#L599-2 assume !(0 == ~T1_E~0); 81330#L604-1 assume !(0 == ~T2_E~0); 81319#L609-1 assume !(0 == ~T3_E~0); 81320#L614-1 assume !(0 == ~T4_E~0); 81476#L619-1 assume !(0 == ~T5_E~0); 81602#L624-1 assume !(0 == ~E_M~0); 81712#L629-1 assume !(0 == ~E_1~0); 81407#L634-1 assume !(0 == ~E_2~0); 81408#L639-1 assume !(0 == ~E_3~0); 81836#L644-1 assume !(0 == ~E_4~0); 81851#L649-1 assume !(0 == ~E_5~0); 81370#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81371#L292 assume !(1 == ~m_pc~0); 81486#L292-2 is_master_triggered_~__retres1~0#1 := 0; 81643#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81761#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81968#L743 assume !(0 != activate_threads_~tmp~1#1); 81443#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81444#L311 assume !(1 == ~t1_pc~0); 81835#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81719#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81305#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81306#L751 assume !(0 != activate_threads_~tmp___0~0#1); 81346#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81838#L330 assume !(1 == ~t2_pc~0); 81606#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81487#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81358#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81359#L759 assume !(0 != activate_threads_~tmp___1~0#1); 81958#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81477#L349 assume !(1 == ~t3_pc~0); 81478#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81796#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81797#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82005#L767 assume !(0 != activate_threads_~tmp___2~0#1); 81950#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81951#L368 assume !(1 == ~t4_pc~0); 81560#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81561#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81693#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81694#L775 assume !(0 != activate_threads_~tmp___3~0#1); 81331#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81332#L387 assume !(1 == ~t5_pc~0); 81736#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81737#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81439#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81440#L783 assume !(0 != activate_threads_~tmp___4~0#1); 81455#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81544#L667 assume !(1 == ~M_E~0); 81637#L667-2 assume !(1 == ~T1_E~0); 81842#L672-1 assume !(1 == ~T2_E~0); 81587#L677-1 assume !(1 == ~T3_E~0); 81588#L682-1 assume !(1 == ~T4_E~0); 81810#L687-1 assume !(1 == ~T5_E~0); 81900#L692-1 assume !(1 == ~E_M~0); 81794#L697-1 assume !(1 == ~E_1~0); 81795#L702-1 assume !(1 == ~E_2~0); 81850#L707-1 assume !(1 == ~E_3~0); 81695#L712-1 assume !(1 == ~E_4~0); 81696#L717-1 assume !(1 == ~E_5~0); 81822#L722-1 assume { :end_inline_reset_delta_events } true; 81823#L928-2 [2022-11-16 11:13:51,342 INFO L750 eck$LassoCheckResult]: Loop: 81823#L928-2 assume !false; 82689#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82687#L574 assume !false; 82685#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 82683#L452 assume !(0 == ~m_st~0); 82681#L456 assume !(0 == ~t1_st~0); 82679#L460 assume !(0 == ~t2_st~0); 82677#L464 assume !(0 == ~t3_st~0); 82675#L468 assume !(0 == ~t4_st~0); 82671#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 82669#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 82667#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 82664#L499 assume !(0 != eval_~tmp~0#1); 82662#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82660#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82658#L599-3 assume !(0 == ~M_E~0); 82656#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 82654#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82652#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82650#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82648#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82646#L624-3 assume !(0 == ~E_M~0); 82644#L629-3 assume !(0 == ~E_1~0); 82642#L634-3 assume !(0 == ~E_2~0); 82640#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 82638#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 82636#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82634#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82632#L292-21 assume !(1 == ~m_pc~0); 82630#L292-23 is_master_triggered_~__retres1~0#1 := 0; 82628#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82626#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 82624#L743-21 assume !(0 != activate_threads_~tmp~1#1); 82622#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82620#L311-21 assume !(1 == ~t1_pc~0); 82618#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 82616#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82614#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82612#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82610#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82607#L330-21 assume !(1 == ~t2_pc~0); 82604#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 82602#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82600#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82598#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82596#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82594#L349-21 assume !(1 == ~t3_pc~0); 82591#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 82587#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82583#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82579#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 82576#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82574#L368-21 assume !(1 == ~t4_pc~0); 82572#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 82570#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82568#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82566#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82564#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82562#L387-21 assume 1 == ~t5_pc~0; 82559#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82556#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82554#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82552#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82550#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82543#L667-3 assume !(1 == ~M_E~0); 82537#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82538#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82527#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82528#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82514#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 82515#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 82501#L697-3 assume !(1 == ~E_1~0); 82502#L702-3 assume !(1 == ~E_2~0); 82490#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82491#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82480#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82481#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 82434#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 82430#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 82761#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 82759#L947 assume !(0 == start_simulation_~tmp~3#1); 82756#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 82723#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 82717#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 82715#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 82714#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82710#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82709#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 82703#L960 assume !(0 != start_simulation_~tmp___0~1#1); 81823#L928-2 [2022-11-16 11:13:51,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:51,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2022-11-16 11:13:51,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:51,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26432813] [2022-11-16 11:13:51,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:51,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:51,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:51,356 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:51,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:51,414 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:51,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:51,415 INFO L85 PathProgramCache]: Analyzing trace with hash -879734976, now seen corresponding path program 1 times [2022-11-16 11:13:51,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:51,415 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347376345] [2022-11-16 11:13:51,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:51,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:51,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:51,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:51,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:51,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347376345] [2022-11-16 11:13:51,471 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347376345] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:51,471 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:51,471 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:51,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828859072] [2022-11-16 11:13:51,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:51,472 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:13:51,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:51,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:51,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:51,473 INFO L87 Difference]: Start difference. First operand 4888 states and 6767 transitions. cyclomatic complexity: 1883 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:51,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:51,566 INFO L93 Difference]: Finished difference Result 8269 states and 11285 transitions. [2022-11-16 11:13:51,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8269 states and 11285 transitions. [2022-11-16 11:13:51,602 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8156 [2022-11-16 11:13:51,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8269 states to 8269 states and 11285 transitions. [2022-11-16 11:13:51,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8269 [2022-11-16 11:13:51,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8269 [2022-11-16 11:13:51,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8269 states and 11285 transitions. [2022-11-16 11:13:51,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:51,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8269 states and 11285 transitions. [2022-11-16 11:13:51,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8269 states and 11285 transitions. [2022-11-16 11:13:51,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8269 to 7957. [2022-11-16 11:13:51,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7957 states, 7957 states have (on average 1.3669724770642202) internal successors, (10877), 7956 states have internal predecessors, (10877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:51,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7957 states to 7957 states and 10877 transitions. [2022-11-16 11:13:51,848 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7957 states and 10877 transitions. [2022-11-16 11:13:51,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:51,859 INFO L428 stractBuchiCegarLoop]: Abstraction has 7957 states and 10877 transitions. [2022-11-16 11:13:51,859 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 11:13:51,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7957 states and 10877 transitions. [2022-11-16 11:13:51,878 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7844 [2022-11-16 11:13:51,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:51,878 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:51,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:51,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:51,880 INFO L748 eck$LassoCheckResult]: Stem: 95107#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 95070#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 94832#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94489#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94490#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 94845#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94846#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95034#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94821#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94822#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95027#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94817#L599 assume !(0 == ~M_E~0); 94818#L599-2 assume !(0 == ~T1_E~0); 94493#L604-1 assume !(0 == ~T2_E~0); 94482#L609-1 assume !(0 == ~T3_E~0); 94483#L614-1 assume !(0 == ~T4_E~0); 94634#L619-1 assume !(0 == ~T5_E~0); 94752#L624-1 assume !(0 == ~E_M~0); 94851#L629-1 assume !(0 == ~E_1~0); 94567#L634-1 assume !(0 == ~E_2~0); 94568#L639-1 assume !(0 == ~E_3~0); 94963#L644-1 assume !(0 == ~E_4~0); 94982#L649-1 assume !(0 == ~E_5~0); 94533#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94534#L292 assume !(1 == ~m_pc~0); 94644#L292-2 is_master_triggered_~__retres1~0#1 := 0; 94789#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94897#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 95077#L743 assume !(0 != activate_threads_~tmp~1#1); 94603#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94604#L311 assume !(1 == ~t1_pc~0); 94962#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94858#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94468#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94469#L751 assume !(0 != activate_threads_~tmp___0~0#1); 94509#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94964#L330 assume !(1 == ~t2_pc~0); 94755#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94645#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94521#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 94522#L759 assume !(0 != activate_threads_~tmp___1~0#1); 95067#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94635#L349 assume !(1 == ~t3_pc~0); 94636#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94927#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94928#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95100#L767 assume !(0 != activate_threads_~tmp___2~0#1); 95061#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95062#L368 assume !(1 == ~t4_pc~0); 94711#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 94712#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94834#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94835#L775 assume !(0 != activate_threads_~tmp___3~0#1); 94494#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94495#L387 assume !(1 == ~t5_pc~0); 94872#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 94873#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94599#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94600#L783 assume !(0 != activate_threads_~tmp___4~0#1); 94613#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94699#L667 assume !(1 == ~M_E~0); 94783#L667-2 assume !(1 == ~T1_E~0); 94969#L672-1 assume !(1 == ~T2_E~0); 94737#L677-1 assume !(1 == ~T3_E~0); 94738#L682-1 assume !(1 == ~T4_E~0); 94939#L687-1 assume !(1 == ~T5_E~0); 95023#L692-1 assume !(1 == ~E_M~0); 94925#L697-1 assume !(1 == ~E_1~0); 94926#L702-1 assume !(1 == ~E_2~0); 94981#L707-1 assume !(1 == ~E_3~0); 94836#L712-1 assume !(1 == ~E_4~0); 94837#L717-1 assume !(1 == ~E_5~0); 94950#L722-1 assume { :end_inline_reset_delta_events } true; 94951#L928-2 assume !false; 99431#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99428#L574 [2022-11-16 11:13:51,882 INFO L750 eck$LassoCheckResult]: Loop: 99428#L574 assume !false; 99426#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 98511#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 98507#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 98505#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 98503#L499 assume 0 != eval_~tmp~0#1; 98500#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 98497#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 98496#L504 assume !(0 == ~t1_st~0); 97276#L518 assume !(0 == ~t2_st~0); 99444#L532 assume !(0 == ~t3_st~0); 99439#L546 assume !(0 == ~t4_st~0); 99435#L560 assume !(0 == ~t5_st~0); 99428#L574 [2022-11-16 11:13:51,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:51,882 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2022-11-16 11:13:51,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:51,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568383533] [2022-11-16 11:13:51,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:51,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:51,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:51,892 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:51,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:51,912 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:51,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:51,912 INFO L85 PathProgramCache]: Analyzing trace with hash 878346699, now seen corresponding path program 1 times [2022-11-16 11:13:51,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:51,913 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246464867] [2022-11-16 11:13:51,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:51,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:51,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:51,916 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:51,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:51,920 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:51,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:51,920 INFO L85 PathProgramCache]: Analyzing trace with hash 136104453, now seen corresponding path program 1 times [2022-11-16 11:13:51,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:51,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282850083] [2022-11-16 11:13:51,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:51,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:51,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:51,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:51,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:51,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282850083] [2022-11-16 11:13:51,958 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282850083] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:51,958 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:51,959 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:51,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1577639366] [2022-11-16 11:13:51,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:52,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:52,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:52,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:52,129 INFO L87 Difference]: Start difference. First operand 7957 states and 10877 transitions. cyclomatic complexity: 2926 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:52,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:52,265 INFO L93 Difference]: Finished difference Result 15130 states and 20503 transitions. [2022-11-16 11:13:52,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15130 states and 20503 transitions. [2022-11-16 11:13:52,406 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14531 [2022-11-16 11:13:52,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15130 states to 15130 states and 20503 transitions. [2022-11-16 11:13:52,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15130 [2022-11-16 11:13:52,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15130 [2022-11-16 11:13:52,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15130 states and 20503 transitions. [2022-11-16 11:13:52,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:52,475 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15130 states and 20503 transitions. [2022-11-16 11:13:52,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15130 states and 20503 transitions. [2022-11-16 11:13:52,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15130 to 14854. [2022-11-16 11:13:52,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14854 states, 14854 states have (on average 1.3557964184731386) internal successors, (20139), 14853 states have internal predecessors, (20139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:52,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14854 states to 14854 states and 20139 transitions. [2022-11-16 11:13:52,822 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14854 states and 20139 transitions. [2022-11-16 11:13:52,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:52,823 INFO L428 stractBuchiCegarLoop]: Abstraction has 14854 states and 20139 transitions. [2022-11-16 11:13:52,823 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 11:13:52,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14854 states and 20139 transitions. [2022-11-16 11:13:52,923 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14255 [2022-11-16 11:13:52,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:52,923 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:52,924 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:52,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:52,924 INFO L748 eck$LassoCheckResult]: Stem: 118297#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 118233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 117947#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 117584#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 117585#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 117960#L414-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 117961#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118189#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118190#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118179#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118180#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 117933#L599 assume !(0 == ~M_E~0); 117934#L599-2 assume !(0 == ~T1_E~0); 117588#L604-1 assume !(0 == ~T2_E~0); 117589#L609-1 assume !(0 == ~T3_E~0); 117733#L614-1 assume !(0 == ~T4_E~0); 117734#L619-1 assume !(0 == ~T5_E~0); 117968#L624-1 assume !(0 == ~E_M~0); 117969#L629-1 assume !(0 == ~E_1~0); 117665#L634-1 assume !(0 == ~E_2~0); 117666#L639-1 assume !(0 == ~E_3~0); 118169#L644-1 assume !(0 == ~E_4~0); 118170#L649-1 assume !(0 == ~E_5~0); 117630#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117631#L292 assume !(1 == ~m_pc~0); 117899#L292-2 is_master_triggered_~__retres1~0#1 := 0; 117900#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118276#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 118277#L743 assume !(0 != activate_threads_~tmp~1#1); 117701#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117702#L311 assume !(1 == ~t1_pc~0); 118148#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 118149#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117563#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 117564#L751 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117606#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118096#L330 assume !(1 == ~t2_pc~0); 117867#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 117746#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117747#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118228#L759 assume !(0 != activate_threads_~tmp___1~0#1); 118229#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117735#L349 assume !(1 == ~t3_pc~0); 117736#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 118052#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118053#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118283#L767 assume !(0 != activate_threads_~tmp___2~0#1); 118284#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118285#L368 assume !(1 == ~t4_pc~0); 118286#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 118163#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117949#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 117950#L775 assume !(0 != activate_threads_~tmp___3~0#1); 118212#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118248#L387 assume !(1 == ~t5_pc~0); 118249#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 118292#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118293#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 117711#L783 assume !(0 != activate_threads_~tmp___4~0#1); 117712#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117893#L667 assume !(1 == ~M_E~0); 117894#L667-2 assume !(1 == ~T1_E~0); 118110#L672-1 assume !(1 == ~T2_E~0); 118111#L677-1 assume !(1 == ~T3_E~0); 118066#L682-1 assume !(1 == ~T4_E~0); 118067#L687-1 assume !(1 == ~T5_E~0); 118242#L692-1 assume !(1 == ~E_M~0); 118243#L697-1 assume !(1 == ~E_1~0); 118274#L702-1 assume !(1 == ~E_2~0); 118275#L707-1 assume !(1 == ~E_3~0); 117951#L712-1 assume !(1 == ~E_4~0); 117952#L717-1 assume !(1 == ~E_5~0); 118079#L722-1 assume { :end_inline_reset_delta_events } true; 118080#L928-2 assume !false; 129783#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129779#L574 [2022-11-16 11:13:52,924 INFO L750 eck$LassoCheckResult]: Loop: 129779#L574 assume !false; 129776#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 129775#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 127044#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 127041#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 127038#L499 assume 0 != eval_~tmp~0#1; 127035#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 127031#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 127032#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 119666#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 129803#L518 assume !(0 == ~t2_st~0); 129799#L532 assume !(0 == ~t3_st~0); 129792#L546 assume !(0 == ~t4_st~0); 129787#L560 assume !(0 == ~t5_st~0); 129779#L574 [2022-11-16 11:13:52,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:52,925 INFO L85 PathProgramCache]: Analyzing trace with hash 1162562755, now seen corresponding path program 1 times [2022-11-16 11:13:52,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:52,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081649753] [2022-11-16 11:13:52,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:52,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:52,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:52,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:52,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:52,960 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081649753] [2022-11-16 11:13:52,961 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081649753] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:52,961 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:52,961 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:52,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266800361] [2022-11-16 11:13:52,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:52,962 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:13:52,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:52,962 INFO L85 PathProgramCache]: Analyzing trace with hash 511053362, now seen corresponding path program 1 times [2022-11-16 11:13:52,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:52,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646333514] [2022-11-16 11:13:52,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:52,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:52,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:52,967 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:52,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:52,971 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:53,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:53,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:53,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:53,106 INFO L87 Difference]: Start difference. First operand 14854 states and 20139 transitions. cyclomatic complexity: 5297 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:53,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:53,173 INFO L93 Difference]: Finished difference Result 12313 states and 16719 transitions. [2022-11-16 11:13:53,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12313 states and 16719 transitions. [2022-11-16 11:13:53,237 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12186 [2022-11-16 11:13:53,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12313 states to 12313 states and 16719 transitions. [2022-11-16 11:13:53,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12313 [2022-11-16 11:13:53,299 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12313 [2022-11-16 11:13:53,299 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12313 states and 16719 transitions. [2022-11-16 11:13:53,315 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:53,315 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12313 states and 16719 transitions. [2022-11-16 11:13:53,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12313 states and 16719 transitions. [2022-11-16 11:13:53,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12313 to 12313. [2022-11-16 11:13:53,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12313 states, 12313 states have (on average 1.3578331844392106) internal successors, (16719), 12312 states have internal predecessors, (16719), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:53,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12313 states to 12313 states and 16719 transitions. [2022-11-16 11:13:53,668 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12313 states and 16719 transitions. [2022-11-16 11:13:53,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:53,669 INFO L428 stractBuchiCegarLoop]: Abstraction has 12313 states and 16719 transitions. [2022-11-16 11:13:53,669 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 11:13:53,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12313 states and 16719 transitions. [2022-11-16 11:13:53,704 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12186 [2022-11-16 11:13:53,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:53,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:53,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:53,705 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:53,705 INFO L748 eck$LassoCheckResult]: Stem: 145396#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 145353#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 145108#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 144757#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 144758#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 145123#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145124#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 145315#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 145094#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 145095#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 145308#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 145090#L599 assume !(0 == ~M_E~0); 145091#L599-2 assume !(0 == ~T1_E~0); 144761#L604-1 assume !(0 == ~T2_E~0); 144750#L609-1 assume !(0 == ~T3_E~0); 144751#L614-1 assume !(0 == ~T4_E~0); 144903#L619-1 assume !(0 == ~T5_E~0); 145023#L624-1 assume !(0 == ~E_M~0); 145129#L629-1 assume !(0 == ~E_1~0); 144836#L634-1 assume !(0 == ~E_2~0); 144837#L639-1 assume !(0 == ~E_3~0); 145245#L644-1 assume !(0 == ~E_4~0); 145265#L649-1 assume !(0 == ~E_5~0); 144802#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144803#L292 assume !(1 == ~m_pc~0); 144913#L292-2 is_master_triggered_~__retres1~0#1 := 0; 145059#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 145177#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 145363#L743 assume !(0 != activate_threads_~tmp~1#1); 144872#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144873#L311 assume !(1 == ~t1_pc~0); 145244#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 145136#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144736#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 144737#L751 assume !(0 != activate_threads_~tmp___0~0#1); 144778#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145246#L330 assume !(1 == ~t2_pc~0); 145026#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 144914#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144790#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144791#L759 assume !(0 != activate_threads_~tmp___1~0#1); 145350#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144904#L349 assume !(1 == ~t3_pc~0); 144905#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 145209#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145210#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 145387#L767 assume !(0 != activate_threads_~tmp___2~0#1); 145342#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145343#L368 assume !(1 == ~t4_pc~0); 144981#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 144982#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 145111#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 145112#L775 assume !(0 != activate_threads_~tmp___3~0#1); 144762#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144763#L387 assume !(1 == ~t5_pc~0); 145149#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 145150#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144868#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 144869#L783 assume !(0 != activate_threads_~tmp___4~0#1); 144883#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144967#L667 assume !(1 == ~M_E~0); 145053#L667-2 assume !(1 == ~T1_E~0); 145251#L672-1 assume !(1 == ~T2_E~0); 145008#L677-1 assume !(1 == ~T3_E~0); 145009#L682-1 assume !(1 == ~T4_E~0); 145220#L687-1 assume !(1 == ~T5_E~0); 145302#L692-1 assume !(1 == ~E_M~0); 145207#L697-1 assume !(1 == ~E_1~0); 145208#L702-1 assume !(1 == ~E_2~0); 145264#L707-1 assume !(1 == ~E_3~0); 145113#L712-1 assume !(1 == ~E_4~0); 145114#L717-1 assume !(1 == ~E_5~0); 145231#L722-1 assume { :end_inline_reset_delta_events } true; 145232#L928-2 assume !false; 150065#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 150062#L574 [2022-11-16 11:13:53,705 INFO L750 eck$LassoCheckResult]: Loop: 150062#L574 assume !false; 150060#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 150057#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 150055#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 149901#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 149899#L499 assume 0 != eval_~tmp~0#1; 149897#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 149894#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 149895#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 145816#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 145817#L518 assume !(0 == ~t2_st~0); 150771#L532 assume !(0 == ~t3_st~0); 150765#L546 assume !(0 == ~t4_st~0); 150069#L560 assume !(0 == ~t5_st~0); 150062#L574 [2022-11-16 11:13:53,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:53,707 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2022-11-16 11:13:53,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:53,707 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981209969] [2022-11-16 11:13:53,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:53,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:53,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:53,718 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:53,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:53,750 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:53,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:53,751 INFO L85 PathProgramCache]: Analyzing trace with hash 511053362, now seen corresponding path program 2 times [2022-11-16 11:13:53,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:53,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983323900] [2022-11-16 11:13:53,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:53,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:53,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:53,755 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:53,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:53,760 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:53,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:53,761 INFO L85 PathProgramCache]: Analyzing trace with hash -1023619784, now seen corresponding path program 1 times [2022-11-16 11:13:53,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:53,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707851541] [2022-11-16 11:13:53,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:53,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:53,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:53,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:53,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:53,801 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707851541] [2022-11-16 11:13:53,801 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707851541] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:53,801 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:53,801 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:53,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536690177] [2022-11-16 11:13:53,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:53,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:53,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:53,935 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:53,935 INFO L87 Difference]: Start difference. First operand 12313 states and 16719 transitions. cyclomatic complexity: 4412 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:54,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:54,082 INFO L93 Difference]: Finished difference Result 22957 states and 31085 transitions. [2022-11-16 11:13:54,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22957 states and 31085 transitions. [2022-11-16 11:13:54,437 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 22784 [2022-11-16 11:13:54,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22957 states to 22957 states and 31085 transitions. [2022-11-16 11:13:54,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22957 [2022-11-16 11:13:54,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22957 [2022-11-16 11:13:54,522 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22957 states and 31085 transitions. [2022-11-16 11:13:54,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:54,538 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22957 states and 31085 transitions. [2022-11-16 11:13:54,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22957 states and 31085 transitions. [2022-11-16 11:13:54,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22957 to 21967. [2022-11-16 11:13:54,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21967 states, 21967 states have (on average 1.3568989848408977) internal successors, (29807), 21966 states have internal predecessors, (29807), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:54,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21967 states to 21967 states and 29807 transitions. [2022-11-16 11:13:54,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21967 states and 29807 transitions. [2022-11-16 11:13:54,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:54,918 INFO L428 stractBuchiCegarLoop]: Abstraction has 21967 states and 29807 transitions. [2022-11-16 11:13:54,918 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 11:13:54,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21967 states and 29807 transitions. [2022-11-16 11:13:54,981 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 21794 [2022-11-16 11:13:54,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:54,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:54,982 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:54,982 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:54,982 INFO L748 eck$LassoCheckResult]: Stem: 180694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 180654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 180384#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 180035#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180036#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 180400#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 180401#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 180610#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 180375#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 180376#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 180605#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 180371#L599 assume !(0 == ~M_E~0); 180372#L599-2 assume !(0 == ~T1_E~0); 180039#L604-1 assume !(0 == ~T2_E~0); 180028#L609-1 assume !(0 == ~T3_E~0); 180029#L614-1 assume !(0 == ~T4_E~0); 180183#L619-1 assume !(0 == ~T5_E~0); 180302#L624-1 assume !(0 == ~E_M~0); 180407#L629-1 assume !(0 == ~E_1~0); 180114#L634-1 assume !(0 == ~E_2~0); 180115#L639-1 assume !(0 == ~E_3~0); 180534#L644-1 assume !(0 == ~E_4~0); 180551#L649-1 assume !(0 == ~E_5~0); 180079#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 180080#L292 assume !(1 == ~m_pc~0); 180193#L292-2 is_master_triggered_~__retres1~0#1 := 0; 180338#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 180457#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 180661#L743 assume !(0 != activate_threads_~tmp~1#1); 180150#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 180151#L311 assume !(1 == ~t1_pc~0); 180533#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 180413#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180014#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 180015#L751 assume !(0 != activate_threads_~tmp___0~0#1); 180055#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180536#L330 assume !(1 == ~t2_pc~0); 180306#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 180196#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180069#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 180070#L759 assume !(0 != activate_threads_~tmp___1~0#1); 180649#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180184#L349 assume !(1 == ~t3_pc~0); 180185#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 180493#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180494#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 180689#L767 assume !(0 != activate_threads_~tmp___2~0#1); 180640#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180641#L368 assume !(1 == ~t4_pc~0); 180264#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 180265#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180385#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 180386#L775 assume !(0 != activate_threads_~tmp___3~0#1); 180040#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 180041#L387 assume !(1 == ~t5_pc~0); 180428#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 180429#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180148#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 180149#L783 assume !(0 != activate_threads_~tmp___4~0#1); 180166#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180250#L667 assume !(1 == ~M_E~0); 180332#L667-2 assume !(1 == ~T1_E~0); 180542#L672-1 assume !(1 == ~T2_E~0); 180287#L677-1 assume !(1 == ~T3_E~0); 180288#L682-1 assume !(1 == ~T4_E~0); 180508#L687-1 assume !(1 == ~T5_E~0); 180598#L692-1 assume !(1 == ~E_M~0); 180491#L697-1 assume !(1 == ~E_1~0); 180492#L702-1 assume !(1 == ~E_2~0); 180549#L707-1 assume !(1 == ~E_3~0); 180387#L712-1 assume !(1 == ~E_4~0); 180388#L717-1 assume !(1 == ~E_5~0); 180519#L722-1 assume { :end_inline_reset_delta_events } true; 180520#L928-2 assume !false; 192337#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 192335#L574 [2022-11-16 11:13:54,983 INFO L750 eck$LassoCheckResult]: Loop: 192335#L574 assume !false; 192333#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 192330#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 192326#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 192324#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 192322#L499 assume 0 != eval_~tmp~0#1; 192320#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 192318#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 192317#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 192315#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 192313#L518 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 189674#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 192311#L532 assume !(0 == ~t3_st~0); 192305#L546 assume !(0 == ~t4_st~0); 192303#L560 assume !(0 == ~t5_st~0); 192335#L574 [2022-11-16 11:13:54,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:54,983 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2022-11-16 11:13:54,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:54,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739283792] [2022-11-16 11:13:54,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:54,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:54,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:54,992 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:54,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:55,010 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:55,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:55,011 INFO L85 PathProgramCache]: Analyzing trace with hash -1506337788, now seen corresponding path program 1 times [2022-11-16 11:13:55,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:55,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795990340] [2022-11-16 11:13:55,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:55,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:55,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:55,015 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:55,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:55,018 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:55,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:55,019 INFO L85 PathProgramCache]: Analyzing trace with hash -1836565058, now seen corresponding path program 1 times [2022-11-16 11:13:55,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:55,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949630763] [2022-11-16 11:13:55,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:55,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:55,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:55,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:55,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:55,057 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949630763] [2022-11-16 11:13:55,057 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [949630763] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:55,057 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:55,057 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:55,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667681132] [2022-11-16 11:13:55,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:55,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:55,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:55,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:55,203 INFO L87 Difference]: Start difference. First operand 21967 states and 29807 transitions. cyclomatic complexity: 7846 Second operand has 3 states, 3 states have (on average 30.0) internal successors, (90), 3 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:55,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:55,604 INFO L93 Difference]: Finished difference Result 39957 states and 54205 transitions. [2022-11-16 11:13:55,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39957 states and 54205 transitions. [2022-11-16 11:13:55,798 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39692 [2022-11-16 11:13:55,946 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39957 states to 39957 states and 54205 transitions. [2022-11-16 11:13:55,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39957 [2022-11-16 11:13:55,979 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39957 [2022-11-16 11:13:55,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39957 states and 54205 transitions. [2022-11-16 11:13:56,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:56,016 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39957 states and 54205 transitions. [2022-11-16 11:13:56,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39957 states and 54205 transitions. [2022-11-16 11:13:56,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39957 to 38697. [2022-11-16 11:13:56,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38697 states, 38697 states have (on average 1.358890870093289) internal successors, (52585), 38696 states have internal predecessors, (52585), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:56,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38697 states to 38697 states and 52585 transitions. [2022-11-16 11:13:56,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38697 states and 52585 transitions. [2022-11-16 11:13:56,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:56,684 INFO L428 stractBuchiCegarLoop]: Abstraction has 38697 states and 52585 transitions. [2022-11-16 11:13:56,685 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 11:13:56,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38697 states and 52585 transitions. [2022-11-16 11:13:57,003 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 38432 [2022-11-16 11:13:57,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:57,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:57,014 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:57,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:57,031 INFO L748 eck$LassoCheckResult]: Stem: 242640#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 242597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 242320#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 241967#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 241968#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 242333#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 242334#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 242557#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 242309#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 242310#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 242550#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 242305#L599 assume !(0 == ~M_E~0); 242306#L599-2 assume !(0 == ~T1_E~0); 241971#L604-1 assume !(0 == ~T2_E~0); 241960#L609-1 assume !(0 == ~T3_E~0); 241961#L614-1 assume !(0 == ~T4_E~0); 242114#L619-1 assume !(0 == ~T5_E~0); 242235#L624-1 assume !(0 == ~E_M~0); 242339#L629-1 assume !(0 == ~E_1~0); 242045#L634-1 assume !(0 == ~E_2~0); 242046#L639-1 assume !(0 == ~E_3~0); 242477#L644-1 assume !(0 == ~E_4~0); 242495#L649-1 assume !(0 == ~E_5~0); 242010#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 242011#L292 assume !(1 == ~m_pc~0); 242124#L292-2 is_master_triggered_~__retres1~0#1 := 0; 242275#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 242392#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 242605#L743 assume !(0 != activate_threads_~tmp~1#1); 242081#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 242082#L311 assume !(1 == ~t1_pc~0); 242476#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 242346#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 241946#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 241947#L751 assume !(0 != activate_threads_~tmp___0~0#1); 241987#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 242479#L330 assume !(1 == ~t2_pc~0); 242238#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 242125#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 241998#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 241999#L759 assume !(0 != activate_threads_~tmp___1~0#1); 242592#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 242115#L349 assume !(1 == ~t3_pc~0); 242116#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 242436#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 242437#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 242631#L767 assume !(0 != activate_threads_~tmp___2~0#1); 242583#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 242584#L368 assume !(1 == ~t4_pc~0); 242192#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 242193#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 242322#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 242323#L775 assume !(0 != activate_threads_~tmp___3~0#1); 241972#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 241973#L387 assume !(1 == ~t5_pc~0); 242359#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 242360#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 242077#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 242078#L783 assume !(0 != activate_threads_~tmp___4~0#1); 242094#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 242179#L667 assume !(1 == ~M_E~0); 242268#L667-2 assume !(1 == ~T1_E~0); 242485#L672-1 assume !(1 == ~T2_E~0); 242217#L677-1 assume !(1 == ~T3_E~0); 242218#L682-1 assume !(1 == ~T4_E~0); 242451#L687-1 assume !(1 == ~T5_E~0); 242545#L692-1 assume !(1 == ~E_M~0); 242434#L697-1 assume !(1 == ~E_1~0); 242435#L702-1 assume !(1 == ~E_2~0); 242494#L707-1 assume !(1 == ~E_3~0); 242324#L712-1 assume !(1 == ~E_4~0); 242325#L717-1 assume !(1 == ~E_5~0); 242462#L722-1 assume { :end_inline_reset_delta_events } true; 242463#L928-2 assume !false; 266663#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 266662#L574 [2022-11-16 11:13:57,031 INFO L750 eck$LassoCheckResult]: Loop: 266662#L574 assume !false; 266659#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 266656#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 266654#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 266652#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 266650#L499 assume 0 != eval_~tmp~0#1; 266648#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 266645#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 266643#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 266634#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 266628#L518 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 266513#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 266621#L532 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 266679#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 266673#L546 assume !(0 == ~t4_st~0); 266667#L560 assume !(0 == ~t5_st~0); 266662#L574 [2022-11-16 11:13:57,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:57,032 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 4 times [2022-11-16 11:13:57,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:57,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890634410] [2022-11-16 11:13:57,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:57,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:57,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:57,052 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:57,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:57,083 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:57,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:57,084 INFO L85 PathProgramCache]: Analyzing trace with hash 542714873, now seen corresponding path program 1 times [2022-11-16 11:13:57,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:57,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372047061] [2022-11-16 11:13:57,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:57,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:57,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:57,090 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:57,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:57,095 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:57,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:57,096 INFO L85 PathProgramCache]: Analyzing trace with hash -1104395905, now seen corresponding path program 1 times [2022-11-16 11:13:57,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:57,096 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391705253] [2022-11-16 11:13:57,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:57,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:57,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:57,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:57,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:57,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [391705253] [2022-11-16 11:13:57,141 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [391705253] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:57,141 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:57,141 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:13:57,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091739150] [2022-11-16 11:13:57,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:57,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:57,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:57,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:57,332 INFO L87 Difference]: Start difference. First operand 38697 states and 52585 transitions. cyclomatic complexity: 13894 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:57,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:57,567 INFO L93 Difference]: Finished difference Result 44799 states and 60795 transitions. [2022-11-16 11:13:57,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44799 states and 60795 transitions. [2022-11-16 11:13:57,737 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 44578 [2022-11-16 11:13:57,870 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44799 states to 44799 states and 60795 transitions. [2022-11-16 11:13:57,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44799 [2022-11-16 11:13:57,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44799 [2022-11-16 11:13:57,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44799 states and 60795 transitions. [2022-11-16 11:13:57,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:13:57,925 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44799 states and 60795 transitions. [2022-11-16 11:13:57,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44799 states and 60795 transitions. [2022-11-16 11:13:58,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44799 to 44007. [2022-11-16 11:13:58,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44007 states, 44007 states have (on average 1.3585793169268525) internal successors, (59787), 44006 states have internal predecessors, (59787), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:58,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44007 states to 44007 states and 59787 transitions. [2022-11-16 11:13:58,758 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44007 states and 59787 transitions. [2022-11-16 11:13:58,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:13:58,759 INFO L428 stractBuchiCegarLoop]: Abstraction has 44007 states and 59787 transitions. [2022-11-16 11:13:58,759 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-16 11:13:58,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44007 states and 59787 transitions. [2022-11-16 11:13:58,887 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 43786 [2022-11-16 11:13:58,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:13:58,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:13:58,888 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:58,888 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:13:58,888 INFO L748 eck$LassoCheckResult]: Stem: 326169#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 326118#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 325819#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 325471#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 325472#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 325834#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 325835#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 326066#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 325803#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 325804#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 326055#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 325799#L599 assume !(0 == ~M_E~0); 325800#L599-2 assume !(0 == ~T1_E~0); 325475#L604-1 assume !(0 == ~T2_E~0); 325464#L609-1 assume !(0 == ~T3_E~0); 325465#L614-1 assume !(0 == ~T4_E~0); 325617#L619-1 assume !(0 == ~T5_E~0); 325735#L624-1 assume !(0 == ~E_M~0); 325840#L629-1 assume !(0 == ~E_1~0); 325550#L634-1 assume !(0 == ~E_2~0); 325551#L639-1 assume !(0 == ~E_3~0); 325978#L644-1 assume !(0 == ~E_4~0); 326000#L649-1 assume !(0 == ~E_5~0); 325513#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 325514#L292 assume !(1 == ~m_pc~0); 325627#L292-2 is_master_triggered_~__retres1~0#1 := 0; 325772#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 325897#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 326126#L743 assume !(0 != activate_threads_~tmp~1#1); 325586#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 325587#L311 assume !(1 == ~t1_pc~0); 325977#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 325846#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 325450#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 325451#L751 assume !(0 != activate_threads_~tmp___0~0#1); 325491#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 325981#L330 assume !(1 == ~t2_pc~0); 325739#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 325628#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 325502#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 325503#L759 assume !(0 != activate_threads_~tmp___1~0#1); 326113#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 325618#L349 assume !(1 == ~t3_pc~0); 325619#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 325937#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 325938#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 326161#L767 assume !(0 != activate_threads_~tmp___2~0#1); 326103#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 326104#L368 assume !(1 == ~t4_pc~0); 325694#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 325695#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 325821#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 325822#L775 assume !(0 != activate_threads_~tmp___3~0#1); 325476#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 325477#L387 assume !(1 == ~t5_pc~0); 325862#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 325863#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 325582#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 325583#L783 assume !(0 != activate_threads_~tmp___4~0#1); 325596#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 325682#L667 assume !(1 == ~M_E~0); 325766#L667-2 assume !(1 == ~T1_E~0); 325986#L672-1 assume !(1 == ~T2_E~0); 325719#L677-1 assume !(1 == ~T3_E~0); 325720#L682-1 assume !(1 == ~T4_E~0); 325953#L687-1 assume !(1 == ~T5_E~0); 326050#L692-1 assume !(1 == ~E_M~0); 325935#L697-1 assume !(1 == ~E_1~0); 325936#L702-1 assume !(1 == ~E_2~0); 325999#L707-1 assume !(1 == ~E_3~0); 325823#L712-1 assume !(1 == ~E_4~0); 325824#L717-1 assume !(1 == ~E_5~0); 325965#L722-1 assume { :end_inline_reset_delta_events } true; 325966#L928-2 assume !false; 362996#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 362994#L574 [2022-11-16 11:13:58,889 INFO L750 eck$LassoCheckResult]: Loop: 362994#L574 assume !false; 362992#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 362989#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 362987#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 362985#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 362983#L499 assume 0 != eval_~tmp~0#1; 362981#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 362979#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 362976#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 362973#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 362971#L518 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 362868#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 360990#L532 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 358467#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 358462#L546 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 358463#L563 assume !(0 != eval_~tmp_ndt_5~0#1); 362103#L560 assume !(0 == ~t5_st~0); 362994#L574 [2022-11-16 11:13:58,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:58,890 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 5 times [2022-11-16 11:13:58,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:58,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339222532] [2022-11-16 11:13:58,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:58,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:58,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:58,899 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:58,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:58,919 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:58,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:58,920 INFO L85 PathProgramCache]: Analyzing trace with hash -355882435, now seen corresponding path program 1 times [2022-11-16 11:13:58,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:58,920 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493576150] [2022-11-16 11:13:58,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:58,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:58,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:58,923 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:13:58,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:13:58,927 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:13:58,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:13:58,928 INFO L85 PathProgramCache]: Analyzing trace with hash 123290999, now seen corresponding path program 1 times [2022-11-16 11:13:58,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:13:58,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461765701] [2022-11-16 11:13:58,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:13:58,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:13:58,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:13:58,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:13:58,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:13:58,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461765701] [2022-11-16 11:13:58,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [461765701] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:13:58,969 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:13:58,970 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:13:58,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495349103] [2022-11-16 11:13:58,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:13:59,175 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:13:59,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:13:59,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:13:59,176 INFO L87 Difference]: Start difference. First operand 44007 states and 59787 transitions. cyclomatic complexity: 15786 Second operand has 3 states, 2 states have (on average 46.0) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:13:59,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:13:59,536 INFO L93 Difference]: Finished difference Result 76657 states and 103983 transitions. [2022-11-16 11:13:59,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76657 states and 103983 transitions. [2022-11-16 11:14:00,266 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 76296 [2022-11-16 11:14:00,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76657 states to 76657 states and 103983 transitions. [2022-11-16 11:14:00,523 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76657 [2022-11-16 11:14:00,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76657 [2022-11-16 11:14:00,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76657 states and 103983 transitions. [2022-11-16 11:14:00,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:14:00,624 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76657 states and 103983 transitions. [2022-11-16 11:14:00,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76657 states and 103983 transitions. [2022-11-16 11:14:01,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76657 to 75921. [2022-11-16 11:14:01,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75921 states, 75921 states have (on average 1.359926765980427) internal successors, (103247), 75920 states have internal predecessors, (103247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:14:01,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75921 states to 75921 states and 103247 transitions. [2022-11-16 11:14:01,894 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75921 states and 103247 transitions. [2022-11-16 11:14:01,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:14:01,895 INFO L428 stractBuchiCegarLoop]: Abstraction has 75921 states and 103247 transitions. [2022-11-16 11:14:01,896 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-16 11:14:01,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75921 states and 103247 transitions. [2022-11-16 11:14:02,150 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 75560 [2022-11-16 11:14:02,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:14:02,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:14:02,152 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:14:02,152 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:14:02,153 INFO L748 eck$LassoCheckResult]: Stem: 446862#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~local~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 446808#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 446501#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 446143#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 446144#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 446515#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 446516#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 446754#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 446487#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 446488#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 446747#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 446483#L599 assume !(0 == ~M_E~0); 446484#L599-2 assume !(0 == ~T1_E~0); 446147#L604-1 assume !(0 == ~T2_E~0); 446136#L609-1 assume !(0 == ~T3_E~0); 446137#L614-1 assume !(0 == ~T4_E~0); 446289#L619-1 assume !(0 == ~T5_E~0); 446413#L624-1 assume !(0 == ~E_M~0); 446522#L629-1 assume !(0 == ~E_1~0); 446222#L634-1 assume !(0 == ~E_2~0); 446223#L639-1 assume !(0 == ~E_3~0); 446662#L644-1 assume !(0 == ~E_4~0); 446683#L649-1 assume !(0 == ~E_5~0); 446185#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446186#L292 assume !(1 == ~m_pc~0); 446299#L292-2 is_master_triggered_~__retres1~0#1 := 0; 446452#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 446581#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 446815#L743 assume !(0 != activate_threads_~tmp~1#1); 446258#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 446259#L311 assume !(1 == ~t1_pc~0); 446659#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 446529#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 446122#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 446123#L751 assume !(0 != activate_threads_~tmp___0~0#1); 446163#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 446664#L330 assume !(1 == ~t2_pc~0); 446416#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 446301#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 446176#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 446177#L759 assume !(0 != activate_threads_~tmp___1~0#1); 446802#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 446290#L349 assume !(1 == ~t3_pc~0); 446291#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 446618#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 446619#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 446854#L767 assume !(0 != activate_threads_~tmp___2~0#1); 446789#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 446790#L368 assume !(1 == ~t4_pc~0); 446375#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 446376#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 446502#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 446503#L775 assume !(0 != activate_threads_~tmp___3~0#1); 446148#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 446149#L387 assume !(1 == ~t5_pc~0); 446545#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 446546#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 446256#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 446257#L783 assume !(0 != activate_threads_~tmp___4~0#1); 446272#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 446356#L667 assume !(1 == ~M_E~0); 446446#L667-2 assume !(1 == ~T1_E~0); 446670#L672-1 assume !(1 == ~T2_E~0); 446398#L677-1 assume !(1 == ~T3_E~0); 446399#L682-1 assume !(1 == ~T4_E~0); 446634#L687-1 assume !(1 == ~T5_E~0); 446741#L692-1 assume !(1 == ~E_M~0); 446616#L697-1 assume !(1 == ~E_1~0); 446617#L702-1 assume !(1 == ~E_2~0); 446681#L707-1 assume !(1 == ~E_3~0); 446504#L712-1 assume !(1 == ~E_4~0); 446505#L717-1 assume !(1 == ~E_5~0); 446646#L722-1 assume { :end_inline_reset_delta_events } true; 446647#L928-2 assume !false; 505412#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 505413#L574 [2022-11-16 11:14:02,153 INFO L750 eck$LassoCheckResult]: Loop: 505413#L574 assume !false; 506426#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 506423#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 506421#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 506419#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 506417#L499 assume 0 != eval_~tmp~0#1; 506414#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 506409#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 506407#L504 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 506405#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 506403#L518 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 506361#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 506399#L532 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 510262#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 510260#L546 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 510258#L563 assume !(0 != eval_~tmp_ndt_5~0#1); 506431#L560 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 506429#L577 assume !(0 != eval_~tmp_ndt_6~0#1); 505413#L574 [2022-11-16 11:14:02,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:14:02,154 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 6 times [2022-11-16 11:14:02,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:14:02,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514615051] [2022-11-16 11:14:02,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:14:02,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:14:02,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:14:02,170 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:14:02,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:14:02,198 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:14:02,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:14:02,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1852542400, now seen corresponding path program 1 times [2022-11-16 11:14:02,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:14:02,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166271569] [2022-11-16 11:14:02,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:14:02,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:14:02,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:14:02,205 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:14:02,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:14:02,211 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:14:02,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:14:02,212 INFO L85 PathProgramCache]: Analyzing trace with hash -472950330, now seen corresponding path program 1 times [2022-11-16 11:14:02,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:14:02,212 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548549642] [2022-11-16 11:14:02,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:14:02,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:14:02,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:14:02,227 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:14:02,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:14:02,258 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:14:04,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:14:04,515 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:14:04,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:14:04,768 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.11 11:14:04 BoogieIcfgContainer [2022-11-16 11:14:04,768 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-16 11:14:04,768 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-16 11:14:04,769 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-16 11:14:04,769 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-16 11:14:04,769 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:13:45" (3/4) ... [2022-11-16 11:14:04,774 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-16 11:14:04,871 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/witness.graphml [2022-11-16 11:14:04,871 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-16 11:14:04,872 INFO L158 Benchmark]: Toolchain (without parser) took 21863.00ms. Allocated memory was 138.4MB in the beginning and 11.3GB in the end (delta: 11.2GB). Free memory was 103.8MB in the beginning and 10.1GB in the end (delta: -10.0GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. [2022-11-16 11:14:04,873 INFO L158 Benchmark]: CDTParser took 0.32ms. Allocated memory is still 86.0MB. Free memory was 57.4MB in the beginning and 57.4MB in the end (delta: 21.3kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-16 11:14:04,873 INFO L158 Benchmark]: CACSL2BoogieTranslator took 451.18ms. Allocated memory is still 138.4MB. Free memory was 103.4MB in the beginning and 109.1MB in the end (delta: -5.7MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-16 11:14:04,873 INFO L158 Benchmark]: Boogie Procedure Inliner took 100.54ms. Allocated memory is still 138.4MB. Free memory was 109.1MB in the beginning and 104.1MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-16 11:14:04,874 INFO L158 Benchmark]: Boogie Preprocessor took 112.05ms. Allocated memory is still 138.4MB. Free memory was 104.1MB in the beginning and 99.8MB in the end (delta: 4.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-16 11:14:04,874 INFO L158 Benchmark]: RCFGBuilder took 1527.48ms. Allocated memory is still 138.4MB. Free memory was 99.8MB in the beginning and 104.5MB in the end (delta: -4.7MB). Peak memory consumption was 60.8MB. Max. memory is 16.1GB. [2022-11-16 11:14:04,874 INFO L158 Benchmark]: BuchiAutomizer took 19562.52ms. Allocated memory was 138.4MB in the beginning and 11.3GB in the end (delta: 11.2GB). Free memory was 104.5MB in the beginning and 10.1GB in the end (delta: -10.0GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. [2022-11-16 11:14:04,875 INFO L158 Benchmark]: Witness Printer took 103.08ms. Allocated memory is still 11.3GB. Free memory was 10.1GB in the beginning and 10.1GB in the end (delta: 11.7MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-11-16 11:14:04,876 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32ms. Allocated memory is still 86.0MB. Free memory was 57.4MB in the beginning and 57.4MB in the end (delta: 21.3kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 451.18ms. Allocated memory is still 138.4MB. Free memory was 103.4MB in the beginning and 109.1MB in the end (delta: -5.7MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 100.54ms. Allocated memory is still 138.4MB. Free memory was 109.1MB in the beginning and 104.1MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 112.05ms. Allocated memory is still 138.4MB. Free memory was 104.1MB in the beginning and 99.8MB in the end (delta: 4.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1527.48ms. Allocated memory is still 138.4MB. Free memory was 99.8MB in the beginning and 104.5MB in the end (delta: -4.7MB). Peak memory consumption was 60.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 19562.52ms. Allocated memory was 138.4MB in the beginning and 11.3GB in the end (delta: 11.2GB). Free memory was 104.5MB in the beginning and 10.1GB in the end (delta: -10.0GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. * Witness Printer took 103.08ms. Allocated memory is still 11.3GB. Free memory was 10.1GB in the beginning and 10.1GB in the end (delta: 11.7MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 75921 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 19.3s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 6.4s. Construction of modules took 0.7s. Büchi inclusion checks took 10.7s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 4.9s AutomataMinimizationTime, 21 MinimizatonAttempts, 21684 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 2.9s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 21647 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 21647 mSDsluCounter, 35047 SdHoareTripleChecker+Invalid, 0.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 17054 mSDsCounter, 305 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 624 IncrementalHoareTripleChecker+Invalid, 929 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 305 mSolverCounterUnsat, 17993 mSDtfsCounter, 624 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 494]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L46] int T4_E = 2; [L47] int T5_E = 2; [L30] int m_st ; [L44] int T2_E = 2; [L45] int T3_E = 2; [L43] int T1_E = 2; [L27] int t3_pc = 0; [L29] int t5_pc = 0; [L63] int local ; [L25] int t1_pc = 0; [L37] int t1_i ; [L42] int M_E = 2; [L48] int E_M = 2; [L36] int m_i ; [L31] int t1_st ; [L33] int t3_st ; [L39] int t3_i ; [L38] int t2_i ; [L41] int t5_i ; [L40] int t4_i ; [L35] int t5_st ; [L28] int t4_pc = 0; [L26] int t2_pc = 0; [L61] int token ; [L49] int E_1 = 2; [L24] int m_pc = 0; [L32] int t2_st ; [L51] int E_3 = 2; [L50] int E_2 = 2; [L53] int E_5 = 2; [L34] int t4_st ; [L52] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L928] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L494] COND TRUE 1 [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE !(\read(tmp_ndt_1)) [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE !(\read(tmp_ndt_2)) [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE !(\read(tmp_ndt_3)) [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE !(\read(tmp_ndt_4)) [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE !(\read(tmp_ndt_5)) [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 494]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L46] int T4_E = 2; [L47] int T5_E = 2; [L30] int m_st ; [L44] int T2_E = 2; [L45] int T3_E = 2; [L43] int T1_E = 2; [L27] int t3_pc = 0; [L29] int t5_pc = 0; [L63] int local ; [L25] int t1_pc = 0; [L37] int t1_i ; [L42] int M_E = 2; [L48] int E_M = 2; [L36] int m_i ; [L31] int t1_st ; [L33] int t3_st ; [L39] int t3_i ; [L38] int t2_i ; [L41] int t5_i ; [L40] int t4_i ; [L35] int t5_st ; [L28] int t4_pc = 0; [L26] int t2_pc = 0; [L61] int token ; [L49] int E_1 = 2; [L24] int m_pc = 0; [L32] int t2_st ; [L51] int E_3 = 2; [L50] int E_2 = 2; [L53] int E_5 = 2; [L34] int t4_st ; [L52] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L928] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L494] COND TRUE 1 [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE !(\read(tmp_ndt_1)) [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE !(\read(tmp_ndt_2)) [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE !(\read(tmp_ndt_3)) [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE !(\read(tmp_ndt_4)) [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE !(\read(tmp_ndt_5)) [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-16 11:14:05,423 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b2ade30-2ebb-4d5f-b593-54e55f208fa7/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)