./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 12:48:58,415 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 12:48:58,417 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 12:48:58,436 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 12:48:58,436 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 12:48:58,437 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 12:48:58,439 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 12:48:58,441 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 12:48:58,443 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 12:48:58,444 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 12:48:58,445 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 12:48:58,446 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 12:48:58,446 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 12:48:58,448 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 12:48:58,449 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 12:48:58,450 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 12:48:58,451 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 12:48:58,453 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 12:48:58,455 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 12:48:58,457 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 12:48:58,459 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 12:48:58,461 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 12:48:58,462 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 12:48:58,463 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 12:48:58,467 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 12:48:58,468 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 12:48:58,468 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 12:48:58,469 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 12:48:58,470 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 12:48:58,471 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 12:48:58,472 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 12:48:58,473 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 12:48:58,474 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 12:48:58,475 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 12:48:58,476 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 12:48:58,476 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 12:48:58,477 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 12:48:58,477 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 12:48:58,478 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 12:48:58,479 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 12:48:58,480 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 12:48:58,483 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 12:48:58,522 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 12:48:58,524 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 12:48:58,526 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 12:48:58,526 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 12:48:58,527 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 12:48:58,528 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 12:48:58,528 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 12:48:58,528 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 12:48:58,528 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 12:48:58,529 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 12:48:58,530 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 12:48:58,530 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 12:48:58,530 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 12:48:58,530 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 12:48:58,531 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 12:48:58,531 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 12:48:58,531 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 12:48:58,531 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 12:48:58,531 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 12:48:58,532 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 12:48:58,532 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 12:48:58,532 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 12:48:58,532 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 12:48:58,532 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 12:48:58,533 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 12:48:58,533 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 12:48:58,533 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 12:48:58,535 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 12:48:58,535 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 12:48:58,535 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 12:48:58,535 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 12:48:58,537 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 12:48:58,537 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 [2022-11-16 12:48:58,844 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 12:48:58,877 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 12:48:58,879 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 12:48:58,881 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 12:48:58,882 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 12:48:58,883 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2022-11-16 12:48:58,969 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/data/84c1d5366/b555c82be85049eda85a0e191581a1a5/FLAGb94e85091 [2022-11-16 12:48:59,554 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 12:48:59,555 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2022-11-16 12:48:59,568 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/data/84c1d5366/b555c82be85049eda85a0e191581a1a5/FLAGb94e85091 [2022-11-16 12:48:59,870 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/data/84c1d5366/b555c82be85049eda85a0e191581a1a5 [2022-11-16 12:48:59,872 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 12:48:59,873 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 12:48:59,875 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 12:48:59,875 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 12:48:59,891 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 12:48:59,892 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:48:59" (1/1) ... [2022-11-16 12:48:59,893 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@31eb461 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:48:59, skipping insertion in model container [2022-11-16 12:48:59,894 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:48:59" (1/1) ... [2022-11-16 12:48:59,904 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 12:48:59,964 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 12:49:00,135 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2022-11-16 12:49:00,214 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:49:00,225 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 12:49:00,237 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2022-11-16 12:49:00,294 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:49:00,313 INFO L208 MainTranslator]: Completed translation [2022-11-16 12:49:00,313 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00 WrapperNode [2022-11-16 12:49:00,313 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 12:49:00,314 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 12:49:00,315 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 12:49:00,315 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 12:49:00,321 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,332 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,414 INFO L138 Inliner]: procedures = 42, calls = 52, calls flagged for inlining = 47, calls inlined = 134, statements flattened = 1989 [2022-11-16 12:49:00,414 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 12:49:00,415 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 12:49:00,415 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 12:49:00,415 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 12:49:00,438 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,438 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,446 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,446 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,484 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,538 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,558 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,563 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,574 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 12:49:00,587 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 12:49:00,587 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 12:49:00,587 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 12:49:00,589 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (1/1) ... [2022-11-16 12:49:00,596 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 12:49:00,610 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:49:00,632 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 12:49:00,658 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_416fc0bb-769d-4a8d-b145-85fbc3d536c6/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 12:49:00,681 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 12:49:00,681 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 12:49:00,681 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 12:49:00,682 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 12:49:00,864 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 12:49:00,866 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 12:49:02,253 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 12:49:02,278 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 12:49:02,278 INFO L300 CfgBuilder]: Removed 10 assume(true) statements. [2022-11-16 12:49:02,283 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:49:02 BoogieIcfgContainer [2022-11-16 12:49:02,283 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 12:49:02,285 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 12:49:02,286 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 12:49:02,290 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 12:49:02,290 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:49:02,290 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 12:48:59" (1/3) ... [2022-11-16 12:49:02,291 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6bf5d774 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:49:02, skipping insertion in model container [2022-11-16 12:49:02,291 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:49:02,292 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:49:00" (2/3) ... [2022-11-16 12:49:02,292 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6bf5d774 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:49:02, skipping insertion in model container [2022-11-16 12:49:02,292 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:49:02,293 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:49:02" (3/3) ... [2022-11-16 12:49:02,294 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-1.c [2022-11-16 12:49:02,384 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 12:49:02,384 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 12:49:02,384 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 12:49:02,384 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 12:49:02,384 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 12:49:02,384 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 12:49:02,385 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 12:49:02,385 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 12:49:02,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:02,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 729 [2022-11-16 12:49:02,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:02,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:02,505 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:02,505 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:02,505 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 12:49:02,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:02,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 729 [2022-11-16 12:49:02,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:02,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:02,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:02,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:02,535 INFO L748 eck$LassoCheckResult]: Stem: 411#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 752#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 306#L1141true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 265#L529true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 561#L536true assume !(1 == ~m_i~0);~m_st~0 := 2; 778#L536-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 251#L541-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 149#L546-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 626#L551-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 138#L556-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 577#L561-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 559#L566-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 360#L571-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 648#L769true assume !(0 == ~M_E~0); 377#L769-2true assume !(0 == ~T1_E~0); 402#L774-1true assume !(0 == ~T2_E~0); 665#L779-1true assume !(0 == ~T3_E~0); 539#L784-1true assume !(0 == ~T4_E~0); 357#L789-1true assume !(0 == ~T5_E~0); 457#L794-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 815#L799-1true assume !(0 == ~T7_E~0); 362#L804-1true assume !(0 == ~E_M~0); 393#L809-1true assume !(0 == ~E_1~0); 570#L814-1true assume !(0 == ~E_2~0); 8#L819-1true assume !(0 == ~E_3~0); 185#L824-1true assume !(0 == ~E_4~0); 805#L829-1true assume !(0 == ~E_5~0); 662#L834-1true assume 0 == ~E_6~0;~E_6~0 := 1; 69#L839-1true assume !(0 == ~E_7~0); 463#L844-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 313#L376true assume !(1 == ~m_pc~0); 311#L376-2true is_master_triggered_~__retres1~0#1 := 0; 761#L387true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 625#L388true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45#L955true assume !(0 != activate_threads_~tmp~1#1); 244#L955-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 379#L395true assume 1 == ~t1_pc~0; 60#L396true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 540#L406true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11#L407true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 585#L963true assume !(0 != activate_threads_~tmp___0~0#1); 319#L963-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 825#L414true assume !(1 == ~t2_pc~0); 569#L414-2true is_transmit2_triggered_~__retres1~2#1 := 0; 813#L425true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 177#L426true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567#L971true assume !(0 != activate_threads_~tmp___1~0#1); 679#L971-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 248#L433true assume 1 == ~t3_pc~0; 209#L434true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 691#L444true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 227#L445true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 504#L979true assume !(0 != activate_threads_~tmp___2~0#1); 55#L979-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 779#L452true assume !(1 == ~t4_pc~0); 136#L452-2true is_transmit4_triggered_~__retres1~4#1 := 0; 347#L463true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 401#L464true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 687#L987true assume !(0 != activate_threads_~tmp___3~0#1); 154#L987-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 443#L471true assume 1 == ~t5_pc~0; 743#L472true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 144#L482true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 394#L483true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 811#L995true assume !(0 != activate_threads_~tmp___4~0#1); 650#L995-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 728#L490true assume 1 == ~t6_pc~0; 608#L491true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 352#L501true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 447#L502true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 354#L1003true assume !(0 != activate_threads_~tmp___5~0#1); 255#L1003-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 232#L509true assume !(1 == ~t7_pc~0); 571#L509-2true is_transmit7_triggered_~__retres1~7#1 := 0; 122#L520true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 684#L521true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 156#L1011true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 689#L1011-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 582#L857true assume !(1 == ~M_E~0); 48#L857-2true assume !(1 == ~T1_E~0); 192#L862-1true assume !(1 == ~T2_E~0); 197#L867-1true assume !(1 == ~T3_E~0); 249#L872-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 421#L877-1true assume !(1 == ~T5_E~0); 607#L882-1true assume !(1 == ~T6_E~0); 735#L887-1true assume !(1 == ~T7_E~0); 478#L892-1true assume !(1 == ~E_M~0); 699#L897-1true assume !(1 == ~E_1~0); 204#L902-1true assume !(1 == ~E_2~0); 494#L907-1true assume !(1 == ~E_3~0); 433#L912-1true assume 1 == ~E_4~0;~E_4~0 := 2; 426#L917-1true assume !(1 == ~E_5~0); 670#L922-1true assume !(1 == ~E_6~0); 787#L927-1true assume !(1 == ~E_7~0); 417#L932-1true assume { :end_inline_reset_delta_events } true; 714#L1178-2true [2022-11-16 12:49:02,537 INFO L750 eck$LassoCheckResult]: Loop: 714#L1178-2true assume !false; 406#L1179true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 226#L744true assume !true; 346#L759true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88#L529-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 646#L769-3true assume 0 == ~M_E~0;~M_E~0 := 1; 246#L769-5true assume !(0 == ~T1_E~0); 384#L774-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 97#L779-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 15#L784-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 828#L789-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 9#L794-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 32#L799-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 160#L804-3true assume 0 == ~E_M~0;~E_M~0 := 1; 315#L809-3true assume !(0 == ~E_1~0); 30#L814-3true assume 0 == ~E_2~0;~E_2~0 := 1; 549#L819-3true assume 0 == ~E_3~0;~E_3~0 := 1; 507#L824-3true assume 0 == ~E_4~0;~E_4~0 := 1; 499#L829-3true assume 0 == ~E_5~0;~E_5~0 := 1; 193#L834-3true assume 0 == ~E_6~0;~E_6~0 := 1; 456#L839-3true assume 0 == ~E_7~0;~E_7~0 := 1; 579#L844-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 727#L376-27true assume 1 == ~m_pc~0; 431#L377-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 382#L387-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 484#L388-9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 680#L955-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 821#L955-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 806#L395-27true assume !(1 == ~t1_pc~0); 260#L395-29true is_transmit1_triggered_~__retres1~1#1 := 0; 194#L406-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 516#L407-9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 376#L963-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 252#L963-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 643#L414-27true assume 1 == ~t2_pc~0; 818#L415-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 425#L425-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 658#L426-9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 300#L971-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38#L971-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83#L433-27true assume !(1 == ~t3_pc~0); 303#L433-29true is_transmit3_triggered_~__retres1~3#1 := 0; 257#L444-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 794#L445-9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124#L979-27true assume !(0 != activate_threads_~tmp___2~0#1); 753#L979-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 739#L452-27true assume !(1 == ~t4_pc~0); 391#L452-29true is_transmit4_triggered_~__retres1~4#1 := 0; 543#L463-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 673#L464-9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 638#L987-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 649#L987-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34#L471-27true assume 1 == ~t5_pc~0; 482#L472-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 822#L482-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 578#L483-9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 445#L995-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 380#L995-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 312#L490-27true assume !(1 == ~t6_pc~0); 600#L490-29true is_transmit6_triggered_~__retres1~6#1 := 0; 130#L501-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 613#L502-9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 432#L1003-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 708#L1003-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19#L509-27true assume 1 == ~t7_pc~0; 337#L510-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 532#L520-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 335#L521-9true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 330#L1011-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 801#L1011-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 343#L857-3true assume 1 == ~M_E~0;~M_E~0 := 2; 374#L857-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 784#L862-3true assume !(1 == ~T2_E~0); 729#L867-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 258#L872-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 336#L877-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 762#L882-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 371#L887-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 108#L892-3true assume 1 == ~E_M~0;~E_M~0 := 2; 529#L897-3true assume 1 == ~E_1~0;~E_1~0 := 2; 824#L902-3true assume !(1 == ~E_2~0); 203#L907-3true assume 1 == ~E_3~0;~E_3~0 := 2; 292#L912-3true assume 1 == ~E_4~0;~E_4~0 := 2; 564#L917-3true assume 1 == ~E_5~0;~E_5~0 := 2; 261#L922-3true assume 1 == ~E_6~0;~E_6~0 := 2; 137#L927-3true assume 1 == ~E_7~0;~E_7~0 := 2; 210#L932-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 59#L584-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 460#L626-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 797#L627-1true start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 240#L1197true assume !(0 == start_simulation_~tmp~3#1); 511#L1197-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 86#L584-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 245#L626-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 35#L627-2true stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 741#L1152true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 525#L1159true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 631#L1160true start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 25#L1210true assume !(0 != start_simulation_~tmp___0~1#1); 714#L1178-2true [2022-11-16 12:49:02,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:02,543 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2022-11-16 12:49:02,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:02,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584284581] [2022-11-16 12:49:02,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:02,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:02,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:02,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:02,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:02,858 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584284581] [2022-11-16 12:49:02,859 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584284581] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:02,859 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:02,859 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:02,861 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210408090] [2022-11-16 12:49:02,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:02,866 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:02,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:02,867 INFO L85 PathProgramCache]: Analyzing trace with hash 617978550, now seen corresponding path program 1 times [2022-11-16 12:49:02,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:02,868 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647830454] [2022-11-16 12:49:02,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:02,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:02,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:02,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:02,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:02,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647830454] [2022-11-16 12:49:02,956 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1647830454] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:02,956 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:02,956 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:49:02,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [754578528] [2022-11-16 12:49:02,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:02,960 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:02,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:02,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:02,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:03,003 INFO L87 Difference]: Start difference. First operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:03,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:03,094 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2022-11-16 12:49:03,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1245 transitions. [2022-11-16 12:49:03,101 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:03,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 830 states and 1240 transitions. [2022-11-16 12:49:03,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-11-16 12:49:03,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-11-16 12:49:03,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1240 transitions. [2022-11-16 12:49:03,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:03,126 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1240 transitions. [2022-11-16 12:49:03,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1240 transitions. [2022-11-16 12:49:03,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-11-16 12:49:03,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4939759036144578) internal successors, (1240), 829 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:03,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1240 transitions. [2022-11-16 12:49:03,183 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1240 transitions. [2022-11-16 12:49:03,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:03,189 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1240 transitions. [2022-11-16 12:49:03,189 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 12:49:03,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1240 transitions. [2022-11-16 12:49:03,193 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:03,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:03,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:03,195 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:03,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:03,200 INFO L748 eck$LassoCheckResult]: Stem: 2319#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 2320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2202#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2152#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2153#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2436#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2135#L541-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1975#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1976#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1957#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1958#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2435#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2260#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2261#L769 assume !(0 == ~M_E~0); 2283#L769-2 assume !(0 == ~T1_E~0); 2284#L774-1 assume !(0 == ~T2_E~0); 2311#L779-1 assume !(0 == ~T3_E~0); 2423#L784-1 assume !(0 == ~T4_E~0); 2256#L789-1 assume !(0 == ~T5_E~0); 2257#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2367#L799-1 assume !(0 == ~T7_E~0); 2263#L804-1 assume !(0 == ~E_M~0); 2264#L809-1 assume !(0 == ~E_1~0); 2304#L814-1 assume !(0 == ~E_2~0); 1693#L819-1 assume !(0 == ~E_3~0); 1694#L824-1 assume !(0 == ~E_4~0); 2045#L829-1 assume !(0 == ~E_5~0); 2482#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1829#L839-1 assume !(0 == ~E_7~0); 1830#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2208#L376 assume !(1 == ~m_pc~0); 2195#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2194#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2465#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1776#L955 assume !(0 != activate_threads_~tmp~1#1); 1777#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2128#L395 assume 1 == ~t1_pc~0; 1806#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1807#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1699#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1700#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2212#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2213#L414 assume !(1 == ~t2_pc~0); 1832#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1833#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2031#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2032#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2439#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2131#L433 assume 1 == ~t3_pc~0; 2076#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1946#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2104#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2105#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1797#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1798#L452 assume !(1 == ~t4_pc~0); 1953#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1954#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2244#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2310#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1986#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1987#L471 assume 1 == ~t5_pc~0; 2355#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1969#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1970#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2305#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2474#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2475#L490 assume 1 == ~t6_pc~0; 2458#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2211#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2251#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2254#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2140#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2109#L509 assume !(1 == ~t7_pc~0); 2110#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1927#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1928#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1991#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1992#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2447#L857 assume !(1 == ~M_E~0); 1783#L857-2 assume !(1 == ~T1_E~0); 1784#L862-1 assume !(1 == ~T2_E~0); 2053#L867-1 assume !(1 == ~T3_E~0); 2058#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2132#L877-1 assume !(1 == ~T5_E~0); 2331#L882-1 assume !(1 == ~T6_E~0); 2457#L887-1 assume !(1 == ~T7_E~0); 2381#L892-1 assume !(1 == ~E_M~0); 2382#L897-1 assume !(1 == ~E_1~0); 2068#L902-1 assume !(1 == ~E_2~0); 2069#L907-1 assume !(1 == ~E_3~0); 2348#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2339#L917-1 assume !(1 == ~E_5~0); 2340#L922-1 assume !(1 == ~E_6~0); 2485#L927-1 assume !(1 == ~E_7~0); 2326#L932-1 assume { :end_inline_reset_delta_events } true; 1732#L1178-2 [2022-11-16 12:49:03,200 INFO L750 eck$LassoCheckResult]: Loop: 1732#L1178-2 assume !false; 2315#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1749#L744 assume !false; 2103#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2176#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1767#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1973#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2427#L641 assume !(0 != eval_~tmp~0#1); 2243#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1867#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1868#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2129#L769-5 assume !(0 == ~T1_E~0); 2130#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1884#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1708#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1709#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1695#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1696#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1747#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2001#L809-3 assume !(0 == ~E_1~0); 1743#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1744#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2403#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2398#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2054#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2055#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2366#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2445#L376-27 assume 1 == ~m_pc~0; 2344#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2290#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2291#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2385#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2488#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2509#L395-27 assume !(1 == ~t1_pc~0); 2148#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2056#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2057#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2282#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2136#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2137#L414-27 assume 1 == ~t2_pc~0; 2472#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2337#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2338#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2197#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1759#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1760#L433-27 assume 1 == ~t3_pc~0; 1856#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2142#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2143#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1930#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1931#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2502#L452-27 assume 1 == ~t4_pc~0; 2503#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2302#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2426#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2468#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2469#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1750#L471-27 assume !(1 == ~t5_pc~0); 1751#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2065#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2444#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2358#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2286#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2207#L490-27 assume 1 == ~t6_pc~0; 2106#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1942#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1943#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2346#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2347#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1717#L509-27 assume !(1 == ~t7_pc~0); 1718#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2108#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2233#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2224#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2225#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2239#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2240#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2280#L862-3 assume !(1 == ~T2_E~0); 2500#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2144#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2145#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2234#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2274#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1904#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1905#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2418#L902-3 assume !(1 == ~E_2~0); 2066#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2067#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2186#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2149#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1955#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1956#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1804#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1707#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2369#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2119#L1197 assume !(0 == start_simulation_~tmp~3#1); 2120#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1863#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1827#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1753#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1754#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2415#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2416#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1731#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1732#L1178-2 [2022-11-16 12:49:03,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:03,201 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2022-11-16 12:49:03,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:03,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113252672] [2022-11-16 12:49:03,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:03,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:03,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:03,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:03,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:03,323 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113252672] [2022-11-16 12:49:03,324 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113252672] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:03,324 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:03,324 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:03,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [859169101] [2022-11-16 12:49:03,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:03,325 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:03,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:03,326 INFO L85 PathProgramCache]: Analyzing trace with hash -802393431, now seen corresponding path program 1 times [2022-11-16 12:49:03,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:03,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652045528] [2022-11-16 12:49:03,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:03,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:03,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:03,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:03,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:03,470 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652045528] [2022-11-16 12:49:03,470 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652045528] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:03,470 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:03,471 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:03,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099555312] [2022-11-16 12:49:03,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:03,472 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:03,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:03,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:03,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:03,473 INFO L87 Difference]: Start difference. First operand 830 states and 1240 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:03,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:03,502 INFO L93 Difference]: Finished difference Result 830 states and 1239 transitions. [2022-11-16 12:49:03,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1239 transitions. [2022-11-16 12:49:03,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:03,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1239 transitions. [2022-11-16 12:49:03,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-11-16 12:49:03,516 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-11-16 12:49:03,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1239 transitions. [2022-11-16 12:49:03,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:03,518 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1239 transitions. [2022-11-16 12:49:03,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1239 transitions. [2022-11-16 12:49:03,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-11-16 12:49:03,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4927710843373494) internal successors, (1239), 829 states have internal predecessors, (1239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:03,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1239 transitions. [2022-11-16 12:49:03,545 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1239 transitions. [2022-11-16 12:49:03,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:03,546 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1239 transitions. [2022-11-16 12:49:03,547 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 12:49:03,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1239 transitions. [2022-11-16 12:49:03,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:03,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:03,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:03,555 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:03,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:03,556 INFO L748 eck$LassoCheckResult]: Stem: 3986#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 3987#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3869#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3819#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3820#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 4103#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3802#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3642#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3643#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3624#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3625#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4102#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3927#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3928#L769 assume !(0 == ~M_E~0); 3950#L769-2 assume !(0 == ~T1_E~0); 3951#L774-1 assume !(0 == ~T2_E~0); 3978#L779-1 assume !(0 == ~T3_E~0); 4090#L784-1 assume !(0 == ~T4_E~0); 3923#L789-1 assume !(0 == ~T5_E~0); 3924#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4034#L799-1 assume !(0 == ~T7_E~0); 3930#L804-1 assume !(0 == ~E_M~0); 3931#L809-1 assume !(0 == ~E_1~0); 3971#L814-1 assume !(0 == ~E_2~0); 3360#L819-1 assume !(0 == ~E_3~0); 3361#L824-1 assume !(0 == ~E_4~0); 3712#L829-1 assume !(0 == ~E_5~0); 4149#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3496#L839-1 assume !(0 == ~E_7~0); 3497#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3875#L376 assume !(1 == ~m_pc~0); 3862#L376-2 is_master_triggered_~__retres1~0#1 := 0; 3861#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4132#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3443#L955 assume !(0 != activate_threads_~tmp~1#1); 3444#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3795#L395 assume 1 == ~t1_pc~0; 3473#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3474#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3366#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3367#L963 assume !(0 != activate_threads_~tmp___0~0#1); 3879#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3880#L414 assume !(1 == ~t2_pc~0); 3499#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3500#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3698#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3699#L971 assume !(0 != activate_threads_~tmp___1~0#1); 4106#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3798#L433 assume 1 == ~t3_pc~0; 3743#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3613#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3771#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3772#L979 assume !(0 != activate_threads_~tmp___2~0#1); 3464#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3465#L452 assume !(1 == ~t4_pc~0); 3620#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3621#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3911#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3977#L987 assume !(0 != activate_threads_~tmp___3~0#1); 3653#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3654#L471 assume 1 == ~t5_pc~0; 4022#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3636#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3637#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3972#L995 assume !(0 != activate_threads_~tmp___4~0#1); 4141#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4142#L490 assume 1 == ~t6_pc~0; 4125#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3878#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3918#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3921#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 3807#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3776#L509 assume !(1 == ~t7_pc~0); 3777#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3594#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3595#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3658#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3659#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4114#L857 assume !(1 == ~M_E~0); 3450#L857-2 assume !(1 == ~T1_E~0); 3451#L862-1 assume !(1 == ~T2_E~0); 3720#L867-1 assume !(1 == ~T3_E~0); 3725#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3799#L877-1 assume !(1 == ~T5_E~0); 3998#L882-1 assume !(1 == ~T6_E~0); 4124#L887-1 assume !(1 == ~T7_E~0); 4048#L892-1 assume !(1 == ~E_M~0); 4049#L897-1 assume !(1 == ~E_1~0); 3735#L902-1 assume !(1 == ~E_2~0); 3736#L907-1 assume !(1 == ~E_3~0); 4015#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4006#L917-1 assume !(1 == ~E_5~0); 4007#L922-1 assume !(1 == ~E_6~0); 4152#L927-1 assume !(1 == ~E_7~0); 3993#L932-1 assume { :end_inline_reset_delta_events } true; 3399#L1178-2 [2022-11-16 12:49:03,557 INFO L750 eck$LassoCheckResult]: Loop: 3399#L1178-2 assume !false; 3982#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3416#L744 assume !false; 3770#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3843#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3434#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3640#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4094#L641 assume !(0 != eval_~tmp~0#1); 3910#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3534#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3535#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3796#L769-5 assume !(0 == ~T1_E~0); 3797#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3551#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3375#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3376#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3362#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3363#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3414#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3668#L809-3 assume !(0 == ~E_1~0); 3410#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3411#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4070#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4065#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3721#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3722#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4033#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4112#L376-27 assume 1 == ~m_pc~0; 4011#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3957#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3958#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4052#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4155#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4176#L395-27 assume !(1 == ~t1_pc~0); 3815#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 3723#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3724#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3949#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3803#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3804#L414-27 assume 1 == ~t2_pc~0; 4139#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4004#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4005#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3864#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3426#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3427#L433-27 assume !(1 == ~t3_pc~0); 3522#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 3809#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3810#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3597#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 3598#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4169#L452-27 assume !(1 == ~t4_pc~0); 3968#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 3969#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4093#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4135#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4136#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3417#L471-27 assume !(1 == ~t5_pc~0); 3418#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 3732#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4111#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4025#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3953#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3874#L490-27 assume 1 == ~t6_pc~0; 3773#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3609#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3610#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4013#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4014#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3384#L509-27 assume !(1 == ~t7_pc~0); 3385#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 3775#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3900#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3891#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3892#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3906#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3907#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3947#L862-3 assume !(1 == ~T2_E~0); 4167#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3811#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3812#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3901#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3941#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3571#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3572#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4085#L902-3 assume !(1 == ~E_2~0); 3733#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3734#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3853#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3816#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3622#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3623#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3471#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3374#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4036#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3786#L1197 assume !(0 == start_simulation_~tmp~3#1); 3787#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3530#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3494#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3420#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 3421#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4082#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4083#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3398#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 3399#L1178-2 [2022-11-16 12:49:03,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:03,558 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2022-11-16 12:49:03,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:03,558 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12742327] [2022-11-16 12:49:03,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:03,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:03,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:03,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:03,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:03,687 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12742327] [2022-11-16 12:49:03,688 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12742327] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:03,688 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:03,688 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:03,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636137650] [2022-11-16 12:49:03,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:03,689 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:03,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:03,690 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 1 times [2022-11-16 12:49:03,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:03,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828911815] [2022-11-16 12:49:03,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:03,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:03,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:03,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:03,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:03,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828911815] [2022-11-16 12:49:03,830 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828911815] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:03,830 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:03,830 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:03,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684010629] [2022-11-16 12:49:03,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:03,831 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:03,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:03,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:03,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:03,832 INFO L87 Difference]: Start difference. First operand 830 states and 1239 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:03,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:03,860 INFO L93 Difference]: Finished difference Result 830 states and 1238 transitions. [2022-11-16 12:49:03,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1238 transitions. [2022-11-16 12:49:03,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:03,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1238 transitions. [2022-11-16 12:49:03,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-11-16 12:49:03,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-11-16 12:49:03,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1238 transitions. [2022-11-16 12:49:03,877 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:03,877 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1238 transitions. [2022-11-16 12:49:03,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1238 transitions. [2022-11-16 12:49:03,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-11-16 12:49:03,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.491566265060241) internal successors, (1238), 829 states have internal predecessors, (1238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:03,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1238 transitions. [2022-11-16 12:49:03,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1238 transitions. [2022-11-16 12:49:03,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:03,901 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1238 transitions. [2022-11-16 12:49:03,901 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 12:49:03,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1238 transitions. [2022-11-16 12:49:03,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:03,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:03,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:03,913 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:03,913 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:03,915 INFO L748 eck$LassoCheckResult]: Stem: 5653#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 5654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5536#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5486#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5487#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 5770#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5469#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5309#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5310#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5291#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5292#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5769#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5594#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5595#L769 assume !(0 == ~M_E~0); 5617#L769-2 assume !(0 == ~T1_E~0); 5618#L774-1 assume !(0 == ~T2_E~0); 5645#L779-1 assume !(0 == ~T3_E~0); 5757#L784-1 assume !(0 == ~T4_E~0); 5590#L789-1 assume !(0 == ~T5_E~0); 5591#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5701#L799-1 assume !(0 == ~T7_E~0); 5597#L804-1 assume !(0 == ~E_M~0); 5598#L809-1 assume !(0 == ~E_1~0); 5638#L814-1 assume !(0 == ~E_2~0); 5027#L819-1 assume !(0 == ~E_3~0); 5028#L824-1 assume !(0 == ~E_4~0); 5379#L829-1 assume !(0 == ~E_5~0); 5816#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5163#L839-1 assume !(0 == ~E_7~0); 5164#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5542#L376 assume !(1 == ~m_pc~0); 5529#L376-2 is_master_triggered_~__retres1~0#1 := 0; 5528#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5799#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5110#L955 assume !(0 != activate_threads_~tmp~1#1); 5111#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5462#L395 assume 1 == ~t1_pc~0; 5140#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5141#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5033#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5034#L963 assume !(0 != activate_threads_~tmp___0~0#1); 5546#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5547#L414 assume !(1 == ~t2_pc~0); 5166#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5167#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5365#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5366#L971 assume !(0 != activate_threads_~tmp___1~0#1); 5773#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5465#L433 assume 1 == ~t3_pc~0; 5410#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5280#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5438#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5439#L979 assume !(0 != activate_threads_~tmp___2~0#1); 5131#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5132#L452 assume !(1 == ~t4_pc~0); 5287#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5288#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5578#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5644#L987 assume !(0 != activate_threads_~tmp___3~0#1); 5320#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5321#L471 assume 1 == ~t5_pc~0; 5689#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5303#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5304#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5639#L995 assume !(0 != activate_threads_~tmp___4~0#1); 5808#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5809#L490 assume 1 == ~t6_pc~0; 5792#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5545#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5585#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5588#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 5474#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5443#L509 assume !(1 == ~t7_pc~0); 5444#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5261#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5262#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5325#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5326#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5781#L857 assume !(1 == ~M_E~0); 5117#L857-2 assume !(1 == ~T1_E~0); 5118#L862-1 assume !(1 == ~T2_E~0); 5387#L867-1 assume !(1 == ~T3_E~0); 5392#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5466#L877-1 assume !(1 == ~T5_E~0); 5665#L882-1 assume !(1 == ~T6_E~0); 5791#L887-1 assume !(1 == ~T7_E~0); 5715#L892-1 assume !(1 == ~E_M~0); 5716#L897-1 assume !(1 == ~E_1~0); 5402#L902-1 assume !(1 == ~E_2~0); 5403#L907-1 assume !(1 == ~E_3~0); 5682#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5673#L917-1 assume !(1 == ~E_5~0); 5674#L922-1 assume !(1 == ~E_6~0); 5819#L927-1 assume !(1 == ~E_7~0); 5660#L932-1 assume { :end_inline_reset_delta_events } true; 5066#L1178-2 [2022-11-16 12:49:03,918 INFO L750 eck$LassoCheckResult]: Loop: 5066#L1178-2 assume !false; 5649#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5083#L744 assume !false; 5437#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5510#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5101#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5307#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5761#L641 assume !(0 != eval_~tmp~0#1); 5577#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5201#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5202#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5463#L769-5 assume !(0 == ~T1_E~0); 5464#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5218#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5042#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5043#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5029#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5030#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5081#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5335#L809-3 assume !(0 == ~E_1~0); 5077#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5078#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5737#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5732#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5388#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5389#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5700#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5779#L376-27 assume 1 == ~m_pc~0; 5678#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5624#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5625#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5719#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5822#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5843#L395-27 assume !(1 == ~t1_pc~0); 5482#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5390#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5391#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5616#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5470#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5471#L414-27 assume 1 == ~t2_pc~0; 5806#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5671#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5672#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5531#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5093#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5094#L433-27 assume !(1 == ~t3_pc~0); 5189#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 5476#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5477#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5264#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 5265#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5836#L452-27 assume !(1 == ~t4_pc~0); 5635#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5636#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5760#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5802#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5803#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5084#L471-27 assume !(1 == ~t5_pc~0); 5085#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 5399#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5778#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5692#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5620#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5541#L490-27 assume 1 == ~t6_pc~0; 5440#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5276#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5277#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5680#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5681#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5051#L509-27 assume !(1 == ~t7_pc~0); 5052#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 5442#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5567#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5558#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5559#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5573#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5574#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5614#L862-3 assume !(1 == ~T2_E~0); 5834#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5478#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5479#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5568#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5608#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5238#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5239#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5752#L902-3 assume !(1 == ~E_2~0); 5400#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5401#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5520#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5483#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5289#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5290#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5138#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5041#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5703#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5453#L1197 assume !(0 == start_simulation_~tmp~3#1); 5454#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5197#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5161#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5087#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 5088#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5749#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5750#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5065#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 5066#L1178-2 [2022-11-16 12:49:03,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:03,919 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2022-11-16 12:49:03,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:03,920 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37265504] [2022-11-16 12:49:03,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:03,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:03,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:03,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,003 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37265504] [2022-11-16 12:49:04,003 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37265504] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,004 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,004 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442803505] [2022-11-16 12:49:04,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,006 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:04,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:04,007 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 2 times [2022-11-16 12:49:04,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:04,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517384163] [2022-11-16 12:49:04,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:04,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:04,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:04,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,107 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517384163] [2022-11-16 12:49:04,107 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517384163] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,108 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,108 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721404740] [2022-11-16 12:49:04,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,109 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:04,109 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:04,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:04,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:04,111 INFO L87 Difference]: Start difference. First operand 830 states and 1238 transitions. cyclomatic complexity: 409 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:04,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:04,134 INFO L93 Difference]: Finished difference Result 830 states and 1237 transitions. [2022-11-16 12:49:04,134 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1237 transitions. [2022-11-16 12:49:04,140 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:04,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1237 transitions. [2022-11-16 12:49:04,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-11-16 12:49:04,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-11-16 12:49:04,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1237 transitions. [2022-11-16 12:49:04,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:04,147 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1237 transitions. [2022-11-16 12:49:04,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1237 transitions. [2022-11-16 12:49:04,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-11-16 12:49:04,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4903614457831325) internal successors, (1237), 829 states have internal predecessors, (1237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:04,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1237 transitions. [2022-11-16 12:49:04,165 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1237 transitions. [2022-11-16 12:49:04,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:04,166 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1237 transitions. [2022-11-16 12:49:04,166 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 12:49:04,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1237 transitions. [2022-11-16 12:49:04,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:04,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:04,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:04,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:04,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:04,178 INFO L748 eck$LassoCheckResult]: Stem: 7320#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 7321#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7203#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7153#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7154#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 7437#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7136#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6976#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6977#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6958#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6959#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7436#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7262#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7263#L769 assume !(0 == ~M_E~0); 7285#L769-2 assume !(0 == ~T1_E~0); 7286#L774-1 assume !(0 == ~T2_E~0); 7312#L779-1 assume !(0 == ~T3_E~0); 7424#L784-1 assume !(0 == ~T4_E~0); 7257#L789-1 assume !(0 == ~T5_E~0); 7258#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7368#L799-1 assume !(0 == ~T7_E~0); 7264#L804-1 assume !(0 == ~E_M~0); 7265#L809-1 assume !(0 == ~E_1~0); 7305#L814-1 assume !(0 == ~E_2~0); 6696#L819-1 assume !(0 == ~E_3~0); 6697#L824-1 assume !(0 == ~E_4~0); 7046#L829-1 assume !(0 == ~E_5~0); 7483#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6830#L839-1 assume !(0 == ~E_7~0); 6831#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7209#L376 assume !(1 == ~m_pc~0); 7199#L376-2 is_master_triggered_~__retres1~0#1 := 0; 7198#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7466#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6779#L955 assume !(0 != activate_threads_~tmp~1#1); 6780#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7129#L395 assume 1 == ~t1_pc~0; 6807#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6808#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6702#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6703#L963 assume !(0 != activate_threads_~tmp___0~0#1); 7214#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7215#L414 assume !(1 == ~t2_pc~0); 6833#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6834#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7032#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7033#L971 assume !(0 != activate_threads_~tmp___1~0#1); 7440#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7132#L433 assume 1 == ~t3_pc~0; 7077#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6949#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7107#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7108#L979 assume !(0 != activate_threads_~tmp___2~0#1); 6798#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6799#L452 assume !(1 == ~t4_pc~0); 6954#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6955#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7246#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7311#L987 assume !(0 != activate_threads_~tmp___3~0#1); 6987#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6988#L471 assume 1 == ~t5_pc~0; 7356#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6970#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6971#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7306#L995 assume !(0 != activate_threads_~tmp___4~0#1); 7475#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7476#L490 assume 1 == ~t6_pc~0; 7460#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7212#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7252#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7255#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 7143#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7110#L509 assume !(1 == ~t7_pc~0); 7111#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6933#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6934#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6992#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6993#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7448#L857 assume !(1 == ~M_E~0); 6784#L857-2 assume !(1 == ~T1_E~0); 6785#L862-1 assume !(1 == ~T2_E~0); 7054#L867-1 assume !(1 == ~T3_E~0); 7059#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7133#L877-1 assume !(1 == ~T5_E~0); 7332#L882-1 assume !(1 == ~T6_E~0); 7458#L887-1 assume !(1 == ~T7_E~0); 7382#L892-1 assume !(1 == ~E_M~0); 7383#L897-1 assume !(1 == ~E_1~0); 7071#L902-1 assume !(1 == ~E_2~0); 7072#L907-1 assume !(1 == ~E_3~0); 7351#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7340#L917-1 assume !(1 == ~E_5~0); 7341#L922-1 assume !(1 == ~E_6~0); 7486#L927-1 assume !(1 == ~E_7~0); 7327#L932-1 assume { :end_inline_reset_delta_events } true; 6733#L1178-2 [2022-11-16 12:49:04,178 INFO L750 eck$LassoCheckResult]: Loop: 6733#L1178-2 assume !false; 7316#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6750#L744 assume !false; 7104#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7178#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6768#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6974#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7430#L641 assume !(0 != eval_~tmp~0#1); 7244#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6868#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6869#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7130#L769-5 assume !(0 == ~T1_E~0); 7131#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6887#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6709#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6710#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6698#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6699#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6748#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7003#L809-3 assume !(0 == ~E_1~0); 6746#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6747#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7405#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7399#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7057#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7058#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7367#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7446#L376-27 assume 1 == ~m_pc~0; 7345#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7291#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7292#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7386#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7489#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7510#L395-27 assume 1 == ~t1_pc~0; 7506#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7055#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7056#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7283#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7137#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7138#L414-27 assume 1 == ~t2_pc~0; 7473#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7338#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7339#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7195#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6760#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6761#L433-27 assume !(1 == ~t3_pc~0); 6856#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 7141#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7142#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6929#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 6930#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7503#L452-27 assume 1 == ~t4_pc~0; 7504#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7303#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7427#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7469#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7470#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6751#L471-27 assume !(1 == ~t5_pc~0); 6752#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 7063#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7445#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7359#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7287#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7208#L490-27 assume 1 == ~t6_pc~0; 7105#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6943#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6944#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7347#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7348#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6718#L509-27 assume 1 == ~t7_pc~0; 6720#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7109#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7234#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7225#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7226#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7240#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7241#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7281#L862-3 assume !(1 == ~T2_E~0); 7501#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7145#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7146#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7235#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7275#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6903#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6904#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7419#L902-3 assume !(1 == ~E_2~0); 7067#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7068#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7187#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7150#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6956#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6957#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6805#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6708#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7370#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7120#L1197 assume !(0 == start_simulation_~tmp~3#1); 7121#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6864#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6828#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6754#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 6755#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7416#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7417#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 6732#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 6733#L1178-2 [2022-11-16 12:49:04,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:04,180 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2022-11-16 12:49:04,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:04,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341102638] [2022-11-16 12:49:04,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:04,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:04,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:04,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341102638] [2022-11-16 12:49:04,234 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341102638] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,235 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,235 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1196510997] [2022-11-16 12:49:04,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,236 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:04,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:04,236 INFO L85 PathProgramCache]: Analyzing trace with hash -929852120, now seen corresponding path program 1 times [2022-11-16 12:49:04,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:04,237 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885023304] [2022-11-16 12:49:04,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:04,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:04,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:04,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1885023304] [2022-11-16 12:49:04,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1885023304] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,306 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,307 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203786804] [2022-11-16 12:49:04,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,307 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:04,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:04,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:04,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:04,309 INFO L87 Difference]: Start difference. First operand 830 states and 1237 transitions. cyclomatic complexity: 408 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:04,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:04,331 INFO L93 Difference]: Finished difference Result 830 states and 1236 transitions. [2022-11-16 12:49:04,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1236 transitions. [2022-11-16 12:49:04,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:04,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1236 transitions. [2022-11-16 12:49:04,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-11-16 12:49:04,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-11-16 12:49:04,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1236 transitions. [2022-11-16 12:49:04,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:04,345 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1236 transitions. [2022-11-16 12:49:04,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1236 transitions. [2022-11-16 12:49:04,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-11-16 12:49:04,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.489156626506024) internal successors, (1236), 829 states have internal predecessors, (1236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:04,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1236 transitions. [2022-11-16 12:49:04,361 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1236 transitions. [2022-11-16 12:49:04,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:04,364 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1236 transitions. [2022-11-16 12:49:04,364 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 12:49:04,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1236 transitions. [2022-11-16 12:49:04,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:04,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:04,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:04,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:04,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:04,374 INFO L748 eck$LassoCheckResult]: Stem: 8987#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 8988#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8870#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8820#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8821#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 9104#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8803#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8643#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8644#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8625#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8626#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9103#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8928#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8929#L769 assume !(0 == ~M_E~0); 8951#L769-2 assume !(0 == ~T1_E~0); 8952#L774-1 assume !(0 == ~T2_E~0); 8979#L779-1 assume !(0 == ~T3_E~0); 9091#L784-1 assume !(0 == ~T4_E~0); 8924#L789-1 assume !(0 == ~T5_E~0); 8925#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9035#L799-1 assume !(0 == ~T7_E~0); 8931#L804-1 assume !(0 == ~E_M~0); 8932#L809-1 assume !(0 == ~E_1~0); 8972#L814-1 assume !(0 == ~E_2~0); 8363#L819-1 assume !(0 == ~E_3~0); 8364#L824-1 assume !(0 == ~E_4~0); 8713#L829-1 assume !(0 == ~E_5~0); 9150#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8497#L839-1 assume !(0 == ~E_7~0); 8498#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8876#L376 assume !(1 == ~m_pc~0); 8863#L376-2 is_master_triggered_~__retres1~0#1 := 0; 8862#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9133#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8444#L955 assume !(0 != activate_threads_~tmp~1#1); 8445#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8796#L395 assume 1 == ~t1_pc~0; 8474#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8475#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8367#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8368#L963 assume !(0 != activate_threads_~tmp___0~0#1); 8880#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8881#L414 assume !(1 == ~t2_pc~0); 8500#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8501#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8699#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8700#L971 assume !(0 != activate_threads_~tmp___1~0#1); 9107#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8799#L433 assume 1 == ~t3_pc~0; 8744#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8616#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8774#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8775#L979 assume !(0 != activate_threads_~tmp___2~0#1); 8465#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8466#L452 assume !(1 == ~t4_pc~0); 8621#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8622#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8912#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8978#L987 assume !(0 != activate_threads_~tmp___3~0#1); 8654#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8655#L471 assume 1 == ~t5_pc~0; 9023#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8637#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8638#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8973#L995 assume !(0 != activate_threads_~tmp___4~0#1); 9142#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9143#L490 assume 1 == ~t6_pc~0; 9126#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8879#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8919#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8922#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 8808#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8777#L509 assume !(1 == ~t7_pc~0); 8778#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8597#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8598#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8659#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8660#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9115#L857 assume !(1 == ~M_E~0); 8451#L857-2 assume !(1 == ~T1_E~0); 8452#L862-1 assume !(1 == ~T2_E~0); 8721#L867-1 assume !(1 == ~T3_E~0); 8726#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8800#L877-1 assume !(1 == ~T5_E~0); 8999#L882-1 assume !(1 == ~T6_E~0); 9125#L887-1 assume !(1 == ~T7_E~0); 9049#L892-1 assume !(1 == ~E_M~0); 9050#L897-1 assume !(1 == ~E_1~0); 8736#L902-1 assume !(1 == ~E_2~0); 8737#L907-1 assume !(1 == ~E_3~0); 9018#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9007#L917-1 assume !(1 == ~E_5~0); 9008#L922-1 assume !(1 == ~E_6~0); 9153#L927-1 assume !(1 == ~E_7~0); 8994#L932-1 assume { :end_inline_reset_delta_events } true; 8400#L1178-2 [2022-11-16 12:49:04,374 INFO L750 eck$LassoCheckResult]: Loop: 8400#L1178-2 assume !false; 8983#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8417#L744 assume !false; 8771#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8845#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8435#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8641#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9097#L641 assume !(0 != eval_~tmp~0#1); 8911#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8535#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8536#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8797#L769-5 assume !(0 == ~T1_E~0); 8798#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8552#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8376#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8377#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8365#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8366#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8415#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8670#L809-3 assume !(0 == ~E_1~0); 8411#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8412#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9071#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9066#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8722#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8723#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9034#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9113#L376-27 assume 1 == ~m_pc~0; 9012#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8958#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8959#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9053#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9156#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9177#L395-27 assume !(1 == ~t1_pc~0); 8817#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 8724#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8725#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8950#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8804#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8805#L414-27 assume 1 == ~t2_pc~0; 9140#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9005#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9006#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8865#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8427#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8428#L433-27 assume !(1 == ~t3_pc~0); 8523#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 8810#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8811#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8600#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 8601#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9170#L452-27 assume 1 == ~t4_pc~0; 9171#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8970#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9094#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9136#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9137#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8418#L471-27 assume !(1 == ~t5_pc~0); 8419#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 8733#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9112#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9026#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8954#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8875#L490-27 assume 1 == ~t6_pc~0; 8772#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8610#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8611#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9014#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9015#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8385#L509-27 assume !(1 == ~t7_pc~0); 8386#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 8776#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8901#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8892#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8893#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8907#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8908#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8946#L862-3 assume !(1 == ~T2_E~0); 9168#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8812#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8813#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8902#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8941#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8570#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8571#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9086#L902-3 assume !(1 == ~E_2~0); 8734#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8735#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8854#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8816#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8623#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8624#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8472#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8373#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9037#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8786#L1197 assume !(0 == start_simulation_~tmp~3#1); 8787#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8528#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8495#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8421#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 8422#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9083#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9084#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8399#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 8400#L1178-2 [2022-11-16 12:49:04,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:04,375 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2022-11-16 12:49:04,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:04,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586002083] [2022-11-16 12:49:04,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:04,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:04,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:04,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1586002083] [2022-11-16 12:49:04,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1586002083] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,420 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,420 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015619080] [2022-11-16 12:49:04,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,426 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:04,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:04,429 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 1 times [2022-11-16 12:49:04,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:04,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099218151] [2022-11-16 12:49:04,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:04,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:04,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:04,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,502 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099218151] [2022-11-16 12:49:04,505 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099218151] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,506 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,506 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154888811] [2022-11-16 12:49:04,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,507 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:04,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:04,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:04,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:04,508 INFO L87 Difference]: Start difference. First operand 830 states and 1236 transitions. cyclomatic complexity: 407 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:04,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:04,540 INFO L93 Difference]: Finished difference Result 830 states and 1235 transitions. [2022-11-16 12:49:04,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1235 transitions. [2022-11-16 12:49:04,545 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:04,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1235 transitions. [2022-11-16 12:49:04,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-11-16 12:49:04,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-11-16 12:49:04,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1235 transitions. [2022-11-16 12:49:04,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:04,553 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1235 transitions. [2022-11-16 12:49:04,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1235 transitions. [2022-11-16 12:49:04,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-11-16 12:49:04,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4879518072289157) internal successors, (1235), 829 states have internal predecessors, (1235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:04,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1235 transitions. [2022-11-16 12:49:04,569 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1235 transitions. [2022-11-16 12:49:04,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:04,571 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1235 transitions. [2022-11-16 12:49:04,572 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 12:49:04,572 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1235 transitions. [2022-11-16 12:49:04,576 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:04,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:04,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:04,580 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:04,580 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:04,580 INFO L748 eck$LassoCheckResult]: Stem: 10654#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 10655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10537#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10487#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10488#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 10771#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10470#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10310#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10311#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10292#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10293#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10770#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10595#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10596#L769 assume !(0 == ~M_E~0); 10618#L769-2 assume !(0 == ~T1_E~0); 10619#L774-1 assume !(0 == ~T2_E~0); 10646#L779-1 assume !(0 == ~T3_E~0); 10758#L784-1 assume !(0 == ~T4_E~0); 10591#L789-1 assume !(0 == ~T5_E~0); 10592#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10702#L799-1 assume !(0 == ~T7_E~0); 10598#L804-1 assume !(0 == ~E_M~0); 10599#L809-1 assume !(0 == ~E_1~0); 10639#L814-1 assume !(0 == ~E_2~0); 10028#L819-1 assume !(0 == ~E_3~0); 10029#L824-1 assume !(0 == ~E_4~0); 10380#L829-1 assume !(0 == ~E_5~0); 10817#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10164#L839-1 assume !(0 == ~E_7~0); 10165#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10543#L376 assume !(1 == ~m_pc~0); 10530#L376-2 is_master_triggered_~__retres1~0#1 := 0; 10529#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10800#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10111#L955 assume !(0 != activate_threads_~tmp~1#1); 10112#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10463#L395 assume 1 == ~t1_pc~0; 10141#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10142#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10034#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10035#L963 assume !(0 != activate_threads_~tmp___0~0#1); 10547#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10548#L414 assume !(1 == ~t2_pc~0); 10167#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10168#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10366#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10367#L971 assume !(0 != activate_threads_~tmp___1~0#1); 10774#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10466#L433 assume 1 == ~t3_pc~0; 10411#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10281#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10439#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10440#L979 assume !(0 != activate_threads_~tmp___2~0#1); 10132#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10133#L452 assume !(1 == ~t4_pc~0); 10288#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10289#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10579#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10645#L987 assume !(0 != activate_threads_~tmp___3~0#1); 10321#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10322#L471 assume 1 == ~t5_pc~0; 10690#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10304#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10305#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10640#L995 assume !(0 != activate_threads_~tmp___4~0#1); 10809#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10810#L490 assume 1 == ~t6_pc~0; 10793#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10546#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10586#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10589#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 10475#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10444#L509 assume !(1 == ~t7_pc~0); 10445#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10262#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10263#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10326#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10327#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10782#L857 assume !(1 == ~M_E~0); 10118#L857-2 assume !(1 == ~T1_E~0); 10119#L862-1 assume !(1 == ~T2_E~0); 10388#L867-1 assume !(1 == ~T3_E~0); 10393#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10467#L877-1 assume !(1 == ~T5_E~0); 10666#L882-1 assume !(1 == ~T6_E~0); 10792#L887-1 assume !(1 == ~T7_E~0); 10716#L892-1 assume !(1 == ~E_M~0); 10717#L897-1 assume !(1 == ~E_1~0); 10403#L902-1 assume !(1 == ~E_2~0); 10404#L907-1 assume !(1 == ~E_3~0); 10683#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10674#L917-1 assume !(1 == ~E_5~0); 10675#L922-1 assume !(1 == ~E_6~0); 10820#L927-1 assume !(1 == ~E_7~0); 10661#L932-1 assume { :end_inline_reset_delta_events } true; 10067#L1178-2 [2022-11-16 12:49:04,581 INFO L750 eck$LassoCheckResult]: Loop: 10067#L1178-2 assume !false; 10650#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10084#L744 assume !false; 10438#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10511#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10102#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10308#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10762#L641 assume !(0 != eval_~tmp~0#1); 10578#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10202#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10203#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10464#L769-5 assume !(0 == ~T1_E~0); 10465#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10219#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10043#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10044#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10030#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10031#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10082#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10336#L809-3 assume !(0 == ~E_1~0); 10078#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10079#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10738#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10733#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10389#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10390#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10701#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10780#L376-27 assume 1 == ~m_pc~0; 10679#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10625#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10626#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10720#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10823#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10844#L395-27 assume !(1 == ~t1_pc~0); 10483#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 10391#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10392#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10617#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10471#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10472#L414-27 assume 1 == ~t2_pc~0; 10807#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10672#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10673#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10532#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10094#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10095#L433-27 assume !(1 == ~t3_pc~0); 10190#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10477#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10478#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10265#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 10266#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10837#L452-27 assume 1 == ~t4_pc~0; 10838#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10637#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10761#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10803#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10804#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10085#L471-27 assume !(1 == ~t5_pc~0); 10086#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 10400#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10779#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10693#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10621#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10542#L490-27 assume 1 == ~t6_pc~0; 10441#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10277#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10278#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10681#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10682#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10052#L509-27 assume !(1 == ~t7_pc~0); 10053#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 10443#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10568#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10559#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10560#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10574#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10575#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10615#L862-3 assume !(1 == ~T2_E~0); 10835#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10479#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10480#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10569#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10609#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10239#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10240#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10753#L902-3 assume !(1 == ~E_2~0); 10401#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10402#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10521#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10484#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10290#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10291#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10139#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10042#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10704#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10454#L1197 assume !(0 == start_simulation_~tmp~3#1); 10455#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10198#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10162#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10088#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 10089#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10750#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10751#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10066#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 10067#L1178-2 [2022-11-16 12:49:04,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:04,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2022-11-16 12:49:04,582 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:04,582 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276611025] [2022-11-16 12:49:04,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:04,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:04,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:04,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,620 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [276611025] [2022-11-16 12:49:04,620 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [276611025] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,621 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,621 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495297963] [2022-11-16 12:49:04,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,621 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:04,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:04,622 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 2 times [2022-11-16 12:49:04,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:04,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562337069] [2022-11-16 12:49:04,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:04,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:04,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:04,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,671 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562337069] [2022-11-16 12:49:04,671 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562337069] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,671 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,671 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [874731347] [2022-11-16 12:49:04,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,672 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:04,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:04,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:04,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:04,673 INFO L87 Difference]: Start difference. First operand 830 states and 1235 transitions. cyclomatic complexity: 406 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:04,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:04,695 INFO L93 Difference]: Finished difference Result 830 states and 1234 transitions. [2022-11-16 12:49:04,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1234 transitions. [2022-11-16 12:49:04,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:04,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1234 transitions. [2022-11-16 12:49:04,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-11-16 12:49:04,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-11-16 12:49:04,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1234 transitions. [2022-11-16 12:49:04,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:04,710 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1234 transitions. [2022-11-16 12:49:04,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1234 transitions. [2022-11-16 12:49:04,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-11-16 12:49:04,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4867469879518072) internal successors, (1234), 829 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:04,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1234 transitions. [2022-11-16 12:49:04,727 INFO L240 hiAutomatonCegarLoop]: Abstraction has 830 states and 1234 transitions. [2022-11-16 12:49:04,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:04,729 INFO L428 stractBuchiCegarLoop]: Abstraction has 830 states and 1234 transitions. [2022-11-16 12:49:04,729 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 12:49:04,729 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1234 transitions. [2022-11-16 12:49:04,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-11-16 12:49:04,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:04,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:04,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:04,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:04,736 INFO L748 eck$LassoCheckResult]: Stem: 12321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 12322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12204#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12154#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12155#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 12438#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12137#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11977#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11978#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11959#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11960#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12437#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12262#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12263#L769 assume !(0 == ~M_E~0); 12285#L769-2 assume !(0 == ~T1_E~0); 12286#L774-1 assume !(0 == ~T2_E~0); 12313#L779-1 assume !(0 == ~T3_E~0); 12425#L784-1 assume !(0 == ~T4_E~0); 12258#L789-1 assume !(0 == ~T5_E~0); 12259#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12369#L799-1 assume !(0 == ~T7_E~0); 12265#L804-1 assume !(0 == ~E_M~0); 12266#L809-1 assume !(0 == ~E_1~0); 12306#L814-1 assume !(0 == ~E_2~0); 11695#L819-1 assume !(0 == ~E_3~0); 11696#L824-1 assume !(0 == ~E_4~0); 12047#L829-1 assume !(0 == ~E_5~0); 12484#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11831#L839-1 assume !(0 == ~E_7~0); 11832#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12210#L376 assume !(1 == ~m_pc~0); 12197#L376-2 is_master_triggered_~__retres1~0#1 := 0; 12196#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12467#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11778#L955 assume !(0 != activate_threads_~tmp~1#1); 11779#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12130#L395 assume 1 == ~t1_pc~0; 11808#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11809#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11701#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11702#L963 assume !(0 != activate_threads_~tmp___0~0#1); 12214#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12215#L414 assume !(1 == ~t2_pc~0); 11834#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11835#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12033#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12034#L971 assume !(0 != activate_threads_~tmp___1~0#1); 12441#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12133#L433 assume 1 == ~t3_pc~0; 12078#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11948#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12106#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12107#L979 assume !(0 != activate_threads_~tmp___2~0#1); 11799#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11800#L452 assume !(1 == ~t4_pc~0); 11955#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11956#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12246#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12312#L987 assume !(0 != activate_threads_~tmp___3~0#1); 11988#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11989#L471 assume 1 == ~t5_pc~0; 12357#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11971#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11972#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12307#L995 assume !(0 != activate_threads_~tmp___4~0#1); 12476#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12477#L490 assume 1 == ~t6_pc~0; 12460#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12213#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12253#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12256#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 12142#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12111#L509 assume !(1 == ~t7_pc~0); 12112#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11929#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11930#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11993#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11994#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12449#L857 assume !(1 == ~M_E~0); 11785#L857-2 assume !(1 == ~T1_E~0); 11786#L862-1 assume !(1 == ~T2_E~0); 12055#L867-1 assume !(1 == ~T3_E~0); 12060#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12134#L877-1 assume !(1 == ~T5_E~0); 12333#L882-1 assume !(1 == ~T6_E~0); 12459#L887-1 assume !(1 == ~T7_E~0); 12383#L892-1 assume !(1 == ~E_M~0); 12384#L897-1 assume !(1 == ~E_1~0); 12070#L902-1 assume !(1 == ~E_2~0); 12071#L907-1 assume !(1 == ~E_3~0); 12350#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12341#L917-1 assume !(1 == ~E_5~0); 12342#L922-1 assume !(1 == ~E_6~0); 12487#L927-1 assume !(1 == ~E_7~0); 12328#L932-1 assume { :end_inline_reset_delta_events } true; 11734#L1178-2 [2022-11-16 12:49:04,736 INFO L750 eck$LassoCheckResult]: Loop: 11734#L1178-2 assume !false; 12317#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11751#L744 assume !false; 12105#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12178#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11769#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11975#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12429#L641 assume !(0 != eval_~tmp~0#1); 12245#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11869#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11870#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12131#L769-5 assume !(0 == ~T1_E~0); 12132#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11886#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11710#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11711#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11697#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11698#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11749#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12003#L809-3 assume !(0 == ~E_1~0); 11745#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11746#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12405#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12400#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12056#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12057#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12368#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12447#L376-27 assume 1 == ~m_pc~0; 12346#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12292#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12293#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12387#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12490#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12511#L395-27 assume !(1 == ~t1_pc~0); 12150#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 12058#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12059#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12284#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12138#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12139#L414-27 assume 1 == ~t2_pc~0; 12474#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12339#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12340#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12199#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11761#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11762#L433-27 assume !(1 == ~t3_pc~0); 11857#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 12144#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12145#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11932#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 11933#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12504#L452-27 assume 1 == ~t4_pc~0; 12505#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12304#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12428#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12470#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12471#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11752#L471-27 assume !(1 == ~t5_pc~0); 11753#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 12067#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12446#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12360#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12288#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12209#L490-27 assume 1 == ~t6_pc~0; 12108#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11944#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11945#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12348#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12349#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11719#L509-27 assume !(1 == ~t7_pc~0); 11720#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 12110#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12235#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12226#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12227#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12241#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12242#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12282#L862-3 assume !(1 == ~T2_E~0); 12502#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12146#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12147#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12236#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12276#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11906#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11907#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12420#L902-3 assume !(1 == ~E_2~0); 12068#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12069#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12188#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12151#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11957#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11958#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11806#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11709#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12371#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12121#L1197 assume !(0 == start_simulation_~tmp~3#1); 12122#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11865#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11829#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11755#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 11756#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12417#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12418#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11733#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 11734#L1178-2 [2022-11-16 12:49:04,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:04,737 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2022-11-16 12:49:04,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:04,738 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105643336] [2022-11-16 12:49:04,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:04,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:04,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:04,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,817 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,817 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105643336] [2022-11-16 12:49:04,822 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2105643336] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,822 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,823 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498931282] [2022-11-16 12:49:04,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,823 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:04,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:04,824 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 3 times [2022-11-16 12:49:04,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:04,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331996984] [2022-11-16 12:49:04,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:04,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:04,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:04,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:04,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:04,897 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331996984] [2022-11-16 12:49:04,897 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [331996984] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:04,898 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:04,898 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:04,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679503841] [2022-11-16 12:49:04,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:04,898 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:04,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:04,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:04,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:04,899 INFO L87 Difference]: Start difference. First operand 830 states and 1234 transitions. cyclomatic complexity: 405 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:05,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:05,056 INFO L93 Difference]: Finished difference Result 1499 states and 2220 transitions. [2022-11-16 12:49:05,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1499 states and 2220 transitions. [2022-11-16 12:49:05,066 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1380 [2022-11-16 12:49:05,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1499 states to 1499 states and 2220 transitions. [2022-11-16 12:49:05,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1499 [2022-11-16 12:49:05,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1499 [2022-11-16 12:49:05,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1499 states and 2220 transitions. [2022-11-16 12:49:05,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:05,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2022-11-16 12:49:05,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1499 states and 2220 transitions. [2022-11-16 12:49:05,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1499 to 1499. [2022-11-16 12:49:05,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1499 states, 1499 states have (on average 1.4809873248832555) internal successors, (2220), 1498 states have internal predecessors, (2220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:05,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1499 states to 1499 states and 2220 transitions. [2022-11-16 12:49:05,110 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2022-11-16 12:49:05,110 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:05,111 INFO L428 stractBuchiCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2022-11-16 12:49:05,111 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 12:49:05,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1499 states and 2220 transitions. [2022-11-16 12:49:05,119 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1380 [2022-11-16 12:49:05,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:05,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:05,121 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:05,121 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:05,121 INFO L748 eck$LassoCheckResult]: Stem: 14668#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 14669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14546#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14496#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14497#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 14794#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14479#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14317#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14318#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14299#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14300#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14793#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14607#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14608#L769 assume !(0 == ~M_E~0); 14630#L769-2 assume !(0 == ~T1_E~0); 14631#L774-1 assume !(0 == ~T2_E~0); 14659#L779-1 assume !(0 == ~T3_E~0); 14779#L784-1 assume !(0 == ~T4_E~0); 14603#L789-1 assume !(0 == ~T5_E~0); 14604#L794-1 assume !(0 == ~T6_E~0); 14720#L799-1 assume !(0 == ~T7_E~0); 14610#L804-1 assume !(0 == ~E_M~0); 14611#L809-1 assume !(0 == ~E_1~0); 14652#L814-1 assume !(0 == ~E_2~0); 14034#L819-1 assume !(0 == ~E_3~0); 14035#L824-1 assume !(0 == ~E_4~0); 14389#L829-1 assume !(0 == ~E_5~0); 14855#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14170#L839-1 assume !(0 == ~E_7~0); 14171#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14552#L376 assume !(1 == ~m_pc~0); 14539#L376-2 is_master_triggered_~__retres1~0#1 := 0; 14538#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14832#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14117#L955 assume !(0 != activate_threads_~tmp~1#1); 14118#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14472#L395 assume 1 == ~t1_pc~0; 14147#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14148#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14040#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14041#L963 assume !(0 != activate_threads_~tmp___0~0#1); 14556#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14557#L414 assume !(1 == ~t2_pc~0); 14173#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14174#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14374#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14375#L971 assume !(0 != activate_threads_~tmp___1~0#1); 14797#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14475#L433 assume 1 == ~t3_pc~0; 14420#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14288#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14448#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14449#L979 assume !(0 != activate_threads_~tmp___2~0#1); 14138#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14139#L452 assume !(1 == ~t4_pc~0); 14295#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14296#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14590#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14658#L987 assume !(0 != activate_threads_~tmp___3~0#1); 14329#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14330#L471 assume 1 == ~t5_pc~0; 14705#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14311#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14312#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14653#L995 assume !(0 != activate_threads_~tmp___4~0#1); 14843#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14844#L490 assume 1 == ~t6_pc~0; 14822#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14555#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14597#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14600#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 14484#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14453#L509 assume !(1 == ~t7_pc~0); 14454#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14268#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14269#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14334#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14335#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14805#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 14806#L857-2 assume !(1 == ~T1_E~0); 14969#L862-1 assume !(1 == ~T2_E~0); 14967#L867-1 assume !(1 == ~T3_E~0); 14965#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14964#L877-1 assume !(1 == ~T5_E~0); 14961#L882-1 assume !(1 == ~T6_E~0); 14820#L887-1 assume !(1 == ~T7_E~0); 14958#L892-1 assume !(1 == ~E_M~0); 14956#L897-1 assume !(1 == ~E_1~0); 14954#L902-1 assume !(1 == ~E_2~0); 14952#L907-1 assume !(1 == ~E_3~0); 14949#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14921#L917-1 assume !(1 == ~E_5~0); 14918#L922-1 assume !(1 == ~E_6~0); 14917#L927-1 assume !(1 == ~E_7~0); 14911#L932-1 assume { :end_inline_reset_delta_events } true; 14905#L1178-2 [2022-11-16 12:49:05,122 INFO L750 eck$LassoCheckResult]: Loop: 14905#L1178-2 assume !false; 14663#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14090#L744 assume !false; 14447#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14520#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14108#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14315#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14783#L641 assume !(0 != eval_~tmp~0#1); 14589#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14208#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14209#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14888#L769-5 assume !(0 == ~T1_E~0); 15492#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15491#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15490#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15489#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15488#L794-3 assume !(0 == ~T6_E~0); 15487#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15486#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15485#L809-3 assume !(0 == ~E_1~0); 15484#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15483#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15482#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15481#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15480#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15479#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15478#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15477#L376-27 assume !(1 == ~m_pc~0); 15475#L376-29 is_master_triggered_~__retres1~0#1 := 0; 15474#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15473#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15472#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15471#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15470#L395-27 assume 1 == ~t1_pc~0; 15468#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15467#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15466#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15465#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15464#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15463#L414-27 assume !(1 == ~t2_pc~0); 15461#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15460#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15459#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15458#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15457#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15456#L433-27 assume 1 == ~t3_pc~0; 15454#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15453#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15452#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15451#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 15450#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15449#L452-27 assume 1 == ~t4_pc~0; 15447#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15446#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15445#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15444#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15443#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15442#L471-27 assume 1 == ~t5_pc~0; 15440#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15439#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15438#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15437#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15436#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15435#L490-27 assume 1 == ~t6_pc~0; 15433#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15432#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15431#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15430#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15429#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15428#L509-27 assume !(1 == ~t7_pc~0); 15426#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 15425#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15424#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15423#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15292#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15291#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14585#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15290#L862-3 assume !(1 == ~T2_E~0); 15278#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14488#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14489#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14579#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14621#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14245#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14246#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14774#L902-3 assume !(1 == ~E_2~0); 14410#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14411#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14530#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14493#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14297#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14298#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14145#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14048#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14722#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 14463#L1197 assume !(0 == start_simulation_~tmp~3#1); 14464#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14204#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14168#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14094#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 14095#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14770#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14771#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 14912#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 14905#L1178-2 [2022-11-16 12:49:05,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:05,123 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2022-11-16 12:49:05,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:05,123 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10300736] [2022-11-16 12:49:05,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:05,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:05,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:05,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:05,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:05,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10300736] [2022-11-16 12:49:05,183 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10300736] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:05,183 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:05,183 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:05,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456948567] [2022-11-16 12:49:05,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:05,184 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:05,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:05,185 INFO L85 PathProgramCache]: Analyzing trace with hash 587005287, now seen corresponding path program 1 times [2022-11-16 12:49:05,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:05,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060757939] [2022-11-16 12:49:05,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:05,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:05,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:05,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:05,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:05,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2060757939] [2022-11-16 12:49:05,230 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2060757939] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:05,230 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:05,230 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:05,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [578682552] [2022-11-16 12:49:05,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:05,231 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:05,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:05,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:05,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:05,231 INFO L87 Difference]: Start difference. First operand 1499 states and 2220 transitions. cyclomatic complexity: 723 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:05,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:05,424 INFO L93 Difference]: Finished difference Result 2703 states and 3991 transitions. [2022-11-16 12:49:05,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2703 states and 3991 transitions. [2022-11-16 12:49:05,446 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2570 [2022-11-16 12:49:05,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2703 states to 2703 states and 3991 transitions. [2022-11-16 12:49:05,460 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2703 [2022-11-16 12:49:05,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2703 [2022-11-16 12:49:05,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2703 states and 3991 transitions. [2022-11-16 12:49:05,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:05,466 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2703 states and 3991 transitions. [2022-11-16 12:49:05,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2703 states and 3991 transitions. [2022-11-16 12:49:05,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2703 to 2701. [2022-11-16 12:49:05,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2701 states, 2701 states have (on average 1.4768604220659016) internal successors, (3989), 2700 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:05,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2701 states to 2701 states and 3989 transitions. [2022-11-16 12:49:05,555 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2701 states and 3989 transitions. [2022-11-16 12:49:05,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:05,556 INFO L428 stractBuchiCegarLoop]: Abstraction has 2701 states and 3989 transitions. [2022-11-16 12:49:05,556 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 12:49:05,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2701 states and 3989 transitions. [2022-11-16 12:49:05,571 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2570 [2022-11-16 12:49:05,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:05,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:05,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:05,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:05,574 INFO L748 eck$LassoCheckResult]: Stem: 18893#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 18894#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 18771#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18715#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18716#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 19026#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18697#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18533#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18534#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18515#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18516#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19025#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18833#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18834#L769 assume !(0 == ~M_E~0); 18857#L769-2 assume !(0 == ~T1_E~0); 18858#L774-1 assume !(0 == ~T2_E~0); 18884#L779-1 assume !(0 == ~T3_E~0); 19013#L784-1 assume !(0 == ~T4_E~0); 18828#L789-1 assume !(0 == ~T5_E~0); 18829#L794-1 assume !(0 == ~T6_E~0); 18947#L799-1 assume !(0 == ~T7_E~0); 18835#L804-1 assume !(0 == ~E_M~0); 18836#L809-1 assume !(0 == ~E_1~0); 18877#L814-1 assume !(0 == ~E_2~0); 18248#L819-1 assume !(0 == ~E_3~0); 18249#L824-1 assume !(0 == ~E_4~0); 18603#L829-1 assume !(0 == ~E_5~0); 19087#L834-1 assume !(0 == ~E_6~0); 18385#L839-1 assume !(0 == ~E_7~0); 18386#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18778#L376 assume !(1 == ~m_pc~0); 18765#L376-2 is_master_triggered_~__retres1~0#1 := 0; 18764#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19068#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18332#L955 assume !(0 != activate_threads_~tmp~1#1); 18333#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18689#L395 assume 1 == ~t1_pc~0; 18362#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18363#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18254#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18255#L963 assume !(0 != activate_threads_~tmp___0~0#1); 18783#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18784#L414 assume !(1 == ~t2_pc~0); 18388#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18389#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18589#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18590#L971 assume !(0 != activate_threads_~tmp___1~0#1); 19031#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18692#L433 assume 1 == ~t3_pc~0; 18636#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18506#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18666#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18667#L979 assume !(0 != activate_threads_~tmp___2~0#1); 18351#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18352#L452 assume !(1 == ~t4_pc~0); 18511#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18512#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18816#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18883#L987 assume !(0 != activate_threads_~tmp___3~0#1); 18544#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18545#L471 assume 1 == ~t5_pc~0; 18934#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18527#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18528#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18878#L995 assume !(0 != activate_threads_~tmp___4~0#1); 19078#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19079#L490 assume 1 == ~t6_pc~0; 19057#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18781#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18822#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18825#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 18704#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18669#L509 assume !(1 == ~t7_pc~0); 18670#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18490#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18491#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18549#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18550#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19041#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 19042#L857-2 assume !(1 == ~T1_E~0); 18611#L862-1 assume !(1 == ~T2_E~0); 18612#L867-1 assume !(1 == ~T3_E~0); 18693#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18694#L877-1 assume !(1 == ~T5_E~0); 19054#L882-1 assume !(1 == ~T6_E~0); 19055#L887-1 assume !(1 == ~T7_E~0); 18962#L892-1 assume !(1 == ~E_M~0); 18963#L897-1 assume !(1 == ~E_1~0); 18630#L902-1 assume !(1 == ~E_2~0); 18631#L907-1 assume !(1 == ~E_3~0); 19222#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19193#L917-1 assume !(1 == ~E_5~0); 19191#L922-1 assume !(1 == ~E_6~0); 19178#L927-1 assume !(1 == ~E_7~0); 19170#L932-1 assume { :end_inline_reset_delta_events } true; 19164#L1178-2 [2022-11-16 12:49:05,575 INFO L750 eck$LassoCheckResult]: Loop: 19164#L1178-2 assume !false; 19159#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19158#L744 assume !false; 19157#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19156#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19148#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19147#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19145#L641 assume !(0 != eval_~tmp~0#1); 19144#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19143#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19141#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19142#L769-5 assume !(0 == ~T1_E~0); 19972#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19970#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19949#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19939#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19931#L794-3 assume !(0 == ~T6_E~0); 19924#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19921#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19918#L809-3 assume !(0 == ~E_1~0); 19908#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19905#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19902#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19897#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19892#L834-3 assume !(0 == ~E_6~0); 19888#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19884#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19880#L376-27 assume !(1 == ~m_pc~0); 19875#L376-29 is_master_triggered_~__retres1~0#1 := 0; 19871#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19866#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19861#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19857#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19853#L395-27 assume 1 == ~t1_pc~0; 19848#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19844#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18997#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18854#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18855#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19828#L414-27 assume 1 == ~t2_pc~0; 19824#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19819#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19741#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19738#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19736#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19734#L433-27 assume 1 == ~t3_pc~0; 19731#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19729#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19727#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19725#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 19723#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19720#L452-27 assume 1 == ~t4_pc~0; 19717#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19715#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19713#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19711#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19709#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19706#L471-27 assume 1 == ~t5_pc~0; 19694#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19692#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19689#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19687#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19685#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19683#L490-27 assume 1 == ~t6_pc~0; 19677#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19675#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19673#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19671#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19669#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19667#L509-27 assume !(1 == ~t7_pc~0); 19658#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19612#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19609#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19607#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19605#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19603#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18810#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19600#L862-3 assume !(1 == ~T2_E~0); 19597#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19533#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19531#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19529#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19526#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19524#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19516#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19501#L902-3 assume !(1 == ~E_2~0); 19492#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19485#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19471#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19469#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19466#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19404#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19380#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19370#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19350#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 19313#L1197 assume !(0 == start_simulation_~tmp~3#1); 19123#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19276#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19266#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19229#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 19228#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19195#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19179#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19171#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 19164#L1178-2 [2022-11-16 12:49:05,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:05,576 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2022-11-16 12:49:05,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:05,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229428638] [2022-11-16 12:49:05,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:05,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:05,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:05,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:05,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:05,659 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229428638] [2022-11-16 12:49:05,660 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229428638] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:05,660 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:05,660 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:05,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309642879] [2022-11-16 12:49:05,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:05,662 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:05,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:05,662 INFO L85 PathProgramCache]: Analyzing trace with hash -933139996, now seen corresponding path program 1 times [2022-11-16 12:49:05,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:05,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946954067] [2022-11-16 12:49:05,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:05,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:05,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:05,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:05,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:05,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946954067] [2022-11-16 12:49:05,717 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [946954067] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:05,717 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:05,718 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:05,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1064706359] [2022-11-16 12:49:05,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:05,718 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:05,719 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:05,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:05,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:05,719 INFO L87 Difference]: Start difference. First operand 2701 states and 3989 transitions. cyclomatic complexity: 1292 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:06,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:06,005 INFO L93 Difference]: Finished difference Result 7458 states and 10846 transitions. [2022-11-16 12:49:06,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7458 states and 10846 transitions. [2022-11-16 12:49:06,053 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7077 [2022-11-16 12:49:06,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7458 states to 7458 states and 10846 transitions. [2022-11-16 12:49:06,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7458 [2022-11-16 12:49:06,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7458 [2022-11-16 12:49:06,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7458 states and 10846 transitions. [2022-11-16 12:49:06,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:06,121 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7458 states and 10846 transitions. [2022-11-16 12:49:06,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7458 states and 10846 transitions. [2022-11-16 12:49:06,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7458 to 7026. [2022-11-16 12:49:06,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7026 states, 7026 states have (on average 1.4594363791631084) internal successors, (10254), 7025 states have internal predecessors, (10254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:06,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7026 states to 7026 states and 10254 transitions. [2022-11-16 12:49:06,353 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7026 states and 10254 transitions. [2022-11-16 12:49:06,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:06,355 INFO L428 stractBuchiCegarLoop]: Abstraction has 7026 states and 10254 transitions. [2022-11-16 12:49:06,355 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 12:49:06,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7026 states and 10254 transitions. [2022-11-16 12:49:06,386 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6877 [2022-11-16 12:49:06,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:06,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:06,388 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:06,388 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:06,389 INFO L748 eck$LassoCheckResult]: Stem: 29093#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 29094#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 28950#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28895#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28896#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 29271#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28876#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28703#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28704#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28684#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28685#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29270#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29024#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29025#L769 assume !(0 == ~M_E~0); 29051#L769-2 assume !(0 == ~T1_E~0); 29052#L774-1 assume !(0 == ~T2_E~0); 29083#L779-1 assume !(0 == ~T3_E~0); 29240#L784-1 assume !(0 == ~T4_E~0); 29019#L789-1 assume !(0 == ~T5_E~0); 29020#L794-1 assume !(0 == ~T6_E~0); 29157#L799-1 assume !(0 == ~T7_E~0); 29027#L804-1 assume !(0 == ~E_M~0); 29028#L809-1 assume !(0 == ~E_1~0); 29074#L814-1 assume !(0 == ~E_2~0); 28415#L819-1 assume !(0 == ~E_3~0); 28416#L824-1 assume !(0 == ~E_4~0); 28777#L829-1 assume !(0 == ~E_5~0); 29368#L834-1 assume !(0 == ~E_6~0); 28550#L839-1 assume !(0 == ~E_7~0); 28551#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28961#L376 assume !(1 == ~m_pc~0); 28958#L376-2 is_master_triggered_~__retres1~0#1 := 0; 28959#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29331#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28497#L955 assume !(0 != activate_threads_~tmp~1#1); 28498#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28868#L395 assume !(1 == ~t1_pc~0); 29054#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29223#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28421#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28422#L963 assume !(0 != activate_threads_~tmp___0~0#1); 28965#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28966#L414 assume !(1 == ~t2_pc~0); 28553#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28554#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28764#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28765#L971 assume !(0 != activate_threads_~tmp___1~0#1); 29277#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28872#L433 assume 1 == ~t3_pc~0; 28812#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28672#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28844#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28845#L979 assume !(0 != activate_threads_~tmp___2~0#1); 28520#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28521#L452 assume !(1 == ~t4_pc~0); 28680#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28681#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29004#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29082#L987 assume !(0 != activate_threads_~tmp___3~0#1); 28715#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28716#L471 assume 1 == ~t5_pc~0; 29137#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28697#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28698#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29075#L995 assume !(0 != activate_threads_~tmp___4~0#1); 29355#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29356#L490 assume 1 == ~t6_pc~0; 29316#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28964#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29012#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29015#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 28881#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28849#L509 assume !(1 == ~t7_pc~0); 28850#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28650#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28651#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28720#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28721#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29288#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 28504#L857-2 assume !(1 == ~T1_E~0); 28505#L862-1 assume !(1 == ~T2_E~0); 30667#L867-1 assume !(1 == ~T3_E~0); 30665#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29105#L877-1 assume !(1 == ~T5_E~0); 29106#L882-1 assume !(1 == ~T6_E~0); 29315#L887-1 assume !(1 == ~T7_E~0); 30592#L892-1 assume !(1 == ~E_M~0); 30590#L897-1 assume !(1 == ~E_1~0); 30589#L902-1 assume !(1 == ~E_2~0); 30588#L907-1 assume !(1 == ~E_3~0); 30587#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30565#L917-1 assume !(1 == ~E_5~0); 30563#L922-1 assume !(1 == ~E_6~0); 30552#L927-1 assume !(1 == ~E_7~0); 30544#L932-1 assume { :end_inline_reset_delta_events } true; 30538#L1178-2 [2022-11-16 12:49:06,389 INFO L750 eck$LassoCheckResult]: Loop: 30538#L1178-2 assume !false; 30533#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30532#L744 assume !false; 30531#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30530#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30522#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30521#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30519#L641 assume !(0 != eval_~tmp~0#1); 30518#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30517#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30514#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30513#L769-5 assume !(0 == ~T1_E~0); 30512#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30511#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30510#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30509#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30508#L794-3 assume !(0 == ~T6_E~0); 30507#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30506#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30505#L809-3 assume !(0 == ~E_1~0); 30502#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30500#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30498#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30496#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30494#L834-3 assume !(0 == ~E_6~0); 30491#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30489#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30487#L376-27 assume !(1 == ~m_pc~0); 30485#L376-29 is_master_triggered_~__retres1~0#1 := 0; 30483#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30481#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30480#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30477#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30475#L395-27 assume !(1 == ~t1_pc~0); 30473#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 30471#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30469#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30467#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30464#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30460#L414-27 assume 1 == ~t2_pc~0; 30461#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31321#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31320#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31319#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31318#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31317#L433-27 assume 1 == ~t3_pc~0; 31076#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31071#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31069#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30419#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 30411#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30408#L452-27 assume 1 == ~t4_pc~0; 30403#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30404#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31058#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31054#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31050#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31045#L471-27 assume !(1 == ~t5_pc~0); 31040#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 31035#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31031#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31027#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31022#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31017#L490-27 assume 1 == ~t6_pc~0; 31010#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31005#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30999#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30993#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30986#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30979#L509-27 assume !(1 == ~t7_pc~0); 30973#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 30967#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30961#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30955#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30948#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30940#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29637#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30929#L862-3 assume !(1 == ~T2_E~0); 30925#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30888#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30886#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30884#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29619#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30870#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30864#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30854#L902-3 assume !(1 == ~E_2~0); 30846#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30841#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29574#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29575#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30788#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30758#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30714#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30704#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30691#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 30683#L1197 assume !(0 == start_simulation_~tmp~3#1); 29440#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30598#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30593#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30591#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 30566#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30564#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30553#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 30545#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 30538#L1178-2 [2022-11-16 12:49:06,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:06,390 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2022-11-16 12:49:06,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:06,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775583016] [2022-11-16 12:49:06,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:06,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:06,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:06,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:06,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:06,451 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775583016] [2022-11-16 12:49:06,452 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775583016] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:06,452 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:06,452 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:06,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [511821977] [2022-11-16 12:49:06,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:06,452 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:06,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:06,453 INFO L85 PathProgramCache]: Analyzing trace with hash -486936090, now seen corresponding path program 1 times [2022-11-16 12:49:06,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:06,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537560648] [2022-11-16 12:49:06,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:06,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:06,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:06,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:06,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:06,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537560648] [2022-11-16 12:49:06,498 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [537560648] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:06,498 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:06,498 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:06,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829631374] [2022-11-16 12:49:06,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:06,499 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:06,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:06,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:06,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:06,500 INFO L87 Difference]: Start difference. First operand 7026 states and 10254 transitions. cyclomatic complexity: 3236 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:06,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:06,910 INFO L93 Difference]: Finished difference Result 19599 states and 28287 transitions. [2022-11-16 12:49:06,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19599 states and 28287 transitions. [2022-11-16 12:49:07,023 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18895 [2022-11-16 12:49:07,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19599 states to 19599 states and 28287 transitions. [2022-11-16 12:49:07,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19599 [2022-11-16 12:49:07,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19599 [2022-11-16 12:49:07,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19599 states and 28287 transitions. [2022-11-16 12:49:07,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:07,164 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19599 states and 28287 transitions. [2022-11-16 12:49:07,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19599 states and 28287 transitions. [2022-11-16 12:49:07,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19599 to 18651. [2022-11-16 12:49:07,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18651 states, 18651 states have (on average 1.4482333386949762) internal successors, (27011), 18650 states have internal predecessors, (27011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:07,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18651 states to 18651 states and 27011 transitions. [2022-11-16 12:49:07,742 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18651 states and 27011 transitions. [2022-11-16 12:49:07,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:07,743 INFO L428 stractBuchiCegarLoop]: Abstraction has 18651 states and 27011 transitions. [2022-11-16 12:49:07,743 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 12:49:07,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18651 states and 27011 transitions. [2022-11-16 12:49:07,914 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18463 [2022-11-16 12:49:07,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:07,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:07,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:07,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:07,916 INFO L748 eck$LassoCheckResult]: Stem: 55718#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 55719#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 55575#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55518#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55519#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 55880#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55501#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55335#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55336#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55316#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55317#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55879#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55649#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55650#L769 assume !(0 == ~M_E~0); 55674#L769-2 assume !(0 == ~T1_E~0); 55675#L774-1 assume !(0 == ~T2_E~0); 55708#L779-1 assume !(0 == ~T3_E~0); 55854#L784-1 assume !(0 == ~T4_E~0); 55644#L789-1 assume !(0 == ~T5_E~0); 55645#L794-1 assume !(0 == ~T6_E~0); 55777#L799-1 assume !(0 == ~T7_E~0); 55652#L804-1 assume !(0 == ~E_M~0); 55653#L809-1 assume !(0 == ~E_1~0); 55698#L814-1 assume !(0 == ~E_2~0); 55050#L819-1 assume !(0 == ~E_3~0); 55051#L824-1 assume !(0 == ~E_4~0); 55409#L829-1 assume !(0 == ~E_5~0); 55961#L834-1 assume !(0 == ~E_6~0); 55181#L839-1 assume !(0 == ~E_7~0); 55182#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55587#L376 assume !(1 == ~m_pc~0); 55582#L376-2 is_master_triggered_~__retres1~0#1 := 0; 55583#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55931#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55132#L955 assume !(0 != activate_threads_~tmp~1#1); 55133#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55493#L395 assume !(1 == ~t1_pc~0); 55677#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55838#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55056#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55057#L963 assume !(0 != activate_threads_~tmp___0~0#1); 55593#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55594#L414 assume !(1 == ~t2_pc~0); 55184#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55185#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55396#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55397#L971 assume !(0 != activate_threads_~tmp___1~0#1); 55885#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55496#L433 assume !(1 == ~t3_pc~0); 55303#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55304#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55469#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55470#L979 assume !(0 != activate_threads_~tmp___2~0#1); 55152#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55153#L452 assume !(1 == ~t4_pc~0); 55312#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55313#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55628#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55707#L987 assume !(0 != activate_threads_~tmp___3~0#1); 55347#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55348#L471 assume 1 == ~t5_pc~0; 55763#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55328#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55329#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55699#L995 assume !(0 != activate_threads_~tmp___4~0#1); 55951#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55952#L490 assume 1 == ~t6_pc~0; 55913#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55592#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55636#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55640#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 55506#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55474#L509 assume !(1 == ~t7_pc~0); 55475#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 55281#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55282#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55352#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 55353#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55893#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 55894#L857-2 assume !(1 == ~T1_E~0); 55417#L862-1 assume !(1 == ~T2_E~0); 55418#L867-1 assume !(1 == ~T3_E~0); 55497#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55498#L877-1 assume !(1 == ~T5_E~0); 55911#L882-1 assume !(1 == ~T6_E~0); 55912#L887-1 assume !(1 == ~T7_E~0); 58616#L892-1 assume !(1 == ~E_M~0); 58614#L897-1 assume !(1 == ~E_1~0); 58612#L902-1 assume !(1 == ~E_2~0); 58610#L907-1 assume !(1 == ~E_3~0); 58608#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 58606#L917-1 assume !(1 == ~E_5~0); 58604#L922-1 assume !(1 == ~E_6~0); 58602#L927-1 assume !(1 == ~E_7~0); 58599#L932-1 assume { :end_inline_reset_delta_events } true; 58600#L1178-2 [2022-11-16 12:49:07,917 INFO L750 eck$LassoCheckResult]: Loop: 58600#L1178-2 assume !false; 58576#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58577#L744 assume !false; 58566#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 58567#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 58527#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 58528#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 57799#L641 assume !(0 != eval_~tmp~0#1); 57801#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72751#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 72750#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 72749#L769-5 assume !(0 == ~T1_E~0); 72748#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72747#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72746#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72745#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 72744#L794-3 assume !(0 == ~T6_E~0); 72743#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72742#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 72741#L809-3 assume !(0 == ~E_1~0); 72740#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 72739#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72738#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 72737#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 72736#L834-3 assume !(0 == ~E_6~0); 72735#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 72734#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72733#L376-27 assume !(1 == ~m_pc~0); 72732#L376-29 is_master_triggered_~__retres1~0#1 := 0; 72731#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72730#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 72729#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72728#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72727#L395-27 assume !(1 == ~t1_pc~0); 72726#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 72725#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72724#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 72723#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72722#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72721#L414-27 assume 1 == ~t2_pc~0; 72720#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 72718#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72717#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 72716#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72715#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72714#L433-27 assume !(1 == ~t3_pc~0); 72713#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 72712#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72711#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 72710#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 72709#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72708#L452-27 assume !(1 == ~t4_pc~0); 72707#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 72705#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72704#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 72703#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 72702#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72701#L471-27 assume 1 == ~t5_pc~0; 72699#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 72698#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72697#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 72696#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 72695#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72694#L490-27 assume !(1 == ~t6_pc~0); 72693#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 72691#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72690#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72689#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 72687#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72686#L509-27 assume 1 == ~t7_pc~0; 72685#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72683#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72682#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72681#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 72680#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72679#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 67039#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72678#L862-3 assume !(1 == ~T2_E~0); 72677#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 72676#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72675#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 72674#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 72522#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72673#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 72672#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 72671#L902-3 assume !(1 == ~E_2~0); 60003#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60004#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59988#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59989#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59978#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59979#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 59856#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 59852#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 59840#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 59834#L1197 assume !(0 == start_simulation_~tmp~3#1); 59832#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 59833#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 72360#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 72359#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 72358#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 72357#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 72356#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 72355#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 58600#L1178-2 [2022-11-16 12:49:07,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:07,918 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2022-11-16 12:49:07,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:07,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97283771] [2022-11-16 12:49:07,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:07,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:07,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:07,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:07,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:07,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97283771] [2022-11-16 12:49:07,970 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97283771] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:07,970 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:07,970 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:49:07,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711674911] [2022-11-16 12:49:07,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:07,970 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:07,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:07,971 INFO L85 PathProgramCache]: Analyzing trace with hash -1435227033, now seen corresponding path program 1 times [2022-11-16 12:49:07,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:07,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353167582] [2022-11-16 12:49:07,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:07,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:07,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:08,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:08,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:08,030 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353167582] [2022-11-16 12:49:08,031 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353167582] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:08,031 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:08,031 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:08,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712357905] [2022-11-16 12:49:08,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:08,032 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:08,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:08,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:08,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:08,033 INFO L87 Difference]: Start difference. First operand 18651 states and 27011 transitions. cyclomatic complexity: 8376 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:08,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:08,315 INFO L93 Difference]: Finished difference Result 35898 states and 51685 transitions. [2022-11-16 12:49:08,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35898 states and 51685 transitions. [2022-11-16 12:49:08,634 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35579 [2022-11-16 12:49:08,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35898 states to 35898 states and 51685 transitions. [2022-11-16 12:49:08,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35898 [2022-11-16 12:49:08,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35898 [2022-11-16 12:49:08,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35898 states and 51685 transitions. [2022-11-16 12:49:08,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:08,957 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35898 states and 51685 transitions. [2022-11-16 12:49:08,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35898 states and 51685 transitions. [2022-11-16 12:49:09,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35898 to 35826. [2022-11-16 12:49:09,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35826 states, 35826 states have (on average 1.4406576229553956) internal successors, (51613), 35825 states have internal predecessors, (51613), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:09,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35826 states to 35826 states and 51613 transitions. [2022-11-16 12:49:09,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35826 states and 51613 transitions. [2022-11-16 12:49:09,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:09,936 INFO L428 stractBuchiCegarLoop]: Abstraction has 35826 states and 51613 transitions. [2022-11-16 12:49:09,936 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 12:49:09,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35826 states and 51613 transitions. [2022-11-16 12:49:10,058 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35507 [2022-11-16 12:49:10,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:10,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:10,060 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:10,060 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:10,060 INFO L748 eck$LassoCheckResult]: Stem: 110271#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 110272#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 110133#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 110077#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 110078#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 110423#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 110058#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 109887#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 109888#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 109869#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 109870#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 110422#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 110201#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 110202#L769 assume !(0 == ~M_E~0); 110226#L769-2 assume !(0 == ~T1_E~0); 110227#L774-1 assume !(0 == ~T2_E~0); 110262#L779-1 assume !(0 == ~T3_E~0); 110402#L784-1 assume !(0 == ~T4_E~0); 110197#L789-1 assume !(0 == ~T5_E~0); 110198#L794-1 assume !(0 == ~T6_E~0); 110328#L799-1 assume !(0 == ~T7_E~0); 110204#L804-1 assume !(0 == ~E_M~0); 110205#L809-1 assume !(0 == ~E_1~0); 110251#L814-1 assume !(0 == ~E_2~0); 109606#L819-1 assume !(0 == ~E_3~0); 109607#L824-1 assume !(0 == ~E_4~0); 109955#L829-1 assume !(0 == ~E_5~0); 110500#L834-1 assume !(0 == ~E_6~0); 109736#L839-1 assume !(0 == ~E_7~0); 109737#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110141#L376 assume !(1 == ~m_pc~0); 110138#L376-2 is_master_triggered_~__retres1~0#1 := 0; 110139#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110473#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 109684#L955 assume !(0 != activate_threads_~tmp~1#1); 109685#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110050#L395 assume !(1 == ~t1_pc~0); 110229#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 110387#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109612#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 109613#L963 assume !(0 != activate_threads_~tmp___0~0#1); 110147#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110148#L414 assume !(1 == ~t2_pc~0); 109739#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 109740#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109942#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 109943#L971 assume !(0 != activate_threads_~tmp___1~0#1); 110430#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110053#L433 assume !(1 == ~t3_pc~0); 109856#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 109857#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110020#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 110021#L979 assume !(0 != activate_threads_~tmp___2~0#1); 109705#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 109706#L452 assume !(1 == ~t4_pc~0); 109865#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 109866#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110181#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 110261#L987 assume !(0 != activate_threads_~tmp___3~0#1); 109899#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 109900#L471 assume !(1 == ~t5_pc~0); 110314#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 109881#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 109882#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 110252#L995 assume !(0 != activate_threads_~tmp___4~0#1); 110488#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110489#L490 assume 1 == ~t6_pc~0; 110459#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 110146#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110189#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 110193#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 110063#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110029#L509 assume !(1 == ~t7_pc~0); 110030#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 109836#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109837#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 109904#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 109905#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110439#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 110440#L857-2 assume !(1 == ~T1_E~0); 109965#L862-1 assume !(1 == ~T2_E~0); 109966#L867-1 assume !(1 == ~T3_E~0); 110054#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110055#L877-1 assume !(1 == ~T5_E~0); 110457#L882-1 assume !(1 == ~T6_E~0); 110458#L887-1 assume !(1 == ~T7_E~0); 110546#L892-1 assume !(1 == ~E_M~0); 110526#L897-1 assume !(1 == ~E_1~0); 110527#L902-1 assume !(1 == ~E_2~0); 110369#L907-1 assume !(1 == ~E_3~0); 110370#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 110295#L917-1 assume !(1 == ~E_5~0); 110296#L922-1 assume !(1 == ~E_6~0); 116114#L927-1 assume !(1 == ~E_7~0); 116610#L932-1 assume { :end_inline_reset_delta_events } true; 116611#L1178-2 [2022-11-16 12:49:10,061 INFO L750 eck$LassoCheckResult]: Loop: 116611#L1178-2 assume !false; 114941#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 114942#L744 assume !false; 114935#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 114936#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 139810#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 139809#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 139807#L641 assume !(0 != eval_~tmp~0#1); 117039#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117035#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117031#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 117027#L769-5 assume !(0 == ~T1_E~0); 117023#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117018#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117014#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117010#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117006#L794-3 assume !(0 == ~T6_E~0); 117002#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 116997#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 116992#L809-3 assume !(0 == ~E_1~0); 116988#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 116984#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 116980#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 116976#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 116972#L834-3 assume !(0 == ~E_6~0); 116968#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 116964#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116960#L376-27 assume !(1 == ~m_pc~0); 116956#L376-29 is_master_triggered_~__retres1~0#1 := 0; 116952#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116947#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 116943#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 116938#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116933#L395-27 assume !(1 == ~t1_pc~0); 116929#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 116925#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116922#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116921#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 116920#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116919#L414-27 assume 1 == ~t2_pc~0; 116917#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 116914#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116912#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 116910#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116908#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116906#L433-27 assume !(1 == ~t3_pc~0); 116904#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 116902#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116899#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 116897#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 116895#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116893#L452-27 assume !(1 == ~t4_pc~0); 116891#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 116888#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116885#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 116883#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 116881#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116879#L471-27 assume !(1 == ~t5_pc~0); 116877#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 116876#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116875#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 116874#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 116872#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116870#L490-27 assume 1 == ~t6_pc~0; 116867#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 116865#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116863#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116861#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 116859#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116857#L509-27 assume !(1 == ~t7_pc~0); 116853#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 116851#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116849#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 116847#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 116845#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116843#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 116645#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116838#L862-3 assume !(1 == ~T2_E~0); 116836#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116834#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116832#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116830#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 116826#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 116824#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116822#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 116820#L902-3 assume !(1 == ~E_2~0); 116818#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116816#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116814#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116812#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 116345#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 116809#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 116756#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 116748#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 116744#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 116739#L1197 assume !(0 == start_simulation_~tmp~3#1); 116737#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 116638#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 116630#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 116626#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 116622#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116618#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116615#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 116612#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 116611#L1178-2 [2022-11-16 12:49:10,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:10,061 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2022-11-16 12:49:10,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:10,062 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724785999] [2022-11-16 12:49:10,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:10,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:10,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:10,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:10,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:10,131 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1724785999] [2022-11-16 12:49:10,131 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1724785999] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:10,131 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:10,131 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:10,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028667417] [2022-11-16 12:49:10,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:10,132 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:10,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:10,133 INFO L85 PathProgramCache]: Analyzing trace with hash -1792045400, now seen corresponding path program 1 times [2022-11-16 12:49:10,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:10,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91035485] [2022-11-16 12:49:10,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:10,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:10,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:10,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:10,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:10,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91035485] [2022-11-16 12:49:10,178 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91035485] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:10,178 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:10,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:10,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983304564] [2022-11-16 12:49:10,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:10,179 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:10,179 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:10,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:10,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:10,180 INFO L87 Difference]: Start difference. First operand 35826 states and 51613 transitions. cyclomatic complexity: 15819 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:11,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:11,065 INFO L93 Difference]: Finished difference Result 98927 states and 141456 transitions. [2022-11-16 12:49:11,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98927 states and 141456 transitions. [2022-11-16 12:49:11,819 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 96097 [2022-11-16 12:49:12,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98927 states to 98927 states and 141456 transitions. [2022-11-16 12:49:12,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98927 [2022-11-16 12:49:12,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98927 [2022-11-16 12:49:12,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98927 states and 141456 transitions. [2022-11-16 12:49:12,563 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:12,564 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98927 states and 141456 transitions. [2022-11-16 12:49:12,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98927 states and 141456 transitions. [2022-11-16 12:49:13,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98927 to 95639. [2022-11-16 12:49:13,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95639 states, 95639 states have (on average 1.4347285103357417) internal successors, (137216), 95638 states have internal predecessors, (137216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:14,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95639 states to 95639 states and 137216 transitions. [2022-11-16 12:49:14,202 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95639 states and 137216 transitions. [2022-11-16 12:49:14,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:14,205 INFO L428 stractBuchiCegarLoop]: Abstraction has 95639 states and 137216 transitions. [2022-11-16 12:49:14,206 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 12:49:14,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95639 states and 137216 transitions. [2022-11-16 12:49:14,869 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 95017 [2022-11-16 12:49:14,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:14,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:14,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:14,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:14,872 INFO L748 eck$LassoCheckResult]: Stem: 245032#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 245033#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 244895#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 244838#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 244839#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 245195#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 244821#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 244649#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 244650#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 244629#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 244630#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 245194#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 244962#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 244963#L769 assume !(0 == ~M_E~0); 244987#L769-2 assume !(0 == ~T1_E~0); 244988#L774-1 assume !(0 == ~T2_E~0); 245022#L779-1 assume !(0 == ~T3_E~0); 245173#L784-1 assume !(0 == ~T4_E~0); 244958#L789-1 assume !(0 == ~T5_E~0); 244959#L794-1 assume !(0 == ~T6_E~0); 245090#L799-1 assume !(0 == ~T7_E~0); 244965#L804-1 assume !(0 == ~E_M~0); 244966#L809-1 assume !(0 == ~E_1~0); 245012#L814-1 assume !(0 == ~E_2~0); 244369#L819-1 assume !(0 == ~E_3~0); 244370#L824-1 assume !(0 == ~E_4~0); 244719#L829-1 assume !(0 == ~E_5~0); 245280#L834-1 assume !(0 == ~E_6~0); 244496#L839-1 assume !(0 == ~E_7~0); 244497#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 244905#L376 assume !(1 == ~m_pc~0); 244901#L376-2 is_master_triggered_~__retres1~0#1 := 0; 244902#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 245243#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 244448#L955 assume !(0 != activate_threads_~tmp~1#1); 244449#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 244814#L395 assume !(1 == ~t1_pc~0); 244990#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 245152#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 244375#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 244376#L963 assume !(0 != activate_threads_~tmp___0~0#1); 244910#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 244911#L414 assume !(1 == ~t2_pc~0); 244499#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 244500#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 244706#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 244707#L971 assume !(0 != activate_threads_~tmp___1~0#1); 245199#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 244817#L433 assume !(1 == ~t3_pc~0); 244616#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 244617#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 244783#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 244784#L979 assume !(0 != activate_threads_~tmp___2~0#1); 244468#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 244469#L452 assume !(1 == ~t4_pc~0); 244625#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 244626#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 244943#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 245021#L987 assume !(0 != activate_threads_~tmp___3~0#1); 244660#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 244661#L471 assume !(1 == ~t5_pc~0); 245073#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 244642#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 244643#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 245013#L995 assume !(0 != activate_threads_~tmp___4~0#1); 245263#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245264#L490 assume !(1 == ~t6_pc~0); 244908#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 244909#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 244951#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 244955#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 244826#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 244792#L509 assume !(1 == ~t7_pc~0); 244793#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 244595#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 244596#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 244665#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 244666#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 245207#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 245208#L857-2 assume !(1 == ~T1_E~0); 283747#L862-1 assume !(1 == ~T2_E~0); 283746#L867-1 assume !(1 == ~T3_E~0); 283745#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 283744#L877-1 assume !(1 == ~T5_E~0); 245228#L882-1 assume !(1 == ~T6_E~0); 245229#L887-1 assume !(1 == ~T7_E~0); 245111#L892-1 assume !(1 == ~E_M~0); 245112#L897-1 assume !(1 == ~E_1~0); 244745#L902-1 assume !(1 == ~E_2~0); 244746#L907-1 assume !(1 == ~E_3~0); 245063#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 245064#L917-1 assume !(1 == ~E_5~0); 245286#L922-1 assume !(1 == ~E_6~0); 245287#L927-1 assume !(1 == ~E_7~0); 245039#L932-1 assume { :end_inline_reset_delta_events } true; 245040#L1178-2 [2022-11-16 12:49:14,872 INFO L750 eck$LassoCheckResult]: Loop: 245040#L1178-2 assume !false; 310055#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 310056#L744 assume !false; 310049#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 310050#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 316123#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 316121#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 316119#L641 assume !(0 != eval_~tmp~0#1); 316120#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 317112#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 317111#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 317110#L769-5 assume !(0 == ~T1_E~0); 317109#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 317108#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 317107#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 317106#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 317105#L794-3 assume !(0 == ~T6_E~0); 317104#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 317103#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 317102#L809-3 assume !(0 == ~E_1~0); 317101#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 317100#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 317099#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 317098#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 317097#L834-3 assume !(0 == ~E_6~0); 317096#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 317095#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 317094#L376-27 assume !(1 == ~m_pc~0); 317093#L376-29 is_master_triggered_~__retres1~0#1 := 0; 317092#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 317091#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 317090#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 317089#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 317088#L395-27 assume !(1 == ~t1_pc~0); 317087#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 317086#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 317085#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 317084#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 317083#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 317082#L414-27 assume !(1 == ~t2_pc~0); 317080#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 317079#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 317078#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 317077#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 317076#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 317075#L433-27 assume !(1 == ~t3_pc~0); 317074#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 317073#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 317072#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 317071#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 317070#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 317069#L452-27 assume !(1 == ~t4_pc~0); 317068#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 317066#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 317065#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 317064#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 317063#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 317062#L471-27 assume !(1 == ~t5_pc~0); 317061#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 317060#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 317059#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 317058#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 317057#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 317056#L490-27 assume !(1 == ~t6_pc~0); 317055#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 317054#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 317053#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 317052#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 317051#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 317050#L509-27 assume !(1 == ~t7_pc~0); 317048#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 317047#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 317046#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 317045#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 317044#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 317043#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 283800#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 317042#L862-3 assume !(1 == ~T2_E~0); 317041#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 317040#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 317039#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 317038#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 308527#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 317037#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 317036#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 317035#L902-3 assume !(1 == ~E_2~0); 317034#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 317033#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 317032#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 317031#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 301473#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 317030#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 317026#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 317021#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 317020#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 316951#L1197 assume !(0 == start_simulation_~tmp~3#1); 316950#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 316946#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 316941#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 316940#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 316931#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 310213#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 310211#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 310209#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 245040#L1178-2 [2022-11-16 12:49:14,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:14,873 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2022-11-16 12:49:14,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:14,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565629167] [2022-11-16 12:49:14,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:14,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:14,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:14,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:14,964 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:14,965 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565629167] [2022-11-16 12:49:14,965 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565629167] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:14,965 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:14,965 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:49:14,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19476406] [2022-11-16 12:49:14,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:14,967 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:14,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:14,968 INFO L85 PathProgramCache]: Analyzing trace with hash -1899577302, now seen corresponding path program 1 times [2022-11-16 12:49:14,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:14,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305850278] [2022-11-16 12:49:14,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:14,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:14,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:15,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:15,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:15,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305850278] [2022-11-16 12:49:15,012 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305850278] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:15,012 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:15,012 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:15,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [273865958] [2022-11-16 12:49:15,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:15,012 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:15,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:15,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:49:15,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:49:15,014 INFO L87 Difference]: Start difference. First operand 95639 states and 137216 transitions. cyclomatic complexity: 41641 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:16,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:16,427 INFO L93 Difference]: Finished difference Result 217819 states and 316152 transitions. [2022-11-16 12:49:16,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217819 states and 316152 transitions. [2022-11-16 12:49:17,623 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 216166 [2022-11-16 12:49:18,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217819 states to 217819 states and 316152 transitions. [2022-11-16 12:49:18,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217819 [2022-11-16 12:49:18,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217819 [2022-11-16 12:49:18,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217819 states and 316152 transitions. [2022-11-16 12:49:19,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:19,094 INFO L218 hiAutomatonCegarLoop]: Abstraction has 217819 states and 316152 transitions. [2022-11-16 12:49:19,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217819 states and 316152 transitions. [2022-11-16 12:49:20,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217819 to 99398. [2022-11-16 12:49:21,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99398 states, 99398 states have (on average 1.4182880943278537) internal successors, (140975), 99397 states have internal predecessors, (140975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:21,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99398 states to 99398 states and 140975 transitions. [2022-11-16 12:49:21,343 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99398 states and 140975 transitions. [2022-11-16 12:49:21,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 12:49:21,345 INFO L428 stractBuchiCegarLoop]: Abstraction has 99398 states and 140975 transitions. [2022-11-16 12:49:21,345 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 12:49:21,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99398 states and 140975 transitions. [2022-11-16 12:49:21,593 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 98773 [2022-11-16 12:49:21,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:21,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:21,595 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:21,595 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:21,596 INFO L748 eck$LassoCheckResult]: Stem: 558514#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 558515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 558370#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 558311#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 558312#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 558678#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 558294#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 558121#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 558122#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 558103#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 558104#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 558677#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 558446#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 558447#L769 assume !(0 == ~M_E~0); 558469#L769-2 assume !(0 == ~T1_E~0); 558470#L774-1 assume !(0 == ~T2_E~0); 558506#L779-1 assume !(0 == ~T3_E~0); 558653#L784-1 assume !(0 == ~T4_E~0); 558441#L789-1 assume !(0 == ~T5_E~0); 558442#L794-1 assume !(0 == ~T6_E~0); 558578#L799-1 assume !(0 == ~T7_E~0); 558448#L804-1 assume !(0 == ~E_M~0); 558449#L809-1 assume !(0 == ~E_1~0); 558495#L814-1 assume !(0 == ~E_2~0); 557840#L819-1 assume !(0 == ~E_3~0); 557841#L824-1 assume !(0 == ~E_4~0); 558191#L829-1 assume !(0 == ~E_5~0); 558769#L834-1 assume !(0 == ~E_6~0); 557967#L839-1 assume !(0 == ~E_7~0); 557968#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 558381#L376 assume !(1 == ~m_pc~0); 558377#L376-2 is_master_triggered_~__retres1~0#1 := 0; 558378#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 558732#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 557917#L955 assume !(0 != activate_threads_~tmp~1#1); 557918#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558284#L395 assume !(1 == ~t1_pc~0); 558473#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 558638#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 557846#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 557847#L963 assume !(0 != activate_threads_~tmp___0~0#1); 558388#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 558389#L414 assume !(1 == ~t2_pc~0); 557970#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 557971#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 558178#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 558179#L971 assume !(0 != activate_threads_~tmp___1~0#1); 558683#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 558289#L433 assume !(1 == ~t3_pc~0); 558093#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 558094#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 558254#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 558255#L979 assume !(0 != activate_threads_~tmp___2~0#1); 557938#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 557939#L452 assume !(1 == ~t4_pc~0); 558099#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 558100#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 558427#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 558505#L987 assume !(0 != activate_threads_~tmp___3~0#1); 558132#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 558133#L471 assume !(1 == ~t5_pc~0); 558559#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 558115#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 558116#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 558496#L995 assume !(0 != activate_threads_~tmp___4~0#1); 558757#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 558758#L490 assume !(1 == ~t6_pc~0); 558386#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 558387#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 558433#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 558436#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 558301#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 558263#L509 assume !(1 == ~t7_pc~0); 558264#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 558073#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 558074#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 558137#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 558138#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 558695#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 558696#L857-2 assume !(1 == ~T1_E~0); 558200#L862-1 assume !(1 == ~T2_E~0); 558201#L867-1 assume !(1 == ~T3_E~0); 558290#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 558291#L877-1 assume !(1 == ~T5_E~0); 558717#L882-1 assume !(1 == ~T6_E~0); 558718#L887-1 assume !(1 == ~T7_E~0); 634054#L892-1 assume !(1 == ~E_M~0); 634053#L897-1 assume !(1 == ~E_1~0); 634044#L902-1 assume !(1 == ~E_2~0); 634042#L907-1 assume !(1 == ~E_3~0); 634040#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 634027#L917-1 assume !(1 == ~E_5~0); 558774#L922-1 assume !(1 == ~E_6~0); 558775#L927-1 assume !(1 == ~E_7~0); 558522#L932-1 assume { :end_inline_reset_delta_events } true; 558523#L1178-2 [2022-11-16 12:49:21,596 INFO L750 eck$LassoCheckResult]: Loop: 558523#L1178-2 assume !false; 648147#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 648145#L744 assume !false; 648143#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 648141#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 648132#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 648130#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 648127#L641 assume !(0 != eval_~tmp~0#1); 648128#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 651218#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 651216#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 651205#L769-5 assume !(0 == ~T1_E~0); 651183#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 651174#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 651166#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 651160#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 651137#L794-3 assume !(0 == ~T6_E~0); 651135#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 651133#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 651132#L809-3 assume !(0 == ~E_1~0); 651131#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 651127#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 651125#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 651121#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 651119#L834-3 assume !(0 == ~E_6~0); 651118#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 651117#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 651116#L376-27 assume !(1 == ~m_pc~0); 651115#L376-29 is_master_triggered_~__retres1~0#1 := 0; 651114#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 651113#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 651112#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 651111#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 651110#L395-27 assume !(1 == ~t1_pc~0); 651109#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 651108#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 651107#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 651106#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 651105#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 651104#L414-27 assume 1 == ~t2_pc~0; 651103#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 651101#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 651100#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 651099#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 651098#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 651097#L433-27 assume !(1 == ~t3_pc~0); 651096#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 651095#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 651094#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 651093#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 651092#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 651091#L452-27 assume 1 == ~t4_pc~0; 651089#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 651088#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 651087#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 651086#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 651085#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 651084#L471-27 assume !(1 == ~t5_pc~0); 651083#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 651082#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 651081#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 651080#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 651079#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 651078#L490-27 assume !(1 == ~t6_pc~0); 651077#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 651076#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 651075#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 651074#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 651073#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 651072#L509-27 assume !(1 == ~t7_pc~0); 651071#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 651069#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 651067#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 651065#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 651062#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 650981#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 631333#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 650974#L862-3 assume !(1 == ~T2_E~0); 650908#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 650851#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 650845#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 650839#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 631401#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 650828#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 650822#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 650816#L902-3 assume !(1 == ~E_2~0); 650810#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 650805#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 650799#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 650793#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 634067#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 650782#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 650607#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 650597#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 650591#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 650586#L1197 assume !(0 == start_simulation_~tmp~3#1); 650528#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 650468#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 650462#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 650460#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 650458#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 650445#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 650440#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 650434#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 558523#L1178-2 [2022-11-16 12:49:21,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:21,597 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2022-11-16 12:49:21,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:21,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430063093] [2022-11-16 12:49:21,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:21,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:21,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:21,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:21,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:21,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430063093] [2022-11-16 12:49:21,659 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430063093] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:21,659 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:21,659 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:49:21,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1975595333] [2022-11-16 12:49:21,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:21,660 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:21,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:21,660 INFO L85 PathProgramCache]: Analyzing trace with hash -1301841750, now seen corresponding path program 1 times [2022-11-16 12:49:21,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:21,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623663420] [2022-11-16 12:49:21,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:21,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:21,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:21,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:21,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:21,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623663420] [2022-11-16 12:49:21,706 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [623663420] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:21,706 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:21,707 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:21,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202051650] [2022-11-16 12:49:21,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:21,707 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:21,707 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:21,708 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:21,708 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:21,708 INFO L87 Difference]: Start difference. First operand 99398 states and 140975 transitions. cyclomatic complexity: 41641 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:22,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:22,166 INFO L93 Difference]: Finished difference Result 124856 states and 177173 transitions. [2022-11-16 12:49:22,166 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124856 states and 177173 transitions. [2022-11-16 12:49:23,545 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124121 [2022-11-16 12:49:23,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124856 states to 124856 states and 177173 transitions. [2022-11-16 12:49:23,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124856 [2022-11-16 12:49:23,912 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124856 [2022-11-16 12:49:23,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124856 states and 177173 transitions. [2022-11-16 12:49:23,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:23,976 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124856 states and 177173 transitions. [2022-11-16 12:49:24,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124856 states and 177173 transitions. [2022-11-16 12:49:25,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124856 to 54166. [2022-11-16 12:49:25,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.4244175312926928) internal successors, (77155), 54165 states have internal predecessors, (77155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:25,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 77155 transitions. [2022-11-16 12:49:25,167 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 77155 transitions. [2022-11-16 12:49:25,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:25,168 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 77155 transitions. [2022-11-16 12:49:25,168 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 12:49:25,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 77155 transitions. [2022-11-16 12:49:25,310 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-11-16 12:49:25,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:25,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:25,312 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:25,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:25,312 INFO L748 eck$LassoCheckResult]: Stem: 782758#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 782759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 782624#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 782565#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 782566#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 782910#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 782548#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 782380#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 782381#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 782362#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 782363#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 782909#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 782691#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 782692#L769 assume !(0 == ~M_E~0); 782714#L769-2 assume !(0 == ~T1_E~0); 782715#L774-1 assume !(0 == ~T2_E~0); 782749#L779-1 assume !(0 == ~T3_E~0); 782892#L784-1 assume !(0 == ~T4_E~0); 782687#L789-1 assume !(0 == ~T5_E~0); 782688#L794-1 assume !(0 == ~T6_E~0); 782817#L799-1 assume !(0 == ~T7_E~0); 782694#L804-1 assume !(0 == ~E_M~0); 782695#L809-1 assume !(0 == ~E_1~0); 782739#L814-1 assume !(0 == ~E_2~0); 782101#L819-1 assume !(0 == ~E_3~0); 782102#L824-1 assume !(0 == ~E_4~0); 782447#L829-1 assume !(0 == ~E_5~0); 782979#L834-1 assume !(0 == ~E_6~0); 782229#L839-1 assume !(0 == ~E_7~0); 782230#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 782634#L376 assume !(1 == ~m_pc~0); 782630#L376-2 is_master_triggered_~__retres1~0#1 := 0; 782631#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 782950#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 782180#L955 assume !(0 != activate_threads_~tmp~1#1); 782181#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 782541#L395 assume !(1 == ~t1_pc~0); 782717#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 782877#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 782107#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 782108#L963 assume !(0 != activate_threads_~tmp___0~0#1); 782639#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 782640#L414 assume !(1 == ~t2_pc~0); 782232#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 782233#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 782434#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 782435#L971 assume !(0 != activate_threads_~tmp___1~0#1); 782914#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 782544#L433 assume !(1 == ~t3_pc~0); 782349#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 782350#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 782512#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 782513#L979 assume !(0 != activate_threads_~tmp___2~0#1); 782201#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 782202#L452 assume !(1 == ~t4_pc~0); 782358#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 782359#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 782673#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 782748#L987 assume !(0 != activate_threads_~tmp___3~0#1); 782391#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 782392#L471 assume !(1 == ~t5_pc~0); 782796#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 782374#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 782375#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 782740#L995 assume !(0 != activate_threads_~tmp___4~0#1); 782966#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 782967#L490 assume !(1 == ~t6_pc~0); 782637#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 782638#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 782680#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 782683#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 782553#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 782522#L509 assume !(1 == ~t7_pc~0); 782523#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 782916#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 783060#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 782396#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 782397#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 782925#L857 assume !(1 == ~M_E~0); 782187#L857-2 assume !(1 == ~T1_E~0); 782188#L862-1 assume !(1 == ~T2_E~0); 782456#L867-1 assume !(1 == ~T3_E~0); 782461#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 782545#L877-1 assume !(1 == ~T5_E~0); 782771#L882-1 assume !(1 == ~T6_E~0); 782936#L887-1 assume !(1 == ~T7_E~0); 782837#L892-1 assume !(1 == ~E_M~0); 782838#L897-1 assume !(1 == ~E_1~0); 782472#L902-1 assume !(1 == ~E_2~0); 782473#L907-1 assume !(1 == ~E_3~0); 782788#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 782779#L917-1 assume !(1 == ~E_5~0); 782780#L922-1 assume !(1 == ~E_6~0); 782983#L927-1 assume !(1 == ~E_7~0); 782766#L932-1 assume { :end_inline_reset_delta_events } true; 782767#L1178-2 [2022-11-16 12:49:25,313 INFO L750 eck$LassoCheckResult]: Loop: 782767#L1178-2 assume !false; 820505#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 820503#L744 assume !false; 820501#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 820499#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 820490#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 820488#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 820485#L641 assume !(0 != eval_~tmp~0#1); 820486#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 824722#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 824720#L769-3 assume !(0 == ~M_E~0); 824718#L769-5 assume !(0 == ~T1_E~0); 824715#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 824713#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 824711#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 824709#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 824707#L794-3 assume !(0 == ~T6_E~0); 824705#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 824702#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 824700#L809-3 assume !(0 == ~E_1~0); 824698#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 824696#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 824694#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 824691#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 824690#L834-3 assume !(0 == ~E_6~0); 824689#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 824687#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 824686#L376-27 assume !(1 == ~m_pc~0); 824685#L376-29 is_master_triggered_~__retres1~0#1 := 0; 824684#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 824682#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 824681#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 824680#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 824679#L395-27 assume !(1 == ~t1_pc~0); 824678#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 824677#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 824676#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 824675#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 824674#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 824673#L414-27 assume !(1 == ~t2_pc~0); 824670#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 824668#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 824666#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 824663#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 824661#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 824659#L433-27 assume !(1 == ~t3_pc~0); 824657#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 824655#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 824653#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 824652#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 824650#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 824648#L452-27 assume 1 == ~t4_pc~0; 824645#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 824643#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 824641#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 824638#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 824636#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 824634#L471-27 assume !(1 == ~t5_pc~0); 824632#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 824630#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 824628#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 824627#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 824625#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 824623#L490-27 assume !(1 == ~t6_pc~0); 824621#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 824619#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 824617#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 824614#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 824612#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 824610#L509-27 assume !(1 == ~t7_pc~0); 824606#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 824604#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 824602#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 824599#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 824596#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 824594#L857-3 assume !(1 == ~M_E~0); 797148#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 824591#L862-3 assume !(1 == ~T2_E~0); 824589#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 824586#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 824584#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 824582#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 824580#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 824578#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 824577#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 824573#L902-3 assume !(1 == ~E_2~0); 824571#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 824569#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 824567#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 824564#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 824562#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 824561#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 822337#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 822331#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 822330#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 797118#L1197 assume !(0 == start_simulation_~tmp~3#1); 797119#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 820592#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 820586#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 820584#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 820582#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 820580#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 820578#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 820576#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 782767#L1178-2 [2022-11-16 12:49:25,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:25,314 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2022-11-16 12:49:25,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:25,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880874327] [2022-11-16 12:49:25,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:25,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:25,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:25,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:25,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:25,390 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880874327] [2022-11-16 12:49:25,390 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1880874327] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:25,390 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:25,390 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:25,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729255634] [2022-11-16 12:49:25,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:25,391 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:25,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:25,391 INFO L85 PathProgramCache]: Analyzing trace with hash -1156970453, now seen corresponding path program 1 times [2022-11-16 12:49:25,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:25,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222203265] [2022-11-16 12:49:25,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:25,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:25,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:25,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:25,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:25,431 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222203265] [2022-11-16 12:49:25,431 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1222203265] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:25,431 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:25,431 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:25,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958794252] [2022-11-16 12:49:25,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:25,432 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:25,432 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:25,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:25,433 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:25,433 INFO L87 Difference]: Start difference. First operand 54166 states and 77155 transitions. cyclomatic complexity: 23005 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:25,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:25,742 INFO L93 Difference]: Finished difference Result 86719 states and 122940 transitions. [2022-11-16 12:49:25,743 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86719 states and 122940 transitions. [2022-11-16 12:49:26,656 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86163 [2022-11-16 12:49:26,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86719 states to 86719 states and 122940 transitions. [2022-11-16 12:49:26,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86719 [2022-11-16 12:49:26,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86719 [2022-11-16 12:49:26,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86719 states and 122940 transitions. [2022-11-16 12:49:27,007 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:27,007 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86719 states and 122940 transitions. [2022-11-16 12:49:27,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86719 states and 122940 transitions. [2022-11-16 12:49:27,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86719 to 62099. [2022-11-16 12:49:27,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62099 states, 62099 states have (on average 1.4212145123109874) internal successors, (88256), 62098 states have internal predecessors, (88256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:27,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62099 states to 62099 states and 88256 transitions. [2022-11-16 12:49:27,842 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62099 states and 88256 transitions. [2022-11-16 12:49:27,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:27,843 INFO L428 stractBuchiCegarLoop]: Abstraction has 62099 states and 88256 transitions. [2022-11-16 12:49:27,843 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 12:49:27,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62099 states and 88256 transitions. [2022-11-16 12:49:28,042 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61679 [2022-11-16 12:49:28,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:28,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:28,044 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:28,044 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:28,045 INFO L748 eck$LassoCheckResult]: Stem: 923662#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 923663#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 923518#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 923465#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 923466#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 923814#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 923448#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 923277#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 923278#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 923259#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 923260#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 923813#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 923592#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 923593#L769 assume !(0 == ~M_E~0); 923615#L769-2 assume !(0 == ~T1_E~0); 923616#L774-1 assume !(0 == ~T2_E~0); 923654#L779-1 assume !(0 == ~T3_E~0); 923792#L784-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 923793#L789-1 assume !(0 == ~T5_E~0); 924022#L794-1 assume !(0 == ~T6_E~0); 923996#L799-1 assume !(0 == ~T7_E~0); 923997#L804-1 assume !(0 == ~E_M~0); 923641#L809-1 assume !(0 == ~E_1~0); 923642#L814-1 assume !(0 == ~E_2~0); 922998#L819-1 assume !(0 == ~E_3~0); 922999#L824-1 assume !(0 == ~E_4~0); 923988#L829-1 assume !(0 == ~E_5~0); 923989#L834-1 assume !(0 == ~E_6~0); 923126#L839-1 assume !(0 == ~E_7~0); 923127#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 923722#L376 assume !(1 == ~m_pc~0); 923523#L376-2 is_master_triggered_~__retres1~0#1 := 0; 923524#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 923861#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 923862#L955 assume !(0 != activate_threads_~tmp~1#1); 924020#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 923617#L395 assume !(1 == ~t1_pc~0); 923618#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 923794#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 923795#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 923837#L963 assume !(0 != activate_threads_~tmp___0~0#1); 923838#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 924000#L414 assume !(1 == ~t2_pc~0); 924001#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 923994#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 923995#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 923820#L971 assume !(0 != activate_threads_~tmp___1~0#1); 923821#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 924019#L433 assume !(1 == ~t3_pc~0); 923246#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 923247#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 923414#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 923415#L979 assume !(0 != activate_threads_~tmp___2~0#1); 923098#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 923099#L452 assume !(1 == ~t4_pc~0); 923255#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 923256#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 923652#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 923653#L987 assume !(0 != activate_threads_~tmp___3~0#1); 923288#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 923289#L471 assume !(1 == ~t5_pc~0); 923698#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 923271#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 923272#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 923992#L995 assume !(0 != activate_threads_~tmp___4~0#1); 923993#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 923941#L490 assume !(1 == ~t6_pc~0); 923942#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 923579#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 923580#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 923702#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 924014#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 924013#L509 assume !(1 == ~t7_pc~0); 923825#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 923226#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 923227#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 923293#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 923294#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 923833#L857 assume !(1 == ~M_E~0); 923834#L857-2 assume !(1 == ~T1_E~0); 923358#L862-1 assume !(1 == ~T2_E~0); 923359#L867-1 assume !(1 == ~T3_E~0); 924010#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 923445#L877-1 assume !(1 == ~T5_E~0); 923674#L882-1 assume !(1 == ~T6_E~0); 923849#L887-1 assume !(1 == ~T7_E~0); 923738#L892-1 assume !(1 == ~E_M~0); 923739#L897-1 assume !(1 == ~E_1~0); 923377#L902-1 assume !(1 == ~E_2~0); 923378#L907-1 assume !(1 == ~E_3~0); 923692#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 923683#L917-1 assume !(1 == ~E_5~0); 923684#L922-1 assume !(1 == ~E_6~0); 923896#L927-1 assume !(1 == ~E_7~0); 923669#L932-1 assume { :end_inline_reset_delta_events } true; 923670#L1178-2 [2022-11-16 12:49:28,046 INFO L750 eck$LassoCheckResult]: Loop: 923670#L1178-2 assume !false; 958773#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 958734#L744 assume !false; 958726#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 958723#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 958715#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 958714#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 958712#L641 assume !(0 != eval_~tmp~0#1); 958713#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 970907#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 970904#L769-3 assume !(0 == ~M_E~0); 970898#L769-5 assume !(0 == ~T1_E~0); 970896#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 970894#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 970892#L784-3 assume !(0 == ~T4_E~0); 970893#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 971295#L794-3 assume !(0 == ~T6_E~0); 971293#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 971288#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 971283#L809-3 assume !(0 == ~E_1~0); 971280#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 971274#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 971272#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 971270#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 971235#L834-3 assume !(0 == ~E_6~0); 971227#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 971149#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 971148#L376-27 assume !(1 == ~m_pc~0); 971147#L376-29 is_master_triggered_~__retres1~0#1 := 0; 971146#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 971145#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 971144#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 971143#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 971142#L395-27 assume !(1 == ~t1_pc~0); 971140#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 971138#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 971136#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 971134#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 971132#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 971130#L414-27 assume 1 == ~t2_pc~0; 971128#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 971125#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 971123#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 971121#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 971119#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 971117#L433-27 assume !(1 == ~t3_pc~0); 971115#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 971113#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 971111#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 971109#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 971107#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 971105#L452-27 assume 1 == ~t4_pc~0; 971103#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 971101#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 971099#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 971097#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 971095#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 971093#L471-27 assume !(1 == ~t5_pc~0); 971090#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 971088#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 971086#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 971084#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 971082#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 971081#L490-27 assume !(1 == ~t6_pc~0); 971080#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 971079#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 971078#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 971077#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 971076#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 971075#L509-27 assume 1 == ~t7_pc~0; 971074#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 971073#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 971071#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 971067#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 971065#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 971064#L857-3 assume !(1 == ~M_E~0); 949675#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 971063#L862-3 assume !(1 == ~T2_E~0); 971062#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 970822#L872-3 assume !(1 == ~T4_E~0); 970812#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 970810#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 970808#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 970805#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 970803#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 970801#L902-3 assume !(1 == ~E_2~0); 970799#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 970797#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 970795#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 970793#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 970736#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 962559#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 962328#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 962323#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 961859#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 949644#L1197 assume !(0 == start_simulation_~tmp~3#1); 949645#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 959071#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 959065#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 959063#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 959060#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 959057#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 959008#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 958997#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 923670#L1178-2 [2022-11-16 12:49:28,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:28,047 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2022-11-16 12:49:28,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:28,047 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089168793] [2022-11-16 12:49:28,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:28,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:28,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:28,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:28,123 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:28,123 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089168793] [2022-11-16 12:49:28,123 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089168793] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:28,123 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:28,123 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:28,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355682742] [2022-11-16 12:49:28,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:28,124 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:28,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:28,125 INFO L85 PathProgramCache]: Analyzing trace with hash -1270050393, now seen corresponding path program 1 times [2022-11-16 12:49:28,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:28,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879258782] [2022-11-16 12:49:28,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:28,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:28,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:28,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:28,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:28,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879258782] [2022-11-16 12:49:28,177 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879258782] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:28,177 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:28,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:28,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571819738] [2022-11-16 12:49:28,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:28,178 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:28,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:28,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:28,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:28,179 INFO L87 Difference]: Start difference. First operand 62099 states and 88256 transitions. cyclomatic complexity: 26173 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:28,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:28,906 INFO L93 Difference]: Finished difference Result 78774 states and 111436 transitions. [2022-11-16 12:49:28,906 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78774 states and 111436 transitions. [2022-11-16 12:49:29,159 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78301 [2022-11-16 12:49:29,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78774 states to 78774 states and 111436 transitions. [2022-11-16 12:49:29,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78774 [2022-11-16 12:49:29,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78774 [2022-11-16 12:49:29,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78774 states and 111436 transitions. [2022-11-16 12:49:29,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:29,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78774 states and 111436 transitions. [2022-11-16 12:49:29,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78774 states and 111436 transitions. [2022-11-16 12:49:30,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78774 to 54166. [2022-11-16 12:49:30,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.4183989956799468) internal successors, (76829), 54165 states have internal predecessors, (76829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:30,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 76829 transitions. [2022-11-16 12:49:30,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 76829 transitions. [2022-11-16 12:49:30,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:30,536 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 76829 transitions. [2022-11-16 12:49:30,536 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 12:49:30,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 76829 transitions. [2022-11-16 12:49:30,668 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-11-16 12:49:30,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:30,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:30,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:30,670 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:30,670 INFO L748 eck$LassoCheckResult]: Stem: 1064533#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 1064534#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1064400#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1064346#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1064347#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1064681#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1064328#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1064158#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1064159#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1064140#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1064141#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1064680#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1064469#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1064470#L769 assume !(0 == ~M_E~0); 1064492#L769-2 assume !(0 == ~T1_E~0); 1064493#L774-1 assume !(0 == ~T2_E~0); 1064525#L779-1 assume !(0 == ~T3_E~0); 1064658#L784-1 assume !(0 == ~T4_E~0); 1064464#L789-1 assume !(0 == ~T5_E~0); 1064465#L794-1 assume !(0 == ~T6_E~0); 1064585#L799-1 assume !(0 == ~T7_E~0); 1064471#L804-1 assume !(0 == ~E_M~0); 1064472#L809-1 assume !(0 == ~E_1~0); 1064514#L814-1 assume !(0 == ~E_2~0); 1063881#L819-1 assume !(0 == ~E_3~0); 1063882#L824-1 assume !(0 == ~E_4~0); 1064227#L829-1 assume !(0 == ~E_5~0); 1064750#L834-1 assume !(0 == ~E_6~0); 1064005#L839-1 assume !(0 == ~E_7~0); 1064006#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1064410#L376 assume !(1 == ~m_pc~0); 1064406#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1064407#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1064721#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1063959#L955 assume !(0 != activate_threads_~tmp~1#1); 1063960#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1064320#L395 assume !(1 == ~t1_pc~0); 1064494#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1064643#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1063887#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1063888#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1064416#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1064417#L414 assume !(1 == ~t2_pc~0); 1064008#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1064009#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1064214#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1064215#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1064686#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1064324#L433 assume !(1 == ~t3_pc~0); 1064127#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1064128#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1064292#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1064293#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1063977#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1063978#L452 assume !(1 == ~t4_pc~0); 1064136#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1064137#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1064450#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1064524#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1064169#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1064170#L471 assume !(1 == ~t5_pc~0); 1064568#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1064152#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1064153#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1064515#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1064736#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1064737#L490 assume !(1 == ~t6_pc~0); 1064413#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1064414#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1064456#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1064460#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1064335#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1064299#L509 assume !(1 == ~t7_pc~0); 1064300#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1064108#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1064109#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1064174#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1064175#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1064695#L857 assume !(1 == ~M_E~0); 1063964#L857-2 assume !(1 == ~T1_E~0); 1063965#L862-1 assume !(1 == ~T2_E~0); 1064237#L867-1 assume !(1 == ~T3_E~0); 1064242#L872-1 assume !(1 == ~T4_E~0); 1064325#L877-1 assume !(1 == ~T5_E~0); 1064544#L882-1 assume !(1 == ~T6_E~0); 1064713#L887-1 assume !(1 == ~T7_E~0); 1064605#L892-1 assume !(1 == ~E_M~0); 1064606#L897-1 assume !(1 == ~E_1~0); 1064254#L902-1 assume !(1 == ~E_2~0); 1064255#L907-1 assume !(1 == ~E_3~0); 1064561#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1064552#L917-1 assume !(1 == ~E_5~0); 1064553#L922-1 assume !(1 == ~E_6~0); 1064754#L927-1 assume !(1 == ~E_7~0); 1064539#L932-1 assume { :end_inline_reset_delta_events } true; 1064540#L1178-2 [2022-11-16 12:49:30,671 INFO L750 eck$LassoCheckResult]: Loop: 1064540#L1178-2 assume !false; 1095978#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1095976#L744 assume !false; 1095974#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1095972#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1095963#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1095961#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1095959#L641 assume !(0 != eval_~tmp~0#1); 1095960#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1102070#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1102069#L769-3 assume !(0 == ~M_E~0); 1102067#L769-5 assume !(0 == ~T1_E~0); 1102066#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1102065#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1102064#L784-3 assume !(0 == ~T4_E~0); 1102063#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1102062#L794-3 assume !(0 == ~T6_E~0); 1102061#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1102060#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1102059#L809-3 assume !(0 == ~E_1~0); 1102058#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1102057#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1102055#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1102053#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1102051#L834-3 assume !(0 == ~E_6~0); 1102049#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1102047#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1102045#L376-27 assume !(1 == ~m_pc~0); 1102043#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1102041#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1102038#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1102035#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1102033#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1102031#L395-27 assume !(1 == ~t1_pc~0); 1102029#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1102027#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1102025#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1102022#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1102020#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1102018#L414-27 assume 1 == ~t2_pc~0; 1102016#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1102013#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1102011#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1102009#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1102007#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1102005#L433-27 assume !(1 == ~t3_pc~0); 1102003#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1102001#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1101999#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1101996#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1101994#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1101992#L452-27 assume 1 == ~t4_pc~0; 1101989#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1101987#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1101985#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1101982#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1101980#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1101978#L471-27 assume !(1 == ~t5_pc~0); 1101976#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1101974#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1101971#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1101970#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1101967#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1101965#L490-27 assume !(1 == ~t6_pc~0); 1101963#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1101961#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1101959#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1101955#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1101953#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1101951#L509-27 assume !(1 == ~t7_pc~0); 1101947#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1101944#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1101942#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1101939#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1101936#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1101934#L857-3 assume !(1 == ~M_E~0); 1091193#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1101933#L862-3 assume !(1 == ~T2_E~0); 1101932#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1101931#L872-3 assume !(1 == ~T4_E~0); 1101930#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1101928#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1101926#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1101924#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1101922#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1101920#L902-3 assume !(1 == ~E_2~0); 1101918#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1101916#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1101914#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1101912#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1101910#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1101908#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1101896#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1101889#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1101888#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1091179#L1197 assume !(0 == start_simulation_~tmp~3#1); 1091180#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1096428#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1096423#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1096422#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1096421#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1096420#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1096419#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1096418#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1064540#L1178-2 [2022-11-16 12:49:30,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:30,672 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2022-11-16 12:49:30,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:30,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082122767] [2022-11-16 12:49:30,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:30,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:30,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:30,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:30,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:30,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082122767] [2022-11-16 12:49:30,738 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082122767] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:30,738 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:30,738 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:30,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386763352] [2022-11-16 12:49:30,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:30,739 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:30,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:30,739 INFO L85 PathProgramCache]: Analyzing trace with hash 482998570, now seen corresponding path program 1 times [2022-11-16 12:49:30,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:30,739 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565746293] [2022-11-16 12:49:30,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:30,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:30,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:30,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:30,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:30,776 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565746293] [2022-11-16 12:49:30,776 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565746293] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:30,776 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:30,777 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:30,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1898165483] [2022-11-16 12:49:30,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:30,777 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:30,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:30,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:30,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:30,778 INFO L87 Difference]: Start difference. First operand 54166 states and 76829 transitions. cyclomatic complexity: 22679 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:31,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:31,126 INFO L93 Difference]: Finished difference Result 86752 states and 121537 transitions. [2022-11-16 12:49:31,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86752 states and 121537 transitions. [2022-11-16 12:49:31,436 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86146 [2022-11-16 12:49:31,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86752 states to 86752 states and 121537 transitions. [2022-11-16 12:49:31,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86752 [2022-11-16 12:49:31,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86752 [2022-11-16 12:49:31,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86752 states and 121537 transitions. [2022-11-16 12:49:31,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:31,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86752 states and 121537 transitions. [2022-11-16 12:49:31,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86752 states and 121537 transitions. [2022-11-16 12:49:32,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86752 to 62099. [2022-11-16 12:49:32,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62099 states, 62099 states have (on average 1.40557818966489) internal successors, (87285), 62098 states have internal predecessors, (87285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:32,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62099 states to 62099 states and 87285 transitions. [2022-11-16 12:49:32,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62099 states and 87285 transitions. [2022-11-16 12:49:32,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:32,961 INFO L428 stractBuchiCegarLoop]: Abstraction has 62099 states and 87285 transitions. [2022-11-16 12:49:32,961 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 12:49:32,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62099 states and 87285 transitions. [2022-11-16 12:49:33,115 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61679 [2022-11-16 12:49:33,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:33,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:33,116 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:33,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:33,117 INFO L748 eck$LassoCheckResult]: Stem: 1205488#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 1205489#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1205335#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1205280#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1205281#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1205660#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1205258#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1205086#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1205087#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1205068#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1205069#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1205658#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1205411#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1205412#L769 assume !(0 == ~M_E~0); 1205436#L769-2 assume !(0 == ~T1_E~0); 1205437#L774-1 assume !(0 == ~T2_E~0); 1205477#L779-1 assume !(0 == ~T3_E~0); 1205635#L784-1 assume !(0 == ~T4_E~0); 1205405#L789-1 assume !(0 == ~T5_E~0); 1205406#L794-1 assume !(0 == ~T6_E~0); 1205547#L799-1 assume !(0 == ~T7_E~0); 1205413#L804-1 assume !(0 == ~E_M~0); 1205414#L809-1 assume !(0 == ~E_1~0); 1205464#L814-1 assume !(0 == ~E_2~0); 1204811#L819-1 assume !(0 == ~E_3~0); 1204812#L824-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1205158#L829-1 assume !(0 == ~E_5~0); 1205847#L834-1 assume !(0 == ~E_6~0); 1204936#L839-1 assume !(0 == ~E_7~0); 1204937#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1205345#L376 assume !(1 == ~m_pc~0); 1205346#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1205817#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1205818#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1204889#L955 assume !(0 != activate_threads_~tmp~1#1); 1204890#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1205438#L395 assume !(1 == ~t1_pc~0); 1205439#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1205636#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1205637#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1205682#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1205683#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1205857#L414 assume !(1 == ~t2_pc~0); 1205858#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1205848#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1205849#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1205666#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1205667#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1205253#L433 assume !(1 == ~t3_pc~0); 1205254#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1205770#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1205771#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1205601#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1205602#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1205829#L452 assume !(1 == ~t4_pc~0); 1205830#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1205877#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1205897#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1205896#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1205895#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1205894#L471 assume !(1 == ~t5_pc~0); 1205893#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1205892#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1205891#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1205890#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1205889#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1205888#L490 assume !(1 == ~t6_pc~0); 1205887#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1205886#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1205885#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1205884#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1205883#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1205882#L509 assume !(1 == ~t7_pc~0); 1205668#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1205039#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1205040#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1205875#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1205874#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1205873#L857 assume !(1 == ~M_E~0); 1205872#L857-2 assume !(1 == ~T1_E~0); 1205871#L862-1 assume !(1 == ~T2_E~0); 1205870#L867-1 assume !(1 == ~T3_E~0); 1205869#L872-1 assume !(1 == ~T4_E~0); 1205868#L877-1 assume !(1 == ~T5_E~0); 1205867#L882-1 assume !(1 == ~T6_E~0); 1205866#L887-1 assume !(1 == ~T7_E~0); 1205865#L892-1 assume !(1 == ~E_M~0); 1205864#L897-1 assume !(1 == ~E_1~0); 1205863#L902-1 assume !(1 == ~E_2~0); 1205862#L907-1 assume !(1 == ~E_3~0); 1205861#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1205510#L917-1 assume !(1 == ~E_5~0); 1205511#L922-1 assume !(1 == ~E_6~0); 1205754#L927-1 assume !(1 == ~E_7~0); 1205496#L932-1 assume { :end_inline_reset_delta_events } true; 1205497#L1178-2 [2022-11-16 12:49:33,117 INFO L750 eck$LassoCheckResult]: Loop: 1205497#L1178-2 assume !false; 1249535#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1249532#L744 assume !false; 1249530#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1249528#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1249519#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1249517#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1249514#L641 assume !(0 != eval_~tmp~0#1); 1249515#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1265346#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1265341#L769-3 assume !(0 == ~M_E~0); 1265335#L769-5 assume !(0 == ~T1_E~0); 1265328#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1265318#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1216183#L784-3 assume !(0 == ~T4_E~0); 1216184#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1264614#L794-3 assume !(0 == ~T6_E~0); 1264613#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1216166#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1216162#L809-3 assume !(0 == ~E_1~0); 1216163#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1258965#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1258963#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1258962#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1258961#L834-3 assume !(0 == ~E_6~0); 1258960#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1258959#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1258958#L376-27 assume !(1 == ~m_pc~0); 1258957#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1258956#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1258955#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1258954#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1258953#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1258952#L395-27 assume !(1 == ~t1_pc~0); 1258951#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1258950#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1258949#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1258948#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1258947#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1258946#L414-27 assume 1 == ~t2_pc~0; 1258945#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1258943#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1258942#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1258941#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1258940#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1258939#L433-27 assume !(1 == ~t3_pc~0); 1258938#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1258937#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1258936#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1258935#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1258934#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1258933#L452-27 assume 1 == ~t4_pc~0; 1258931#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1258930#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1258929#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1258928#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1258927#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1258926#L471-27 assume !(1 == ~t5_pc~0); 1258925#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1258924#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1258923#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1258922#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1258921#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1258920#L490-27 assume !(1 == ~t6_pc~0); 1258919#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1258918#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1258917#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1258916#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1258915#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1258914#L509-27 assume !(1 == ~t7_pc~0); 1258913#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1258911#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1258909#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1258907#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1258905#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1258904#L857-3 assume !(1 == ~M_E~0); 1233051#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1258903#L862-3 assume !(1 == ~T2_E~0); 1258902#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1258901#L872-3 assume !(1 == ~T4_E~0); 1258900#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1258899#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1258898#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1258897#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1258896#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1258895#L902-3 assume !(1 == ~E_2~0); 1258894#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1258893#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1258892#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1258889#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1258887#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1258885#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1258873#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1258867#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1255274#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1232903#L1197 assume !(0 == start_simulation_~tmp~3#1); 1232904#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1249754#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1249748#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1249746#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1249744#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1249742#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1249740#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1249738#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1205497#L1178-2 [2022-11-16 12:49:33,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:33,118 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2022-11-16 12:49:33,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:33,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740239594] [2022-11-16 12:49:33,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:33,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:33,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:33,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:33,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:33,174 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740239594] [2022-11-16 12:49:33,174 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740239594] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:33,174 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:33,174 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:33,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593403599] [2022-11-16 12:49:33,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:33,175 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:33,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:33,175 INFO L85 PathProgramCache]: Analyzing trace with hash 482998570, now seen corresponding path program 2 times [2022-11-16 12:49:33,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:33,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837172213] [2022-11-16 12:49:33,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:33,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:33,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:33,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:33,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:33,213 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837172213] [2022-11-16 12:49:33,213 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837172213] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:33,213 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:33,213 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:33,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [390084216] [2022-11-16 12:49:33,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:33,214 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:33,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:33,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:33,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:33,215 INFO L87 Difference]: Start difference. First operand 62099 states and 87285 transitions. cyclomatic complexity: 25202 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:33,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:33,510 INFO L93 Difference]: Finished difference Result 77737 states and 108679 transitions. [2022-11-16 12:49:33,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77737 states and 108679 transitions. [2022-11-16 12:49:34,416 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 77246 [2022-11-16 12:49:34,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77737 states to 77737 states and 108679 transitions. [2022-11-16 12:49:34,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77737 [2022-11-16 12:49:34,597 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77737 [2022-11-16 12:49:34,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77737 states and 108679 transitions. [2022-11-16 12:49:34,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:34,634 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77737 states and 108679 transitions. [2022-11-16 12:49:34,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77737 states and 108679 transitions. [2022-11-16 12:49:35,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77737 to 54166. [2022-11-16 12:49:35,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.4004726212014917) internal successors, (75858), 54165 states have internal predecessors, (75858), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:35,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 75858 transitions. [2022-11-16 12:49:35,318 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 75858 transitions. [2022-11-16 12:49:35,319 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:35,319 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 75858 transitions. [2022-11-16 12:49:35,320 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 12:49:35,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 75858 transitions. [2022-11-16 12:49:35,493 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-11-16 12:49:35,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:35,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:35,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:35,495 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:35,495 INFO L748 eck$LassoCheckResult]: Stem: 1345302#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 1345303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1345167#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1345115#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1345116#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1345462#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1345095#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1344931#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1344932#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1344914#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1344915#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1345460#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1345235#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1345236#L769 assume !(0 == ~M_E~0); 1345259#L769-2 assume !(0 == ~T1_E~0); 1345260#L774-1 assume !(0 == ~T2_E~0); 1345294#L779-1 assume !(0 == ~T3_E~0); 1345438#L784-1 assume !(0 == ~T4_E~0); 1345230#L789-1 assume !(0 == ~T5_E~0); 1345231#L794-1 assume !(0 == ~T6_E~0); 1345363#L799-1 assume !(0 == ~T7_E~0); 1345237#L804-1 assume !(0 == ~E_M~0); 1345238#L809-1 assume !(0 == ~E_1~0); 1345284#L814-1 assume !(0 == ~E_2~0); 1344657#L819-1 assume !(0 == ~E_3~0); 1344658#L824-1 assume !(0 == ~E_4~0); 1345000#L829-1 assume !(0 == ~E_5~0); 1345538#L834-1 assume !(0 == ~E_6~0); 1344782#L839-1 assume !(0 == ~E_7~0); 1344783#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1345176#L376 assume !(1 == ~m_pc~0); 1345172#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1345173#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1345509#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1344735#L955 assume !(0 != activate_threads_~tmp~1#1); 1344736#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1345088#L395 assume !(1 == ~t1_pc~0); 1345261#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1345422#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1344661#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1344662#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1345183#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1345184#L414 assume !(1 == ~t2_pc~0); 1344785#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1344786#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1344987#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1344988#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1345468#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1345091#L433 assume !(1 == ~t3_pc~0); 1344901#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1344902#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1345063#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1345064#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1344753#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1344754#L452 assume !(1 == ~t4_pc~0); 1344910#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1344911#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1345216#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1345293#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1344942#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1344943#L471 assume !(1 == ~t5_pc~0); 1345345#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1344925#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1344926#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1345285#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1345525#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1345526#L490 assume !(1 == ~t6_pc~0); 1345179#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1345180#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1345225#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1345228#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1345104#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1345068#L509 assume !(1 == ~t7_pc~0); 1345069#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1344886#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1344887#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1344947#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1344948#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1345478#L857 assume !(1 == ~M_E~0); 1344740#L857-2 assume !(1 == ~T1_E~0); 1344741#L862-1 assume !(1 == ~T2_E~0); 1345009#L867-1 assume !(1 == ~T3_E~0); 1345014#L872-1 assume !(1 == ~T4_E~0); 1345092#L877-1 assume !(1 == ~T5_E~0); 1345316#L882-1 assume !(1 == ~T6_E~0); 1345491#L887-1 assume !(1 == ~T7_E~0); 1345383#L892-1 assume !(1 == ~E_M~0); 1345384#L897-1 assume !(1 == ~E_1~0); 1345027#L902-1 assume !(1 == ~E_2~0); 1345028#L907-1 assume !(1 == ~E_3~0); 1345334#L912-1 assume !(1 == ~E_4~0); 1345324#L917-1 assume !(1 == ~E_5~0); 1345325#L922-1 assume !(1 == ~E_6~0); 1345541#L927-1 assume !(1 == ~E_7~0); 1345311#L932-1 assume { :end_inline_reset_delta_events } true; 1345312#L1178-2 [2022-11-16 12:49:35,496 INFO L750 eck$LassoCheckResult]: Loop: 1345312#L1178-2 assume !false; 1362533#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1362515#L744 assume !false; 1362510#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1362223#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1362214#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1362211#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1362208#L641 assume !(0 != eval_~tmp~0#1); 1362206#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1362204#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1362192#L769-3 assume !(0 == ~M_E~0); 1362183#L769-5 assume !(0 == ~T1_E~0); 1362173#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1362163#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1362158#L784-3 assume !(0 == ~T4_E~0); 1362152#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1362147#L794-3 assume !(0 == ~T6_E~0); 1362142#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1362137#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1362131#L809-3 assume !(0 == ~E_1~0); 1362126#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1362122#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1362117#L824-3 assume !(0 == ~E_4~0); 1362111#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1362106#L834-3 assume !(0 == ~E_6~0); 1362102#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1362096#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1362091#L376-27 assume !(1 == ~m_pc~0); 1362085#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1362080#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1362074#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1362069#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1362064#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1362059#L395-27 assume !(1 == ~t1_pc~0); 1362053#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1362048#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1362043#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1362038#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1362033#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1361943#L414-27 assume !(1 == ~t2_pc~0); 1361910#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1361904#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1361898#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1361892#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1361808#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1361805#L433-27 assume !(1 == ~t3_pc~0); 1361803#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1361801#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1361800#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1361798#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1361796#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1361794#L452-27 assume !(1 == ~t4_pc~0); 1361791#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1361789#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1361787#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1361785#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1361783#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1361781#L471-27 assume !(1 == ~t5_pc~0); 1361779#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1361777#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1361775#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1361773#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1361742#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1361723#L490-27 assume !(1 == ~t6_pc~0); 1361722#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1361721#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1361720#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1361719#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1361718#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1361717#L509-27 assume !(1 == ~t7_pc~0); 1361714#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1361705#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1361703#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1361701#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1361698#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1361696#L857-3 assume !(1 == ~M_E~0); 1354609#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1361691#L862-3 assume !(1 == ~T2_E~0); 1361689#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1361687#L872-3 assume !(1 == ~T4_E~0); 1361685#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1361682#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1361680#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1361678#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1361677#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1361675#L902-3 assume !(1 == ~E_2~0); 1361673#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1361671#L912-3 assume !(1 == ~E_4~0); 1361669#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1361667#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1361653#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1361647#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1358163#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1358157#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1358155#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1354647#L1197 assume !(0 == start_simulation_~tmp~3#1); 1354648#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1362626#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1362612#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1362594#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1362582#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1362573#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1362553#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1362546#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1345312#L1178-2 [2022-11-16 12:49:35,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:35,497 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2022-11-16 12:49:35,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:35,497 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792394410] [2022-11-16 12:49:35,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:35,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:35,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:49:35,514 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:49:35,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:49:35,576 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:49:35,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:35,577 INFO L85 PathProgramCache]: Analyzing trace with hash 565272940, now seen corresponding path program 1 times [2022-11-16 12:49:35,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:35,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781878564] [2022-11-16 12:49:35,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:35,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:35,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:35,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:35,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:35,622 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781878564] [2022-11-16 12:49:35,622 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1781878564] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:35,623 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:35,623 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:35,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758199123] [2022-11-16 12:49:35,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:35,624 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:35,624 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:35,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:35,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:35,625 INFO L87 Difference]: Start difference. First operand 54166 states and 75858 transitions. cyclomatic complexity: 21708 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:36,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:36,247 INFO L93 Difference]: Finished difference Result 62099 states and 86740 transitions. [2022-11-16 12:49:36,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62099 states and 86740 transitions. [2022-11-16 12:49:36,443 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61679 [2022-11-16 12:49:36,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62099 states to 62099 states and 86740 transitions. [2022-11-16 12:49:36,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62099 [2022-11-16 12:49:36,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62099 [2022-11-16 12:49:36,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62099 states and 86740 transitions. [2022-11-16 12:49:36,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:36,589 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62099 states and 86740 transitions. [2022-11-16 12:49:36,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62099 states and 86740 transitions. [2022-11-16 12:49:36,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62099 to 62099. [2022-11-16 12:49:36,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62099 states, 62099 states have (on average 1.3968018808676468) internal successors, (86740), 62098 states have internal predecessors, (86740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:37,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62099 states to 62099 states and 86740 transitions. [2022-11-16 12:49:37,087 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62099 states and 86740 transitions. [2022-11-16 12:49:37,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:37,088 INFO L428 stractBuchiCegarLoop]: Abstraction has 62099 states and 86740 transitions. [2022-11-16 12:49:37,088 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-16 12:49:37,088 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62099 states and 86740 transitions. [2022-11-16 12:49:37,235 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61679 [2022-11-16 12:49:37,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:37,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:37,236 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:37,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:37,237 INFO L748 eck$LassoCheckResult]: Stem: 1461580#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 1461581#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1461441#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1461384#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1461385#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1461748#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1461367#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1461199#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1461200#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1461182#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1461183#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1461747#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1461513#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1461514#L769 assume !(0 == ~M_E~0); 1461536#L769-2 assume !(0 == ~T1_E~0); 1461537#L774-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1461571#L779-1 assume !(0 == ~T3_E~0); 1461725#L784-1 assume !(0 == ~T4_E~0); 1461726#L789-1 assume !(0 == ~T5_E~0); 1461975#L794-1 assume !(0 == ~T6_E~0); 1461974#L799-1 assume !(0 == ~T7_E~0); 1461515#L804-1 assume !(0 == ~E_M~0); 1461516#L809-1 assume !(0 == ~E_1~0); 1461561#L814-1 assume !(0 == ~E_2~0); 1460926#L819-1 assume !(0 == ~E_3~0); 1460927#L824-1 assume !(0 == ~E_4~0); 1461972#L829-1 assume !(0 == ~E_5~0); 1461834#L834-1 assume !(0 == ~E_6~0); 1461835#L839-1 assume !(0 == ~E_7~0); 1461971#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1461450#L376 assume !(1 == ~m_pc~0); 1461451#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1461906#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1461907#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1461005#L955 assume !(0 != activate_threads_~tmp~1#1); 1461006#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1461359#L395 assume !(1 == ~t1_pc~0); 1461707#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1461708#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1460932#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1460933#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1461457#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1461458#L414 assume !(1 == ~t2_pc~0); 1461940#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1461968#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1461254#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1461255#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1461844#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1461362#L433 assume !(1 == ~t3_pc~0); 1461363#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1461966#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1461965#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1461964#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1461963#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1461961#L452 assume !(1 == ~t4_pc~0); 1461178#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1461179#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1461960#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1461854#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1461855#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1461959#L471 assume !(1 == ~t5_pc~0); 1461877#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1461878#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1461958#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1461957#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1461821#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1461822#L490 assume !(1 == ~t6_pc~0); 1461454#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1461455#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1461956#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1461955#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1461954#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1461953#L509 assume !(1 == ~t7_pc~0); 1461758#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1461154#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1461155#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1461215#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1461216#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1461768#L857 assume !(1 == ~M_E~0); 1461010#L857-2 assume !(1 == ~T1_E~0); 1461011#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1461277#L867-1 assume !(1 == ~T3_E~0); 1461282#L872-1 assume !(1 == ~T4_E~0); 1461364#L877-1 assume !(1 == ~T5_E~0); 1461593#L882-1 assume !(1 == ~T6_E~0); 1461787#L887-1 assume !(1 == ~T7_E~0); 1461664#L892-1 assume !(1 == ~E_M~0); 1461665#L897-1 assume !(1 == ~E_1~0); 1461295#L902-1 assume !(1 == ~E_2~0); 1461296#L907-1 assume !(1 == ~E_3~0); 1461610#L912-1 assume !(1 == ~E_4~0); 1461601#L917-1 assume !(1 == ~E_5~0); 1461602#L922-1 assume !(1 == ~E_6~0); 1461841#L927-1 assume !(1 == ~E_7~0); 1461588#L932-1 assume { :end_inline_reset_delta_events } true; 1461589#L1178-2 [2022-11-16 12:49:37,238 INFO L750 eck$LassoCheckResult]: Loop: 1461589#L1178-2 assume !false; 1497698#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1497692#L744 assume !false; 1497687#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1497613#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1497598#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1497590#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1497582#L641 assume !(0 != eval_~tmp~0#1); 1497583#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1498199#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1498197#L769-3 assume !(0 == ~M_E~0); 1498195#L769-5 assume !(0 == ~T1_E~0); 1498192#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1498193#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1499438#L784-3 assume !(0 == ~T4_E~0); 1499436#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1499434#L794-3 assume !(0 == ~T6_E~0); 1499432#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1499429#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1499427#L809-3 assume !(0 == ~E_1~0); 1499425#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1499423#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1499421#L824-3 assume !(0 == ~E_4~0); 1499419#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1499417#L834-3 assume !(0 == ~E_6~0); 1499415#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1499413#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1499411#L376-27 assume !(1 == ~m_pc~0); 1499409#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1499406#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1499404#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1499402#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1499400#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1499398#L395-27 assume !(1 == ~t1_pc~0); 1499396#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1499394#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1499393#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1499392#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1499391#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1499389#L414-27 assume !(1 == ~t2_pc~0); 1499386#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1499383#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1499381#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1499379#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1499377#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1499375#L433-27 assume !(1 == ~t3_pc~0); 1499373#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1499371#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1499369#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1499367#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1499365#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1499363#L452-27 assume !(1 == ~t4_pc~0); 1499360#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1499357#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1499355#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1499353#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1499332#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1498726#L471-27 assume !(1 == ~t5_pc~0); 1498717#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1498715#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1498713#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1498711#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1498709#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1498707#L490-27 assume !(1 == ~t6_pc~0); 1498690#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1498681#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1498671#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1498665#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1498662#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1497982#L509-27 assume 1 == ~t7_pc~0; 1497980#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1497981#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1497988#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1497971#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1497969#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1497967#L857-3 assume !(1 == ~M_E~0); 1497963#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1497961#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1497958#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1497954#L872-3 assume !(1 == ~T4_E~0); 1497952#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1497950#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1497948#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1497945#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1497943#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1497942#L902-3 assume !(1 == ~E_2~0); 1497941#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1497940#L912-3 assume !(1 == ~E_4~0); 1497938#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1497936#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1497934#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1497932#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1497839#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1497824#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1497809#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1497797#L1197 assume !(0 == start_simulation_~tmp~3#1); 1497795#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1497749#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1497743#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1497742#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1497739#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1497737#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1497722#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1497715#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1461589#L1178-2 [2022-11-16 12:49:37,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:37,238 INFO L85 PathProgramCache]: Analyzing trace with hash -243852155, now seen corresponding path program 1 times [2022-11-16 12:49:37,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:37,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116794048] [2022-11-16 12:49:37,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:37,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:37,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:37,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:37,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:37,293 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116794048] [2022-11-16 12:49:37,293 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116794048] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:37,293 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:37,293 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:37,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329706803] [2022-11-16 12:49:37,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:37,294 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:37,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:37,294 INFO L85 PathProgramCache]: Analyzing trace with hash 1183963239, now seen corresponding path program 1 times [2022-11-16 12:49:37,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:37,294 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145571654] [2022-11-16 12:49:37,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:37,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:37,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:37,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:37,329 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:37,329 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145571654] [2022-11-16 12:49:37,330 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145571654] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:37,330 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:37,330 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:37,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1189906503] [2022-11-16 12:49:37,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:37,331 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:37,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:37,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:49:37,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:49:37,331 INFO L87 Difference]: Start difference. First operand 62099 states and 86740 transitions. cyclomatic complexity: 24657 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:37,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:37,961 INFO L93 Difference]: Finished difference Result 78788 states and 109924 transitions. [2022-11-16 12:49:37,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78788 states and 109924 transitions. [2022-11-16 12:49:38,215 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78301 [2022-11-16 12:49:38,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78788 states to 78788 states and 109924 transitions. [2022-11-16 12:49:38,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78788 [2022-11-16 12:49:38,405 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78788 [2022-11-16 12:49:38,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78788 states and 109924 transitions. [2022-11-16 12:49:38,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:38,451 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78788 states and 109924 transitions. [2022-11-16 12:49:38,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78788 states and 109924 transitions. [2022-11-16 12:49:38,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78788 to 54166. [2022-11-16 12:49:38,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.3984602887420152) internal successors, (75749), 54165 states have internal predecessors, (75749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:38,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 75749 transitions. [2022-11-16 12:49:38,991 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 75749 transitions. [2022-11-16 12:49:38,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:49:38,991 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 75749 transitions. [2022-11-16 12:49:38,992 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-16 12:49:38,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 75749 transitions. [2022-11-16 12:49:39,491 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-11-16 12:49:39,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:39,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:39,493 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:39,493 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:39,494 INFO L748 eck$LassoCheckResult]: Stem: 1602466#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 1602467#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1602333#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1602277#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1602278#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1602612#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1602257#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1602099#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1602100#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1602082#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1602083#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1602611#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1602401#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1602402#L769 assume !(0 == ~M_E~0); 1602424#L769-2 assume !(0 == ~T1_E~0); 1602425#L774-1 assume !(0 == ~T2_E~0); 1602458#L779-1 assume !(0 == ~T3_E~0); 1602594#L784-1 assume !(0 == ~T4_E~0); 1602395#L789-1 assume !(0 == ~T5_E~0); 1602396#L794-1 assume !(0 == ~T6_E~0); 1602519#L799-1 assume !(0 == ~T7_E~0); 1602403#L804-1 assume !(0 == ~E_M~0); 1602404#L809-1 assume !(0 == ~E_1~0); 1602448#L814-1 assume !(0 == ~E_2~0); 1601825#L819-1 assume !(0 == ~E_3~0); 1601826#L824-1 assume !(0 == ~E_4~0); 1602167#L829-1 assume !(0 == ~E_5~0); 1602677#L834-1 assume !(0 == ~E_6~0); 1601949#L839-1 assume !(0 == ~E_7~0); 1601950#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1602342#L376 assume !(1 == ~m_pc~0); 1602338#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1602339#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1602647#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1601903#L955 assume !(0 != activate_threads_~tmp~1#1); 1601904#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1602250#L395 assume !(1 == ~t1_pc~0); 1602426#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1602578#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1601829#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1601830#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1602348#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1602349#L414 assume !(1 == ~t2_pc~0); 1601952#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1601953#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1602153#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1602154#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1602618#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1602253#L433 assume !(1 == ~t3_pc~0); 1602072#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1602073#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1602227#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1602228#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1601921#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1601922#L452 assume !(1 == ~t4_pc~0); 1602078#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1602079#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1602382#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1602457#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1602110#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1602111#L471 assume !(1 == ~t5_pc~0); 1602502#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1602093#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1602094#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1602449#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1602665#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1602666#L490 assume !(1 == ~t6_pc~0); 1602345#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1602346#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1602390#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1602393#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1602265#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1602230#L509 assume !(1 == ~t7_pc~0); 1602231#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1602055#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1602056#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1602115#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1602116#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1602627#L857 assume !(1 == ~M_E~0); 1601908#L857-2 assume !(1 == ~T1_E~0); 1601909#L862-1 assume !(1 == ~T2_E~0); 1602175#L867-1 assume !(1 == ~T3_E~0); 1602180#L872-1 assume !(1 == ~T4_E~0); 1602254#L877-1 assume !(1 == ~T5_E~0); 1602478#L882-1 assume !(1 == ~T6_E~0); 1602637#L887-1 assume !(1 == ~T7_E~0); 1602538#L892-1 assume !(1 == ~E_M~0); 1602539#L897-1 assume !(1 == ~E_1~0); 1602193#L902-1 assume !(1 == ~E_2~0); 1602194#L907-1 assume !(1 == ~E_3~0); 1602498#L912-1 assume !(1 == ~E_4~0); 1602486#L917-1 assume !(1 == ~E_5~0); 1602487#L922-1 assume !(1 == ~E_6~0); 1602681#L927-1 assume !(1 == ~E_7~0); 1602473#L932-1 assume { :end_inline_reset_delta_events } true; 1602474#L1178-2 [2022-11-16 12:49:39,494 INFO L750 eck$LassoCheckResult]: Loop: 1602474#L1178-2 assume !false; 1630159#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1630157#L744 assume !false; 1630155#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1630153#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1630144#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1630142#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1630139#L641 assume !(0 != eval_~tmp~0#1); 1630137#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1630135#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1630133#L769-3 assume !(0 == ~M_E~0); 1630131#L769-5 assume !(0 == ~T1_E~0); 1630129#L774-3 assume !(0 == ~T2_E~0); 1630127#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1630125#L784-3 assume !(0 == ~T4_E~0); 1630123#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1630121#L794-3 assume !(0 == ~T6_E~0); 1630119#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1630117#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1630115#L809-3 assume !(0 == ~E_1~0); 1630113#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1630111#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1630109#L824-3 assume !(0 == ~E_4~0); 1630107#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1630105#L834-3 assume !(0 == ~E_6~0); 1630103#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1630101#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1630099#L376-27 assume !(1 == ~m_pc~0); 1630097#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1630095#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1630093#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1630090#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1630088#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1630086#L395-27 assume !(1 == ~t1_pc~0); 1630084#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1630082#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1630078#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1630076#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1630074#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1630072#L414-27 assume !(1 == ~t2_pc~0); 1630063#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1630061#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1630059#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1630014#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1630003#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1629993#L433-27 assume !(1 == ~t3_pc~0); 1629984#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1629979#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1629974#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1629970#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1629967#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1629669#L452-27 assume !(1 == ~t4_pc~0); 1629666#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1629664#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1629662#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1629660#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1629658#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1629656#L471-27 assume !(1 == ~t5_pc~0); 1629654#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1629652#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1629648#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1629646#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1629644#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1629632#L490-27 assume !(1 == ~t6_pc~0); 1629626#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1629625#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1629624#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1629622#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1629621#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1629620#L509-27 assume 1 == ~t7_pc~0; 1629618#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1629617#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1629616#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1629613#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1629611#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1629609#L857-3 assume !(1 == ~M_E~0); 1626324#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1629606#L862-3 assume !(1 == ~T2_E~0); 1629604#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1629602#L872-3 assume !(1 == ~T4_E~0); 1629600#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1629598#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1627202#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1627198#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1627197#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1627196#L902-3 assume !(1 == ~E_2~0); 1627195#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1627194#L912-3 assume !(1 == ~E_4~0); 1627193#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1627192#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1627191#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1627190#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1626496#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1626491#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1626482#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1626450#L1197 assume !(0 == start_simulation_~tmp~3#1); 1626451#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1630299#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1630293#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1630291#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1630289#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1630287#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1630285#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1630283#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1602474#L1178-2 [2022-11-16 12:49:39,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:39,495 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2022-11-16 12:49:39,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:39,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758441565] [2022-11-16 12:49:39,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:39,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:39,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:49:39,507 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:49:39,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:49:39,540 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:49:39,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:39,541 INFO L85 PathProgramCache]: Analyzing trace with hash -1216276313, now seen corresponding path program 1 times [2022-11-16 12:49:39,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:39,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973559612] [2022-11-16 12:49:39,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:39,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:39,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:39,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:39,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:39,576 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973559612] [2022-11-16 12:49:39,576 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973559612] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:39,576 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:39,577 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:49:39,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1350554922] [2022-11-16 12:49:39,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:39,577 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:39,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:39,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:39,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:39,578 INFO L87 Difference]: Start difference. First operand 54166 states and 75749 transitions. cyclomatic complexity: 21599 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:39,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:39,927 INFO L93 Difference]: Finished difference Result 101010 states and 139464 transitions. [2022-11-16 12:49:39,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101010 states and 139464 transitions. [2022-11-16 12:49:40,293 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 100342 [2022-11-16 12:49:40,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101010 states to 101010 states and 139464 transitions. [2022-11-16 12:49:40,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101010 [2022-11-16 12:49:40,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101010 [2022-11-16 12:49:40,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101010 states and 139464 transitions. [2022-11-16 12:49:40,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:40,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101010 states and 139464 transitions. [2022-11-16 12:49:40,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101010 states and 139464 transitions. [2022-11-16 12:49:41,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101010 to 100974. [2022-11-16 12:49:42,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100974 states, 100974 states have (on average 1.3808307088953593) internal successors, (139428), 100973 states have internal predecessors, (139428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:42,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100974 states to 100974 states and 139428 transitions. [2022-11-16 12:49:42,232 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100974 states and 139428 transitions. [2022-11-16 12:49:42,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:42,233 INFO L428 stractBuchiCegarLoop]: Abstraction has 100974 states and 139428 transitions. [2022-11-16 12:49:42,233 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-16 12:49:42,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100974 states and 139428 transitions. [2022-11-16 12:49:42,562 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 100306 [2022-11-16 12:49:42,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:42,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:42,564 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:42,564 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:42,565 INFO L748 eck$LassoCheckResult]: Stem: 1757669#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 1757670#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1757527#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1757470#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1757471#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1757831#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1757450#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1757276#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1757277#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1757258#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1757259#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1757830#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1757599#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1757600#L769 assume !(0 == ~M_E~0); 1757623#L769-2 assume !(0 == ~T1_E~0); 1757624#L774-1 assume !(0 == ~T2_E~0); 1757659#L779-1 assume !(0 == ~T3_E~0); 1757808#L784-1 assume !(0 == ~T4_E~0); 1757594#L789-1 assume !(0 == ~T5_E~0); 1757595#L794-1 assume !(0 == ~T6_E~0); 1757729#L799-1 assume !(0 == ~T7_E~0); 1757602#L804-1 assume !(0 == ~E_M~0); 1757603#L809-1 assume !(0 == ~E_1~0); 1757647#L814-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1757840#L819-1 assume !(0 == ~E_3~0); 1757345#L824-1 assume !(0 == ~E_4~0); 1757346#L829-1 assume !(0 == ~E_5~0); 1758031#L834-1 assume !(0 == ~E_6~0); 1757129#L839-1 assume !(0 == ~E_7~0); 1757130#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1757736#L376 assume !(1 == ~m_pc~0); 1757533#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1757534#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1757889#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1757890#L955 assume !(0 != activate_threads_~tmp~1#1); 1758051#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1757626#L395 assume !(1 == ~t1_pc~0); 1757627#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1757809#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1757810#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1757855#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1757856#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1758048#L414 assume !(1 == ~t2_pc~0); 1757839#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1757132#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1758036#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1757836#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1757837#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1758067#L433 assume !(1 == ~t3_pc~0); 1757245#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1757246#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1758066#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1758065#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1758064#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1758012#L452 assume !(1 == ~t4_pc~0); 1757995#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1757578#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1757579#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1757658#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1757287#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1757288#L471 assume !(1 == ~t5_pc~0); 1757712#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1757269#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1757270#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1758060#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1757909#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1757910#L490 assume !(1 == ~t6_pc~0); 1757540#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1757541#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1758058#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1757590#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1757456#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1757421#L509 assume !(1 == ~t7_pc~0); 1757422#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1757225#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1757226#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1758044#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1757947#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1757948#L857 assume !(1 == ~M_E~0); 1757089#L857-2 assume !(1 == ~T1_E~0); 1757090#L862-1 assume !(1 == ~T2_E~0); 1757362#L867-1 assume !(1 == ~T3_E~0); 1757363#L872-1 assume !(1 == ~T4_E~0); 1757447#L877-1 assume !(1 == ~T5_E~0); 1757682#L882-1 assume !(1 == ~T6_E~0); 1757987#L887-1 assume !(1 == ~T7_E~0); 1757752#L892-1 assume !(1 == ~E_M~0); 1757753#L897-1 assume !(1 == ~E_1~0); 1757374#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1757375#L907-1 assume !(1 == ~E_3~0); 1757701#L912-1 assume !(1 == ~E_4~0); 1757690#L917-1 assume !(1 == ~E_5~0); 1757691#L922-1 assume !(1 == ~E_6~0); 1757930#L927-1 assume !(1 == ~E_7~0); 1757677#L932-1 assume { :end_inline_reset_delta_events } true; 1757678#L1178-2 [2022-11-16 12:49:42,565 INFO L750 eck$LassoCheckResult]: Loop: 1757678#L1178-2 assume !false; 1831424#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1831422#L744 assume !false; 1831419#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1830171#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1830157#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1830054#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1830050#L641 assume !(0 != eval_~tmp~0#1); 1830051#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1831869#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1831867#L769-3 assume !(0 == ~M_E~0); 1831865#L769-5 assume !(0 == ~T1_E~0); 1831863#L774-3 assume !(0 == ~T2_E~0); 1831861#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1831859#L784-3 assume !(0 == ~T4_E~0); 1831857#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1831855#L794-3 assume !(0 == ~T6_E~0); 1831853#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1831851#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1831849#L809-3 assume !(0 == ~E_1~0); 1831847#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1831846#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1831844#L824-3 assume !(0 == ~E_4~0); 1831842#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1831840#L834-3 assume !(0 == ~E_6~0); 1831838#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1831836#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1831834#L376-27 assume !(1 == ~m_pc~0); 1831832#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1831830#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1831828#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1831826#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1831824#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1831822#L395-27 assume !(1 == ~t1_pc~0); 1831820#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1831818#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1831816#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1831814#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1831812#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1831810#L414-27 assume 1 == ~t2_pc~0; 1831806#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1831803#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1831801#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1831799#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1831797#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1831795#L433-27 assume !(1 == ~t3_pc~0); 1831793#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1831791#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1831789#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1831787#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1831785#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1831782#L452-27 assume !(1 == ~t4_pc~0); 1831779#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1831777#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1831775#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1831773#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1831771#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1831769#L471-27 assume !(1 == ~t5_pc~0); 1831767#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1831765#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1831763#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1831761#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1831759#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1831757#L490-27 assume !(1 == ~t6_pc~0); 1831755#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1831753#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1831751#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1831749#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1831747#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1831743#L509-27 assume !(1 == ~t7_pc~0); 1831739#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1831737#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1831735#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1831732#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1831729#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1831725#L857-3 assume !(1 == ~M_E~0); 1831721#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1831719#L862-3 assume !(1 == ~T2_E~0); 1831717#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1831715#L872-3 assume !(1 == ~T4_E~0); 1831713#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1831711#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1831709#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1831707#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1831705#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1831704#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1831702#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1831701#L912-3 assume !(1 == ~E_4~0); 1831692#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1831690#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1831688#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1831685#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1831562#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1831556#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1831554#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1831550#L1197 assume !(0 == start_simulation_~tmp~3#1); 1831549#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1831542#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1831536#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1831534#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1831532#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1831530#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1831528#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1831526#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1757678#L1178-2 [2022-11-16 12:49:42,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:42,566 INFO L85 PathProgramCache]: Analyzing trace with hash -223159163, now seen corresponding path program 1 times [2022-11-16 12:49:42,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:42,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448131867] [2022-11-16 12:49:42,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:42,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:42,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:42,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:42,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:42,621 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448131867] [2022-11-16 12:49:42,621 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [448131867] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:42,622 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:42,622 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:49:42,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498284543] [2022-11-16 12:49:42,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:42,623 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:49:42,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:42,623 INFO L85 PathProgramCache]: Analyzing trace with hash 1848073575, now seen corresponding path program 1 times [2022-11-16 12:49:42,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:42,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138048725] [2022-11-16 12:49:42,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:42,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:42,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:42,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:42,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:42,692 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138048725] [2022-11-16 12:49:42,692 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1138048725] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:42,693 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:42,693 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:49:42,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36840243] [2022-11-16 12:49:42,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:42,694 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:42,694 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:42,694 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:49:42,694 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:49:42,694 INFO L87 Difference]: Start difference. First operand 100974 states and 139428 transitions. cyclomatic complexity: 38470 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:42,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:42,893 INFO L93 Difference]: Finished difference Result 54166 states and 74742 transitions. [2022-11-16 12:49:42,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54166 states and 74742 transitions. [2022-11-16 12:49:43,849 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-11-16 12:49:44,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54166 states to 54166 states and 74742 transitions. [2022-11-16 12:49:44,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54166 [2022-11-16 12:49:44,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54166 [2022-11-16 12:49:44,045 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54166 states and 74742 transitions. [2022-11-16 12:49:44,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:44,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54166 states and 74742 transitions. [2022-11-16 12:49:44,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54166 states and 74742 transitions. [2022-11-16 12:49:44,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54166 to 54166. [2022-11-16 12:49:44,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54166 states, 54166 states have (on average 1.3798692906989625) internal successors, (74742), 54165 states have internal predecessors, (74742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:44,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54166 states to 54166 states and 74742 transitions. [2022-11-16 12:49:44,509 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54166 states and 74742 transitions. [2022-11-16 12:49:44,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:49:44,510 INFO L428 stractBuchiCegarLoop]: Abstraction has 54166 states and 74742 transitions. [2022-11-16 12:49:44,510 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-16 12:49:44,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54166 states and 74742 transitions. [2022-11-16 12:49:44,648 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 53817 [2022-11-16 12:49:44,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:44,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:44,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:44,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:44,650 INFO L748 eck$LassoCheckResult]: Stem: 1912794#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 1912795#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1912662#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1912605#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1912606#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1912937#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1912587#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1912427#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1912428#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1912409#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1912410#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1912936#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1912728#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1912729#L769 assume !(0 == ~M_E~0); 1912751#L769-2 assume !(0 == ~T1_E~0); 1912752#L774-1 assume !(0 == ~T2_E~0); 1912784#L779-1 assume !(0 == ~T3_E~0); 1912923#L784-1 assume !(0 == ~T4_E~0); 1912724#L789-1 assume !(0 == ~T5_E~0); 1912725#L794-1 assume !(0 == ~T6_E~0); 1912851#L799-1 assume !(0 == ~T7_E~0); 1912731#L804-1 assume !(0 == ~E_M~0); 1912732#L809-1 assume !(0 == ~E_1~0); 1912772#L814-1 assume !(0 == ~E_2~0); 1912152#L819-1 assume !(0 == ~E_3~0); 1912153#L824-1 assume !(0 == ~E_4~0); 1912494#L829-1 assume !(0 == ~E_5~0); 1913013#L834-1 assume !(0 == ~E_6~0); 1912278#L839-1 assume !(0 == ~E_7~0); 1912279#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1912672#L376 assume !(1 == ~m_pc~0); 1912668#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1912669#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1912985#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1912231#L955 assume !(0 != activate_threads_~tmp~1#1); 1912232#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1912579#L395 assume !(1 == ~t1_pc~0); 1912754#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1912906#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1912158#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1912159#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1912677#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1912678#L414 assume !(1 == ~t2_pc~0); 1912281#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1912946#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1912481#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1912482#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1912944#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1912583#L433 assume !(1 == ~t3_pc~0); 1912396#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1912397#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1912553#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1912554#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1912251#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1912252#L452 assume !(1 == ~t4_pc~0); 1912405#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1912406#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1912709#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1912783#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1912438#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1912439#L471 assume !(1 == ~t5_pc~0); 1912833#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1912421#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1912422#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1912773#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1913002#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1913003#L490 assume !(1 == ~t6_pc~0); 1912675#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1912676#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1912716#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1912720#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1912592#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1912559#L509 assume !(1 == ~t7_pc~0); 1912560#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1912376#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1912377#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1912443#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1912444#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1912954#L857 assume !(1 == ~M_E~0); 1912238#L857-2 assume !(1 == ~T1_E~0); 1912239#L862-1 assume !(1 == ~T2_E~0); 1912503#L867-1 assume !(1 == ~T3_E~0); 1912508#L872-1 assume !(1 == ~T4_E~0); 1912584#L877-1 assume !(1 == ~T5_E~0); 1912807#L882-1 assume !(1 == ~T6_E~0); 1912969#L887-1 assume !(1 == ~T7_E~0); 1912873#L892-1 assume !(1 == ~E_M~0); 1912874#L897-1 assume !(1 == ~E_1~0); 1912518#L902-1 assume !(1 == ~E_2~0); 1912519#L907-1 assume !(1 == ~E_3~0); 1912824#L912-1 assume !(1 == ~E_4~0); 1912815#L917-1 assume !(1 == ~E_5~0); 1912816#L922-1 assume !(1 == ~E_6~0); 1913017#L927-1 assume !(1 == ~E_7~0); 1912802#L932-1 assume { :end_inline_reset_delta_events } true; 1912803#L1178-2 [2022-11-16 12:49:44,650 INFO L750 eck$LassoCheckResult]: Loop: 1912803#L1178-2 assume !false; 1942330#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1942326#L744 assume !false; 1942322#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1942278#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1942269#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1942267#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1942264#L641 assume !(0 != eval_~tmp~0#1); 1942265#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1943265#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1943264#L769-3 assume !(0 == ~M_E~0); 1943260#L769-5 assume !(0 == ~T1_E~0); 1943258#L774-3 assume !(0 == ~T2_E~0); 1943256#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1943238#L784-3 assume !(0 == ~T4_E~0); 1943229#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1943221#L794-3 assume !(0 == ~T6_E~0); 1943209#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1943203#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1943202#L809-3 assume !(0 == ~E_1~0); 1943201#L814-3 assume !(0 == ~E_2~0); 1943199#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1943198#L824-3 assume !(0 == ~E_4~0); 1943172#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1943156#L834-3 assume !(0 == ~E_6~0); 1943126#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1943122#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1943117#L376-27 assume !(1 == ~m_pc~0); 1943112#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1943106#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1943101#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1943096#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1943091#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1943086#L395-27 assume !(1 == ~t1_pc~0); 1943081#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1943076#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1943072#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1943067#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1943062#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1943057#L414-27 assume !(1 == ~t2_pc~0); 1943051#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1943049#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1943048#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1943004#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1942999#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1942979#L433-27 assume !(1 == ~t3_pc~0); 1942974#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1942971#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1942965#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1942959#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1942953#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1942948#L452-27 assume !(1 == ~t4_pc~0); 1942941#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1942935#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1942929#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1942922#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1942916#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1942910#L471-27 assume !(1 == ~t5_pc~0); 1942904#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1942898#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1942890#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1942884#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1942878#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1942872#L490-27 assume !(1 == ~t6_pc~0); 1942865#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1942859#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1942853#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1942847#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1942841#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1942786#L509-27 assume !(1 == ~t7_pc~0); 1942782#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1942780#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1942778#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1942776#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1942766#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1942758#L857-3 assume !(1 == ~M_E~0); 1942746#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1942740#L862-3 assume !(1 == ~T2_E~0); 1942734#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1942727#L872-3 assume !(1 == ~T4_E~0); 1942720#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1942713#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1942706#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1942699#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1942691#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1942683#L902-3 assume !(1 == ~E_2~0); 1942676#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1942670#L912-3 assume !(1 == ~E_4~0); 1942664#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1942659#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1942653#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1942648#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1942627#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1942614#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1942608#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1942601#L1197 assume !(0 == start_simulation_~tmp~3#1); 1942597#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1942474#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1942468#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1942466#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1942463#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1942461#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1942359#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1942349#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1912803#L1178-2 [2022-11-16 12:49:44,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:44,651 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2022-11-16 12:49:44,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:44,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2048109220] [2022-11-16 12:49:44,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:44,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:44,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:49:44,663 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:49:44,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:49:44,695 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:49:44,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:44,696 INFO L85 PathProgramCache]: Analyzing trace with hash -1342358296, now seen corresponding path program 1 times [2022-11-16 12:49:44,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:44,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875027198] [2022-11-16 12:49:44,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:44,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:44,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:44,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:44,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:44,748 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875027198] [2022-11-16 12:49:44,748 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1875027198] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:44,749 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:44,749 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:49:44,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [990848028] [2022-11-16 12:49:44,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:44,749 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:44,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:44,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:49:44,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:49:44,750 INFO L87 Difference]: Start difference. First operand 54166 states and 74742 transitions. cyclomatic complexity: 20592 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:45,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:45,112 INFO L93 Difference]: Finished difference Result 97237 states and 132459 transitions. [2022-11-16 12:49:45,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97237 states and 132459 transitions. [2022-11-16 12:49:46,089 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 96640 [2022-11-16 12:49:46,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97237 states to 97237 states and 132459 transitions. [2022-11-16 12:49:46,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97237 [2022-11-16 12:49:46,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97237 [2022-11-16 12:49:46,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97237 states and 132459 transitions. [2022-11-16 12:49:46,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:46,297 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97237 states and 132459 transitions. [2022-11-16 12:49:46,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97237 states and 132459 transitions. [2022-11-16 12:49:46,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97237 to 54490. [2022-11-16 12:49:46,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54490 states, 54490 states have (on average 1.377610570746926) internal successors, (75066), 54489 states have internal predecessors, (75066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:46,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54490 states to 54490 states and 75066 transitions. [2022-11-16 12:49:46,882 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54490 states and 75066 transitions. [2022-11-16 12:49:46,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 12:49:46,883 INFO L428 stractBuchiCegarLoop]: Abstraction has 54490 states and 75066 transitions. [2022-11-16 12:49:46,883 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-11-16 12:49:46,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54490 states and 75066 transitions. [2022-11-16 12:49:47,021 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 54141 [2022-11-16 12:49:47,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:49:47,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:49:47,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:47,023 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:49:47,023 INFO L748 eck$LassoCheckResult]: Stem: 2064239#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2; 2064240#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2064093#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2064037#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2064038#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2064405#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2064019#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2063849#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2063850#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2063831#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2063832#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2064404#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2064166#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2064167#L769 assume !(0 == ~M_E~0); 2064192#L769-2 assume !(0 == ~T1_E~0); 2064193#L774-1 assume !(0 == ~T2_E~0); 2064230#L779-1 assume !(0 == ~T3_E~0); 2064384#L784-1 assume !(0 == ~T4_E~0); 2064161#L789-1 assume !(0 == ~T5_E~0); 2064162#L794-1 assume !(0 == ~T6_E~0); 2064296#L799-1 assume !(0 == ~T7_E~0); 2064169#L804-1 assume !(0 == ~E_M~0); 2064170#L809-1 assume !(0 == ~E_1~0); 2064218#L814-1 assume !(0 == ~E_2~0); 2063571#L819-1 assume !(0 == ~E_3~0); 2063572#L824-1 assume !(0 == ~E_4~0); 2063919#L829-1 assume !(0 == ~E_5~0); 2064489#L834-1 assume !(0 == ~E_6~0); 2063699#L839-1 assume !(0 == ~E_7~0); 2063700#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2064103#L376 assume !(1 == ~m_pc~0); 2064099#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2064100#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2064454#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2063650#L955 assume !(0 != activate_threads_~tmp~1#1); 2063651#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2064012#L395 assume !(1 == ~t1_pc~0); 2064195#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2064367#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2063577#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2063578#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2064109#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2064110#L414 assume !(1 == ~t2_pc~0); 2063702#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2064412#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2063906#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2063907#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2064410#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2064015#L433 assume !(1 == ~t3_pc~0); 2063818#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2063819#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2063982#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2063983#L979 assume !(0 != activate_threads_~tmp___2~0#1); 2063671#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2063672#L452 assume !(1 == ~t4_pc~0); 2063827#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2063828#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2064146#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2064229#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2063860#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2063861#L471 assume !(1 == ~t5_pc~0); 2064278#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2063842#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2063843#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2064219#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2064473#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2064474#L490 assume !(1 == ~t6_pc~0); 2064107#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2064108#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2064153#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2064157#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2064024#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2063992#L509 assume !(1 == ~t7_pc~0); 2063993#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2063797#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2063798#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2063865#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 2063866#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2064421#L857 assume !(1 == ~M_E~0); 2063657#L857-2 assume !(1 == ~T1_E~0); 2063658#L862-1 assume !(1 == ~T2_E~0); 2063928#L867-1 assume !(1 == ~T3_E~0); 2063934#L872-1 assume !(1 == ~T4_E~0); 2064016#L877-1 assume !(1 == ~T5_E~0); 2064251#L882-1 assume !(1 == ~T6_E~0); 2064438#L887-1 assume !(1 == ~T7_E~0); 2064322#L892-1 assume !(1 == ~E_M~0); 2064323#L897-1 assume !(1 == ~E_1~0); 2063945#L902-1 assume !(1 == ~E_2~0); 2063946#L907-1 assume !(1 == ~E_3~0); 2064268#L912-1 assume !(1 == ~E_4~0); 2064259#L917-1 assume !(1 == ~E_5~0); 2064260#L922-1 assume !(1 == ~E_6~0); 2064493#L927-1 assume !(1 == ~E_7~0); 2064247#L932-1 assume { :end_inline_reset_delta_events } true; 2063609#L1178-2 [2022-11-16 12:49:47,023 INFO L750 eck$LassoCheckResult]: Loop: 2063609#L1178-2 assume !false; 2064234#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2063623#L744 assume !false; 2063981#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2064063#L584 assume !(0 == ~m_st~0); 2117520#L588 assume !(0 == ~t1_st~0); 2117521#L592 assume !(0 == ~t2_st~0); 2117523#L596 assume !(0 == ~t3_st~0); 2117518#L600 assume !(0 == ~t4_st~0); 2117519#L604 assume !(0 == ~t5_st~0); 2117522#L608 assume !(0 == ~t6_st~0); 2117516#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 2117515#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2089445#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2089446#L641 assume !(0 != eval_~tmp~0#1); 2117634#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2117633#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2117632#L769-3 assume !(0 == ~M_E~0); 2117631#L769-5 assume !(0 == ~T1_E~0); 2117630#L774-3 assume !(0 == ~T2_E~0); 2117629#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2117628#L784-3 assume !(0 == ~T4_E~0); 2117627#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2117626#L794-3 assume !(0 == ~T6_E~0); 2117625#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2117624#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2117623#L809-3 assume !(0 == ~E_1~0); 2117509#L814-3 assume !(0 == ~E_2~0); 2117510#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2117501#L824-3 assume !(0 == ~E_4~0); 2117502#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2063929#L834-3 assume !(0 == ~E_6~0); 2063930#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2064295#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2117621#L376-27 assume !(1 == ~m_pc~0); 2064577#L376-29 is_master_triggered_~__retres1~0#1 := 0; 2064578#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2064330#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2064331#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2117472#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2117473#L395-27 assume !(1 == ~t1_pc~0); 2117468#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2117469#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2064364#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2064190#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2064191#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2064467#L414-27 assume !(1 == ~t2_pc~0); 2064469#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2064257#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2064258#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2064088#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2063634#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2063635#L433-27 assume !(1 == ~t3_pc~0); 2063725#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2064026#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2064027#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2063802#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 2063803#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2064541#L452-27 assume !(1 == ~t4_pc~0); 2064213#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2064214#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2064387#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2064460#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2064461#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2064472#L471-27 assume !(1 == ~t5_pc~0); 2063941#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2063942#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2064417#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2064280#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2064196#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2064101#L490-27 assume !(1 == ~t6_pc~0); 2064102#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2063814#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2063815#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2064266#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2064267#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2063595#L509-27 assume 1 == ~t7_pc~0; 2063597#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2117640#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2117641#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2117636#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2064125#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2064141#L857-3 assume !(1 == ~M_E~0); 2064142#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2117887#L862-3 assume !(1 == ~T2_E~0); 2117886#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2117885#L872-3 assume !(1 == ~T4_E~0); 2117884#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2117883#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2117882#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2117881#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2117880#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2117879#L902-3 assume !(1 == ~E_2~0); 2117878#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2117877#L912-3 assume !(1 == ~E_4~0); 2117876#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2117875#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2117874#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2117873#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2063679#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2063585#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2064298#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2064004#L1197 assume !(0 == start_simulation_~tmp~3#1); 2064005#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2063731#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2063697#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2063628#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 2063629#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2064373#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2064374#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2063608#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 2063609#L1178-2 [2022-11-16 12:49:47,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:47,024 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2022-11-16 12:49:47,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:47,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283451660] [2022-11-16 12:49:47,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:47,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:47,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:49:47,036 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:49:47,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:49:47,066 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:49:47,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:49:47,067 INFO L85 PathProgramCache]: Analyzing trace with hash -187526411, now seen corresponding path program 1 times [2022-11-16 12:49:47,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:49:47,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828074271] [2022-11-16 12:49:47,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:49:47,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:49:47,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:49:47,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:49:47,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:49:47,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828074271] [2022-11-16 12:49:47,168 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828074271] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:49:47,168 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:49:47,168 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:49:47,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711923921] [2022-11-16 12:49:47,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:49:47,169 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:49:47,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:49:47,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:49:47,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:49:47,170 INFO L87 Difference]: Start difference. First operand 54490 states and 75066 transitions. cyclomatic complexity: 20592 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:49:47,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:49:47,956 INFO L93 Difference]: Finished difference Result 89930 states and 123281 transitions. [2022-11-16 12:49:47,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89930 states and 123281 transitions. [2022-11-16 12:49:48,240 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 89517 [2022-11-16 12:49:48,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89930 states to 89930 states and 123281 transitions. [2022-11-16 12:49:48,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89930 [2022-11-16 12:49:48,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89930 [2022-11-16 12:49:48,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89930 states and 123281 transitions. [2022-11-16 12:49:48,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:49:48,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 89930 states and 123281 transitions. [2022-11-16 12:49:48,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89930 states and 123281 transitions.