./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:30:43,463 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:30:43,465 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:30:43,493 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:30:43,494 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:30:43,498 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:30:43,500 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:30:43,505 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:30:43,507 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:30:43,513 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:30:43,515 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:30:43,517 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:30:43,517 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:30:43,520 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:30:43,521 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:30:43,523 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:30:43,525 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:30:43,526 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:30:43,528 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:30:43,531 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:30:43,537 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:30:43,538 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:30:43,541 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:30:43,542 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:30:43,552 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:30:43,552 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:30:43,552 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:30:43,553 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:30:43,554 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:30:43,555 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:30:43,555 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:30:43,556 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:30:43,556 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:30:43,557 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:30:43,558 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:30:43,558 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:30:43,559 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:30:43,559 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:30:43,560 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:30:43,560 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:30:43,561 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:30:43,566 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 11:30:43,603 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:30:43,603 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:30:43,603 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:30:43,603 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:30:43,608 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:30:43,609 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:30:43,609 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:30:43,609 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 11:30:43,609 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 11:30:43,609 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 11:30:43,610 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 11:30:43,610 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 11:30:43,611 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 11:30:43,611 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:30:43,611 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 11:30:43,611 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 11:30:43,611 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:30:43,612 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 11:30:43,612 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:30:43,612 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 11:30:43,612 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 11:30:43,612 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 11:30:43,612 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 11:30:43,614 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:30:43,614 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 11:30:43,615 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:30:43,615 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 11:30:43,615 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:30:43,615 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:30:43,615 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:30:43,616 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:30:43,617 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 11:30:43,617 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 [2022-11-16 11:30:43,934 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:30:43,956 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:30:43,959 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:30:43,960 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:30:43,961 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:30:43,963 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2022-11-16 11:30:44,046 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/data/df226c725/beadf543c4bc4e78b65784adbc31b0f0/FLAGf2b080737 [2022-11-16 11:30:44,669 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:30:44,669 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2022-11-16 11:30:44,697 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/data/df226c725/beadf543c4bc4e78b65784adbc31b0f0/FLAGf2b080737 [2022-11-16 11:30:44,992 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/data/df226c725/beadf543c4bc4e78b65784adbc31b0f0 [2022-11-16 11:30:44,997 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:30:44,999 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:30:45,004 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:30:45,004 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:30:45,008 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:30:45,009 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:30:44" (1/1) ... [2022-11-16 11:30:45,010 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@689e4d7c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45, skipping insertion in model container [2022-11-16 11:30:45,010 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:30:44" (1/1) ... [2022-11-16 11:30:45,017 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:30:45,055 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:30:45,256 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[671,684] [2022-11-16 11:30:45,389 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:30:45,400 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:30:45,411 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[671,684] [2022-11-16 11:30:45,459 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:30:45,476 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:30:45,476 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45 WrapperNode [2022-11-16 11:30:45,477 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:30:45,478 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:30:45,478 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:30:45,478 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:30:45,486 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,497 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,592 INFO L138 Inliner]: procedures = 44, calls = 55, calls flagged for inlining = 50, calls inlined = 157, statements flattened = 2358 [2022-11-16 11:30:45,593 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:30:45,594 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:30:45,594 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:30:45,594 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:30:45,603 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,603 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,610 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,610 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,631 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,652 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,656 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,661 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,670 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:30:45,671 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:30:45,671 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:30:45,671 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:30:45,672 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (1/1) ... [2022-11-16 11:30:45,687 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:30:45,710 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:30:45,736 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:30:45,760 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc702dcc-3ad5-400a-a191-1d387b90e565/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 11:30:45,788 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 11:30:45,788 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 11:30:45,788 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:30:45,789 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:30:45,940 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:30:45,942 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:30:47,581 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:30:47,602 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:30:47,604 INFO L300 CfgBuilder]: Removed 11 assume(true) statements. [2022-11-16 11:30:47,608 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:30:47 BoogieIcfgContainer [2022-11-16 11:30:47,609 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:30:47,610 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 11:30:47,611 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 11:30:47,615 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 11:30:47,616 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:30:47,616 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 11:30:44" (1/3) ... [2022-11-16 11:30:47,617 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@42eeb353 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:30:47, skipping insertion in model container [2022-11-16 11:30:47,618 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:30:47,618 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:30:45" (2/3) ... [2022-11-16 11:30:47,618 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@42eeb353 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:30:47, skipping insertion in model container [2022-11-16 11:30:47,618 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:30:47,618 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:30:47" (3/3) ... [2022-11-16 11:30:47,620 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-1.c [2022-11-16 11:30:47,719 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 11:30:47,719 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 11:30:47,719 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 11:30:47,719 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 11:30:47,719 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 11:30:47,720 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 11:30:47,733 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 11:30:47,746 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 11:30:47,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:47,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 880 [2022-11-16 11:30:47,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:47,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:47,836 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:47,840 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:47,840 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 11:30:47,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:47,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 880 [2022-11-16 11:30:47,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:47,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:47,886 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:47,891 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:47,906 INFO L748 eck$LassoCheckResult]: Stem: 478#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 909#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 24#L1266true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40#L590true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 844#L597true assume !(1 == ~m_i~0);~m_st~0 := 2; 429#L597-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 973#L602-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 162#L607-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 473#L612-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 131#L617-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 276#L622-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 959#L627-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 257#L632-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 549#L637-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 483#L854true assume !(0 == ~M_E~0); 318#L854-2true assume !(0 == ~T1_E~0); 615#L859-1true assume !(0 == ~T2_E~0); 68#L864-1true assume !(0 == ~T3_E~0); 124#L869-1true assume !(0 == ~T4_E~0); 857#L874-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 791#L879-1true assume !(0 == ~T6_E~0); 310#L884-1true assume !(0 == ~T7_E~0); 9#L889-1true assume !(0 == ~T8_E~0); 171#L894-1true assume !(0 == ~E_M~0); 969#L899-1true assume !(0 == ~E_1~0); 488#L904-1true assume !(0 == ~E_2~0); 267#L909-1true assume !(0 == ~E_3~0); 420#L914-1true assume 0 == ~E_4~0;~E_4~0 := 1; 443#L919-1true assume !(0 == ~E_5~0); 217#L924-1true assume !(0 == ~E_6~0); 116#L929-1true assume !(0 == ~E_7~0); 811#L934-1true assume !(0 == ~E_8~0); 255#L939-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18#L418true assume !(1 == ~m_pc~0); 892#L418-2true is_master_triggered_~__retres1~0#1 := 0; 691#L429true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 897#L430true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 600#L1061true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 510#L1061-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 874#L437true assume 1 == ~t1_pc~0; 962#L438true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 608#L448true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 553#L449true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 190#L1069true assume !(0 != activate_threads_~tmp___0~0#1); 802#L1069-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 592#L456true assume !(1 == ~t2_pc~0); 418#L456-2true is_transmit2_triggered_~__retres1~2#1 := 0; 863#L467true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 363#L468true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 635#L1077true assume !(0 != activate_threads_~tmp___1~0#1); 344#L1077-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66#L475true assume 1 == ~t3_pc~0; 289#L476true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94#L486true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 896#L487true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 772#L1085true assume !(0 != activate_threads_~tmp___2~0#1); 192#L1085-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 687#L494true assume !(1 == ~t4_pc~0); 214#L494-2true is_transmit4_triggered_~__retres1~4#1 := 0; 400#L505true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 357#L506true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 943#L1093true assume !(0 != activate_threads_~tmp___3~0#1); 440#L1093-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92#L513true assume 1 == ~t5_pc~0; 566#L514true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 903#L524true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 240#L525true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73#L1101true assume !(0 != activate_threads_~tmp___4~0#1); 880#L1101-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52#L532true assume !(1 == ~t6_pc~0); 392#L532-2true is_transmit6_triggered_~__retres1~6#1 := 0; 292#L543true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 353#L544true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 828#L1109true assume !(0 != activate_threads_~tmp___5~0#1); 175#L1109-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 640#L551true assume 1 == ~t7_pc~0; 649#L552true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 446#L562true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 668#L563true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 997#L1117true assume !(0 != activate_threads_~tmp___6~0#1); 934#L1117-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 283#L570true assume 1 == ~t8_pc~0; 364#L571true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 728#L581true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 490#L582true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 360#L1125true assume !(0 != activate_threads_~tmp___7~0#1); 63#L1125-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 612#L952true assume 1 == ~M_E~0;~M_E~0 := 2; 41#L952-2true assume !(1 == ~T1_E~0); 576#L957-1true assume !(1 == ~T2_E~0); 884#L962-1true assume !(1 == ~T3_E~0); 375#L967-1true assume !(1 == ~T4_E~0); 846#L972-1true assume !(1 == ~T5_E~0); 641#L977-1true assume !(1 == ~T6_E~0); 940#L982-1true assume !(1 == ~T7_E~0); 127#L987-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 132#L992-1true assume !(1 == ~E_M~0); 342#L997-1true assume !(1 == ~E_1~0); 796#L1002-1true assume !(1 == ~E_2~0); 333#L1007-1true assume !(1 == ~E_3~0); 10#L1012-1true assume !(1 == ~E_4~0); 546#L1017-1true assume !(1 == ~E_5~0); 335#L1022-1true assume !(1 == ~E_6~0); 354#L1027-1true assume 1 == ~E_7~0;~E_7~0 := 2; 799#L1032-1true assume !(1 == ~E_8~0); 467#L1037-1true assume { :end_inline_reset_delta_events } true; 568#L1303-2true [2022-11-16 11:30:47,911 INFO L750 eck$LassoCheckResult]: Loop: 568#L1303-2true assume !false; 601#L1304true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 889#L829true assume !true; 562#L844true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27#L590-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 454#L854-3true assume 0 == ~M_E~0;~M_E~0 := 1; 435#L854-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 954#L859-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 916#L864-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 784#L869-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 293#L874-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 343#L879-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 374#L884-3true assume !(0 == ~T7_E~0); 329#L889-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 111#L894-3true assume 0 == ~E_M~0;~E_M~0 := 1; 479#L899-3true assume 0 == ~E_1~0;~E_1~0 := 1; 129#L904-3true assume 0 == ~E_2~0;~E_2~0 := 1; 308#L909-3true assume 0 == ~E_3~0;~E_3~0 := 1; 98#L914-3true assume 0 == ~E_4~0;~E_4~0 := 1; 122#L919-3true assume 0 == ~E_5~0;~E_5~0 := 1; 706#L924-3true assume !(0 == ~E_6~0); 516#L929-3true assume 0 == ~E_7~0;~E_7~0 := 1; 421#L934-3true assume 0 == ~E_8~0;~E_8~0 := 1; 643#L939-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 551#L418-30true assume !(1 == ~m_pc~0); 369#L418-32true is_master_triggered_~__retres1~0#1 := 0; 563#L429-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 303#L430-10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 816#L1061-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146#L1061-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216#L437-30true assume 1 == ~t1_pc~0; 457#L438-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 359#L448-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 534#L449-10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 900#L1069-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 864#L1069-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 195#L456-30true assume 1 == ~t2_pc~0; 693#L457-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 505#L467-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 873#L468-10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86#L1077-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 277#L1077-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 742#L475-30true assume 1 == ~t3_pc~0; 633#L476-10true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 434#L486-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 795#L487-10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 887#L1085-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 206#L1085-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 988#L494-30true assume !(1 == ~t4_pc~0); 100#L494-32true is_transmit4_triggered_~__retres1~4#1 := 0; 3#L505-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 715#L506-10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 908#L1093-30true assume !(0 != activate_threads_~tmp___3~0#1); 672#L1093-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 946#L513-30true assume 1 == ~t5_pc~0; 974#L514-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 326#L524-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 871#L525-10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 531#L1101-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 771#L1101-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 286#L532-30true assume !(1 == ~t6_pc~0); 961#L532-32true is_transmit6_triggered_~__retres1~6#1 := 0; 65#L543-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74#L544-10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 604#L1109-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 105#L1109-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 134#L551-30true assume !(1 == ~t7_pc~0); 684#L551-32true is_transmit7_triggered_~__retres1~7#1 := 0; 619#L562-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97#L563-10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11#L1117-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 193#L1117-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 735#L570-30true assume 1 == ~t8_pc~0; 610#L571-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 133#L581-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 107#L582-10true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39#L1125-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 231#L1125-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253#L952-3true assume 1 == ~M_E~0;~M_E~0 := 2; 948#L952-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 731#L957-3true assume !(1 == ~T2_E~0); 744#L962-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 591#L967-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 775#L972-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 487#L977-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 984#L982-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 964#L987-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 223#L992-3true assume 1 == ~E_M~0;~E_M~0 := 2; 349#L997-3true assume !(1 == ~E_1~0); 221#L1002-3true assume 1 == ~E_2~0;~E_2~0 := 2; 444#L1007-3true assume 1 == ~E_3~0;~E_3~0 := 2; 118#L1012-3true assume 1 == ~E_4~0;~E_4~0 := 2; 170#L1017-3true assume 1 == ~E_5~0;~E_5~0 := 2; 309#L1022-3true assume 1 == ~E_6~0;~E_6~0 := 2; 334#L1027-3true assume 1 == ~E_7~0;~E_7~0 := 2; 26#L1032-3true assume 1 == ~E_8~0;~E_8~0 := 2; 415#L1037-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 140#L650-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 743#L697-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 90#L698-1true start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 808#L1322true assume !(0 == start_simulation_~tmp~3#1); 243#L1322-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 61#L650-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 732#L697-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 851#L698-2true stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 19#L1277true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 489#L1284true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 785#L1285true start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 646#L1335true assume !(0 != start_simulation_~tmp___0~1#1); 568#L1303-2true [2022-11-16 11:30:47,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:47,928 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2022-11-16 11:30:47,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:47,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999941077] [2022-11-16 11:30:47,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:47,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:48,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:48,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:48,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:48,254 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999941077] [2022-11-16 11:30:48,255 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999941077] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:48,255 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:48,256 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:48,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1619105544] [2022-11-16 11:30:48,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:48,263 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:48,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:48,264 INFO L85 PathProgramCache]: Analyzing trace with hash 1151427140, now seen corresponding path program 1 times [2022-11-16 11:30:48,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:48,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442423614] [2022-11-16 11:30:48,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:48,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:48,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:48,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:48,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:48,316 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442423614] [2022-11-16 11:30:48,317 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442423614] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:48,317 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:48,317 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:30:48,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893120882] [2022-11-16 11:30:48,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:48,319 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:48,320 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:48,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:48,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:48,359 INFO L87 Difference]: Start difference. First operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:48,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:48,431 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2022-11-16 11:30:48,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1486 transitions. [2022-11-16 11:30:48,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:48,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 993 states and 1481 transitions. [2022-11-16 11:30:48,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-11-16 11:30:48,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-11-16 11:30:48,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1481 transitions. [2022-11-16 11:30:48,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:48,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1481 transitions. [2022-11-16 11:30:48,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1481 transitions. [2022-11-16 11:30:48,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-11-16 11:30:48,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4914400805639476) internal successors, (1481), 992 states have internal predecessors, (1481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:48,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1481 transitions. [2022-11-16 11:30:48,562 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1481 transitions. [2022-11-16 11:30:48,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:48,567 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1481 transitions. [2022-11-16 11:30:48,567 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 11:30:48,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1481 transitions. [2022-11-16 11:30:48,576 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:48,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:48,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:48,580 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:48,580 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:48,581 INFO L748 eck$LassoCheckResult]: Stem: 2766#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 2767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2053#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2054#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2091#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2717#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2718#L602-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2339#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2340#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2280#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2281#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2524#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2497#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2498#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2770#L854 assume !(0 == ~M_E~0); 2584#L854-2 assume !(0 == ~T1_E~0); 2585#L859-1 assume !(0 == ~T2_E~0); 2155#L864-1 assume !(0 == ~T3_E~0); 2156#L869-1 assume !(0 == ~T4_E~0); 2269#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2969#L879-1 assume !(0 == ~T6_E~0); 2572#L884-1 assume !(0 == ~T7_E~0); 2023#L889-1 assume !(0 == ~T8_E~0); 2024#L894-1 assume !(0 == ~E_M~0); 2354#L899-1 assume !(0 == ~E_1~0); 2777#L904-1 assume !(0 == ~E_2~0); 2513#L909-1 assume !(0 == ~E_3~0); 2514#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2708#L919-1 assume !(0 == ~E_5~0); 2434#L924-1 assume !(0 == ~E_6~0); 2252#L929-1 assume !(0 == ~E_7~0); 2253#L934-1 assume !(0 == ~E_8~0); 2494#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2041#L418 assume !(1 == ~m_pc~0); 2013#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2012#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2928#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2877#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2802#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2803#L437 assume 1 == ~t1_pc~0; 2986#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2885#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2838#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2389#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2390#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2868#L456 assume !(1 == ~t2_pc~0); 2305#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2304#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2643#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2644#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2619#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2149#L475 assume 1 == ~t3_pc~0; 2150#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2210#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2211#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2964#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2393#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2394#L494 assume !(1 == ~t4_pc~0); 2429#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2430#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2634#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2635#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2731#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2205#L513 assume 1 == ~t5_pc~0; 2206#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2431#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2468#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2166#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2167#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2118#L532 assume !(1 == ~t6_pc~0); 2119#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2270#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2549#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2628#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2359#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2360#L551 assume 1 == ~t7_pc~0; 2906#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2735#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2736#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2917#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 2995#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2533#L570 assume 1 == ~t8_pc~0; 2534#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2645#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2779#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2639#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2143#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2144#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 2092#L952-2 assume !(1 == ~T1_E~0); 2093#L957-1 assume !(1 == ~T2_E~0); 2850#L962-1 assume !(1 == ~T3_E~0); 2655#L967-1 assume !(1 == ~T4_E~0); 2656#L972-1 assume !(1 == ~T5_E~0); 2907#L977-1 assume !(1 == ~T6_E~0); 2908#L982-1 assume !(1 == ~T7_E~0); 2272#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2273#L992-1 assume !(1 == ~E_M~0); 2282#L997-1 assume !(1 == ~E_1~0); 2617#L1002-1 assume !(1 == ~E_2~0); 2605#L1007-1 assume !(1 == ~E_3~0); 2025#L1012-1 assume !(1 == ~E_4~0); 2026#L1017-1 assume !(1 == ~E_5~0); 2606#L1022-1 assume !(1 == ~E_6~0); 2607#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2629#L1032-1 assume !(1 == ~E_8~0); 2754#L1037-1 assume { :end_inline_reset_delta_events } true; 2755#L1303-2 [2022-11-16 11:30:48,582 INFO L750 eck$LassoCheckResult]: Loop: 2755#L1303-2 assume !false; 2845#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2036#L829 assume !false; 2799#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2414#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2342#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2745#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2723#L712 assume !(0 != eval_~tmp~0#1); 2724#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2060#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2061#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2726#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2727#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2993#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2967#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2550#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2551#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2618#L884-3 assume !(0 == ~T7_E~0); 2599#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2243#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2244#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2276#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2277#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2217#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2218#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2265#L924-3 assume !(0 == ~E_6~0); 2807#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2709#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2710#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2836#L418-30 assume 1 == ~m_pc~0; 2107#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2108#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2562#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2563#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2306#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2307#L437-30 assume !(1 == ~t1_pc~0); 2432#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2637#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2638#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2825#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2984#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2398#L456-30 assume !(1 == ~t2_pc~0); 2400#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2796#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2797#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2191#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2192#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2525#L475-30 assume 1 == ~t3_pc~0; 2900#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2074#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2725#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2970#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2416#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2417#L494-30 assume 1 == ~t4_pc~0; 2410#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2009#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2010#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2941#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2920#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2921#L513-30 assume !(1 == ~t5_pc~0); 2530#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2531#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2595#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2821#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2822#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2541#L532-30 assume !(1 == ~t6_pc~0); 2542#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2147#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2148#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2169#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2231#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2232#L551-30 assume 1 == ~t7_pc~0; 2284#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2344#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2216#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2027#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2028#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2395#L570-30 assume 1 == ~t8_pc~0; 2886#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2283#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2235#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2089#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2090#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2456#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2491#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2948#L957-3 assume !(1 == ~T2_E~0); 2949#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2866#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2867#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2775#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2776#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2998#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2444#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2445#L997-3 assume !(1 == ~E_1~0); 2440#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2441#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2256#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2257#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2353#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2571#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2058#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2059#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2296#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2297#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2201#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2202#L1322 assume !(0 == start_simulation_~tmp~3#1); 2470#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2137#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2138#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2950#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2042#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2043#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2778#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2910#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2755#L1303-2 [2022-11-16 11:30:48,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:48,583 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2022-11-16 11:30:48,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:48,583 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140083541] [2022-11-16 11:30:48,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:48,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:48,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:48,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:48,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:48,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140083541] [2022-11-16 11:30:48,733 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1140083541] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:48,733 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:48,733 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:48,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713839564] [2022-11-16 11:30:48,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:48,734 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:48,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:48,735 INFO L85 PathProgramCache]: Analyzing trace with hash -500294447, now seen corresponding path program 1 times [2022-11-16 11:30:48,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:48,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984070569] [2022-11-16 11:30:48,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:48,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:48,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:48,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:48,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:48,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984070569] [2022-11-16 11:30:48,852 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984070569] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:48,853 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:48,853 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:48,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2003451306] [2022-11-16 11:30:48,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:48,854 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:48,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:48,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:48,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:48,855 INFO L87 Difference]: Start difference. First operand 993 states and 1481 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:48,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:48,885 INFO L93 Difference]: Finished difference Result 993 states and 1480 transitions. [2022-11-16 11:30:48,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1480 transitions. [2022-11-16 11:30:48,892 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:48,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1480 transitions. [2022-11-16 11:30:48,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-11-16 11:30:48,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-11-16 11:30:48,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1480 transitions. [2022-11-16 11:30:48,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:48,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1480 transitions. [2022-11-16 11:30:48,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1480 transitions. [2022-11-16 11:30:48,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-11-16 11:30:48,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4904330312185297) internal successors, (1480), 992 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:48,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1480 transitions. [2022-11-16 11:30:48,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1480 transitions. [2022-11-16 11:30:48,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:48,920 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1480 transitions. [2022-11-16 11:30:48,920 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 11:30:48,920 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1480 transitions. [2022-11-16 11:30:48,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:48,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:48,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:48,927 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:48,927 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:48,928 INFO L748 eck$LassoCheckResult]: Stem: 4759#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 4760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4046#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4047#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4084#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 4710#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4711#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4332#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4333#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4273#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4274#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4517#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4490#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4491#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4763#L854 assume !(0 == ~M_E~0); 4577#L854-2 assume !(0 == ~T1_E~0); 4578#L859-1 assume !(0 == ~T2_E~0); 4148#L864-1 assume !(0 == ~T3_E~0); 4149#L869-1 assume !(0 == ~T4_E~0); 4262#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4962#L879-1 assume !(0 == ~T6_E~0); 4565#L884-1 assume !(0 == ~T7_E~0); 4016#L889-1 assume !(0 == ~T8_E~0); 4017#L894-1 assume !(0 == ~E_M~0); 4347#L899-1 assume !(0 == ~E_1~0); 4770#L904-1 assume !(0 == ~E_2~0); 4506#L909-1 assume !(0 == ~E_3~0); 4507#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4701#L919-1 assume !(0 == ~E_5~0); 4427#L924-1 assume !(0 == ~E_6~0); 4245#L929-1 assume !(0 == ~E_7~0); 4246#L934-1 assume !(0 == ~E_8~0); 4487#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4034#L418 assume !(1 == ~m_pc~0); 4006#L418-2 is_master_triggered_~__retres1~0#1 := 0; 4005#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4921#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4870#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4795#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4796#L437 assume 1 == ~t1_pc~0; 4979#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4878#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4831#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4382#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 4383#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4861#L456 assume !(1 == ~t2_pc~0); 4298#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4297#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4636#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4637#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 4612#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4142#L475 assume 1 == ~t3_pc~0; 4143#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4203#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4204#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4957#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 4386#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4387#L494 assume !(1 == ~t4_pc~0); 4422#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4423#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4627#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4628#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 4724#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4198#L513 assume 1 == ~t5_pc~0; 4199#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4424#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4461#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4159#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 4160#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4111#L532 assume !(1 == ~t6_pc~0); 4112#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4263#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4542#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4621#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 4352#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4353#L551 assume 1 == ~t7_pc~0; 4899#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4728#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4729#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4910#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 4988#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4526#L570 assume 1 == ~t8_pc~0; 4527#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4638#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4772#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4632#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 4136#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4137#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 4085#L952-2 assume !(1 == ~T1_E~0); 4086#L957-1 assume !(1 == ~T2_E~0); 4843#L962-1 assume !(1 == ~T3_E~0); 4648#L967-1 assume !(1 == ~T4_E~0); 4649#L972-1 assume !(1 == ~T5_E~0); 4900#L977-1 assume !(1 == ~T6_E~0); 4901#L982-1 assume !(1 == ~T7_E~0); 4265#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4266#L992-1 assume !(1 == ~E_M~0); 4275#L997-1 assume !(1 == ~E_1~0); 4610#L1002-1 assume !(1 == ~E_2~0); 4598#L1007-1 assume !(1 == ~E_3~0); 4018#L1012-1 assume !(1 == ~E_4~0); 4019#L1017-1 assume !(1 == ~E_5~0); 4599#L1022-1 assume !(1 == ~E_6~0); 4600#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4622#L1032-1 assume !(1 == ~E_8~0); 4747#L1037-1 assume { :end_inline_reset_delta_events } true; 4748#L1303-2 [2022-11-16 11:30:48,928 INFO L750 eck$LassoCheckResult]: Loop: 4748#L1303-2 assume !false; 4838#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4029#L829 assume !false; 4792#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4407#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4335#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4738#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4716#L712 assume !(0 != eval_~tmp~0#1); 4717#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4053#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4054#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4719#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4720#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4986#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4960#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4543#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4544#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4611#L884-3 assume !(0 == ~T7_E~0); 4592#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4236#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4237#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4269#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4270#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4210#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4211#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4258#L924-3 assume !(0 == ~E_6~0); 4800#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4702#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4703#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4829#L418-30 assume 1 == ~m_pc~0; 4100#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4101#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4555#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4556#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4299#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4300#L437-30 assume !(1 == ~t1_pc~0); 4425#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4630#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4631#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4818#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4977#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4391#L456-30 assume 1 == ~t2_pc~0; 4392#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4789#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4790#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4184#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4185#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4518#L475-30 assume !(1 == ~t3_pc~0); 4066#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4067#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4718#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4963#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4409#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4410#L494-30 assume 1 == ~t4_pc~0; 4403#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4002#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4003#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4934#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 4913#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4914#L513-30 assume !(1 == ~t5_pc~0); 4523#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4524#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4588#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4814#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4815#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4534#L532-30 assume !(1 == ~t6_pc~0); 4535#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4140#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4141#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4162#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4224#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4225#L551-30 assume 1 == ~t7_pc~0; 4277#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4337#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4209#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4020#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4021#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4388#L570-30 assume !(1 == ~t8_pc~0); 4709#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4276#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4228#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4082#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4083#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4449#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4484#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4941#L957-3 assume !(1 == ~T2_E~0); 4942#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4859#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4860#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4768#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4769#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4991#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4437#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4438#L997-3 assume !(1 == ~E_1~0); 4433#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4434#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4249#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4250#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4346#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4564#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4051#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4052#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4289#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4290#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4194#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4195#L1322 assume !(0 == start_simulation_~tmp~3#1); 4463#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4130#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4131#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4943#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 4035#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4036#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4771#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4903#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 4748#L1303-2 [2022-11-16 11:30:48,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:48,929 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2022-11-16 11:30:48,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:48,929 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706306067] [2022-11-16 11:30:48,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:48,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:48,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:48,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:48,983 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:48,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706306067] [2022-11-16 11:30:48,984 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706306067] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:48,984 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:48,984 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:48,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [376803812] [2022-11-16 11:30:48,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:48,985 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:48,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:48,985 INFO L85 PathProgramCache]: Analyzing trace with hash 630471762, now seen corresponding path program 1 times [2022-11-16 11:30:48,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:48,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673872316] [2022-11-16 11:30:48,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:48,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:49,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:49,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673872316] [2022-11-16 11:30:49,132 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673872316] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:49,132 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:49,132 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:49,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707449329] [2022-11-16 11:30:49,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:49,133 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:49,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:49,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:49,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:49,134 INFO L87 Difference]: Start difference. First operand 993 states and 1480 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:49,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:49,163 INFO L93 Difference]: Finished difference Result 993 states and 1479 transitions. [2022-11-16 11:30:49,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1479 transitions. [2022-11-16 11:30:49,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:49,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1479 transitions. [2022-11-16 11:30:49,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-11-16 11:30:49,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-11-16 11:30:49,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1479 transitions. [2022-11-16 11:30:49,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:49,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1479 transitions. [2022-11-16 11:30:49,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1479 transitions. [2022-11-16 11:30:49,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-11-16 11:30:49,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4894259818731117) internal successors, (1479), 992 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:49,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1479 transitions. [2022-11-16 11:30:49,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1479 transitions. [2022-11-16 11:30:49,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:49,201 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1479 transitions. [2022-11-16 11:30:49,201 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 11:30:49,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1479 transitions. [2022-11-16 11:30:49,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:49,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:49,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:49,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:49,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:49,213 INFO L748 eck$LassoCheckResult]: Stem: 6752#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 6753#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6039#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6040#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6077#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 6703#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6704#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6325#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6326#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6266#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6267#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6510#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6483#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6484#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6756#L854 assume !(0 == ~M_E~0); 6570#L854-2 assume !(0 == ~T1_E~0); 6571#L859-1 assume !(0 == ~T2_E~0); 6141#L864-1 assume !(0 == ~T3_E~0); 6142#L869-1 assume !(0 == ~T4_E~0); 6255#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6955#L879-1 assume !(0 == ~T6_E~0); 6558#L884-1 assume !(0 == ~T7_E~0); 6009#L889-1 assume !(0 == ~T8_E~0); 6010#L894-1 assume !(0 == ~E_M~0); 6340#L899-1 assume !(0 == ~E_1~0); 6763#L904-1 assume !(0 == ~E_2~0); 6499#L909-1 assume !(0 == ~E_3~0); 6500#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6694#L919-1 assume !(0 == ~E_5~0); 6420#L924-1 assume !(0 == ~E_6~0); 6238#L929-1 assume !(0 == ~E_7~0); 6239#L934-1 assume !(0 == ~E_8~0); 6480#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6027#L418 assume !(1 == ~m_pc~0); 5999#L418-2 is_master_triggered_~__retres1~0#1 := 0; 5998#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6914#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6863#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6788#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6789#L437 assume 1 == ~t1_pc~0; 6972#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6871#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6824#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6375#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 6376#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6854#L456 assume !(1 == ~t2_pc~0); 6291#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6290#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6629#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6630#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 6605#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6135#L475 assume 1 == ~t3_pc~0; 6136#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6196#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6197#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6950#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 6379#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6380#L494 assume !(1 == ~t4_pc~0); 6415#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6416#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6620#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6621#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 6717#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6191#L513 assume 1 == ~t5_pc~0; 6192#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6417#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6454#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6152#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 6153#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6104#L532 assume !(1 == ~t6_pc~0); 6105#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6256#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6535#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6614#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 6345#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6346#L551 assume 1 == ~t7_pc~0; 6892#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6721#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6722#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6903#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 6981#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6519#L570 assume 1 == ~t8_pc~0; 6520#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6631#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6765#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6625#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 6129#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6130#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 6078#L952-2 assume !(1 == ~T1_E~0); 6079#L957-1 assume !(1 == ~T2_E~0); 6836#L962-1 assume !(1 == ~T3_E~0); 6641#L967-1 assume !(1 == ~T4_E~0); 6642#L972-1 assume !(1 == ~T5_E~0); 6893#L977-1 assume !(1 == ~T6_E~0); 6894#L982-1 assume !(1 == ~T7_E~0); 6258#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6259#L992-1 assume !(1 == ~E_M~0); 6268#L997-1 assume !(1 == ~E_1~0); 6603#L1002-1 assume !(1 == ~E_2~0); 6591#L1007-1 assume !(1 == ~E_3~0); 6011#L1012-1 assume !(1 == ~E_4~0); 6012#L1017-1 assume !(1 == ~E_5~0); 6592#L1022-1 assume !(1 == ~E_6~0); 6593#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6615#L1032-1 assume !(1 == ~E_8~0); 6740#L1037-1 assume { :end_inline_reset_delta_events } true; 6741#L1303-2 [2022-11-16 11:30:49,213 INFO L750 eck$LassoCheckResult]: Loop: 6741#L1303-2 assume !false; 6831#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6022#L829 assume !false; 6785#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6400#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6328#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6731#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6709#L712 assume !(0 != eval_~tmp~0#1); 6710#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6046#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6047#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6712#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6713#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6979#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6953#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6536#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6537#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6604#L884-3 assume !(0 == ~T7_E~0); 6585#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6229#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6230#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6262#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6263#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6203#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6204#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6251#L924-3 assume !(0 == ~E_6~0); 6793#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6695#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6696#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6822#L418-30 assume 1 == ~m_pc~0; 6093#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6094#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6548#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6549#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6292#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6293#L437-30 assume !(1 == ~t1_pc~0); 6418#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 6623#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6624#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6811#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6970#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6384#L456-30 assume 1 == ~t2_pc~0; 6385#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6782#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6783#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6177#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6178#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6511#L475-30 assume 1 == ~t3_pc~0; 6886#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6060#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6711#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6956#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6402#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6403#L494-30 assume !(1 == ~t4_pc~0); 6208#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 5995#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5996#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6927#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 6906#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6907#L513-30 assume !(1 == ~t5_pc~0); 6516#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 6517#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6581#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6807#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6808#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6527#L532-30 assume !(1 == ~t6_pc~0); 6528#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 6133#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6134#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6155#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6217#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6218#L551-30 assume 1 == ~t7_pc~0; 6270#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6330#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6202#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6013#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6014#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6381#L570-30 assume 1 == ~t8_pc~0; 6872#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6269#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6221#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6075#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6076#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6442#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6477#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6934#L957-3 assume !(1 == ~T2_E~0); 6935#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6852#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6853#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6761#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6762#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6984#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6430#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6431#L997-3 assume !(1 == ~E_1~0); 6426#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6427#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6242#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6243#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6339#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6557#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6044#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6045#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6282#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6283#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6187#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6188#L1322 assume !(0 == start_simulation_~tmp~3#1); 6456#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6123#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6124#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6936#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 6028#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6029#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6764#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6896#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 6741#L1303-2 [2022-11-16 11:30:49,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:49,215 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2022-11-16 11:30:49,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:49,216 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112301224] [2022-11-16 11:30:49,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:49,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:49,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:49,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112301224] [2022-11-16 11:30:49,320 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112301224] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:49,321 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:49,321 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:49,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058243383] [2022-11-16 11:30:49,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:49,322 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:49,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:49,322 INFO L85 PathProgramCache]: Analyzing trace with hash -1603750319, now seen corresponding path program 1 times [2022-11-16 11:30:49,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:49,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013185561] [2022-11-16 11:30:49,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:49,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:49,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:49,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013185561] [2022-11-16 11:30:49,411 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1013185561] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:49,412 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:49,412 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:49,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310406712] [2022-11-16 11:30:49,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:49,414 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:49,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:49,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:49,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:49,417 INFO L87 Difference]: Start difference. First operand 993 states and 1479 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:49,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:49,439 INFO L93 Difference]: Finished difference Result 993 states and 1478 transitions. [2022-11-16 11:30:49,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1478 transitions. [2022-11-16 11:30:49,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:49,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1478 transitions. [2022-11-16 11:30:49,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-11-16 11:30:49,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-11-16 11:30:49,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1478 transitions. [2022-11-16 11:30:49,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:49,454 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1478 transitions. [2022-11-16 11:30:49,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1478 transitions. [2022-11-16 11:30:49,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-11-16 11:30:49,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4884189325276937) internal successors, (1478), 992 states have internal predecessors, (1478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:49,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1478 transitions. [2022-11-16 11:30:49,472 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1478 transitions. [2022-11-16 11:30:49,472 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:49,473 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1478 transitions. [2022-11-16 11:30:49,473 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 11:30:49,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1478 transitions. [2022-11-16 11:30:49,478 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:49,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:49,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:49,481 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:49,481 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:49,481 INFO L748 eck$LassoCheckResult]: Stem: 8745#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 8746#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8032#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8033#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8070#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 8696#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8697#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8318#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8319#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8259#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8260#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8503#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8476#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8477#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8749#L854 assume !(0 == ~M_E~0); 8563#L854-2 assume !(0 == ~T1_E~0); 8564#L859-1 assume !(0 == ~T2_E~0); 8134#L864-1 assume !(0 == ~T3_E~0); 8135#L869-1 assume !(0 == ~T4_E~0); 8248#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8948#L879-1 assume !(0 == ~T6_E~0); 8551#L884-1 assume !(0 == ~T7_E~0); 8002#L889-1 assume !(0 == ~T8_E~0); 8003#L894-1 assume !(0 == ~E_M~0); 8333#L899-1 assume !(0 == ~E_1~0); 8756#L904-1 assume !(0 == ~E_2~0); 8492#L909-1 assume !(0 == ~E_3~0); 8493#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8687#L919-1 assume !(0 == ~E_5~0); 8413#L924-1 assume !(0 == ~E_6~0); 8231#L929-1 assume !(0 == ~E_7~0); 8232#L934-1 assume !(0 == ~E_8~0); 8473#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8020#L418 assume !(1 == ~m_pc~0); 7992#L418-2 is_master_triggered_~__retres1~0#1 := 0; 7991#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8907#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8856#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8781#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8782#L437 assume 1 == ~t1_pc~0; 8965#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8864#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8817#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8368#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 8369#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8847#L456 assume !(1 == ~t2_pc~0); 8284#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8283#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8622#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8623#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 8598#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8128#L475 assume 1 == ~t3_pc~0; 8129#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8189#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8190#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8943#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 8372#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8373#L494 assume !(1 == ~t4_pc~0); 8408#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8409#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8613#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8614#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 8710#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8184#L513 assume 1 == ~t5_pc~0; 8185#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8410#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8447#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8145#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 8146#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8097#L532 assume !(1 == ~t6_pc~0); 8098#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8249#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8528#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8607#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 8338#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8339#L551 assume 1 == ~t7_pc~0; 8885#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8714#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8715#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8896#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 8974#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8512#L570 assume 1 == ~t8_pc~0; 8513#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8624#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8758#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8618#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 8122#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8123#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 8071#L952-2 assume !(1 == ~T1_E~0); 8072#L957-1 assume !(1 == ~T2_E~0); 8829#L962-1 assume !(1 == ~T3_E~0); 8634#L967-1 assume !(1 == ~T4_E~0); 8635#L972-1 assume !(1 == ~T5_E~0); 8886#L977-1 assume !(1 == ~T6_E~0); 8887#L982-1 assume !(1 == ~T7_E~0); 8251#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8252#L992-1 assume !(1 == ~E_M~0); 8261#L997-1 assume !(1 == ~E_1~0); 8596#L1002-1 assume !(1 == ~E_2~0); 8584#L1007-1 assume !(1 == ~E_3~0); 8004#L1012-1 assume !(1 == ~E_4~0); 8005#L1017-1 assume !(1 == ~E_5~0); 8585#L1022-1 assume !(1 == ~E_6~0); 8586#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8608#L1032-1 assume !(1 == ~E_8~0); 8733#L1037-1 assume { :end_inline_reset_delta_events } true; 8734#L1303-2 [2022-11-16 11:30:49,482 INFO L750 eck$LassoCheckResult]: Loop: 8734#L1303-2 assume !false; 8824#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8015#L829 assume !false; 8778#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8393#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8321#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8724#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8702#L712 assume !(0 != eval_~tmp~0#1); 8703#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8039#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8040#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8705#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8706#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8972#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8946#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8529#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8530#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8597#L884-3 assume !(0 == ~T7_E~0); 8578#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8222#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8223#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8255#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8256#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8196#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8197#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8244#L924-3 assume !(0 == ~E_6~0); 8786#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8688#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8689#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8815#L418-30 assume 1 == ~m_pc~0; 8086#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8087#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8541#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8542#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8285#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8286#L437-30 assume !(1 == ~t1_pc~0); 8411#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 8616#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8617#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8804#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8963#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8377#L456-30 assume 1 == ~t2_pc~0; 8378#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8775#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8776#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8170#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8171#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8504#L475-30 assume !(1 == ~t3_pc~0); 8052#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 8053#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8704#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8949#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8395#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8396#L494-30 assume 1 == ~t4_pc~0; 8389#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7988#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7989#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8920#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 8899#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8900#L513-30 assume 1 == ~t5_pc~0; 8976#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8510#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8574#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8800#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8801#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8520#L532-30 assume !(1 == ~t6_pc~0); 8521#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 8126#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8127#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8148#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8210#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8211#L551-30 assume 1 == ~t7_pc~0; 8263#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8323#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8195#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8006#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8007#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8374#L570-30 assume 1 == ~t8_pc~0; 8865#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8262#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8214#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8068#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8069#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8435#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8470#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8927#L957-3 assume !(1 == ~T2_E~0); 8928#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8845#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8846#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8754#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8755#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8977#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8423#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8424#L997-3 assume !(1 == ~E_1~0); 8419#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8420#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8235#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8236#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8332#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8550#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8037#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8038#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8275#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8276#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8180#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8181#L1322 assume !(0 == start_simulation_~tmp~3#1); 8449#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8116#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8117#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8929#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 8021#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8022#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8757#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8889#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 8734#L1303-2 [2022-11-16 11:30:49,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:49,483 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2022-11-16 11:30:49,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:49,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208160547] [2022-11-16 11:30:49,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:49,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:49,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:49,539 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208160547] [2022-11-16 11:30:49,539 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1208160547] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:49,539 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:49,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:49,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808899073] [2022-11-16 11:30:49,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:49,540 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:49,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:49,541 INFO L85 PathProgramCache]: Analyzing trace with hash 613340432, now seen corresponding path program 1 times [2022-11-16 11:30:49,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:49,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830347746] [2022-11-16 11:30:49,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:49,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:49,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,609 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:49,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830347746] [2022-11-16 11:30:49,610 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830347746] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:49,610 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:49,610 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:49,610 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627919807] [2022-11-16 11:30:49,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:49,612 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:49,613 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:49,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:49,614 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:49,614 INFO L87 Difference]: Start difference. First operand 993 states and 1478 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:49,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:49,635 INFO L93 Difference]: Finished difference Result 993 states and 1477 transitions. [2022-11-16 11:30:49,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1477 transitions. [2022-11-16 11:30:49,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:49,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1477 transitions. [2022-11-16 11:30:49,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-11-16 11:30:49,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-11-16 11:30:49,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1477 transitions. [2022-11-16 11:30:49,651 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:49,651 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1477 transitions. [2022-11-16 11:30:49,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1477 transitions. [2022-11-16 11:30:49,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-11-16 11:30:49,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.487411883182276) internal successors, (1477), 992 states have internal predecessors, (1477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:49,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1477 transitions. [2022-11-16 11:30:49,670 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1477 transitions. [2022-11-16 11:30:49,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:49,672 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1477 transitions. [2022-11-16 11:30:49,673 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 11:30:49,673 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1477 transitions. [2022-11-16 11:30:49,678 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:49,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:49,678 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:49,681 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:49,681 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:49,682 INFO L748 eck$LassoCheckResult]: Stem: 10738#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 10739#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10025#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10026#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10063#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 10689#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10690#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10311#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10312#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10252#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10253#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10496#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10469#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10470#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10742#L854 assume !(0 == ~M_E~0); 10556#L854-2 assume !(0 == ~T1_E~0); 10557#L859-1 assume !(0 == ~T2_E~0); 10127#L864-1 assume !(0 == ~T3_E~0); 10128#L869-1 assume !(0 == ~T4_E~0); 10241#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10941#L879-1 assume !(0 == ~T6_E~0); 10544#L884-1 assume !(0 == ~T7_E~0); 9995#L889-1 assume !(0 == ~T8_E~0); 9996#L894-1 assume !(0 == ~E_M~0); 10326#L899-1 assume !(0 == ~E_1~0); 10749#L904-1 assume !(0 == ~E_2~0); 10485#L909-1 assume !(0 == ~E_3~0); 10486#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10680#L919-1 assume !(0 == ~E_5~0); 10406#L924-1 assume !(0 == ~E_6~0); 10224#L929-1 assume !(0 == ~E_7~0); 10225#L934-1 assume !(0 == ~E_8~0); 10466#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10013#L418 assume !(1 == ~m_pc~0); 9985#L418-2 is_master_triggered_~__retres1~0#1 := 0; 9984#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10900#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10849#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10774#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10775#L437 assume 1 == ~t1_pc~0; 10958#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10857#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10810#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10361#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 10362#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10840#L456 assume !(1 == ~t2_pc~0); 10277#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10276#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10615#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10616#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 10591#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10121#L475 assume 1 == ~t3_pc~0; 10122#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10182#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10183#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10936#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 10365#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10366#L494 assume !(1 == ~t4_pc~0); 10401#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10402#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10606#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10607#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 10703#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10177#L513 assume 1 == ~t5_pc~0; 10178#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10403#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10440#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10138#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 10139#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10090#L532 assume !(1 == ~t6_pc~0); 10091#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10242#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10521#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10600#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 10331#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10332#L551 assume 1 == ~t7_pc~0; 10878#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10707#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10708#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10889#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 10967#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10505#L570 assume 1 == ~t8_pc~0; 10506#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10617#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10751#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10611#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 10115#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10116#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 10064#L952-2 assume !(1 == ~T1_E~0); 10065#L957-1 assume !(1 == ~T2_E~0); 10822#L962-1 assume !(1 == ~T3_E~0); 10627#L967-1 assume !(1 == ~T4_E~0); 10628#L972-1 assume !(1 == ~T5_E~0); 10879#L977-1 assume !(1 == ~T6_E~0); 10880#L982-1 assume !(1 == ~T7_E~0); 10244#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10245#L992-1 assume !(1 == ~E_M~0); 10254#L997-1 assume !(1 == ~E_1~0); 10589#L1002-1 assume !(1 == ~E_2~0); 10577#L1007-1 assume !(1 == ~E_3~0); 9997#L1012-1 assume !(1 == ~E_4~0); 9998#L1017-1 assume !(1 == ~E_5~0); 10578#L1022-1 assume !(1 == ~E_6~0); 10579#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10601#L1032-1 assume !(1 == ~E_8~0); 10726#L1037-1 assume { :end_inline_reset_delta_events } true; 10727#L1303-2 [2022-11-16 11:30:49,682 INFO L750 eck$LassoCheckResult]: Loop: 10727#L1303-2 assume !false; 10817#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10008#L829 assume !false; 10771#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10386#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10314#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10717#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10695#L712 assume !(0 != eval_~tmp~0#1); 10696#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10032#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10033#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10698#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10699#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10965#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10939#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10522#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10523#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10590#L884-3 assume !(0 == ~T7_E~0); 10571#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10215#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10216#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10248#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10249#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10189#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10190#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10237#L924-3 assume !(0 == ~E_6~0); 10779#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10681#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10682#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10808#L418-30 assume !(1 == ~m_pc~0); 10081#L418-32 is_master_triggered_~__retres1~0#1 := 0; 10080#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10534#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10535#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10278#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10279#L437-30 assume !(1 == ~t1_pc~0); 10404#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 10609#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10610#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10797#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10956#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10370#L456-30 assume 1 == ~t2_pc~0; 10371#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10768#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10769#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10163#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10164#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10497#L475-30 assume 1 == ~t3_pc~0; 10872#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10046#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10697#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10942#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10388#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10389#L494-30 assume !(1 == ~t4_pc~0); 10194#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 9981#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9982#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10913#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 10892#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10893#L513-30 assume !(1 == ~t5_pc~0); 10502#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10503#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10567#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10793#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10794#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10513#L532-30 assume !(1 == ~t6_pc~0); 10514#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10119#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10120#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10141#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10203#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10204#L551-30 assume 1 == ~t7_pc~0; 10256#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10316#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10188#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9999#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10000#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10367#L570-30 assume !(1 == ~t8_pc~0); 10688#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 10255#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10207#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10061#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10062#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10428#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10463#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10920#L957-3 assume !(1 == ~T2_E~0); 10921#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10838#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10839#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10747#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10748#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10970#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10416#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10417#L997-3 assume !(1 == ~E_1~0); 10412#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10413#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10228#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10229#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10325#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10543#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10030#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10031#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10268#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10269#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10173#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10174#L1322 assume !(0 == start_simulation_~tmp~3#1); 10442#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10109#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10110#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10922#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 10014#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10015#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10750#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10882#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 10727#L1303-2 [2022-11-16 11:30:49,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:49,685 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2022-11-16 11:30:49,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:49,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948050585] [2022-11-16 11:30:49,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:49,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:49,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:49,747 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948050585] [2022-11-16 11:30:49,747 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948050585] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:49,748 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:49,748 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:49,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1578349115] [2022-11-16 11:30:49,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:49,753 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:49,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:49,756 INFO L85 PathProgramCache]: Analyzing trace with hash -1695676973, now seen corresponding path program 1 times [2022-11-16 11:30:49,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:49,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334062346] [2022-11-16 11:30:49,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:49,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:49,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:49,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334062346] [2022-11-16 11:30:49,831 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334062346] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:49,831 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:49,832 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:49,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [959149371] [2022-11-16 11:30:49,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:49,833 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:49,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:49,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:49,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:49,834 INFO L87 Difference]: Start difference. First operand 993 states and 1477 transitions. cyclomatic complexity: 485 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:49,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:49,867 INFO L93 Difference]: Finished difference Result 993 states and 1476 transitions. [2022-11-16 11:30:49,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1476 transitions. [2022-11-16 11:30:49,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:49,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1476 transitions. [2022-11-16 11:30:49,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-11-16 11:30:49,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-11-16 11:30:49,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1476 transitions. [2022-11-16 11:30:49,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:49,885 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1476 transitions. [2022-11-16 11:30:49,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1476 transitions. [2022-11-16 11:30:49,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-11-16 11:30:49,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.486404833836858) internal successors, (1476), 992 states have internal predecessors, (1476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:49,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1476 transitions. [2022-11-16 11:30:49,907 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1476 transitions. [2022-11-16 11:30:49,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:49,910 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1476 transitions. [2022-11-16 11:30:49,910 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 11:30:49,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1476 transitions. [2022-11-16 11:30:49,916 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:49,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:49,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:49,918 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:49,918 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:49,919 INFO L748 eck$LassoCheckResult]: Stem: 12731#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 12732#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12018#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12019#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12056#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 12682#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12683#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12304#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12305#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12245#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12246#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12489#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12462#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12463#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12735#L854 assume !(0 == ~M_E~0); 12549#L854-2 assume !(0 == ~T1_E~0); 12550#L859-1 assume !(0 == ~T2_E~0); 12120#L864-1 assume !(0 == ~T3_E~0); 12121#L869-1 assume !(0 == ~T4_E~0); 12234#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12934#L879-1 assume !(0 == ~T6_E~0); 12537#L884-1 assume !(0 == ~T7_E~0); 11988#L889-1 assume !(0 == ~T8_E~0); 11989#L894-1 assume !(0 == ~E_M~0); 12319#L899-1 assume !(0 == ~E_1~0); 12742#L904-1 assume !(0 == ~E_2~0); 12478#L909-1 assume !(0 == ~E_3~0); 12479#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12673#L919-1 assume !(0 == ~E_5~0); 12399#L924-1 assume !(0 == ~E_6~0); 12217#L929-1 assume !(0 == ~E_7~0); 12218#L934-1 assume !(0 == ~E_8~0); 12459#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12006#L418 assume !(1 == ~m_pc~0); 11978#L418-2 is_master_triggered_~__retres1~0#1 := 0; 11977#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12893#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12842#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12767#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12768#L437 assume 1 == ~t1_pc~0; 12951#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12850#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12803#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12354#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 12355#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12833#L456 assume !(1 == ~t2_pc~0); 12270#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12269#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12608#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12609#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 12584#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12114#L475 assume 1 == ~t3_pc~0; 12115#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12175#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12176#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12929#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 12358#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12359#L494 assume !(1 == ~t4_pc~0); 12394#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12395#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12599#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12600#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 12696#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12170#L513 assume 1 == ~t5_pc~0; 12171#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12396#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12433#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12131#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 12132#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12083#L532 assume !(1 == ~t6_pc~0); 12084#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12235#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12514#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12593#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 12324#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12325#L551 assume 1 == ~t7_pc~0; 12871#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12700#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12701#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12882#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 12960#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12498#L570 assume 1 == ~t8_pc~0; 12499#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12610#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12744#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12604#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 12108#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12109#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 12057#L952-2 assume !(1 == ~T1_E~0); 12058#L957-1 assume !(1 == ~T2_E~0); 12815#L962-1 assume !(1 == ~T3_E~0); 12620#L967-1 assume !(1 == ~T4_E~0); 12621#L972-1 assume !(1 == ~T5_E~0); 12872#L977-1 assume !(1 == ~T6_E~0); 12873#L982-1 assume !(1 == ~T7_E~0); 12237#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12238#L992-1 assume !(1 == ~E_M~0); 12247#L997-1 assume !(1 == ~E_1~0); 12582#L1002-1 assume !(1 == ~E_2~0); 12570#L1007-1 assume !(1 == ~E_3~0); 11990#L1012-1 assume !(1 == ~E_4~0); 11991#L1017-1 assume !(1 == ~E_5~0); 12571#L1022-1 assume !(1 == ~E_6~0); 12572#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12594#L1032-1 assume !(1 == ~E_8~0); 12719#L1037-1 assume { :end_inline_reset_delta_events } true; 12720#L1303-2 [2022-11-16 11:30:49,919 INFO L750 eck$LassoCheckResult]: Loop: 12720#L1303-2 assume !false; 12810#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12001#L829 assume !false; 12764#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12379#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12307#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12710#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12688#L712 assume !(0 != eval_~tmp~0#1); 12689#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12025#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12026#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12691#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12692#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12958#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12932#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12515#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12516#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12583#L884-3 assume !(0 == ~T7_E~0); 12564#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12208#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12209#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12241#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12242#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12182#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12183#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12230#L924-3 assume !(0 == ~E_6~0); 12772#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12674#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12675#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12801#L418-30 assume 1 == ~m_pc~0; 12072#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12073#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12527#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12528#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12271#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12272#L437-30 assume !(1 == ~t1_pc~0); 12397#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 12602#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12603#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12790#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12949#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12363#L456-30 assume 1 == ~t2_pc~0; 12364#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12761#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12762#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12156#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12157#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12490#L475-30 assume 1 == ~t3_pc~0; 12865#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12039#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12690#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12935#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12381#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12382#L494-30 assume 1 == ~t4_pc~0; 12375#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11974#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11975#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12906#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 12885#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12886#L513-30 assume 1 == ~t5_pc~0; 12962#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12496#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12560#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12786#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12787#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12506#L532-30 assume !(1 == ~t6_pc~0); 12507#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 12112#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12113#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12134#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12196#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12197#L551-30 assume 1 == ~t7_pc~0; 12249#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12309#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12181#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11992#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11993#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12360#L570-30 assume 1 == ~t8_pc~0; 12851#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12248#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12200#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12054#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12055#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12421#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12456#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12913#L957-3 assume !(1 == ~T2_E~0); 12914#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12831#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12832#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12740#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12741#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12963#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12409#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12410#L997-3 assume !(1 == ~E_1~0); 12405#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12406#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12221#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12222#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12318#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12536#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12023#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12024#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12261#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12262#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12166#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12167#L1322 assume !(0 == start_simulation_~tmp~3#1); 12435#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12102#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12103#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12915#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 12007#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12008#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12743#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12875#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 12720#L1303-2 [2022-11-16 11:30:49,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:49,920 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2022-11-16 11:30:49,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:49,920 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441815401] [2022-11-16 11:30:49,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:49,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:49,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:49,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:49,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [441815401] [2022-11-16 11:30:49,959 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [441815401] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:49,959 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:49,959 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:49,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869030436] [2022-11-16 11:30:49,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:49,959 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:49,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:49,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1524153841, now seen corresponding path program 1 times [2022-11-16 11:30:49,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:49,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284633215] [2022-11-16 11:30:49,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:49,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:49,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:50,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:50,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:50,019 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284633215] [2022-11-16 11:30:50,019 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284633215] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:50,019 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:50,019 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:50,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2012392851] [2022-11-16 11:30:50,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:50,020 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:50,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:50,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:50,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:50,021 INFO L87 Difference]: Start difference. First operand 993 states and 1476 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:50,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:50,042 INFO L93 Difference]: Finished difference Result 993 states and 1475 transitions. [2022-11-16 11:30:50,042 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1475 transitions. [2022-11-16 11:30:50,048 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:50,054 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1475 transitions. [2022-11-16 11:30:50,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-11-16 11:30:50,055 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-11-16 11:30:50,055 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1475 transitions. [2022-11-16 11:30:50,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:50,056 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1475 transitions. [2022-11-16 11:30:50,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1475 transitions. [2022-11-16 11:30:50,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-11-16 11:30:50,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.48539778449144) internal successors, (1475), 992 states have internal predecessors, (1475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:50,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1475 transitions. [2022-11-16 11:30:50,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1475 transitions. [2022-11-16 11:30:50,074 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:50,076 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1475 transitions. [2022-11-16 11:30:50,077 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 11:30:50,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1475 transitions. [2022-11-16 11:30:50,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:50,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:50,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:50,084 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:50,084 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:50,084 INFO L748 eck$LassoCheckResult]: Stem: 14724#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 14725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14011#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14012#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14049#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 14675#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14676#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14297#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14298#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14238#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14239#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14482#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14455#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14456#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14728#L854 assume !(0 == ~M_E~0); 14542#L854-2 assume !(0 == ~T1_E~0); 14543#L859-1 assume !(0 == ~T2_E~0); 14113#L864-1 assume !(0 == ~T3_E~0); 14114#L869-1 assume !(0 == ~T4_E~0); 14227#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14927#L879-1 assume !(0 == ~T6_E~0); 14530#L884-1 assume !(0 == ~T7_E~0); 13981#L889-1 assume !(0 == ~T8_E~0); 13982#L894-1 assume !(0 == ~E_M~0); 14312#L899-1 assume !(0 == ~E_1~0); 14735#L904-1 assume !(0 == ~E_2~0); 14471#L909-1 assume !(0 == ~E_3~0); 14472#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14666#L919-1 assume !(0 == ~E_5~0); 14392#L924-1 assume !(0 == ~E_6~0); 14210#L929-1 assume !(0 == ~E_7~0); 14211#L934-1 assume !(0 == ~E_8~0); 14452#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13999#L418 assume !(1 == ~m_pc~0); 13971#L418-2 is_master_triggered_~__retres1~0#1 := 0; 13970#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14886#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14835#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14760#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14761#L437 assume 1 == ~t1_pc~0; 14944#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14843#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14796#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14347#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 14348#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14826#L456 assume !(1 == ~t2_pc~0); 14263#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14262#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14601#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14602#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 14577#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14107#L475 assume 1 == ~t3_pc~0; 14108#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14168#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14169#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14922#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 14351#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14352#L494 assume !(1 == ~t4_pc~0); 14387#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14388#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14592#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14593#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 14689#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14163#L513 assume 1 == ~t5_pc~0; 14164#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14389#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14426#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14124#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 14125#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14076#L532 assume !(1 == ~t6_pc~0); 14077#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14228#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14507#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14586#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 14317#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14318#L551 assume 1 == ~t7_pc~0; 14864#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14693#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14694#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14875#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 14953#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14491#L570 assume 1 == ~t8_pc~0; 14492#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14603#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14737#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14597#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 14101#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14102#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 14050#L952-2 assume !(1 == ~T1_E~0); 14051#L957-1 assume !(1 == ~T2_E~0); 14808#L962-1 assume !(1 == ~T3_E~0); 14613#L967-1 assume !(1 == ~T4_E~0); 14614#L972-1 assume !(1 == ~T5_E~0); 14865#L977-1 assume !(1 == ~T6_E~0); 14866#L982-1 assume !(1 == ~T7_E~0); 14230#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14231#L992-1 assume !(1 == ~E_M~0); 14240#L997-1 assume !(1 == ~E_1~0); 14575#L1002-1 assume !(1 == ~E_2~0); 14563#L1007-1 assume !(1 == ~E_3~0); 13983#L1012-1 assume !(1 == ~E_4~0); 13984#L1017-1 assume !(1 == ~E_5~0); 14564#L1022-1 assume !(1 == ~E_6~0); 14565#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14587#L1032-1 assume !(1 == ~E_8~0); 14712#L1037-1 assume { :end_inline_reset_delta_events } true; 14713#L1303-2 [2022-11-16 11:30:50,085 INFO L750 eck$LassoCheckResult]: Loop: 14713#L1303-2 assume !false; 14803#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13994#L829 assume !false; 14757#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14372#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14300#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14703#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14681#L712 assume !(0 != eval_~tmp~0#1); 14682#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14018#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14019#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14684#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14685#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14951#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14925#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14508#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14509#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14576#L884-3 assume !(0 == ~T7_E~0); 14557#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14201#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14202#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14234#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14235#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14175#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14176#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14223#L924-3 assume !(0 == ~E_6~0); 14765#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14667#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14668#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14794#L418-30 assume 1 == ~m_pc~0; 14065#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14066#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14520#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14521#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14264#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14265#L437-30 assume !(1 == ~t1_pc~0); 14390#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 14595#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14596#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14783#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14942#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14356#L456-30 assume 1 == ~t2_pc~0; 14357#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14754#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14755#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14149#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14150#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14483#L475-30 assume 1 == ~t3_pc~0; 14858#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14032#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14683#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14928#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14374#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14375#L494-30 assume 1 == ~t4_pc~0; 14368#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13967#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13968#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14899#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 14878#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14879#L513-30 assume !(1 == ~t5_pc~0); 14488#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 14489#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14553#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14779#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14780#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14499#L532-30 assume !(1 == ~t6_pc~0); 14500#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 14105#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14106#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14127#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14189#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14190#L551-30 assume 1 == ~t7_pc~0; 14242#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14302#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14174#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13985#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13986#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14353#L570-30 assume !(1 == ~t8_pc~0); 14674#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 14241#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14193#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14047#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14048#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14414#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14449#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14906#L957-3 assume !(1 == ~T2_E~0); 14907#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14824#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14825#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14733#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14734#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14956#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14402#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14403#L997-3 assume !(1 == ~E_1~0); 14398#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14399#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14214#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14215#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14311#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14529#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14016#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14017#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14254#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14255#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14159#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14160#L1322 assume !(0 == start_simulation_~tmp~3#1); 14428#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14095#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14096#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14908#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 14000#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14001#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14736#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14868#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 14713#L1303-2 [2022-11-16 11:30:50,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:50,085 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2022-11-16 11:30:50,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:50,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555042104] [2022-11-16 11:30:50,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:50,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:50,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:50,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:50,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:50,158 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555042104] [2022-11-16 11:30:50,158 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555042104] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:50,158 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:50,158 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:50,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55999411] [2022-11-16 11:30:50,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:50,159 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:50,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:50,160 INFO L85 PathProgramCache]: Analyzing trace with hash -1507022511, now seen corresponding path program 1 times [2022-11-16 11:30:50,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:50,160 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797391937] [2022-11-16 11:30:50,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:50,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:50,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:50,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:50,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:50,218 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797391937] [2022-11-16 11:30:50,218 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797391937] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:50,219 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:50,219 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:50,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768079566] [2022-11-16 11:30:50,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:50,219 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:50,220 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:50,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:50,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:50,220 INFO L87 Difference]: Start difference. First operand 993 states and 1475 transitions. cyclomatic complexity: 483 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:50,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:50,243 INFO L93 Difference]: Finished difference Result 993 states and 1474 transitions. [2022-11-16 11:30:50,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1474 transitions. [2022-11-16 11:30:50,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:50,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1474 transitions. [2022-11-16 11:30:50,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-11-16 11:30:50,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-11-16 11:30:50,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1474 transitions. [2022-11-16 11:30:50,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:50,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 993 states and 1474 transitions. [2022-11-16 11:30:50,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1474 transitions. [2022-11-16 11:30:50,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-11-16 11:30:50,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4843907351460222) internal successors, (1474), 992 states have internal predecessors, (1474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:50,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1474 transitions. [2022-11-16 11:30:50,275 INFO L240 hiAutomatonCegarLoop]: Abstraction has 993 states and 1474 transitions. [2022-11-16 11:30:50,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:50,276 INFO L428 stractBuchiCegarLoop]: Abstraction has 993 states and 1474 transitions. [2022-11-16 11:30:50,276 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 11:30:50,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1474 transitions. [2022-11-16 11:30:50,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-11-16 11:30:50,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:50,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:50,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:50,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:50,283 INFO L748 eck$LassoCheckResult]: Stem: 16717#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 16718#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 16004#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16005#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16042#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 16668#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16669#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16290#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16291#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16231#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16232#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16475#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16448#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16449#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16721#L854 assume !(0 == ~M_E~0); 16535#L854-2 assume !(0 == ~T1_E~0); 16536#L859-1 assume !(0 == ~T2_E~0); 16106#L864-1 assume !(0 == ~T3_E~0); 16107#L869-1 assume !(0 == ~T4_E~0); 16220#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16920#L879-1 assume !(0 == ~T6_E~0); 16523#L884-1 assume !(0 == ~T7_E~0); 15974#L889-1 assume !(0 == ~T8_E~0); 15975#L894-1 assume !(0 == ~E_M~0); 16305#L899-1 assume !(0 == ~E_1~0); 16728#L904-1 assume !(0 == ~E_2~0); 16464#L909-1 assume !(0 == ~E_3~0); 16465#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16659#L919-1 assume !(0 == ~E_5~0); 16385#L924-1 assume !(0 == ~E_6~0); 16203#L929-1 assume !(0 == ~E_7~0); 16204#L934-1 assume !(0 == ~E_8~0); 16445#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15992#L418 assume !(1 == ~m_pc~0); 15964#L418-2 is_master_triggered_~__retres1~0#1 := 0; 15963#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16879#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16828#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16753#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16754#L437 assume 1 == ~t1_pc~0; 16937#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16836#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16789#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16340#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 16341#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16819#L456 assume !(1 == ~t2_pc~0); 16256#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16255#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16594#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16595#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 16570#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16100#L475 assume 1 == ~t3_pc~0; 16101#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16161#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16162#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16915#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 16344#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16345#L494 assume !(1 == ~t4_pc~0); 16380#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16381#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16585#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16586#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 16682#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16156#L513 assume 1 == ~t5_pc~0; 16157#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16382#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16419#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16117#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 16118#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16069#L532 assume !(1 == ~t6_pc~0); 16070#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16221#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16500#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16579#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 16310#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16311#L551 assume 1 == ~t7_pc~0; 16857#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16686#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16687#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16868#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 16946#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16484#L570 assume 1 == ~t8_pc~0; 16485#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16596#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16730#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16590#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 16094#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16095#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 16043#L952-2 assume !(1 == ~T1_E~0); 16044#L957-1 assume !(1 == ~T2_E~0); 16801#L962-1 assume !(1 == ~T3_E~0); 16606#L967-1 assume !(1 == ~T4_E~0); 16607#L972-1 assume !(1 == ~T5_E~0); 16858#L977-1 assume !(1 == ~T6_E~0); 16859#L982-1 assume !(1 == ~T7_E~0); 16223#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16224#L992-1 assume !(1 == ~E_M~0); 16233#L997-1 assume !(1 == ~E_1~0); 16568#L1002-1 assume !(1 == ~E_2~0); 16556#L1007-1 assume !(1 == ~E_3~0); 15976#L1012-1 assume !(1 == ~E_4~0); 15977#L1017-1 assume !(1 == ~E_5~0); 16557#L1022-1 assume !(1 == ~E_6~0); 16558#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16580#L1032-1 assume !(1 == ~E_8~0); 16705#L1037-1 assume { :end_inline_reset_delta_events } true; 16706#L1303-2 [2022-11-16 11:30:50,284 INFO L750 eck$LassoCheckResult]: Loop: 16706#L1303-2 assume !false; 16796#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15987#L829 assume !false; 16750#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16365#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16293#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16696#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16674#L712 assume !(0 != eval_~tmp~0#1); 16675#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16011#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16012#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16677#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16678#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16944#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16918#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16501#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16502#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16569#L884-3 assume !(0 == ~T7_E~0); 16550#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16194#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16195#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16227#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16228#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16168#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16169#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16216#L924-3 assume !(0 == ~E_6~0); 16758#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16660#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16661#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16787#L418-30 assume 1 == ~m_pc~0; 16058#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16059#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16513#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16514#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16257#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16258#L437-30 assume 1 == ~t1_pc~0; 16384#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16588#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16589#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16776#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16935#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16349#L456-30 assume 1 == ~t2_pc~0; 16350#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16747#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16748#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16142#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16143#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16476#L475-30 assume 1 == ~t3_pc~0; 16851#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16025#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16676#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16921#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16367#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16368#L494-30 assume 1 == ~t4_pc~0; 16361#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15960#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15961#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16892#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 16871#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16872#L513-30 assume !(1 == ~t5_pc~0); 16481#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 16482#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16546#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16772#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16773#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16492#L532-30 assume !(1 == ~t6_pc~0); 16493#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 16098#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16099#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16120#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16182#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16183#L551-30 assume 1 == ~t7_pc~0; 16235#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16295#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16167#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15978#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15979#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16346#L570-30 assume 1 == ~t8_pc~0; 16837#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16234#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16186#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16040#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16041#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16407#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16442#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16899#L957-3 assume !(1 == ~T2_E~0); 16900#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16817#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16818#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16726#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16727#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16949#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16395#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16396#L997-3 assume !(1 == ~E_1~0); 16391#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16392#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16207#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16208#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16304#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16522#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16009#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16010#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16247#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16248#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16152#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 16153#L1322 assume !(0 == start_simulation_~tmp~3#1); 16421#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16088#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16089#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16901#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 15993#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15994#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16729#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16861#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 16706#L1303-2 [2022-11-16 11:30:50,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:50,285 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2022-11-16 11:30:50,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:50,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454647109] [2022-11-16 11:30:50,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:50,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:50,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:50,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:50,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:50,359 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454647109] [2022-11-16 11:30:50,359 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454647109] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:50,359 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:50,359 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:50,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350911625] [2022-11-16 11:30:50,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:50,360 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:50,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:50,361 INFO L85 PathProgramCache]: Analyzing trace with hash -1695255281, now seen corresponding path program 1 times [2022-11-16 11:30:50,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:50,361 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237946546] [2022-11-16 11:30:50,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:50,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:50,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:50,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:50,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:50,410 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237946546] [2022-11-16 11:30:50,410 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1237946546] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:50,410 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:50,411 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:50,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551792639] [2022-11-16 11:30:50,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:50,411 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:50,411 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:50,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:30:50,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:30:50,412 INFO L87 Difference]: Start difference. First operand 993 states and 1474 transitions. cyclomatic complexity: 482 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:50,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:50,521 INFO L93 Difference]: Finished difference Result 1806 states and 2671 transitions. [2022-11-16 11:30:50,521 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1806 states and 2671 transitions. [2022-11-16 11:30:50,534 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1673 [2022-11-16 11:30:50,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1806 states to 1806 states and 2671 transitions. [2022-11-16 11:30:50,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1806 [2022-11-16 11:30:50,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1806 [2022-11-16 11:30:50,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1806 states and 2671 transitions. [2022-11-16 11:30:50,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:50,548 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2022-11-16 11:30:50,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1806 states and 2671 transitions. [2022-11-16 11:30:50,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1806 to 1806. [2022-11-16 11:30:50,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1806 states, 1806 states have (on average 1.4789590254706533) internal successors, (2671), 1805 states have internal predecessors, (2671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:50,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1806 states to 1806 states and 2671 transitions. [2022-11-16 11:30:50,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2022-11-16 11:30:50,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:30:50,587 INFO L428 stractBuchiCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2022-11-16 11:30:50,587 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 11:30:50,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1806 states and 2671 transitions. [2022-11-16 11:30:50,616 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1673 [2022-11-16 11:30:50,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:50,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:50,619 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:50,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:50,620 INFO L748 eck$LassoCheckResult]: Stem: 19540#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 19541#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 18813#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18814#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18851#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 19488#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19489#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19101#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19102#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19041#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19042#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19291#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19264#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19265#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19545#L854 assume !(0 == ~M_E~0); 19352#L854-2 assume !(0 == ~T1_E~0); 19353#L859-1 assume !(0 == ~T2_E~0); 18915#L864-1 assume !(0 == ~T3_E~0); 18916#L869-1 assume !(0 == ~T4_E~0); 19030#L874-1 assume !(0 == ~T5_E~0); 19776#L879-1 assume !(0 == ~T6_E~0); 19340#L884-1 assume !(0 == ~T7_E~0); 18783#L889-1 assume !(0 == ~T8_E~0); 18784#L894-1 assume !(0 == ~E_M~0); 19116#L899-1 assume !(0 == ~E_1~0); 19552#L904-1 assume !(0 == ~E_2~0); 19280#L909-1 assume !(0 == ~E_3~0); 19281#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19479#L919-1 assume !(0 == ~E_5~0); 19198#L924-1 assume !(0 == ~E_6~0); 19013#L929-1 assume !(0 == ~E_7~0); 19014#L934-1 assume !(0 == ~E_8~0); 19261#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18801#L418 assume !(1 == ~m_pc~0); 18773#L418-2 is_master_triggered_~__retres1~0#1 := 0; 18772#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19723#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19662#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19578#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19579#L437 assume 1 == ~t1_pc~0; 19799#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19672#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19619#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19151#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 19152#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19653#L456 assume !(1 == ~t2_pc~0); 19067#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19066#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19413#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19414#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 19389#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18909#L475 assume 1 == ~t3_pc~0; 18910#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18971#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18972#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19768#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 19155#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19156#L494 assume !(1 == ~t4_pc~0); 19193#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19194#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19404#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19405#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 19502#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18966#L513 assume 1 == ~t5_pc~0; 18967#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19195#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19234#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18926#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 18927#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18878#L532 assume !(1 == ~t6_pc~0); 18879#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19031#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19316#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19398#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 19121#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19122#L551 assume 1 == ~t7_pc~0; 19696#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19507#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19508#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19711#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 19811#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19300#L570 assume 1 == ~t8_pc~0; 19301#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19415#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19554#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19409#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 18903#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18904#L952 assume !(1 == ~M_E~0); 19676#L952-2 assume !(1 == ~T1_E~0); 19944#L957-1 assume !(1 == ~T2_E~0); 19942#L962-1 assume !(1 == ~T3_E~0); 19940#L967-1 assume !(1 == ~T4_E~0); 19939#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19697#L977-1 assume !(1 == ~T6_E~0); 19698#L982-1 assume !(1 == ~T7_E~0); 19033#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19034#L992-1 assume !(1 == ~E_M~0); 19043#L997-1 assume !(1 == ~E_1~0); 19387#L1002-1 assume !(1 == ~E_2~0); 19375#L1007-1 assume !(1 == ~E_3~0); 18785#L1012-1 assume !(1 == ~E_4~0); 18786#L1017-1 assume !(1 == ~E_5~0); 19851#L1022-1 assume !(1 == ~E_6~0); 19849#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19847#L1032-1 assume !(1 == ~E_8~0); 19846#L1037-1 assume { :end_inline_reset_delta_events } true; 19628#L1303-2 [2022-11-16 11:30:50,620 INFO L750 eck$LassoCheckResult]: Loop: 19628#L1303-2 assume !false; 19629#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19837#L829 assume !false; 19575#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19178#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19104#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19827#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19825#L712 assume !(0 != eval_~tmp~0#1); 19626#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18820#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18821#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19823#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20236#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20235#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20234#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20233#L874-3 assume !(0 == ~T5_E~0); 20232#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20231#L884-3 assume !(0 == ~T7_E~0); 20230#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20229#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20228#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20227#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20226#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20225#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20224#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20223#L924-3 assume !(0 == ~E_6~0); 20222#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20221#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20220#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20219#L418-30 assume 1 == ~m_pc~0; 20217#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20216#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20215#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20214#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20213#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20212#L437-30 assume !(1 == ~t1_pc~0); 20210#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 20209#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20208#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20207#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20206#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20205#L456-30 assume 1 == ~t2_pc~0; 20203#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20202#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20201#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20200#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20199#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20198#L475-30 assume !(1 == ~t3_pc~0); 20196#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 20195#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20194#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20193#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20192#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20191#L494-30 assume 1 == ~t4_pc~0; 20189#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20188#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20187#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20186#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 20185#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20184#L513-30 assume 1 == ~t5_pc~0; 20182#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20181#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20180#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20179#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20178#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20177#L532-30 assume 1 == ~t6_pc~0; 20176#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20174#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20173#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20172#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20171#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20170#L551-30 assume 1 == ~t7_pc~0; 20168#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20167#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20166#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20165#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20164#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20163#L570-30 assume !(1 == ~t8_pc~0); 20160#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 20157#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20155#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20153#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20151#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20149#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19257#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20145#L957-3 assume !(1 == ~T2_E~0); 20143#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20141#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20139#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19769#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20136#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20133#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20131#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20129#L997-3 assume !(1 == ~E_1~0); 20127#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20125#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20123#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20120#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20118#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20116#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20114#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20113#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20104#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20103#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20102#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20101#L1322 assume !(0 == start_simulation_~tmp~3#1); 19566#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20099#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19749#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19750#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 20089#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20088#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19773#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19774#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 19628#L1303-2 [2022-11-16 11:30:50,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:50,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2022-11-16 11:30:50,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:50,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873750960] [2022-11-16 11:30:50,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:50,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:50,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:50,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:50,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:50,692 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [873750960] [2022-11-16 11:30:50,693 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [873750960] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:50,694 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:50,694 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:50,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1635872150] [2022-11-16 11:30:50,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:50,695 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:50,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:50,696 INFO L85 PathProgramCache]: Analyzing trace with hash 1301437970, now seen corresponding path program 1 times [2022-11-16 11:30:50,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:50,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510842870] [2022-11-16 11:30:50,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:50,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:50,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:50,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:50,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:50,746 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510842870] [2022-11-16 11:30:50,746 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510842870] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:50,746 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:50,747 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:50,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896969412] [2022-11-16 11:30:50,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:50,747 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:50,748 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:50,748 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:30:50,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:30:50,749 INFO L87 Difference]: Start difference. First operand 1806 states and 2671 transitions. cyclomatic complexity: 867 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:50,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:50,921 INFO L93 Difference]: Finished difference Result 3286 states and 4848 transitions. [2022-11-16 11:30:50,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3286 states and 4848 transitions. [2022-11-16 11:30:50,942 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3133 [2022-11-16 11:30:50,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3286 states to 3286 states and 4848 transitions. [2022-11-16 11:30:50,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3286 [2022-11-16 11:30:50,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3286 [2022-11-16 11:30:50,965 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3286 states and 4848 transitions. [2022-11-16 11:30:50,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:50,969 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3286 states and 4848 transitions. [2022-11-16 11:30:50,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3286 states and 4848 transitions. [2022-11-16 11:30:51,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3286 to 3284. [2022-11-16 11:30:51,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3284 states, 3284 states have (on average 1.4756394640682096) internal successors, (4846), 3283 states have internal predecessors, (4846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:51,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3284 states to 3284 states and 4846 transitions. [2022-11-16 11:30:51,049 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3284 states and 4846 transitions. [2022-11-16 11:30:51,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:30:51,050 INFO L428 stractBuchiCegarLoop]: Abstraction has 3284 states and 4846 transitions. [2022-11-16 11:30:51,050 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 11:30:51,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3284 states and 4846 transitions. [2022-11-16 11:30:51,065 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3133 [2022-11-16 11:30:51,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:51,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:51,067 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:51,067 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:51,067 INFO L748 eck$LassoCheckResult]: Stem: 24659#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 24660#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 23917#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23918#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23956#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 24606#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24607#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24207#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24208#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24147#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24148#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24402#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24375#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24376#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24663#L854 assume !(0 == ~M_E~0); 24464#L854-2 assume !(0 == ~T1_E~0); 24465#L859-1 assume !(0 == ~T2_E~0); 24020#L864-1 assume !(0 == ~T3_E~0); 24021#L869-1 assume !(0 == ~T4_E~0); 24136#L874-1 assume !(0 == ~T5_E~0); 24917#L879-1 assume !(0 == ~T6_E~0); 24452#L884-1 assume !(0 == ~T7_E~0); 23885#L889-1 assume !(0 == ~T8_E~0); 23886#L894-1 assume !(0 == ~E_M~0); 24224#L899-1 assume !(0 == ~E_1~0); 24670#L904-1 assume !(0 == ~E_2~0); 24391#L909-1 assume !(0 == ~E_3~0); 24392#L914-1 assume !(0 == ~E_4~0); 24596#L919-1 assume !(0 == ~E_5~0); 24309#L924-1 assume !(0 == ~E_6~0); 24118#L929-1 assume !(0 == ~E_7~0); 24119#L934-1 assume !(0 == ~E_8~0); 24372#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23905#L418 assume !(1 == ~m_pc~0); 23875#L418-2 is_master_triggered_~__retres1~0#1 := 0; 23874#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24860#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24790#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24697#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24698#L437 assume 1 == ~t1_pc~0; 24948#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24798#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24741#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24260#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 24261#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24780#L456 assume !(1 == ~t2_pc~0); 24173#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24172#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24528#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24529#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 24503#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24014#L475 assume 1 == ~t3_pc~0; 24015#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24076#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24077#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24908#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 24264#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24265#L494 assume !(1 == ~t4_pc~0); 24304#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24305#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24519#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24520#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 24620#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24070#L513 assume 1 == ~t5_pc~0; 24071#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24306#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24345#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24031#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 24032#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23983#L532 assume !(1 == ~t6_pc~0); 23984#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24137#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24429#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24513#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 24230#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24231#L551 assume 1 == ~t7_pc~0; 24824#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24624#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24625#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24841#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 24968#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24413#L570 assume 1 == ~t8_pc~0; 24414#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24530#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24672#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24524#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 24008#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24009#L952 assume !(1 == ~M_E~0); 24802#L952-2 assume !(1 == ~T1_E~0); 24760#L957-1 assume !(1 == ~T2_E~0); 24761#L962-1 assume !(1 == ~T3_E~0); 24542#L967-1 assume !(1 == ~T4_E~0); 24543#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25157#L977-1 assume !(1 == ~T6_E~0); 25155#L982-1 assume !(1 == ~T7_E~0); 25153#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24149#L992-1 assume !(1 == ~E_M~0); 24150#L997-1 assume !(1 == ~E_1~0); 25100#L1002-1 assume !(1 == ~E_2~0); 24485#L1007-1 assume !(1 == ~E_3~0); 24486#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25065#L1017-1 assume !(1 == ~E_5~0); 25042#L1022-1 assume !(1 == ~E_6~0); 25027#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25025#L1032-1 assume !(1 == ~E_8~0); 25015#L1037-1 assume { :end_inline_reset_delta_events } true; 25008#L1303-2 [2022-11-16 11:30:51,068 INFO L750 eck$LassoCheckResult]: Loop: 25008#L1303-2 assume !false; 25003#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25001#L829 assume !false; 25000#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24995#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 24990#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24989#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 24987#L712 assume !(0 != eval_~tmp~0#1); 24986#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24985#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24983#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24984#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25660#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25658#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25656#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25654#L874-3 assume !(0 == ~T5_E~0); 25652#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25650#L884-3 assume !(0 == ~T7_E~0); 25648#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25646#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25644#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25642#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25640#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25638#L914-3 assume !(0 == ~E_4~0); 25636#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25634#L924-3 assume !(0 == ~E_6~0); 25632#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25630#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25628#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25626#L418-30 assume 1 == ~m_pc~0; 25623#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25620#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25618#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25616#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25614#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25612#L437-30 assume !(1 == ~t1_pc~0); 25609#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 25606#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25604#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25602#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25600#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25598#L456-30 assume 1 == ~t2_pc~0; 25595#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25592#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25590#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25588#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25586#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25584#L475-30 assume !(1 == ~t3_pc~0); 25581#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 25578#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25576#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25574#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25572#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25570#L494-30 assume !(1 == ~t4_pc~0); 25568#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 25564#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25562#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25560#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 25558#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25556#L513-30 assume 1 == ~t5_pc~0; 25553#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25550#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25548#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25546#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25544#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25542#L532-30 assume !(1 == ~t6_pc~0); 25539#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 25536#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25534#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25532#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25530#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25528#L551-30 assume 1 == ~t7_pc~0; 25525#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25522#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25520#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25518#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25515#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25511#L570-30 assume !(1 == ~t8_pc~0); 25507#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 25503#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25500#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25497#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25494#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25490#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24368#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25485#L957-3 assume !(1 == ~T2_E~0); 25482#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25479#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25476#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25472#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25470#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25468#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25466#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25464#L997-3 assume !(1 == ~E_1~0); 25462#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25452#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25447#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25439#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25434#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25429#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25137#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25135#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25109#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25107#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25106#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25104#L1322 assume !(0 == start_simulation_~tmp~3#1); 24684#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25063#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25054#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25041#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 25039#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25026#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25024#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25014#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 25008#L1303-2 [2022-11-16 11:30:51,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:51,069 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2022-11-16 11:30:51,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:51,069 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275786686] [2022-11-16 11:30:51,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:51,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:51,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:51,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:51,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:51,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275786686] [2022-11-16 11:30:51,167 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275786686] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:51,167 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:51,167 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:30:51,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1433768615] [2022-11-16 11:30:51,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:51,168 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:51,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:51,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1857591446, now seen corresponding path program 1 times [2022-11-16 11:30:51,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:51,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572244113] [2022-11-16 11:30:51,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:51,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:51,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:51,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:51,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:51,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572244113] [2022-11-16 11:30:51,230 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [572244113] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:51,230 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:51,230 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:51,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22067248] [2022-11-16 11:30:51,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:51,231 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:51,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:51,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:30:51,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:30:51,232 INFO L87 Difference]: Start difference. First operand 3284 states and 4846 transitions. cyclomatic complexity: 1566 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:51,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:51,537 INFO L93 Difference]: Finished difference Result 9426 states and 13840 transitions. [2022-11-16 11:30:51,537 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9426 states and 13840 transitions. [2022-11-16 11:30:51,595 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9048 [2022-11-16 11:30:51,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9426 states to 9426 states and 13840 transitions. [2022-11-16 11:30:51,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9426 [2022-11-16 11:30:51,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9426 [2022-11-16 11:30:51,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9426 states and 13840 transitions. [2022-11-16 11:30:51,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:51,662 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9426 states and 13840 transitions. [2022-11-16 11:30:51,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9426 states and 13840 transitions. [2022-11-16 11:30:51,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9426 to 3404. [2022-11-16 11:30:51,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3404 states, 3404 states have (on average 1.4588719153936545) internal successors, (4966), 3403 states have internal predecessors, (4966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:51,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3404 states to 3404 states and 4966 transitions. [2022-11-16 11:30:51,837 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3404 states and 4966 transitions. [2022-11-16 11:30:51,837 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 11:30:51,838 INFO L428 stractBuchiCegarLoop]: Abstraction has 3404 states and 4966 transitions. [2022-11-16 11:30:51,838 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 11:30:51,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3404 states and 4966 transitions. [2022-11-16 11:30:51,856 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3250 [2022-11-16 11:30:51,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:51,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:51,859 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:51,859 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:51,859 INFO L748 eck$LassoCheckResult]: Stem: 37380#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 37381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 36639#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36640#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36677#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 37328#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37329#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36928#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36929#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36868#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36869#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37120#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37093#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37094#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37385#L854 assume !(0 == ~M_E~0); 37183#L854-2 assume !(0 == ~T1_E~0); 37184#L859-1 assume !(0 == ~T2_E~0); 36741#L864-1 assume !(0 == ~T3_E~0); 36742#L869-1 assume !(0 == ~T4_E~0); 36856#L874-1 assume !(0 == ~T5_E~0); 37648#L879-1 assume !(0 == ~T6_E~0); 37170#L884-1 assume !(0 == ~T7_E~0); 36608#L889-1 assume !(0 == ~T8_E~0); 36609#L894-1 assume !(0 == ~E_M~0); 36945#L899-1 assume !(0 == ~E_1~0); 37394#L904-1 assume !(0 == ~E_2~0); 37110#L909-1 assume !(0 == ~E_3~0); 37111#L914-1 assume !(0 == ~E_4~0); 37318#L919-1 assume !(0 == ~E_5~0); 37027#L924-1 assume !(0 == ~E_6~0); 36843#L929-1 assume !(0 == ~E_7~0); 36844#L934-1 assume !(0 == ~E_8~0); 37090#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36627#L418 assume !(1 == ~m_pc~0); 36600#L418-2 is_master_triggered_~__retres1~0#1 := 0; 37593#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37594#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37515#L1061 assume !(0 != activate_threads_~tmp~1#1); 37424#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37425#L437 assume 1 == ~t1_pc~0; 37676#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37525#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37469#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36978#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 36979#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37506#L456 assume !(1 == ~t2_pc~0); 36893#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36892#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37245#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37246#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 37221#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36735#L475 assume 1 == ~t3_pc~0; 36736#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36798#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36799#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37637#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 36982#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36983#L494 assume !(1 == ~t4_pc~0); 37022#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37023#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37236#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37237#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 37342#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36791#L513 assume 1 == ~t5_pc~0; 36792#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37024#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37063#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36752#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 36753#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36704#L532 assume !(1 == ~t6_pc~0); 36705#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36857#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37146#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37230#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 36948#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36949#L551 assume 1 == ~t7_pc~0; 37555#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37346#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37347#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37577#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 37699#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37130#L570 assume 1 == ~t8_pc~0; 37131#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37248#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37395#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37243#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 36733#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36734#L952 assume !(1 == ~M_E~0); 37530#L952-2 assume !(1 == ~T1_E~0); 37487#L957-1 assume !(1 == ~T2_E~0); 37488#L962-1 assume !(1 == ~T3_E~0); 37263#L967-1 assume !(1 == ~T4_E~0); 37264#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37826#L977-1 assume !(1 == ~T6_E~0); 37704#L982-1 assume !(1 == ~T7_E~0); 37705#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36870#L992-1 assume !(1 == ~E_M~0); 36871#L997-1 assume !(1 == ~E_1~0); 37650#L1002-1 assume !(1 == ~E_2~0); 37651#L1007-1 assume !(1 == ~E_3~0); 37808#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 37806#L1017-1 assume !(1 == ~E_5~0); 37804#L1022-1 assume !(1 == ~E_6~0); 37800#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37798#L1032-1 assume !(1 == ~E_8~0); 37788#L1037-1 assume { :end_inline_reset_delta_events } true; 37781#L1303-2 [2022-11-16 11:30:51,860 INFO L750 eck$LassoCheckResult]: Loop: 37781#L1303-2 assume !false; 37776#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37774#L829 assume !false; 37773#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37768#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37763#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37762#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37760#L712 assume !(0 != eval_~tmp~0#1); 37759#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37758#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37756#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37757#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39083#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39081#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39079#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39077#L874-3 assume !(0 == ~T5_E~0); 39075#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39073#L884-3 assume !(0 == ~T7_E~0); 39071#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39069#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39067#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39065#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39063#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39061#L914-3 assume !(0 == ~E_4~0); 39059#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39057#L924-3 assume !(0 == ~E_6~0); 39055#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 39053#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39042#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39041#L418-30 assume !(1 == ~m_pc~0); 39040#L418-32 is_master_triggered_~__retres1~0#1 := 0; 39038#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39036#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39034#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 39031#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39029#L437-30 assume !(1 == ~t1_pc~0); 39025#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 39023#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39021#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39019#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39017#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39015#L456-30 assume 1 == ~t2_pc~0; 39011#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39009#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39007#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39005#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39003#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39001#L475-30 assume !(1 == ~t3_pc~0); 38997#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 38995#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38993#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38991#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38989#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38987#L494-30 assume 1 == ~t4_pc~0; 38983#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38981#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38979#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38977#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 38975#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38973#L513-30 assume 1 == ~t5_pc~0; 38969#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38967#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38965#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38963#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38961#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38959#L532-30 assume !(1 == ~t6_pc~0); 38955#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 38953#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38951#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38949#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38947#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38945#L551-30 assume 1 == ~t7_pc~0; 38941#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38939#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38937#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38935#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38933#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38931#L570-30 assume 1 == ~t8_pc~0; 38928#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38925#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38923#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38921#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38911#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38908#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37086#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38902#L957-3 assume !(1 == ~T2_E~0); 38899#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38896#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38792#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38787#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38785#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38783#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38781#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38779#L997-3 assume !(1 == ~E_1~0); 38777#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38774#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38772#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38769#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38767#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38765#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38763#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38760#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38750#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38748#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38746#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 38744#L1322 assume !(0 == start_simulation_~tmp~3#1); 37410#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38731#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38721#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38719#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 38717#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38715#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37797#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 37787#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 37781#L1303-2 [2022-11-16 11:30:51,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:51,861 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2022-11-16 11:30:51,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:51,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791939814] [2022-11-16 11:30:51,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:51,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:51,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:51,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:51,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:51,946 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [791939814] [2022-11-16 11:30:51,946 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [791939814] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:51,946 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:51,947 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:51,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027932502] [2022-11-16 11:30:51,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:51,947 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:51,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:51,948 INFO L85 PathProgramCache]: Analyzing trace with hash 1723741911, now seen corresponding path program 1 times [2022-11-16 11:30:51,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:51,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070259001] [2022-11-16 11:30:51,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:51,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:51,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:52,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:52,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:52,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070259001] [2022-11-16 11:30:52,009 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070259001] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:52,009 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:52,009 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:52,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1809987971] [2022-11-16 11:30:52,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:52,010 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:52,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:52,010 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:30:52,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:30:52,011 INFO L87 Difference]: Start difference. First operand 3404 states and 4966 transitions. cyclomatic complexity: 1566 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:52,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:52,277 INFO L93 Difference]: Finished difference Result 9349 states and 13457 transitions. [2022-11-16 11:30:52,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9349 states and 13457 transitions. [2022-11-16 11:30:52,327 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8920 [2022-11-16 11:30:52,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9349 states to 9349 states and 13457 transitions. [2022-11-16 11:30:52,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9349 [2022-11-16 11:30:52,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9349 [2022-11-16 11:30:52,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9349 states and 13457 transitions. [2022-11-16 11:30:52,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:52,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9349 states and 13457 transitions. [2022-11-16 11:30:52,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9349 states and 13457 transitions. [2022-11-16 11:30:52,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9349 to 8861. [2022-11-16 11:30:52,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8861 states, 8861 states have (on average 1.4432908249633225) internal successors, (12789), 8860 states have internal predecessors, (12789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:52,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8861 states to 8861 states and 12789 transitions. [2022-11-16 11:30:52,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8861 states and 12789 transitions. [2022-11-16 11:30:52,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:30:52,685 INFO L428 stractBuchiCegarLoop]: Abstraction has 8861 states and 12789 transitions. [2022-11-16 11:30:52,686 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 11:30:52,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8861 states and 12789 transitions. [2022-11-16 11:30:52,723 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8692 [2022-11-16 11:30:52,723 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:52,723 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:52,726 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:52,726 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:52,726 INFO L748 eck$LassoCheckResult]: Stem: 50194#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 50195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 49399#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49400#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49438#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 50125#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50126#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49692#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49693#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49630#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49631#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49889#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49861#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49862#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50198#L854 assume !(0 == ~M_E~0); 49961#L854-2 assume !(0 == ~T1_E~0); 49962#L859-1 assume !(0 == ~T2_E~0); 49502#L864-1 assume !(0 == ~T3_E~0); 49503#L869-1 assume !(0 == ~T4_E~0); 49619#L874-1 assume !(0 == ~T5_E~0); 50529#L879-1 assume !(0 == ~T6_E~0); 49948#L884-1 assume !(0 == ~T7_E~0); 49368#L889-1 assume !(0 == ~T8_E~0); 49369#L894-1 assume !(0 == ~E_M~0); 49709#L899-1 assume !(0 == ~E_1~0); 50206#L904-1 assume !(0 == ~E_2~0); 49876#L909-1 assume !(0 == ~E_3~0); 49877#L914-1 assume !(0 == ~E_4~0); 50113#L919-1 assume !(0 == ~E_5~0); 49792#L924-1 assume !(0 == ~E_6~0); 49601#L929-1 assume !(0 == ~E_7~0); 49602#L934-1 assume !(0 == ~E_8~0); 49858#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49386#L418 assume !(1 == ~m_pc~0); 49387#L418-2 is_master_triggered_~__retres1~0#1 := 0; 50440#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50441#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50344#L1061 assume !(0 != activate_threads_~tmp~1#1); 50236#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50237#L437 assume !(1 == ~t1_pc~0); 50510#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50355#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50288#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49744#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 49745#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50332#L456 assume !(1 == ~t2_pc~0); 49655#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49654#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50028#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50029#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 50002#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49496#L475 assume 1 == ~t3_pc~0; 49497#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49559#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49560#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50511#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 49748#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49749#L494 assume !(1 == ~t4_pc~0); 49788#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49789#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50017#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50018#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 50140#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49553#L513 assume 1 == ~t5_pc~0; 49554#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49790#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49832#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49513#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 49514#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49465#L532 assume !(1 == ~t6_pc~0); 49466#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49620#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49920#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50011#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 49715#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49716#L551 assume 1 == ~t7_pc~0; 50384#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50146#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50147#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50417#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 50603#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49903#L570 assume 1 == ~t8_pc~0; 49904#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50030#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50208#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50023#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 49490#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49491#L952 assume !(1 == ~M_E~0); 49439#L952-2 assume !(1 == ~T1_E~0); 49440#L957-1 assume !(1 == ~T2_E~0); 50312#L962-1 assume !(1 == ~T3_E~0); 50047#L967-1 assume !(1 == ~T4_E~0); 50048#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54182#L977-1 assume !(1 == ~T6_E~0); 57101#L982-1 assume !(1 == ~T7_E~0); 57100#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57099#L992-1 assume !(1 == ~E_M~0); 57098#L997-1 assume !(1 == ~E_1~0); 57097#L1002-1 assume !(1 == ~E_2~0); 57096#L1007-1 assume !(1 == ~E_3~0); 57095#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49371#L1017-1 assume !(1 == ~E_5~0); 49985#L1022-1 assume !(1 == ~E_6~0); 49986#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50012#L1032-1 assume !(1 == ~E_8~0); 50177#L1037-1 assume { :end_inline_reset_delta_events } true; 50178#L1303-2 [2022-11-16 11:30:52,727 INFO L750 eck$LassoCheckResult]: Loop: 50178#L1303-2 assume !false; 50303#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57075#L829 assume !false; 57074#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49773#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49695#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 50161#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50162#L712 assume !(0 != eval_~tmp~0#1); 57064#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57062#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57059#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 57060#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57055#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57056#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57051#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57052#L874-3 assume !(0 == ~T5_E~0); 57047#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 57048#L884-3 assume !(0 == ~T7_E~0); 57043#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57044#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57039#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57040#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57022#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57023#L914-3 assume !(0 == ~E_4~0); 57016#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57017#L924-3 assume !(0 == ~E_6~0); 57006#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57007#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50391#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50392#L418-30 assume !(1 == ~m_pc~0); 56953#L418-32 is_master_triggered_~__retres1~0#1 := 0; 56954#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56949#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56950#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 56945#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56946#L437-30 assume !(1 == ~t1_pc~0); 56941#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 56942#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56937#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56938#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56933#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56934#L456-30 assume !(1 == ~t2_pc~0); 56929#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 56928#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56923#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 56924#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 56919#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56920#L475-30 assume !(1 == ~t3_pc~0); 56913#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 56914#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56909#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56910#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56905#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56906#L494-30 assume 1 == ~t4_pc~0; 56899#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56900#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56895#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56896#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 56891#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56892#L513-30 assume 1 == ~t5_pc~0; 56886#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56885#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56884#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56883#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56882#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56881#L532-30 assume 1 == ~t6_pc~0; 56880#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 56878#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56877#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56705#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49580#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49581#L551-30 assume 1 == ~t7_pc~0; 49634#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49697#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49565#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49372#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49373#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49750#L570-30 assume 1 == ~t8_pc~0; 50356#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49633#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49584#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49436#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49437#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49819#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49855#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50474#L957-3 assume !(1 == ~T2_E~0); 50475#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50330#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50331#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50204#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50205#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50616#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49804#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49805#L997-3 assume !(1 == ~E_1~0); 49800#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49801#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49605#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49606#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49708#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49947#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49984#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51286#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 51273#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 50707#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 50676#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 50537#L1322 assume !(0 == start_simulation_~tmp~3#1); 49834#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49484#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49485#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 50476#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 49388#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49389#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50207#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 50394#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 50178#L1303-2 [2022-11-16 11:30:52,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:52,727 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2022-11-16 11:30:52,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:52,728 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460073479] [2022-11-16 11:30:52,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:52,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:52,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:52,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:52,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:52,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460073479] [2022-11-16 11:30:52,795 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460073479] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:52,795 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:52,795 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:52,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143815549] [2022-11-16 11:30:52,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:52,796 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:52,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:52,797 INFO L85 PathProgramCache]: Analyzing trace with hash -1907440681, now seen corresponding path program 1 times [2022-11-16 11:30:52,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:52,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901659062] [2022-11-16 11:30:52,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:52,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:52,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:52,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:52,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:52,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901659062] [2022-11-16 11:30:52,912 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901659062] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:52,912 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:52,912 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:52,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598468554] [2022-11-16 11:30:52,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:52,913 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:52,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:52,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:30:52,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:30:52,915 INFO L87 Difference]: Start difference. First operand 8861 states and 12789 transitions. cyclomatic complexity: 3936 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:53,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:53,226 INFO L93 Difference]: Finished difference Result 25208 states and 35974 transitions. [2022-11-16 11:30:53,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25208 states and 35974 transitions. [2022-11-16 11:30:53,439 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24428 [2022-11-16 11:30:53,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25208 states to 25208 states and 35974 transitions. [2022-11-16 11:30:53,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25208 [2022-11-16 11:30:53,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25208 [2022-11-16 11:30:53,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25208 states and 35974 transitions. [2022-11-16 11:30:53,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:53,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25208 states and 35974 transitions. [2022-11-16 11:30:53,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25208 states and 35974 transitions. [2022-11-16 11:30:54,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25208 to 24378. [2022-11-16 11:30:54,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24378 states, 24378 states have (on average 1.4299778488801378) internal successors, (34860), 24377 states have internal predecessors, (34860), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:54,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24378 states to 24378 states and 34860 transitions. [2022-11-16 11:30:54,251 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24378 states and 34860 transitions. [2022-11-16 11:30:54,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:30:54,251 INFO L428 stractBuchiCegarLoop]: Abstraction has 24378 states and 34860 transitions. [2022-11-16 11:30:54,252 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 11:30:54,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24378 states and 34860 transitions. [2022-11-16 11:30:54,319 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24170 [2022-11-16 11:30:54,319 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:54,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:54,321 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:54,321 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:54,322 INFO L748 eck$LassoCheckResult]: Stem: 84229#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 84230#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 83479#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 83480#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83516#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 84164#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84165#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83769#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83770#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83706#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83707#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83952#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83925#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83926#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84233#L854 assume !(0 == ~M_E~0); 84018#L854-2 assume !(0 == ~T1_E~0); 84019#L859-1 assume !(0 == ~T2_E~0); 83579#L864-1 assume !(0 == ~T3_E~0); 83580#L869-1 assume !(0 == ~T4_E~0); 83693#L874-1 assume !(0 == ~T5_E~0); 84508#L879-1 assume !(0 == ~T6_E~0); 84002#L884-1 assume !(0 == ~T7_E~0); 83447#L889-1 assume !(0 == ~T8_E~0); 83448#L894-1 assume !(0 == ~E_M~0); 83782#L899-1 assume !(0 == ~E_1~0); 84241#L904-1 assume !(0 == ~E_2~0); 83942#L909-1 assume !(0 == ~E_3~0); 83943#L914-1 assume !(0 == ~E_4~0); 84152#L919-1 assume !(0 == ~E_5~0); 83859#L924-1 assume !(0 == ~E_6~0); 83680#L929-1 assume !(0 == ~E_7~0); 83681#L934-1 assume !(0 == ~E_8~0); 83924#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83466#L418 assume !(1 == ~m_pc~0); 83467#L418-2 is_master_triggered_~__retres1~0#1 := 0; 84446#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84447#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 84368#L1061 assume !(0 != activate_threads_~tmp~1#1); 84268#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84269#L437 assume !(1 == ~t1_pc~0); 84494#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84377#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84313#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 83814#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 83815#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84361#L456 assume !(1 == ~t2_pc~0); 83732#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83731#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84079#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84080#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 84050#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83574#L475 assume !(1 == ~t3_pc~0); 83575#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83636#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83637#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 84497#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 83818#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83819#L494 assume !(1 == ~t4_pc~0); 83854#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 83855#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84070#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 84071#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 84178#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83631#L513 assume 1 == ~t5_pc~0; 83632#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83858#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83894#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83590#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 83591#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83545#L532 assume !(1 == ~t6_pc~0); 83546#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 83694#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83980#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84061#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 83785#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83786#L551 assume 1 == ~t7_pc~0; 84407#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84182#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84183#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84424#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 84563#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83962#L570 assume 1 == ~t8_pc~0; 83963#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84082#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84242#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84076#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 83572#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83573#L952 assume !(1 == ~M_E~0); 84382#L952-2 assume !(1 == ~T1_E~0); 84336#L957-1 assume !(1 == ~T2_E~0); 84337#L962-1 assume !(1 == ~T3_E~0); 84095#L967-1 assume !(1 == ~T4_E~0); 84096#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84408#L977-1 assume !(1 == ~T6_E~0); 84409#L982-1 assume !(1 == ~T7_E~0); 83696#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 83697#L992-1 assume !(1 == ~E_M~0); 83708#L997-1 assume !(1 == ~E_1~0); 84047#L1002-1 assume !(1 == ~E_2~0); 84034#L1007-1 assume !(1 == ~E_3~0); 84035#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 88341#L1017-1 assume !(1 == ~E_5~0); 88340#L1022-1 assume !(1 == ~E_6~0); 88339#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 84510#L1032-1 assume !(1 == ~E_8~0); 84511#L1037-1 assume { :end_inline_reset_delta_events } true; 88324#L1303-2 [2022-11-16 11:30:54,322 INFO L750 eck$LassoCheckResult]: Loop: 88324#L1303-2 assume !false; 102417#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102416#L829 assume !false; 102415#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 88288#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 88284#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 88273#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 88274#L712 assume !(0 != eval_~tmp~0#1); 102354#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 102898#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 102897#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 102896#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 102895#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 102894#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 102893#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 102892#L874-3 assume !(0 == ~T5_E~0); 102891#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 102890#L884-3 assume !(0 == ~T7_E~0); 102889#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 102888#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 102887#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 102886#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 102885#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102884#L914-3 assume !(0 == ~E_4~0); 102883#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102882#L924-3 assume !(0 == ~E_6~0); 102881#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 102880#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 102879#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102878#L418-30 assume !(1 == ~m_pc~0); 102877#L418-32 is_master_triggered_~__retres1~0#1 := 0; 102876#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102875#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 102874#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 102873#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102872#L437-30 assume !(1 == ~t1_pc~0); 102871#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 102870#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102869#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 102868#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 102867#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102866#L456-30 assume !(1 == ~t2_pc~0); 102865#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 102863#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102862#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 102861#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 102860#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102859#L475-30 assume !(1 == ~t3_pc~0); 102858#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 102857#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102856#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 102855#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 102854#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102853#L494-30 assume 1 == ~t4_pc~0; 102851#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 102850#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102849#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 102848#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 102847#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102846#L513-30 assume !(1 == ~t5_pc~0); 102845#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 102843#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102842#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102841#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 102840#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102839#L532-30 assume !(1 == ~t6_pc~0); 102837#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 102836#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102835#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102834#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 102833#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102832#L551-30 assume !(1 == ~t7_pc~0); 102831#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 102829#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102828#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102827#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 102826#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102825#L570-30 assume !(1 == ~t8_pc~0); 102823#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 102822#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102821#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102820#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102819#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102818#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88751#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102817#L957-3 assume !(1 == ~T2_E~0); 102816#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102815#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 102727#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 102726#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 102725#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 102724#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 102723#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 102722#L997-3 assume !(1 == ~E_1~0); 102721#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 102720#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 102719#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88722#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 102718#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 102717#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 102716#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 102715#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 102706#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 102705#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 102704#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 102703#L1322 assume !(0 == start_simulation_~tmp~3#1); 102701#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 102699#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 102691#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 102690#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 102689#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 102688#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102687#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 102686#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 88324#L1303-2 [2022-11-16 11:30:54,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:54,323 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2022-11-16 11:30:54,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:54,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000288990] [2022-11-16 11:30:54,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:54,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:54,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:54,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:54,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:54,415 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000288990] [2022-11-16 11:30:54,416 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1000288990] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:54,416 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:54,417 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:30:54,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248635371] [2022-11-16 11:30:54,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:54,417 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:54,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:54,420 INFO L85 PathProgramCache]: Analyzing trace with hash 1476424283, now seen corresponding path program 1 times [2022-11-16 11:30:54,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:54,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046228181] [2022-11-16 11:30:54,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:54,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:54,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:54,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:54,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:54,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046228181] [2022-11-16 11:30:54,467 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1046228181] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:54,467 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:54,467 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:54,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284207229] [2022-11-16 11:30:54,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:54,468 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:54,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:54,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:30:54,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:30:54,470 INFO L87 Difference]: Start difference. First operand 24378 states and 34860 transitions. cyclomatic complexity: 10498 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:54,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:54,825 INFO L93 Difference]: Finished difference Result 45992 states and 65497 transitions. [2022-11-16 11:30:54,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45992 states and 65497 transitions. [2022-11-16 11:30:55,028 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45653 [2022-11-16 11:30:55,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45992 states to 45992 states and 65497 transitions. [2022-11-16 11:30:55,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45992 [2022-11-16 11:30:55,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45992 [2022-11-16 11:30:55,408 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45992 states and 65497 transitions. [2022-11-16 11:30:55,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:55,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45992 states and 65497 transitions. [2022-11-16 11:30:55,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45992 states and 65497 transitions. [2022-11-16 11:30:56,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45992 to 45920. [2022-11-16 11:30:56,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45920 states, 45920 states have (on average 1.4247604529616724) internal successors, (65425), 45919 states have internal predecessors, (65425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:56,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45920 states to 45920 states and 65425 transitions. [2022-11-16 11:30:56,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45920 states and 65425 transitions. [2022-11-16 11:30:56,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:30:56,910 INFO L428 stractBuchiCegarLoop]: Abstraction has 45920 states and 65425 transitions. [2022-11-16 11:30:56,910 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 11:30:56,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45920 states and 65425 transitions. [2022-11-16 11:30:57,091 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45581 [2022-11-16 11:30:57,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:30:57,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:30:57,093 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:57,093 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:30:57,093 INFO L748 eck$LassoCheckResult]: Stem: 154624#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 154625#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 153855#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 153856#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153892#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 154563#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154564#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154144#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154145#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 154081#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154082#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154339#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 154310#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 154311#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 154629#L854 assume !(0 == ~M_E~0); 154410#L854-2 assume !(0 == ~T1_E~0); 154411#L859-1 assume !(0 == ~T2_E~0); 153955#L864-1 assume !(0 == ~T3_E~0); 153956#L869-1 assume !(0 == ~T4_E~0); 154069#L874-1 assume !(0 == ~T5_E~0); 154915#L879-1 assume !(0 == ~T6_E~0); 154393#L884-1 assume !(0 == ~T7_E~0); 153823#L889-1 assume !(0 == ~T8_E~0); 153824#L894-1 assume !(0 == ~E_M~0); 154160#L899-1 assume !(0 == ~E_1~0); 154638#L904-1 assume !(0 == ~E_2~0); 154328#L909-1 assume !(0 == ~E_3~0); 154329#L914-1 assume !(0 == ~E_4~0); 154550#L919-1 assume !(0 == ~E_5~0); 154245#L924-1 assume !(0 == ~E_6~0); 154056#L929-1 assume !(0 == ~E_7~0); 154057#L934-1 assume !(0 == ~E_8~0); 154307#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153842#L418 assume !(1 == ~m_pc~0); 153843#L418-2 is_master_triggered_~__retres1~0#1 := 0; 154847#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154848#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 154766#L1061 assume !(0 != activate_threads_~tmp~1#1); 154667#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154668#L437 assume !(1 == ~t1_pc~0); 154901#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 154774#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154716#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 154195#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 154196#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 154759#L456 assume !(1 == ~t2_pc~0); 154107#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 154106#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154469#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 154470#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 154442#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153950#L475 assume !(1 == ~t3_pc~0); 153951#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154012#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154013#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154902#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 154199#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154200#L494 assume !(1 == ~t4_pc~0); 154240#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 154241#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 154460#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 154461#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 154577#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154008#L513 assume !(1 == ~t5_pc~0); 154009#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 154244#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154280#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 153966#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 153967#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 153921#L532 assume !(1 == ~t6_pc~0); 153922#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 154070#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154369#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154453#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 154164#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154165#L551 assume 1 == ~t7_pc~0; 154806#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 154581#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154582#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154825#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 154978#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 154350#L570 assume 1 == ~t8_pc~0; 154351#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 154472#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 154639#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154466#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 153948#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153949#L952 assume !(1 == ~M_E~0); 154780#L952-2 assume !(1 == ~T1_E~0); 160469#L957-1 assume !(1 == ~T2_E~0); 160468#L962-1 assume !(1 == ~T3_E~0); 160467#L967-1 assume !(1 == ~T4_E~0); 160465#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 160466#L977-1 assume !(1 == ~T6_E~0); 162023#L982-1 assume !(1 == ~T7_E~0); 162022#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 162021#L992-1 assume !(1 == ~E_M~0); 162020#L997-1 assume !(1 == ~E_1~0); 162019#L1002-1 assume !(1 == ~E_2~0); 162018#L1007-1 assume !(1 == ~E_3~0); 162017#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 153826#L1017-1 assume !(1 == ~E_5~0); 154430#L1022-1 assume !(1 == ~E_6~0); 154431#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 154454#L1032-1 assume !(1 == ~E_8~0); 154613#L1037-1 assume { :end_inline_reset_delta_events } true; 154614#L1303-2 [2022-11-16 11:30:57,094 INFO L750 eck$LassoCheckResult]: Loop: 154614#L1303-2 assume !false; 194755#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 194752#L829 assume !false; 194750#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 194741#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 165434#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 165431#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 165432#L712 assume !(0 != eval_~tmp~0#1); 194731#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 195031#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 195030#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 195029#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 195028#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 195027#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 195026#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 195025#L874-3 assume !(0 == ~T5_E~0); 195024#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 195023#L884-3 assume !(0 == ~T7_E~0); 195022#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 195021#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 195020#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 195019#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 195018#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 195017#L914-3 assume !(0 == ~E_4~0); 195016#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 195015#L924-3 assume !(0 == ~E_6~0); 195014#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 195013#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 195012#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 195011#L418-30 assume !(1 == ~m_pc~0); 195010#L418-32 is_master_triggered_~__retres1~0#1 := 0; 195009#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 195008#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 195007#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 195006#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 195005#L437-30 assume !(1 == ~t1_pc~0); 195004#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 195003#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 195002#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 195001#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 195000#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194999#L456-30 assume !(1 == ~t2_pc~0); 194998#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 194996#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 194995#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 194994#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 194993#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 194992#L475-30 assume !(1 == ~t3_pc~0); 194991#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 194990#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194989#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 194988#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 194987#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194986#L494-30 assume 1 == ~t4_pc~0; 194984#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 194983#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 194982#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 194981#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 194980#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 194979#L513-30 assume !(1 == ~t5_pc~0); 194978#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 194977#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 194976#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 194975#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 194974#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 194973#L532-30 assume !(1 == ~t6_pc~0); 194971#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 194970#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 194969#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 194968#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 194967#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 194966#L551-30 assume 1 == ~t7_pc~0; 194964#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 194963#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 194962#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 194961#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 194960#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 194959#L570-30 assume 1 == ~t8_pc~0; 194958#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 194956#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 194955#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 194954#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 194953#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194952#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 171987#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 194951#L957-3 assume !(1 == ~T2_E~0); 194950#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 194949#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 194948#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 184889#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 194947#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 194946#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 194945#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 194944#L997-3 assume !(1 == ~E_1~0); 194943#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 194942#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 194941#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 171971#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 194940#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 194939#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 194938#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 194937#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 194928#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 194927#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 194926#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 194925#L1322 assume !(0 == start_simulation_~tmp~3#1); 194923#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 194921#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 194913#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 194912#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 194911#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 194910#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 194909#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 194908#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 154614#L1303-2 [2022-11-16 11:30:57,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:57,095 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2022-11-16 11:30:57,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:57,095 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914925459] [2022-11-16 11:30:57,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:57,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:57,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:57,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:57,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:57,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [914925459] [2022-11-16 11:30:57,167 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [914925459] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:57,167 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:57,167 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:57,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135425942] [2022-11-16 11:30:57,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:57,168 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:30:57,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:30:57,168 INFO L85 PathProgramCache]: Analyzing trace with hash -1547365991, now seen corresponding path program 1 times [2022-11-16 11:30:57,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:30:57,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214515774] [2022-11-16 11:30:57,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:30:57,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:30:57,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:30:57,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:30:57,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:30:57,319 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1214515774] [2022-11-16 11:30:57,319 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1214515774] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:30:57,319 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:30:57,319 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:30:57,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181757596] [2022-11-16 11:30:57,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:30:57,320 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:30:57,320 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:30:57,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:30:57,321 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:30:57,321 INFO L87 Difference]: Start difference. First operand 45920 states and 65425 transitions. cyclomatic complexity: 19537 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:30:58,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:30:58,269 INFO L93 Difference]: Finished difference Result 127061 states and 179748 transitions. [2022-11-16 11:30:58,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127061 states and 179748 transitions. [2022-11-16 11:30:59,084 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123987 [2022-11-16 11:30:59,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127061 states to 127061 states and 179748 transitions. [2022-11-16 11:30:59,655 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127061 [2022-11-16 11:30:59,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127061 [2022-11-16 11:30:59,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127061 states and 179748 transitions. [2022-11-16 11:30:59,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:30:59,979 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127061 states and 179748 transitions. [2022-11-16 11:31:00,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127061 states and 179748 transitions. [2022-11-16 11:31:01,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127061 to 123549. [2022-11-16 11:31:01,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123549 states, 123549 states have (on average 1.4182227294433787) internal successors, (175220), 123548 states have internal predecessors, (175220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:02,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123549 states to 123549 states and 175220 transitions. [2022-11-16 11:31:02,260 INFO L240 hiAutomatonCegarLoop]: Abstraction has 123549 states and 175220 transitions. [2022-11-16 11:31:02,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:31:02,261 INFO L428 stractBuchiCegarLoop]: Abstraction has 123549 states and 175220 transitions. [2022-11-16 11:31:02,261 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 11:31:02,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123549 states and 175220 transitions. [2022-11-16 11:31:02,986 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 122907 [2022-11-16 11:31:03,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:03,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:03,017 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:03,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:03,017 INFO L748 eck$LassoCheckResult]: Stem: 327616#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 327617#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 326845#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326846#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 326883#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 327554#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 327555#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 327141#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 327142#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 327074#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 327075#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 327331#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 327303#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 327304#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 327619#L854 assume !(0 == ~M_E~0); 327397#L854-2 assume !(0 == ~T1_E~0); 327398#L859-1 assume !(0 == ~T2_E~0); 326948#L864-1 assume !(0 == ~T3_E~0); 326949#L869-1 assume !(0 == ~T4_E~0); 327062#L874-1 assume !(0 == ~T5_E~0); 327905#L879-1 assume !(0 == ~T6_E~0); 327381#L884-1 assume !(0 == ~T7_E~0); 326814#L889-1 assume !(0 == ~T8_E~0); 326815#L894-1 assume !(0 == ~E_M~0); 327154#L899-1 assume !(0 == ~E_1~0); 327627#L904-1 assume !(0 == ~E_2~0); 327321#L909-1 assume !(0 == ~E_3~0); 327322#L914-1 assume !(0 == ~E_4~0); 327543#L919-1 assume !(0 == ~E_5~0); 327235#L924-1 assume !(0 == ~E_6~0); 327049#L929-1 assume !(0 == ~E_7~0); 327050#L934-1 assume !(0 == ~E_8~0); 327302#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 326833#L418 assume !(1 == ~m_pc~0); 326834#L418-2 is_master_triggered_~__retres1~0#1 := 0; 327841#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 327842#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 327758#L1061 assume !(0 != activate_threads_~tmp~1#1); 327657#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 327658#L437 assume !(1 == ~t1_pc~0); 327889#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 327766#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 327705#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 327188#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 327189#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 327751#L456 assume !(1 == ~t2_pc~0); 327100#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 327099#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 327459#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 327460#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 327430#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326943#L475 assume !(1 == ~t3_pc~0); 326944#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 327005#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 327006#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 327890#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 327192#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 327193#L494 assume !(1 == ~t4_pc~0); 327231#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 327232#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 327450#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 327451#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 327571#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 327001#L513 assume !(1 == ~t5_pc~0); 327002#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 327234#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 327273#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 326959#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 326960#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 326912#L532 assume !(1 == ~t6_pc~0); 326913#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 327063#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 327358#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 327440#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 327157#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 327158#L551 assume !(1 == ~t7_pc~0); 327629#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 327575#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 327576#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 327819#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 327974#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 327341#L570 assume 1 == ~t8_pc~0; 327342#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 327462#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 327628#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 327456#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 326941#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 326942#L952 assume !(1 == ~M_E~0); 327771#L952-2 assume !(1 == ~T1_E~0); 327727#L957-1 assume !(1 == ~T2_E~0); 327728#L962-1 assume !(1 == ~T3_E~0); 327477#L967-1 assume !(1 == ~T4_E~0); 327478#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 335974#L977-1 assume !(1 == ~T6_E~0); 335973#L982-1 assume !(1 == ~T7_E~0); 335972#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 335971#L992-1 assume !(1 == ~E_M~0); 335970#L997-1 assume !(1 == ~E_1~0); 335969#L1002-1 assume !(1 == ~E_2~0); 335968#L1007-1 assume !(1 == ~E_3~0); 335966#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 335967#L1017-1 assume !(1 == ~E_5~0); 336230#L1022-1 assume !(1 == ~E_6~0); 336229#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 336228#L1032-1 assume !(1 == ~E_8~0); 336226#L1037-1 assume { :end_inline_reset_delta_events } true; 336227#L1303-2 [2022-11-16 11:31:03,018 INFO L750 eck$LassoCheckResult]: Loop: 336227#L1303-2 assume !false; 433888#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 433886#L829 assume !false; 433885#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 433880#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 433875#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 433874#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 433872#L712 assume !(0 != eval_~tmp~0#1); 433873#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 439447#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 439446#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 439445#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 439444#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 439443#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 439442#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 439441#L874-3 assume !(0 == ~T5_E~0); 439440#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 439439#L884-3 assume !(0 == ~T7_E~0); 439438#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 439437#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 439436#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 439435#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 439434#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 439433#L914-3 assume !(0 == ~E_4~0); 439432#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 439431#L924-3 assume !(0 == ~E_6~0); 439430#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 439429#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 439428#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 439427#L418-30 assume !(1 == ~m_pc~0); 439426#L418-32 is_master_triggered_~__retres1~0#1 := 0; 439425#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 439424#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 439423#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 439422#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 439421#L437-30 assume !(1 == ~t1_pc~0); 439420#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 439419#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 439418#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 439417#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 439416#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 439415#L456-30 assume !(1 == ~t2_pc~0); 439414#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 439412#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 439411#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 439410#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 439409#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 439408#L475-30 assume !(1 == ~t3_pc~0); 439407#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 439406#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 439405#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 439404#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 439403#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 439402#L494-30 assume 1 == ~t4_pc~0; 439400#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 439399#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 439398#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 439397#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 439396#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 439395#L513-30 assume !(1 == ~t5_pc~0); 439394#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 439393#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 439392#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 439391#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 439390#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 439389#L532-30 assume 1 == ~t6_pc~0; 439388#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 439386#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 439385#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 439384#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 439383#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 439382#L551-30 assume !(1 == ~t7_pc~0); 439381#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 439380#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 439379#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 439378#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 439377#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 439376#L570-30 assume !(1 == ~t8_pc~0); 439374#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 439373#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 439372#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 439371#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 439370#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 438951#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 396797#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 438948#L957-3 assume !(1 == ~T2_E~0); 438946#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 438944#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 438942#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 438938#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 438936#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 438934#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 438931#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 438929#L997-3 assume !(1 == ~E_1~0); 438927#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 438925#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 438923#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 396287#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 438920#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 438918#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 438916#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 438914#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 438884#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 438882#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 438880#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 438878#L1322 assume !(0 == start_simulation_~tmp~3#1); 438875#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 438867#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 438858#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 438856#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 438854#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 438850#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 438848#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 438846#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 336227#L1303-2 [2022-11-16 11:31:03,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:03,028 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2022-11-16 11:31:03,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:03,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630961428] [2022-11-16 11:31:03,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:03,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:03,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:03,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:03,120 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:03,121 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [630961428] [2022-11-16 11:31:03,121 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [630961428] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:03,121 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:03,121 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:31:03,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2036542396] [2022-11-16 11:31:03,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:03,122 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:03,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:03,122 INFO L85 PathProgramCache]: Analyzing trace with hash 8220954, now seen corresponding path program 1 times [2022-11-16 11:31:03,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:03,123 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383850096] [2022-11-16 11:31:03,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:03,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:03,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:03,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:03,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:03,170 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383850096] [2022-11-16 11:31:03,171 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [383850096] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:03,171 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:03,171 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:03,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901291956] [2022-11-16 11:31:03,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:03,172 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:31:03,172 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:03,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:31:03,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:31:03,173 INFO L87 Difference]: Start difference. First operand 123549 states and 175220 transitions. cyclomatic complexity: 51735 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:04,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:04,335 INFO L93 Difference]: Finished difference Result 231925 states and 328130 transitions. [2022-11-16 11:31:04,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 231925 states and 328130 transitions. [2022-11-16 11:31:05,469 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 230356 [2022-11-16 11:31:06,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 231925 states to 231925 states and 328130 transitions. [2022-11-16 11:31:06,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231925 [2022-11-16 11:31:06,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231925 [2022-11-16 11:31:06,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 231925 states and 328130 transitions. [2022-11-16 11:31:06,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:31:06,471 INFO L218 hiAutomatonCegarLoop]: Abstraction has 231925 states and 328130 transitions. [2022-11-16 11:31:06,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231925 states and 328130 transitions. [2022-11-16 11:31:08,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231925 to 231493. [2022-11-16 11:31:09,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 231493 states, 231493 states have (on average 1.4155849204943562) internal successors, (327698), 231492 states have internal predecessors, (327698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:10,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231493 states to 231493 states and 327698 transitions. [2022-11-16 11:31:10,300 INFO L240 hiAutomatonCegarLoop]: Abstraction has 231493 states and 327698 transitions. [2022-11-16 11:31:10,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:31:10,301 INFO L428 stractBuchiCegarLoop]: Abstraction has 231493 states and 327698 transitions. [2022-11-16 11:31:10,301 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 11:31:10,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 231493 states and 327698 transitions. [2022-11-16 11:31:10,891 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 229924 [2022-11-16 11:31:10,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:10,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:10,892 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:10,893 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:10,893 INFO L748 eck$LassoCheckResult]: Stem: 683114#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 683115#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 682327#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 682328#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 682364#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 683043#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 683044#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 682626#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 682627#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 682558#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 682559#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 682817#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 682788#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 682789#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 683119#L854 assume !(0 == ~M_E~0); 682889#L854-2 assume !(0 == ~T1_E~0); 682890#L859-1 assume !(0 == ~T2_E~0); 682429#L864-1 assume !(0 == ~T3_E~0); 682430#L869-1 assume !(0 == ~T4_E~0); 682546#L874-1 assume !(0 == ~T5_E~0); 683438#L879-1 assume !(0 == ~T6_E~0); 682871#L884-1 assume !(0 == ~T7_E~0); 682295#L889-1 assume !(0 == ~T8_E~0); 682296#L894-1 assume !(0 == ~E_M~0); 682640#L899-1 assume !(0 == ~E_1~0); 683127#L904-1 assume !(0 == ~E_2~0); 682808#L909-1 assume !(0 == ~E_3~0); 682809#L914-1 assume !(0 == ~E_4~0); 683029#L919-1 assume !(0 == ~E_5~0); 682722#L924-1 assume !(0 == ~E_6~0); 682533#L929-1 assume !(0 == ~E_7~0); 682534#L934-1 assume !(0 == ~E_8~0); 682785#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 682315#L418 assume !(1 == ~m_pc~0); 682316#L418-2 is_master_triggered_~__retres1~0#1 := 0; 683349#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 683350#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 683264#L1061 assume !(0 != activate_threads_~tmp~1#1); 683156#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 683157#L437 assume !(1 == ~t1_pc~0); 683417#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 683275#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 683209#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 682672#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 682673#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 683256#L456 assume !(1 == ~t2_pc~0); 682585#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 682584#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 682949#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 682950#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 682922#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 682424#L475 assume !(1 == ~t3_pc~0); 682425#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 682487#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 682488#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 683421#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 682676#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 682677#L494 assume !(1 == ~t4_pc~0); 682718#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 682719#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 682940#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 682941#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 683060#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 682483#L513 assume !(1 == ~t5_pc~0); 682484#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 682721#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 682758#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 682440#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 682441#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 682393#L532 assume !(1 == ~t6_pc~0); 682394#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 682547#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 682848#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 682933#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 682643#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 682644#L551 assume !(1 == ~t7_pc~0); 683129#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 683064#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 683065#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 683325#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 683517#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 682831#L570 assume !(1 == ~t8_pc~0); 682832#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 683383#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 683128#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 682946#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 682422#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 682423#L952 assume !(1 == ~M_E~0); 682365#L952-2 assume !(1 == ~T1_E~0); 682366#L957-1 assume !(1 == ~T2_E~0); 683233#L962-1 assume !(1 == ~T3_E~0); 682966#L967-1 assume !(1 == ~T4_E~0); 682967#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 683469#L977-1 assume !(1 == ~T6_E~0); 715717#L982-1 assume !(1 == ~T7_E~0); 715715#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 715713#L992-1 assume !(1 == ~E_M~0); 715711#L997-1 assume !(1 == ~E_1~0); 715709#L1002-1 assume !(1 == ~E_2~0); 715707#L1007-1 assume !(1 == ~E_3~0); 715703#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 715702#L1017-1 assume !(1 == ~E_5~0); 715701#L1022-1 assume !(1 == ~E_6~0); 715697#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 715695#L1032-1 assume !(1 == ~E_8~0); 715693#L1037-1 assume { :end_inline_reset_delta_events } true; 715691#L1303-2 [2022-11-16 11:31:10,894 INFO L750 eck$LassoCheckResult]: Loop: 715691#L1303-2 assume !false; 715486#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 715485#L829 assume !false; 715484#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 715479#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 715474#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 715473#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 715471#L712 assume !(0 != eval_~tmp~0#1); 715472#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 715983#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 715982#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 715981#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 715980#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 715979#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 715978#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 715977#L874-3 assume !(0 == ~T5_E~0); 715976#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 715975#L884-3 assume !(0 == ~T7_E~0); 715974#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 715972#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 715970#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 715968#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 715966#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 715964#L914-3 assume !(0 == ~E_4~0); 715962#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 715960#L924-3 assume !(0 == ~E_6~0); 715958#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 715956#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 715954#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 715952#L418-30 assume !(1 == ~m_pc~0); 715950#L418-32 is_master_triggered_~__retres1~0#1 := 0; 715948#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 715946#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 715944#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 715941#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 715939#L437-30 assume !(1 == ~t1_pc~0); 715937#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 715935#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 715933#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 715930#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 715929#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 715927#L456-30 assume 1 == ~t2_pc~0; 715924#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 715922#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 715920#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 715918#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 715916#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 715914#L475-30 assume !(1 == ~t3_pc~0); 715912#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 715910#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 715908#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 715906#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 715904#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 715902#L494-30 assume 1 == ~t4_pc~0; 715898#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 715896#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 715894#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 715892#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 715890#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 715888#L513-30 assume !(1 == ~t5_pc~0); 715886#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 715884#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 715882#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 715880#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 715878#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 715876#L532-30 assume !(1 == ~t6_pc~0); 715872#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 715870#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 715868#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 715866#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 715864#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 715862#L551-30 assume !(1 == ~t7_pc~0); 715860#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 715858#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 715856#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 715854#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 715852#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 715850#L570-30 assume !(1 == ~t8_pc~0); 715847#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 715845#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 715843#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 715841#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 715839#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 715837#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 715833#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 715831#L957-3 assume !(1 == ~T2_E~0); 715829#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 715827#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 715825#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 715821#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 715819#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 715817#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 715815#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 715813#L997-3 assume !(1 == ~E_1~0); 715811#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 715809#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 715807#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 715803#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 715801#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 715799#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 715797#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 715795#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 715777#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 715775#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 715773#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 715771#L1322 assume !(0 == start_simulation_~tmp~3#1); 715769#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 715766#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 715757#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 715755#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 715753#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 715751#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 715749#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 715692#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 715691#L1303-2 [2022-11-16 11:31:10,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:10,894 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2022-11-16 11:31:10,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:10,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330416161] [2022-11-16 11:31:10,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:10,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:10,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:10,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:10,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:10,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330416161] [2022-11-16 11:31:10,966 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1330416161] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:10,966 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:10,966 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:10,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84544905] [2022-11-16 11:31:10,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:10,967 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:10,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:10,968 INFO L85 PathProgramCache]: Analyzing trace with hash -655563750, now seen corresponding path program 1 times [2022-11-16 11:31:10,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:10,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007216724] [2022-11-16 11:31:10,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:10,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:10,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:11,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:11,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:11,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007216724] [2022-11-16 11:31:11,018 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007216724] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:11,018 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:11,018 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:11,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931468152] [2022-11-16 11:31:11,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:11,019 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:31:11,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:11,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:31:11,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:31:11,020 INFO L87 Difference]: Start difference. First operand 231493 states and 327698 transitions. cyclomatic complexity: 96333 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:12,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:12,240 INFO L93 Difference]: Finished difference Result 176932 states and 249822 transitions. [2022-11-16 11:31:12,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176932 states and 249822 transitions. [2022-11-16 11:31:12,922 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 175750 [2022-11-16 11:31:13,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176932 states to 176932 states and 249822 transitions. [2022-11-16 11:31:13,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176932 [2022-11-16 11:31:13,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176932 [2022-11-16 11:31:13,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176932 states and 249822 transitions. [2022-11-16 11:31:13,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:31:13,515 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176932 states and 249822 transitions. [2022-11-16 11:31:13,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176932 states and 249822 transitions. [2022-11-16 11:31:15,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176932 to 122397. [2022-11-16 11:31:15,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122397 states, 122397 states have (on average 1.4123140273045909) internal successors, (172863), 122396 states have internal predecessors, (172863), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:16,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122397 states to 122397 states and 172863 transitions. [2022-11-16 11:31:16,113 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122397 states and 172863 transitions. [2022-11-16 11:31:16,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:31:16,121 INFO L428 stractBuchiCegarLoop]: Abstraction has 122397 states and 172863 transitions. [2022-11-16 11:31:16,121 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 11:31:16,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122397 states and 172863 transitions. [2022-11-16 11:31:16,359 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121576 [2022-11-16 11:31:16,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:16,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:16,360 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:16,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:16,360 INFO L748 eck$LassoCheckResult]: Stem: 1091526#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 1091527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1090763#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1090764#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1090798#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1091464#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1091465#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1091051#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1091052#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1090989#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1090990#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1091251#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1091220#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1091221#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1091529#L854 assume !(0 == ~M_E~0); 1091319#L854-2 assume !(0 == ~T1_E~0); 1091320#L859-1 assume !(0 == ~T2_E~0); 1090863#L864-1 assume !(0 == ~T3_E~0); 1090864#L869-1 assume !(0 == ~T4_E~0); 1090977#L874-1 assume !(0 == ~T5_E~0); 1091843#L879-1 assume !(0 == ~T6_E~0); 1091303#L884-1 assume !(0 == ~T7_E~0); 1090730#L889-1 assume !(0 == ~T8_E~0); 1090731#L894-1 assume !(0 == ~E_M~0); 1091068#L899-1 assume !(0 == ~E_1~0); 1091536#L904-1 assume !(0 == ~E_2~0); 1091240#L909-1 assume !(0 == ~E_3~0); 1091241#L914-1 assume !(0 == ~E_4~0); 1091453#L919-1 assume !(0 == ~E_5~0); 1091152#L924-1 assume !(0 == ~E_6~0); 1090964#L929-1 assume !(0 == ~E_7~0); 1090965#L934-1 assume !(0 == ~E_8~0); 1091219#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1090748#L418 assume !(1 == ~m_pc~0); 1090749#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1091759#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1091760#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1091676#L1061 assume !(0 != activate_threads_~tmp~1#1); 1091568#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1091569#L437 assume !(1 == ~t1_pc~0); 1091826#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1091685#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1091620#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1091102#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1091103#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1091669#L456 assume !(1 == ~t2_pc~0); 1091015#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1091014#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1091379#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1091380#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1091351#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1090858#L475 assume !(1 == ~t3_pc~0); 1090859#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1090920#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1090921#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1091827#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1091106#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1091107#L494 assume !(1 == ~t4_pc~0); 1091147#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1091148#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1091370#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1091371#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1091479#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1090913#L513 assume !(1 == ~t5_pc~0); 1090914#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1091151#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1091190#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1090874#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1090875#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1090827#L532 assume !(1 == ~t6_pc~0); 1090828#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1090978#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1091280#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1091362#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1091071#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1091072#L551 assume !(1 == ~t7_pc~0); 1091539#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1091484#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1091485#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1091735#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1091914#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1091264#L570 assume !(1 == ~t8_pc~0); 1091265#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1091788#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1091538#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1091376#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1090856#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1090857#L952 assume !(1 == ~M_E~0); 1090799#L952-2 assume !(1 == ~T1_E~0); 1090800#L957-1 assume !(1 == ~T2_E~0); 1091645#L962-1 assume !(1 == ~T3_E~0); 1091395#L967-1 assume !(1 == ~T4_E~0); 1091396#L972-1 assume !(1 == ~T5_E~0); 1091717#L977-1 assume !(1 == ~T6_E~0); 1091718#L982-1 assume !(1 == ~T7_E~0); 1090980#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1090981#L992-1 assume !(1 == ~E_M~0); 1090991#L997-1 assume !(1 == ~E_1~0); 1091349#L1002-1 assume !(1 == ~E_2~0); 1091335#L1007-1 assume !(1 == ~E_3~0); 1090732#L1012-1 assume !(1 == ~E_4~0); 1090733#L1017-1 assume !(1 == ~E_5~0); 1091336#L1022-1 assume !(1 == ~E_6~0); 1091337#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1091363#L1032-1 assume !(1 == ~E_8~0); 1091512#L1037-1 assume { :end_inline_reset_delta_events } true; 1091513#L1303-2 [2022-11-16 11:31:16,361 INFO L750 eck$LassoCheckResult]: Loop: 1091513#L1303-2 assume !false; 1128139#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1128133#L829 assume !false; 1128128#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1127842#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1127836#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1127834#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1127776#L712 assume !(0 != eval_~tmp~0#1); 1127777#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1129714#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1129712#L854-3 assume !(0 == ~M_E~0); 1129709#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1129706#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1129703#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1129700#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1129697#L874-3 assume !(0 == ~T5_E~0); 1129694#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1129691#L884-3 assume !(0 == ~T7_E~0); 1129688#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1129685#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1129682#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1129679#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1129676#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1129673#L914-3 assume !(0 == ~E_4~0); 1129670#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1129667#L924-3 assume !(0 == ~E_6~0); 1129664#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1129661#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1129658#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1129655#L418-30 assume !(1 == ~m_pc~0); 1129652#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1129649#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1129646#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1129643#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1129640#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1129637#L437-30 assume !(1 == ~t1_pc~0); 1129634#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1129631#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1129629#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1129627#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1129625#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1129623#L456-30 assume !(1 == ~t2_pc~0); 1129621#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1129618#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1129616#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1129613#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1129611#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1129609#L475-30 assume !(1 == ~t3_pc~0); 1129607#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1129605#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1129603#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1129601#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1129599#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1129597#L494-30 assume !(1 == ~t4_pc~0); 1129595#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1129592#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1129590#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1129587#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1129585#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1129583#L513-30 assume !(1 == ~t5_pc~0); 1129581#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1129579#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1129578#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1129577#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1129576#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1129575#L532-30 assume 1 == ~t6_pc~0; 1129573#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1129570#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1129568#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1129566#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1129564#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1129562#L551-30 assume !(1 == ~t7_pc~0); 1129560#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1129557#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1129555#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1129553#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1129551#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1129549#L570-30 assume !(1 == ~t8_pc~0); 1129547#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1129545#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1129543#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1129541#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1129539#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1129537#L952-3 assume !(1 == ~M_E~0); 1129535#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1129532#L957-3 assume !(1 == ~T2_E~0); 1129530#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1129528#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1129526#L972-3 assume !(1 == ~T5_E~0); 1129524#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1129521#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1129520#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1129517#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1129515#L997-3 assume !(1 == ~E_1~0); 1129513#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1129511#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1129509#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1129477#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1128998#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1128997#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1128996#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1128995#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1128847#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1128840#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1128833#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1128826#L1322 assume !(0 == start_simulation_~tmp~3#1); 1128824#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1128185#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1128176#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1128175#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1128173#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1128171#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1128169#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1128167#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1091513#L1303-2 [2022-11-16 11:31:16,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:16,362 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2022-11-16 11:31:16,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:16,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499457642] [2022-11-16 11:31:16,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:16,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:16,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:16,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:16,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:16,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499457642] [2022-11-16 11:31:16,427 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [499457642] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:16,428 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:16,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:16,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673052399] [2022-11-16 11:31:16,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:16,428 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:16,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:16,429 INFO L85 PathProgramCache]: Analyzing trace with hash -1105280679, now seen corresponding path program 1 times [2022-11-16 11:31:16,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:16,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714690646] [2022-11-16 11:31:16,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:16,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:16,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:16,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:16,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:16,484 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1714690646] [2022-11-16 11:31:16,484 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1714690646] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:16,484 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:16,484 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:16,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479905006] [2022-11-16 11:31:16,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:16,485 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:31:16,486 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:16,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:31:16,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:31:16,486 INFO L87 Difference]: Start difference. First operand 122397 states and 172863 transitions. cyclomatic complexity: 50530 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:17,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:17,012 INFO L93 Difference]: Finished difference Result 196401 states and 277064 transitions. [2022-11-16 11:31:17,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196401 states and 277064 transitions. [2022-11-16 11:31:18,284 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 195138 [2022-11-16 11:31:18,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196401 states to 196401 states and 277064 transitions. [2022-11-16 11:31:18,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 196401 [2022-11-16 11:31:18,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 196401 [2022-11-16 11:31:18,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196401 states and 277064 transitions. [2022-11-16 11:31:18,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:31:18,687 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196401 states and 277064 transitions. [2022-11-16 11:31:18,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196401 states and 277064 transitions. [2022-11-16 11:31:20,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196401 to 139577. [2022-11-16 11:31:20,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139577 states, 139577 states have (on average 1.4126611117877588) internal successors, (197175), 139576 states have internal predecessors, (197175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:20,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139577 states to 139577 states and 197175 transitions. [2022-11-16 11:31:20,795 INFO L240 hiAutomatonCegarLoop]: Abstraction has 139577 states and 197175 transitions. [2022-11-16 11:31:20,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:31:20,796 INFO L428 stractBuchiCegarLoop]: Abstraction has 139577 states and 197175 transitions. [2022-11-16 11:31:20,796 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 11:31:20,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139577 states and 197175 transitions. [2022-11-16 11:31:21,782 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 138680 [2022-11-16 11:31:21,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:21,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:21,784 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:21,784 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:21,785 INFO L748 eck$LassoCheckResult]: Stem: 1410351#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 1410352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1409572#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1409573#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1409606#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1410282#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1410283#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1409866#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1409867#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1409800#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1409801#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1410061#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1410032#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1410033#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1410354#L854 assume !(0 == ~M_E~0); 1410126#L854-2 assume !(0 == ~T1_E~0); 1410127#L859-1 assume !(0 == ~T2_E~0); 1409671#L864-1 assume !(0 == ~T3_E~0); 1409672#L869-1 assume !(0 == ~T4_E~0); 1409787#L874-1 assume !(0 == ~T5_E~0); 1410649#L879-1 assume !(0 == ~T6_E~0); 1410109#L884-1 assume !(0 == ~T7_E~0); 1409538#L889-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1409539#L894-1 assume !(0 == ~E_M~0); 1409879#L899-1 assume !(0 == ~E_1~0); 1410362#L904-1 assume !(0 == ~E_2~0); 1410053#L909-1 assume !(0 == ~E_3~0); 1410054#L914-1 assume !(0 == ~E_4~0); 1410301#L919-1 assume !(0 == ~E_5~0); 1410302#L924-1 assume !(0 == ~E_6~0); 1409773#L929-1 assume !(0 == ~E_7~0); 1409774#L934-1 assume !(0 == ~E_8~0); 1410771#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1409557#L418 assume !(1 == ~m_pc~0); 1409558#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1410579#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1410580#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1410487#L1061 assume !(0 != activate_threads_~tmp~1#1); 1410390#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1410391#L437 assume !(1 == ~t1_pc~0); 1410631#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1410632#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1410437#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1410438#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1410652#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1410653#L456 assume !(1 == ~t2_pc~0); 1409825#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1409824#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1410185#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1410186#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1410157#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1410158#L475 assume !(1 == ~t3_pc~0); 1410232#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1410233#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1410699#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1410700#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1409919#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1409920#L494 assume !(1 == ~t4_pc~0); 1409958#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1409959#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1410176#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1410177#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1410298#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1410299#L513 assume !(1 == ~t5_pc~0); 1409962#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1409963#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1410002#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1409682#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1409683#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1409635#L532 assume !(1 == ~t6_pc~0); 1409636#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1409788#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1410087#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1410167#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1409884#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1409885#L551 assume !(1 == ~t7_pc~0); 1410364#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1410305#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1410306#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1410553#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1410719#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1410720#L570 assume !(1 == ~t8_pc~0); 1410754#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1410753#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1410752#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1410751#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1410750#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1410749#L952 assume !(1 == ~M_E~0); 1410748#L952-2 assume !(1 == ~T1_E~0); 1410747#L957-1 assume !(1 == ~T2_E~0); 1410746#L962-1 assume !(1 == ~T3_E~0); 1410745#L967-1 assume !(1 == ~T4_E~0); 1410744#L972-1 assume !(1 == ~T5_E~0); 1410743#L977-1 assume !(1 == ~T6_E~0); 1410742#L982-1 assume !(1 == ~T7_E~0); 1410741#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1409791#L992-1 assume !(1 == ~E_M~0); 1409802#L997-1 assume !(1 == ~E_1~0); 1410155#L1002-1 assume !(1 == ~E_2~0); 1410143#L1007-1 assume !(1 == ~E_3~0); 1409541#L1012-1 assume !(1 == ~E_4~0); 1409542#L1017-1 assume !(1 == ~E_5~0); 1410146#L1022-1 assume !(1 == ~E_6~0); 1410147#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1410168#L1032-1 assume !(1 == ~E_8~0); 1410339#L1037-1 assume { :end_inline_reset_delta_events } true; 1410340#L1303-2 [2022-11-16 11:31:21,785 INFO L750 eck$LassoCheckResult]: Loop: 1410340#L1303-2 assume !false; 1497161#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1497158#L829 assume !false; 1497155#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1497141#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1497135#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1497133#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1497130#L712 assume !(0 != eval_~tmp~0#1); 1497127#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1497125#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1497123#L854-3 assume !(0 == ~M_E~0); 1497121#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1497119#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1497117#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1497114#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1497112#L874-3 assume !(0 == ~T5_E~0); 1497110#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1497108#L884-3 assume !(0 == ~T7_E~0); 1497105#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1497106#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1504269#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1504268#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1504266#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1504265#L914-3 assume !(0 == ~E_4~0); 1504264#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1504263#L924-3 assume !(0 == ~E_6~0); 1504261#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1504258#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1504256#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1504254#L418-30 assume !(1 == ~m_pc~0); 1504252#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1504250#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1504248#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1504246#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1504244#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1504242#L437-30 assume !(1 == ~t1_pc~0); 1504240#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1504238#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1504234#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1504232#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1504230#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1504228#L456-30 assume !(1 == ~t2_pc~0); 1504032#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1504029#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1504027#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1504025#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1504022#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1504020#L475-30 assume !(1 == ~t3_pc~0); 1504018#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1504016#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1504014#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1504012#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1504010#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1504008#L494-30 assume !(1 == ~t4_pc~0); 1504006#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1504003#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1504001#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1503999#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1503998#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1503995#L513-30 assume !(1 == ~t5_pc~0); 1503993#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1503991#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1503989#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1503987#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1503985#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1503983#L532-30 assume !(1 == ~t6_pc~0); 1503980#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1503978#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1503976#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1503974#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1503972#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1503970#L551-30 assume !(1 == ~t7_pc~0); 1497064#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1497061#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1497059#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1497057#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1497055#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1497053#L570-30 assume !(1 == ~t8_pc~0); 1497051#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1497049#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1497047#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1497045#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1497043#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1497041#L952-3 assume !(1 == ~M_E~0); 1497039#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1497036#L957-3 assume !(1 == ~T2_E~0); 1497034#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1497032#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1497030#L972-3 assume !(1 == ~T5_E~0); 1497028#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1497026#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1496965#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1496963#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1496961#L997-3 assume !(1 == ~E_1~0); 1496959#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1496957#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1496955#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1496952#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1496950#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1496948#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1496946#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1496944#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1496625#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1496623#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1496620#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1445897#L1322 assume !(0 == start_simulation_~tmp~3#1); 1445898#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1497376#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1497367#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1497365#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1497363#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1497361#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1497359#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1497357#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1410340#L1303-2 [2022-11-16 11:31:21,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:21,786 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2022-11-16 11:31:21,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:21,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1379102150] [2022-11-16 11:31:21,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:21,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:21,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:21,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:21,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:21,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1379102150] [2022-11-16 11:31:21,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1379102150] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:21,845 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:21,845 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:21,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143206594] [2022-11-16 11:31:21,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:21,846 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:21,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:21,846 INFO L85 PathProgramCache]: Analyzing trace with hash 362922650, now seen corresponding path program 1 times [2022-11-16 11:31:21,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:21,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829911878] [2022-11-16 11:31:21,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:21,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:21,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:21,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:21,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:21,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1829911878] [2022-11-16 11:31:21,887 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1829911878] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:21,887 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:21,887 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:21,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719612613] [2022-11-16 11:31:21,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:21,888 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:31:21,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:21,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:31:21,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:31:21,888 INFO L87 Difference]: Start difference. First operand 139577 states and 197175 transitions. cyclomatic complexity: 57662 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:22,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:22,315 INFO L93 Difference]: Finished difference Result 122397 states and 172321 transitions. [2022-11-16 11:31:22,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122397 states and 172321 transitions. [2022-11-16 11:31:22,694 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121576 [2022-11-16 11:31:23,672 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122397 states to 122397 states and 172321 transitions. [2022-11-16 11:31:23,672 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122397 [2022-11-16 11:31:23,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122397 [2022-11-16 11:31:23,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122397 states and 172321 transitions. [2022-11-16 11:31:23,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:31:23,788 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122397 states and 172321 transitions. [2022-11-16 11:31:23,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122397 states and 172321 transitions. [2022-11-16 11:31:24,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122397 to 122397. [2022-11-16 11:31:24,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122397 states, 122397 states have (on average 1.4078858141947923) internal successors, (172321), 122396 states have internal predecessors, (172321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:25,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122397 states to 122397 states and 172321 transitions. [2022-11-16 11:31:25,478 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122397 states and 172321 transitions. [2022-11-16 11:31:25,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:31:25,479 INFO L428 stractBuchiCegarLoop]: Abstraction has 122397 states and 172321 transitions. [2022-11-16 11:31:25,481 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 11:31:25,481 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122397 states and 172321 transitions. [2022-11-16 11:31:25,713 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121576 [2022-11-16 11:31:25,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:31:25,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:31:25,714 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:25,714 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:25,715 INFO L748 eck$LassoCheckResult]: Stem: 1672314#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 1672315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1671555#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1671556#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1671589#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1672252#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1672253#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1671847#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1671848#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1671779#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1671780#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1672034#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1672007#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1672008#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1672318#L854 assume !(0 == ~M_E~0); 1672099#L854-2 assume !(0 == ~T1_E~0); 1672100#L859-1 assume !(0 == ~T2_E~0); 1671654#L864-1 assume !(0 == ~T3_E~0); 1671655#L869-1 assume !(0 == ~T4_E~0); 1671767#L874-1 assume !(0 == ~T5_E~0); 1672597#L879-1 assume !(0 == ~T6_E~0); 1672083#L884-1 assume !(0 == ~T7_E~0); 1671522#L889-1 assume !(0 == ~T8_E~0); 1671523#L894-1 assume !(0 == ~E_M~0); 1671860#L899-1 assume !(0 == ~E_1~0); 1672326#L904-1 assume !(0 == ~E_2~0); 1672026#L909-1 assume !(0 == ~E_3~0); 1672027#L914-1 assume !(0 == ~E_4~0); 1672238#L919-1 assume !(0 == ~E_5~0); 1671942#L924-1 assume !(0 == ~E_6~0); 1671754#L929-1 assume !(0 == ~E_7~0); 1671755#L934-1 assume !(0 == ~E_8~0); 1672006#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1671540#L418 assume !(1 == ~m_pc~0); 1671541#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1672535#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1672536#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1672451#L1061 assume !(0 != activate_threads_~tmp~1#1); 1672356#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1672357#L437 assume !(1 == ~t1_pc~0); 1672581#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1672463#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1672400#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1671896#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1671897#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1672445#L456 assume !(1 == ~t2_pc~0); 1671805#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1671804#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1672157#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1672158#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1672130#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1671649#L475 assume !(1 == ~t3_pc~0); 1671650#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1671710#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1671711#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1672583#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1671900#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1671901#L494 assume !(1 == ~t4_pc~0); 1671938#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1671939#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1672148#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1672149#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1672267#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1671706#L513 assume !(1 == ~t5_pc~0); 1671707#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1671941#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1671978#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1671665#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1671666#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1671618#L532 assume !(1 == ~t6_pc~0); 1671619#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1671768#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1672061#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1672140#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1671865#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1671866#L551 assume !(1 == ~t7_pc~0); 1672328#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1672271#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1672272#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1672512#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1672653#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1672044#L570 assume !(1 == ~t8_pc~0); 1672045#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1672558#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1672327#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1672154#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1671647#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1671648#L952 assume !(1 == ~M_E~0); 1671590#L952-2 assume !(1 == ~T1_E~0); 1671591#L957-1 assume !(1 == ~T2_E~0); 1672423#L962-1 assume !(1 == ~T3_E~0); 1672173#L967-1 assume !(1 == ~T4_E~0); 1672174#L972-1 assume !(1 == ~T5_E~0); 1672492#L977-1 assume !(1 == ~T6_E~0); 1672493#L982-1 assume !(1 == ~T7_E~0); 1671770#L987-1 assume !(1 == ~T8_E~0); 1671771#L992-1 assume !(1 == ~E_M~0); 1671781#L997-1 assume !(1 == ~E_1~0); 1672127#L1002-1 assume !(1 == ~E_2~0); 1672115#L1007-1 assume !(1 == ~E_3~0); 1671524#L1012-1 assume !(1 == ~E_4~0); 1671525#L1017-1 assume !(1 == ~E_5~0); 1672118#L1022-1 assume !(1 == ~E_6~0); 1672119#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1672141#L1032-1 assume !(1 == ~E_8~0); 1672302#L1037-1 assume { :end_inline_reset_delta_events } true; 1672303#L1303-2 [2022-11-16 11:31:25,715 INFO L750 eck$LassoCheckResult]: Loop: 1672303#L1303-2 assume !false; 1705124#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1705122#L829 assume !false; 1705120#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1705072#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1705063#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1705057#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1705048#L712 assume !(0 != eval_~tmp~0#1); 1705049#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1705329#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1705328#L854-3 assume !(0 == ~M_E~0); 1705327#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1705326#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1705325#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1705324#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1705323#L874-3 assume !(0 == ~T5_E~0); 1705322#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1705321#L884-3 assume !(0 == ~T7_E~0); 1705320#L889-3 assume !(0 == ~T8_E~0); 1705319#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1705318#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1705317#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1705316#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1705315#L914-3 assume !(0 == ~E_4~0); 1705314#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1705313#L924-3 assume !(0 == ~E_6~0); 1705312#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1705311#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1705310#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1705309#L418-30 assume !(1 == ~m_pc~0); 1705308#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1705307#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1705306#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1705305#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1705304#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1705303#L437-30 assume !(1 == ~t1_pc~0); 1705302#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1705301#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1705300#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1705299#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1705298#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1705297#L456-30 assume 1 == ~t2_pc~0; 1705295#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1705294#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1705293#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1705292#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1705291#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1705290#L475-30 assume !(1 == ~t3_pc~0); 1705289#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1705288#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1705286#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1705284#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1705282#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1705280#L494-30 assume !(1 == ~t4_pc~0); 1705278#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1705275#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1705273#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1705271#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1705269#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1705267#L513-30 assume !(1 == ~t5_pc~0); 1705265#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1705263#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1705261#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1705258#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1705256#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1705254#L532-30 assume !(1 == ~t6_pc~0); 1705251#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1705249#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1705247#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1705245#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1705243#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1705241#L551-30 assume !(1 == ~t7_pc~0); 1705239#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1705237#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1705235#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1705232#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1705230#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1705228#L570-30 assume !(1 == ~t8_pc~0); 1705226#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1705224#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1705222#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1705219#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1705217#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1705215#L952-3 assume !(1 == ~M_E~0); 1705213#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1705211#L957-3 assume !(1 == ~T2_E~0); 1705209#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1705206#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1705205#L972-3 assume !(1 == ~T5_E~0); 1705204#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1705203#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1705202#L987-3 assume !(1 == ~T8_E~0); 1705201#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1705200#L997-3 assume !(1 == ~E_1~0); 1705199#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1705198#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1705196#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1705194#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1705192#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1705190#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1705188#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1705186#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1705166#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1705164#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1705162#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1705159#L1322 assume !(0 == start_simulation_~tmp~3#1); 1705157#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1705151#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1705142#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1705139#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1705137#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1705135#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1705133#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1705131#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1672303#L1303-2 [2022-11-16 11:31:25,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:25,716 INFO L85 PathProgramCache]: Analyzing trace with hash 1031757063, now seen corresponding path program 1 times [2022-11-16 11:31:25,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:25,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301163007] [2022-11-16 11:31:25,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:25,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:25,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:25,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:25,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:25,779 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301163007] [2022-11-16 11:31:25,780 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301163007] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:25,780 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:25,780 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:25,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1959013842] [2022-11-16 11:31:25,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:25,781 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:31:25,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:25,781 INFO L85 PathProgramCache]: Analyzing trace with hash -336267623, now seen corresponding path program 1 times [2022-11-16 11:31:25,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:25,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324842772] [2022-11-16 11:31:25,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:25,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:25,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:25,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:31:25,820 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:25,820 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324842772] [2022-11-16 11:31:25,820 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324842772] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:25,821 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:25,821 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:25,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072791979] [2022-11-16 11:31:25,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:25,821 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:31:25,822 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:25,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:31:25,822 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:31:25,822 INFO L87 Difference]: Start difference. First operand 122397 states and 172321 transitions. cyclomatic complexity: 49988 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:31:26,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:26,374 INFO L93 Difference]: Finished difference Result 190541 states and 267918 transitions. [2022-11-16 11:31:26,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190541 states and 267918 transitions. [2022-11-16 11:31:27,707 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 189178 [2022-11-16 11:31:28,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190541 states to 190541 states and 267918 transitions. [2022-11-16 11:31:28,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 190541 [2022-11-16 11:31:28,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 190541 [2022-11-16 11:31:28,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 190541 states and 267918 transitions. [2022-11-16 11:31:28,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:31:28,245 INFO L218 hiAutomatonCegarLoop]: Abstraction has 190541 states and 267918 transitions.