./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:06:59,730 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:06:59,738 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:06:59,781 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:06:59,783 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:06:59,787 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:06:59,790 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:06:59,794 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:06:59,798 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:06:59,805 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:06:59,807 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:06:59,810 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:06:59,811 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:06:59,814 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:06:59,815 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:06:59,819 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:06:59,821 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:06:59,822 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:06:59,824 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:06:59,832 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:06:59,834 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:06:59,840 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:06:59,843 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:06:59,845 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:06:59,855 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:06:59,855 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:06:59,856 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:06:59,858 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:06:59,859 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:06:59,860 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:06:59,861 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:06:59,862 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:06:59,864 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:06:59,867 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:06:59,870 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:06:59,870 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:06:59,871 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:06:59,871 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:06:59,872 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:06:59,873 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:06:59,873 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:06:59,874 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 11:06:59,924 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:06:59,924 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:06:59,925 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:06:59,926 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:06:59,927 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:06:59,928 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:06:59,928 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:06:59,928 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 11:06:59,929 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 11:06:59,929 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 11:06:59,930 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 11:06:59,931 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 11:06:59,931 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 11:06:59,931 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:06:59,931 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 11:06:59,932 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 11:06:59,932 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:06:59,932 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 11:06:59,932 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:06:59,933 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 11:06:59,933 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 11:06:59,933 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 11:06:59,933 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 11:06:59,935 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:06:59,936 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 11:06:59,936 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:06:59,936 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 11:06:59,936 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:06:59,937 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:06:59,937 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:06:59,937 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:06:59,939 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 11:06:59,940 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 [2022-11-16 11:07:00,324 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:07:00,361 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:07:00,365 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:07:00,366 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:07:00,368 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:07:00,369 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/token_ring.15.cil.c [2022-11-16 11:07:00,452 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/data/c32ee4da2/1db4fe256c424596a4ce79b34892113c/FLAGdce91756d [2022-11-16 11:07:01,089 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:07:01,089 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/sv-benchmarks/c/systemc/token_ring.15.cil.c [2022-11-16 11:07:01,107 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/data/c32ee4da2/1db4fe256c424596a4ce79b34892113c/FLAGdce91756d [2022-11-16 11:07:01,393 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/data/c32ee4da2/1db4fe256c424596a4ce79b34892113c [2022-11-16 11:07:01,399 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:07:01,401 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:07:01,403 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:07:01,403 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:07:01,411 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:07:01,412 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:07:01" (1/1) ... [2022-11-16 11:07:01,414 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@14bce213 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:01, skipping insertion in model container [2022-11-16 11:07:01,414 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:07:01" (1/1) ... [2022-11-16 11:07:01,424 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:07:01,510 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:07:01,722 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2022-11-16 11:07:01,955 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:07:01,968 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:07:01,992 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2022-11-16 11:07:02,135 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:07:02,167 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:07:02,168 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02 WrapperNode [2022-11-16 11:07:02,169 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:07:02,170 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:07:02,171 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:07:02,171 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:07:02,180 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,211 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,392 INFO L138 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4663 [2022-11-16 11:07:02,393 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:07:02,394 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:07:02,394 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:07:02,394 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:07:02,406 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,406 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,423 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,424 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,481 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,532 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,539 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,552 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,570 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:07:02,571 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:07:02,571 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:07:02,572 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:07:02,573 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (1/1) ... [2022-11-16 11:07:02,580 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:07:02,593 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:07:02,610 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:07:02,638 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d2cac33a-96bf-4f21-803d-9ba486f1db19/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 11:07:02,668 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 11:07:02,669 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 11:07:02,669 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:07:02,669 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:07:02,886 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:07:02,901 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:07:06,189 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:07:06,223 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:07:06,223 INFO L300 CfgBuilder]: Removed 16 assume(true) statements. [2022-11-16 11:07:06,232 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:07:06 BoogieIcfgContainer [2022-11-16 11:07:06,232 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:07:06,234 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 11:07:06,234 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 11:07:06,239 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 11:07:06,240 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:07:06,240 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 11:07:01" (1/3) ... [2022-11-16 11:07:06,242 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@77b1e49e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:07:06, skipping insertion in model container [2022-11-16 11:07:06,242 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:07:06,242 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:07:02" (2/3) ... [2022-11-16 11:07:06,243 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@77b1e49e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:07:06, skipping insertion in model container [2022-11-16 11:07:06,243 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:07:06,243 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:07:06" (3/3) ... [2022-11-16 11:07:06,246 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.15.cil.c [2022-11-16 11:07:06,368 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 11:07:06,369 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 11:07:06,369 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 11:07:06,369 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 11:07:06,369 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 11:07:06,370 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 11:07:06,370 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 11:07:06,370 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 11:07:06,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:06,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1850 [2022-11-16 11:07:06,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:06,509 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:06,530 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:06,544 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:06,544 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 11:07:06,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:06,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1850 [2022-11-16 11:07:06,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:06,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:06,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:06,609 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:06,625 INFO L748 eck$LassoCheckResult]: Stem: 461#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1952#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 301#L1898true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1869#L902true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1829#L909true assume !(1 == ~m_i~0);~m_st~0 := 2; 1940#L909-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 409#L914-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 433#L919-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1229#L924-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1101#L929-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1857#L934-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1267#L939-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1671#L944-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 304#L949-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1320#L954-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1961#L959-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 630#L964-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1171#L969-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 1762#L974-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1910#L1286true assume 0 == ~M_E~0;~M_E~0 := 1; 1444#L1286-2true assume !(0 == ~T1_E~0); 256#L1291-1true assume !(0 == ~T2_E~0); 1844#L1296-1true assume !(0 == ~T3_E~0); 690#L1301-1true assume !(0 == ~T4_E~0); 1216#L1306-1true assume !(0 == ~T5_E~0); 1184#L1311-1true assume !(0 == ~T6_E~0); 234#L1316-1true assume !(0 == ~T7_E~0); 1680#L1321-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 705#L1326-1true assume !(0 == ~T9_E~0); 140#L1331-1true assume !(0 == ~T10_E~0); 4#L1336-1true assume !(0 == ~T11_E~0); 1064#L1341-1true assume !(0 == ~T12_E~0); 28#L1346-1true assume !(0 == ~T13_E~0); 1488#L1351-1true assume !(0 == ~E_M~0); 204#L1356-1true assume !(0 == ~E_1~0); 1969#L1361-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1647#L1366-1true assume !(0 == ~E_3~0); 229#L1371-1true assume !(0 == ~E_4~0); 1451#L1376-1true assume !(0 == ~E_5~0); 742#L1381-1true assume !(0 == ~E_6~0); 1737#L1386-1true assume !(0 == ~E_7~0); 1881#L1391-1true assume !(0 == ~E_8~0); 1793#L1396-1true assume !(0 == ~E_9~0); 653#L1401-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1279#L1406-1true assume !(0 == ~E_11~0); 900#L1411-1true assume !(0 == ~E_12~0); 1703#L1416-1true assume !(0 == ~E_13~0); 605#L1421-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 498#L635true assume !(1 == ~m_pc~0); 37#L635-2true is_master_triggered_~__retres1~0#1 := 0; 200#L646true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 583#L647true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1304#L1598true assume !(0 != activate_threads_~tmp~1#1); 120#L1598-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 568#L654true assume 1 == ~t1_pc~0; 509#L655true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1727#L665true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1923#L666true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 567#L1606true assume !(0 != activate_threads_~tmp___0~0#1); 817#L1606-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 142#L673true assume 1 == ~t2_pc~0; 1784#L674true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 870#L684true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1856#L685true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1884#L1614true assume !(0 != activate_threads_~tmp___1~0#1); 1984#L1614-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 620#L692true assume !(1 == ~t3_pc~0); 499#L692-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1776#L703true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 411#L704true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 389#L1622true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1709#L1622-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153#L711true assume 1 == ~t4_pc~0; 420#L712true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1315#L722true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 722#L723true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15#L1630true assume !(0 != activate_threads_~tmp___3~0#1); 1830#L1630-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1827#L730true assume !(1 == ~t5_pc~0); 1965#L730-2true is_transmit5_triggered_~__retres1~5#1 := 0; 100#L741true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 275#L742true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 157#L1638true assume !(0 != activate_threads_~tmp___4~0#1); 341#L1638-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 868#L749true assume 1 == ~t6_pc~0; 217#L750true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 410#L760true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 324#L761true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1447#L1646true assume !(0 != activate_threads_~tmp___5~0#1); 457#L1646-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6#L768true assume !(1 == ~t7_pc~0); 1660#L768-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1383#L779true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117#L780true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1359#L1654true assume !(0 != activate_threads_~tmp___6~0#1); 779#L1654-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 235#L787true assume 1 == ~t8_pc~0; 1117#L788true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1689#L798true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1372#L799true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1899#L1662true assume !(0 != activate_threads_~tmp___7~0#1); 27#L1662-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1185#L806true assume 1 == ~t9_pc~0; 1130#L807true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44#L817true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 805#L818true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 158#L1670true assume !(0 != activate_threads_~tmp___8~0#1); 1592#L1670-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1109#L825true assume !(1 == ~t10_pc~0); 1377#L825-2true is_transmit10_triggered_~__retres1~10#1 := 0; 735#L836true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 844#L837true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 201#L1678true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2016#L1678-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 540#L844true assume 1 == ~t11_pc~0; 352#L845true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1258#L855true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 587#L856true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1167#L1686true assume !(0 != activate_threads_~tmp___10~0#1); 1096#L1686-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1399#L863true assume !(1 == ~t12_pc~0); 1459#L863-2true is_transmit12_triggered_~__retres1~12#1 := 0; 194#L874true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1525#L875true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1223#L1694true assume !(0 != activate_threads_~tmp___11~0#1); 1616#L1694-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 628#L882true assume 1 == ~t13_pc~0; 899#L883true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1851#L893true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1547#L894true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1174#L1702true assume !(0 != activate_threads_~tmp___12~0#1); 841#L1702-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1573#L1434true assume !(1 == ~M_E~0); 1939#L1434-2true assume !(1 == ~T1_E~0); 1849#L1439-1true assume !(1 == ~T2_E~0); 150#L1444-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 904#L1449-1true assume !(1 == ~T4_E~0); 387#L1454-1true assume !(1 == ~T5_E~0); 1483#L1459-1true assume !(1 == ~T6_E~0); 780#L1464-1true assume !(1 == ~T7_E~0); 850#L1469-1true assume !(1 == ~T8_E~0); 1724#L1474-1true assume !(1 == ~T9_E~0); 606#L1479-1true assume !(1 == ~T10_E~0); 788#L1484-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1247#L1489-1true assume !(1 == ~T12_E~0); 519#L1494-1true assume !(1 == ~T13_E~0); 1835#L1499-1true assume !(1 == ~E_M~0); 644#L1504-1true assume !(1 == ~E_1~0); 1533#L1509-1true assume !(1 == ~E_2~0); 1246#L1514-1true assume !(1 == ~E_3~0); 879#L1519-1true assume !(1 == ~E_4~0); 1953#L1524-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1691#L1529-1true assume !(1 == ~E_6~0); 1766#L1534-1true assume !(1 == ~E_7~0); 52#L1539-1true assume !(1 == ~E_8~0); 266#L1544-1true assume !(1 == ~E_9~0); 1608#L1549-1true assume !(1 == ~E_10~0); 1632#L1554-1true assume !(1 == ~E_11~0); 1605#L1559-1true assume !(1 == ~E_12~0); 1305#L1564-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1672#L1569-1true assume { :end_inline_reset_delta_events } true; 1980#L1935-2true [2022-11-16 11:07:06,628 INFO L750 eck$LassoCheckResult]: Loop: 1980#L1935-2true assume !false; 56#L1936true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1721#L1261true assume false; 813#L1276true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1260#L902-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1348#L1286-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1482#L1286-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 964#L1291-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1860#L1296-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1771#L1301-3true assume !(0 == ~T4_E~0); 1631#L1306-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 578#L1311-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 164#L1316-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 221#L1321-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 666#L1326-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1596#L1331-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 882#L1336-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1518#L1341-3true assume !(0 == ~T12_E~0); 383#L1346-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 375#L1351-3true assume 0 == ~E_M~0;~E_M~0 := 1; 347#L1356-3true assume 0 == ~E_1~0;~E_1~0 := 1; 727#L1361-3true assume 0 == ~E_2~0;~E_2~0 := 1; 756#L1366-3true assume 0 == ~E_3~0;~E_3~0 := 1; 22#L1371-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1275#L1376-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1562#L1381-3true assume !(0 == ~E_6~0); 1067#L1386-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1695#L1391-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1324#L1396-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1976#L1401-3true assume 0 == ~E_10~0;~E_10~0 := 1; 199#L1406-3true assume 0 == ~E_11~0;~E_11~0 := 1; 121#L1411-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1770#L1416-3true assume 0 == ~E_13~0;~E_13~0 := 1; 465#L1421-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65#L635-45true assume !(1 == ~m_pc~0); 757#L635-47true is_master_triggered_~__retres1~0#1 := 0; 842#L646-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1405#L647-15true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1095#L1598-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 210#L1598-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 719#L654-45true assume !(1 == ~t1_pc~0); 1842#L654-47true is_transmit1_triggered_~__retres1~1#1 := 0; 1037#L665-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47#L666-15true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58#L1606-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1445#L1606-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 504#L673-45true assume 1 == ~t2_pc~0; 852#L674-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 731#L684-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1560#L685-15true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1496#L1614-45true assume !(0 != activate_threads_~tmp___1~0#1); 1170#L1614-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 281#L692-45true assume 1 == ~t3_pc~0; 1757#L693-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1200#L703-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 785#L704-15true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 308#L1622-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 497#L1622-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2012#L711-45true assume 1 == ~t4_pc~0; 582#L712-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1970#L722-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 483#L723-15true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1694#L1630-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 764#L1630-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223#L730-45true assume 1 == ~t5_pc~0; 143#L731-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2030#L741-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 358#L742-15true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 887#L1638-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 990#L1638-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131#L749-45true assume 1 == ~t6_pc~0; 1111#L750-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1204#L760-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 865#L761-15true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1412#L1646-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1013#L1646-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 294#L768-45true assume !(1 == ~t7_pc~0); 428#L768-47true is_transmit7_triggered_~__retres1~7#1 := 0; 1172#L779-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 953#L780-15true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1840#L1654-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 992#L1654-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1897#L787-45true assume !(1 == ~t8_pc~0); 2019#L787-47true is_transmit8_triggered_~__retres1~8#1 := 0; 372#L798-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1682#L799-15true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 643#L1662-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 886#L1662-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1764#L806-45true assume 1 == ~t9_pc~0; 1614#L807-15true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 520#L817-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1135#L818-15true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 417#L1670-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 360#L1670-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1816#L825-45true assume !(1 == ~t10_pc~0); 701#L825-47true is_transmit10_triggered_~__retres1~10#1 := 0; 1836#L836-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 792#L837-15true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 921#L1678-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1014#L1678-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 170#L844-45true assume !(1 == ~t11_pc~0); 1535#L844-47true is_transmit11_triggered_~__retres1~11#1 := 0; 466#L855-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 476#L856-15true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 761#L1686-45true assume !(0 != activate_threads_~tmp___10~0#1); 1329#L1686-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 188#L863-45true assume !(1 == ~t12_pc~0); 647#L863-47true is_transmit12_triggered_~__retres1~12#1 := 0; 3#L874-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1422#L875-15true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 254#L1694-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 768#L1694-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1106#L882-45true assume !(1 == ~t13_pc~0); 445#L882-47true is_transmit13_triggered_~__retres1~13#1 := 0; 11#L893-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 315#L894-15true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1314#L1702-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1368#L1702-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 854#L1434-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1070#L1434-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1035#L1439-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 148#L1444-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 230#L1449-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1630#L1454-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 847#L1459-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 2007#L1464-3true assume !(1 == ~T7_E~0); 1406#L1469-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1278#L1474-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1638#L1479-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1414#L1484-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 581#L1489-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1166#L1494-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1790#L1499-3true assume 1 == ~E_M~0;~E_M~0 := 2; 794#L1504-3true assume !(1 == ~E_1~0); 1293#L1509-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1357#L1514-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1891#L1519-3true assume 1 == ~E_4~0;~E_4~0 := 2; 521#L1524-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1469#L1529-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1690#L1534-3true assume 1 == ~E_7~0;~E_7~0 := 2; 734#L1539-3true assume 1 == ~E_8~0;~E_8~0 := 2; 368#L1544-3true assume !(1 == ~E_9~0); 1421#L1549-3true assume 1 == ~E_10~0;~E_10~0 := 2; 706#L1554-3true assume 1 == ~E_11~0;~E_11~0 := 2; 172#L1559-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1191#L1564-3true assume 1 == ~E_13~0;~E_13~0 := 2; 932#L1569-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1110#L987-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 426#L1059-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1098#L1060-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 913#L1954true assume !(0 == start_simulation_~tmp~3#1); 1673#L1954-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1193#L987-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 989#L1059-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1380#L1060-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1149#L1909true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1287#L1916true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1397#L1917true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1792#L1967true assume !(0 != start_simulation_~tmp___0~1#1); 1980#L1935-2true [2022-11-16 11:07:06,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:06,638 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2022-11-16 11:07:06,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:06,650 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279009016] [2022-11-16 11:07:06,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:06,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:06,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:07,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:07,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:07,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [279009016] [2022-11-16 11:07:07,215 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [279009016] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:07,215 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:07,215 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:07,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291419771] [2022-11-16 11:07:07,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:07,224 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:07,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:07,225 INFO L85 PathProgramCache]: Analyzing trace with hash 1082867769, now seen corresponding path program 1 times [2022-11-16 11:07:07,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:07,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818070173] [2022-11-16 11:07:07,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:07,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:07,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:07,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:07,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:07,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818070173] [2022-11-16 11:07:07,298 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818070173] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:07,299 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:07,299 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:07:07,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343021697] [2022-11-16 11:07:07,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:07,301 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:07,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:07,342 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-16 11:07:07,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 11:07:07,349 INFO L87 Difference]: Start difference. First operand has 2029 states, 2028 states have (on average 1.4960552268244576) internal successors, (3034), 2028 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:07,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:07,440 INFO L93 Difference]: Finished difference Result 2027 states and 2998 transitions. [2022-11-16 11:07:07,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2027 states and 2998 transitions. [2022-11-16 11:07:07,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:07,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2027 states to 2021 states and 2992 transitions. [2022-11-16 11:07:07,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:07,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:07,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2992 transitions. [2022-11-16 11:07:07,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:07,510 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2022-11-16 11:07:07,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2992 transitions. [2022-11-16 11:07:07,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:07,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4804552201880257) internal successors, (2992), 2020 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:07,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2992 transitions. [2022-11-16 11:07:07,633 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2022-11-16 11:07:07,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-16 11:07:07,643 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2992 transitions. [2022-11-16 11:07:07,644 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 11:07:07,644 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2992 transitions. [2022-11-16 11:07:07,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:07,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:07,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:07,664 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:07,664 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:07,665 INFO L748 eck$LassoCheckResult]: Stem: 4941#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4673#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4674#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6064#L909 assume !(1 == ~m_i~0);~m_st~0 := 2; 6065#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4860#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4861#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4895#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5732#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5733#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5845#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5846#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4679#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4680#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5882#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5204#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5205#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5786#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6052#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 5942#L1286-2 assume !(0 == ~T1_E~0); 4588#L1291-1 assume !(0 == ~T2_E~0); 4589#L1296-1 assume !(0 == ~T3_E~0); 5294#L1301-1 assume !(0 == ~T4_E~0); 5295#L1306-1 assume !(0 == ~T5_E~0); 5795#L1311-1 assume !(0 == ~T6_E~0); 4548#L1316-1 assume !(0 == ~T7_E~0); 4549#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5314#L1326-1 assume !(0 == ~T9_E~0); 4363#L1331-1 assume !(0 == ~T10_E~0); 4069#L1336-1 assume !(0 == ~T11_E~0); 4070#L1341-1 assume !(0 == ~T12_E~0); 4121#L1346-1 assume !(0 == ~T13_E~0); 4122#L1351-1 assume !(0 == ~E_M~0); 4495#L1356-1 assume !(0 == ~E_1~0); 4496#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 6015#L1366-1 assume !(0 == ~E_3~0); 4541#L1371-1 assume !(0 == ~E_4~0); 4542#L1376-1 assume !(0 == ~E_5~0); 5355#L1381-1 assume !(0 == ~E_6~0); 5356#L1386-1 assume !(0 == ~E_7~0); 6043#L1391-1 assume !(0 == ~E_8~0); 6056#L1396-1 assume !(0 == ~E_9~0); 5238#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5239#L1406-1 assume !(0 == ~E_11~0); 5541#L1411-1 assume !(0 == ~E_12~0); 5542#L1416-1 assume !(0 == ~E_13~0); 5162#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5000#L635 assume !(1 == ~m_pc~0); 4139#L635-2 is_master_triggered_~__retres1~0#1 := 0; 4140#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4490#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5126#L1598 assume !(0 != activate_threads_~tmp~1#1); 4318#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4319#L654 assume 1 == ~t1_pc~0; 5024#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5025#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6040#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5106#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 5107#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4366#L673 assume 1 == ~t2_pc~0; 4367#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5511#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5512#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6070#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 6077#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5185#L692 assume !(1 == ~t3_pc~0); 5002#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5003#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4862#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4830#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4831#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4391#L711 assume 1 == ~t4_pc~0; 4392#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4875#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5332#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4094#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 4095#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6063#L730 assume !(1 == ~t5_pc~0); 5445#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4273#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4274#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4401#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 4402#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4744#L749 assume 1 == ~t6_pc~0; 4518#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4278#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4710#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4711#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 4933#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4074#L768 assume !(1 == ~t7_pc~0); 4075#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5379#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4311#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4312#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 5398#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4550#L787 assume 1 == ~t8_pc~0; 4551#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5746#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5910#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5911#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 4119#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4120#L806 assume 1 == ~t9_pc~0; 5757#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4154#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4155#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4403#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 4404#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5740#L825 assume !(1 == ~t10_pc~0); 5741#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5346#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5347#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4491#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4492#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5075#L844 assume 1 == ~t11_pc~0; 4765#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4766#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5132#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5133#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 5728#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5729#L863 assume !(1 == ~t12_pc~0); 4254#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4253#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4481#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5820#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 5821#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5199#L882 assume 1 == ~t13_pc~0; 5200#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5484#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5985#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5788#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 5471#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5472#L1434 assume !(1 == ~M_E~0); 5993#L1434-2 assume !(1 == ~T1_E~0); 6069#L1439-1 assume !(1 == ~T2_E~0); 4384#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4385#L1449-1 assume !(1 == ~T4_E~0); 4827#L1454-1 assume !(1 == ~T5_E~0); 4828#L1459-1 assume !(1 == ~T6_E~0); 5399#L1464-1 assume !(1 == ~T7_E~0); 5400#L1469-1 assume !(1 == ~T8_E~0); 5485#L1474-1 assume !(1 == ~T9_E~0); 5163#L1479-1 assume !(1 == ~T10_E~0); 5164#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5407#L1489-1 assume !(1 == ~T12_E~0); 5041#L1494-1 assume !(1 == ~T13_E~0); 5042#L1499-1 assume !(1 == ~E_M~0); 5223#L1504-1 assume !(1 == ~E_1~0); 5224#L1509-1 assume !(1 == ~E_2~0); 5837#L1514-1 assume !(1 == ~E_3~0); 5522#L1519-1 assume !(1 == ~E_4~0); 5523#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6027#L1529-1 assume !(1 == ~E_6~0); 6028#L1534-1 assume !(1 == ~E_7~0); 4174#L1539-1 assume !(1 == ~E_8~0); 4175#L1544-1 assume !(1 == ~E_9~0); 4605#L1549-1 assume !(1 == ~E_10~0); 6005#L1554-1 assume !(1 == ~E_11~0); 6003#L1559-1 assume !(1 == ~E_12~0); 5865#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 5866#L1569-1 assume { :end_inline_reset_delta_events } true; 6021#L1935-2 [2022-11-16 11:07:07,666 INFO L750 eck$LassoCheckResult]: Loop: 6021#L1935-2 assume !false; 4183#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4184#L1261 assume !false; 5411#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5412#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4314#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4484#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4485#L1074 assume !(0 != eval_~tmp~0#1); 4842#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5440#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5841#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5897#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5616#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5617#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6053#L1301-3 assume !(0 == ~T4_E~0); 6011#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5119#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4418#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4419#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4524#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5260#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5525#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5526#L1341-3 assume !(0 == ~T12_E~0); 4820#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4811#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4755#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4756#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5336#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4109#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4110#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5852#L1381-3 assume !(0 == ~E_6~0); 5701#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5702#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5883#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5884#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4489#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4320#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4321#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 4948#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4198#L635-45 assume 1 == ~m_pc~0; 4199#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4993#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5473#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5727#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4507#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4508#L654-45 assume 1 == ~t1_pc~0; 5328#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5676#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4161#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4162#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4187#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5014#L673-45 assume !(1 == ~t2_pc~0); 5015#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5339#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5340#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5965#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 5785#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4632#L692-45 assume !(1 == ~t3_pc~0); 4358#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 4359#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5403#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4686#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4687#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4999#L711-45 assume 1 == ~t4_pc~0; 5123#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5124#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4976#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4977#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5380#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4531#L730-45 assume 1 == ~t5_pc~0; 4369#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4370#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4779#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4780#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5531#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4342#L749-45 assume !(1 == ~t6_pc~0); 4343#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 5743#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5506#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5507#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5658#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4658#L768-45 assume 1 == ~t7_pc~0; 4659#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4798#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5602#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5603#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5642#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5643#L787-45 assume 1 == ~t8_pc~0; 5811#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4804#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4805#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5221#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5222#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5530#L806-45 assume 1 == ~t9_pc~0; 6006#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4218#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5043#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4871#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4783#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4784#L825-45 assume 1 == ~t10_pc~0; 5395#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5308#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5413#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5414#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5566#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4426#L844-45 assume !(1 == ~t11_pc~0); 4427#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4949#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4950#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4966#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 5377#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4466#L863-45 assume 1 == ~t12_pc~0; 4467#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4067#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4068#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4583#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4584#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5383#L882-45 assume !(1 == ~t13_pc~0); 4913#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 4086#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4087#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4695#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5874#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5490#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5491#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5675#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4380#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4381#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4543#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5480#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5481#L1464-3 assume !(1 == ~T7_E~0); 5927#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5854#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5855#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5929#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5121#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5122#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5782#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5417#L1504-3 assume !(1 == ~E_1~0); 5418#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5863#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5903#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5044#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5045#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5950#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5345#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4799#L1544-3 assume !(1 == ~E_9~0); 4800#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5315#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4431#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4432#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5581#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5582#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4316#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4881#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5552#L1954 assume !(0 == start_simulation_~tmp~3#1); 5554#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5804#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4599#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5640#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5770#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5771#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5861#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5923#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 6021#L1935-2 [2022-11-16 11:07:07,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:07,669 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2022-11-16 11:07:07,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:07,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972567548] [2022-11-16 11:07:07,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:07,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:07,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:07,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:07,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:07,891 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972567548] [2022-11-16 11:07:07,892 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972567548] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:07,892 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:07,892 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:07,893 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496205899] [2022-11-16 11:07:07,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:07,893 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:07,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:07,894 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 1 times [2022-11-16 11:07:07,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:07,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438398362] [2022-11-16 11:07:07,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:07,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:07,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:08,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:08,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:08,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [438398362] [2022-11-16 11:07:08,166 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [438398362] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:08,166 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:08,166 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:08,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1968693460] [2022-11-16 11:07:08,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:08,167 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:08,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:08,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:08,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:08,170 INFO L87 Difference]: Start difference. First operand 2021 states and 2992 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:08,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:08,245 INFO L93 Difference]: Finished difference Result 2021 states and 2991 transitions. [2022-11-16 11:07:08,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2991 transitions. [2022-11-16 11:07:08,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:08,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2991 transitions. [2022-11-16 11:07:08,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:08,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:08,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2991 transitions. [2022-11-16 11:07:08,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:08,283 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2022-11-16 11:07:08,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2991 transitions. [2022-11-16 11:07:08,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:08,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.479960415635824) internal successors, (2991), 2020 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:08,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2991 transitions. [2022-11-16 11:07:08,327 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2022-11-16 11:07:08,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:08,329 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2991 transitions. [2022-11-16 11:07:08,329 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 11:07:08,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2991 transitions. [2022-11-16 11:07:08,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:08,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:08,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:08,352 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:08,353 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:08,354 INFO L748 eck$LassoCheckResult]: Stem: 8990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8722#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8723#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10113#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 10114#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8909#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8910#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8944#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9781#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9782#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9894#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9895#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8728#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8729#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9931#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9253#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9254#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9835#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10101#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 9991#L1286-2 assume !(0 == ~T1_E~0); 8637#L1291-1 assume !(0 == ~T2_E~0); 8638#L1296-1 assume !(0 == ~T3_E~0); 9343#L1301-1 assume !(0 == ~T4_E~0); 9344#L1306-1 assume !(0 == ~T5_E~0); 9844#L1311-1 assume !(0 == ~T6_E~0); 8597#L1316-1 assume !(0 == ~T7_E~0); 8598#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9363#L1326-1 assume !(0 == ~T9_E~0); 8412#L1331-1 assume !(0 == ~T10_E~0); 8118#L1336-1 assume !(0 == ~T11_E~0); 8119#L1341-1 assume !(0 == ~T12_E~0); 8170#L1346-1 assume !(0 == ~T13_E~0); 8171#L1351-1 assume !(0 == ~E_M~0); 8544#L1356-1 assume !(0 == ~E_1~0); 8545#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10064#L1366-1 assume !(0 == ~E_3~0); 8590#L1371-1 assume !(0 == ~E_4~0); 8591#L1376-1 assume !(0 == ~E_5~0); 9404#L1381-1 assume !(0 == ~E_6~0); 9405#L1386-1 assume !(0 == ~E_7~0); 10092#L1391-1 assume !(0 == ~E_8~0); 10105#L1396-1 assume !(0 == ~E_9~0); 9287#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9288#L1406-1 assume !(0 == ~E_11~0); 9590#L1411-1 assume !(0 == ~E_12~0); 9591#L1416-1 assume !(0 == ~E_13~0); 9211#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9049#L635 assume !(1 == ~m_pc~0); 8188#L635-2 is_master_triggered_~__retres1~0#1 := 0; 8189#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8539#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9175#L1598 assume !(0 != activate_threads_~tmp~1#1); 8367#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8368#L654 assume 1 == ~t1_pc~0; 9073#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9074#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10089#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9155#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 9156#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8415#L673 assume 1 == ~t2_pc~0; 8416#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9560#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9561#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10119#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 10126#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9234#L692 assume !(1 == ~t3_pc~0); 9051#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9052#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8911#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8879#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8880#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8440#L711 assume 1 == ~t4_pc~0; 8441#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8924#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9381#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8143#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 8144#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10112#L730 assume !(1 == ~t5_pc~0); 9494#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8322#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8323#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8450#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 8451#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8793#L749 assume 1 == ~t6_pc~0; 8567#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8327#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8759#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8760#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 8982#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8123#L768 assume !(1 == ~t7_pc~0); 8124#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9428#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8360#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8361#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 9447#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8599#L787 assume 1 == ~t8_pc~0; 8600#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9795#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9959#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9960#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 8168#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8169#L806 assume 1 == ~t9_pc~0; 9806#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8203#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8204#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8452#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 8453#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9789#L825 assume !(1 == ~t10_pc~0); 9790#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9395#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9396#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8540#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8541#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9124#L844 assume 1 == ~t11_pc~0; 8814#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8815#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9181#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9182#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 9777#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9778#L863 assume !(1 == ~t12_pc~0); 8303#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8302#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8530#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9869#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 9870#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9248#L882 assume 1 == ~t13_pc~0; 9249#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9533#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 10034#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9837#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 9520#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9521#L1434 assume !(1 == ~M_E~0); 10042#L1434-2 assume !(1 == ~T1_E~0); 10118#L1439-1 assume !(1 == ~T2_E~0); 8433#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8434#L1449-1 assume !(1 == ~T4_E~0); 8876#L1454-1 assume !(1 == ~T5_E~0); 8877#L1459-1 assume !(1 == ~T6_E~0); 9448#L1464-1 assume !(1 == ~T7_E~0); 9449#L1469-1 assume !(1 == ~T8_E~0); 9534#L1474-1 assume !(1 == ~T9_E~0); 9212#L1479-1 assume !(1 == ~T10_E~0); 9213#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9456#L1489-1 assume !(1 == ~T12_E~0); 9090#L1494-1 assume !(1 == ~T13_E~0); 9091#L1499-1 assume !(1 == ~E_M~0); 9272#L1504-1 assume !(1 == ~E_1~0); 9273#L1509-1 assume !(1 == ~E_2~0); 9886#L1514-1 assume !(1 == ~E_3~0); 9571#L1519-1 assume !(1 == ~E_4~0); 9572#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 10076#L1529-1 assume !(1 == ~E_6~0); 10077#L1534-1 assume !(1 == ~E_7~0); 8223#L1539-1 assume !(1 == ~E_8~0); 8224#L1544-1 assume !(1 == ~E_9~0); 8654#L1549-1 assume !(1 == ~E_10~0); 10054#L1554-1 assume !(1 == ~E_11~0); 10052#L1559-1 assume !(1 == ~E_12~0); 9914#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 9915#L1569-1 assume { :end_inline_reset_delta_events } true; 10070#L1935-2 [2022-11-16 11:07:08,354 INFO L750 eck$LassoCheckResult]: Loop: 10070#L1935-2 assume !false; 8232#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8233#L1261 assume !false; 9460#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9461#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8363#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8533#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8534#L1074 assume !(0 != eval_~tmp~0#1); 8891#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9489#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9890#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9946#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9665#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9666#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10102#L1301-3 assume !(0 == ~T4_E~0); 10060#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9168#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8467#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8468#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8573#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9309#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9574#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9575#L1341-3 assume !(0 == ~T12_E~0); 8869#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8860#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8804#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8805#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9385#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8158#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8159#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9901#L1381-3 assume !(0 == ~E_6~0); 9750#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9751#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9932#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9933#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8538#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8369#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8370#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 8997#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8247#L635-45 assume 1 == ~m_pc~0; 8248#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9042#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9522#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9776#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8556#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8557#L654-45 assume 1 == ~t1_pc~0; 9377#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9725#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8210#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8211#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8236#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9063#L673-45 assume !(1 == ~t2_pc~0); 9064#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9388#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9389#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10014#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 9834#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8681#L692-45 assume !(1 == ~t3_pc~0); 8407#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 8408#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9452#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8735#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8736#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9048#L711-45 assume 1 == ~t4_pc~0; 9172#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9173#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9025#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9026#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9429#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8580#L730-45 assume 1 == ~t5_pc~0; 8418#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8419#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8828#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8829#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9580#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8391#L749-45 assume !(1 == ~t6_pc~0); 8392#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 9792#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9555#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9556#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9707#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8707#L768-45 assume 1 == ~t7_pc~0; 8708#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8847#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9651#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9652#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9691#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9692#L787-45 assume 1 == ~t8_pc~0; 9860#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8853#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8854#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9270#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9271#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9579#L806-45 assume 1 == ~t9_pc~0; 10055#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8267#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9092#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8920#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8832#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8833#L825-45 assume 1 == ~t10_pc~0; 9444#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9357#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9462#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9463#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9615#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8475#L844-45 assume !(1 == ~t11_pc~0); 8476#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8998#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8999#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9015#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 9426#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8515#L863-45 assume 1 == ~t12_pc~0; 8516#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8116#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8117#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8632#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8633#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9432#L882-45 assume !(1 == ~t13_pc~0); 8962#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 8135#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8136#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8744#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 9923#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9539#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9540#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9724#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8429#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8430#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8592#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9529#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9530#L1464-3 assume !(1 == ~T7_E~0); 9976#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9903#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9904#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9978#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9170#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9171#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9831#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9466#L1504-3 assume !(1 == ~E_1~0); 9467#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9912#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9952#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9093#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9094#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9999#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9394#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8848#L1544-3 assume !(1 == ~E_9~0); 8849#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9364#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8480#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8481#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9630#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9631#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8365#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8930#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9601#L1954 assume !(0 == start_simulation_~tmp~3#1); 9603#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9853#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8648#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9689#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 9819#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9820#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9910#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 9972#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 10070#L1935-2 [2022-11-16 11:07:08,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:08,359 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2022-11-16 11:07:08,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:08,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290606354] [2022-11-16 11:07:08,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:08,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:08,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:08,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:08,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:08,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290606354] [2022-11-16 11:07:08,477 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290606354] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:08,478 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:08,478 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:08,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709725061] [2022-11-16 11:07:08,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:08,479 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:08,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:08,481 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 2 times [2022-11-16 11:07:08,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:08,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694402729] [2022-11-16 11:07:08,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:08,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:08,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:08,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:08,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:08,662 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694402729] [2022-11-16 11:07:08,664 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694402729] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:08,665 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:08,665 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:08,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1634277227] [2022-11-16 11:07:08,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:08,667 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:08,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:08,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:08,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:08,669 INFO L87 Difference]: Start difference. First operand 2021 states and 2991 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:08,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:08,741 INFO L93 Difference]: Finished difference Result 2021 states and 2990 transitions. [2022-11-16 11:07:08,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2990 transitions. [2022-11-16 11:07:08,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:08,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2990 transitions. [2022-11-16 11:07:08,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:08,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:08,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2990 transitions. [2022-11-16 11:07:08,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:08,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2022-11-16 11:07:08,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2990 transitions. [2022-11-16 11:07:08,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:08,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.479465611083622) internal successors, (2990), 2020 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:08,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2990 transitions. [2022-11-16 11:07:08,850 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2022-11-16 11:07:08,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:08,852 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2990 transitions. [2022-11-16 11:07:08,852 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 11:07:08,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2990 transitions. [2022-11-16 11:07:08,866 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:08,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:08,867 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:08,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:08,871 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:08,872 INFO L748 eck$LassoCheckResult]: Stem: 13039#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 13040#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12771#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12772#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14162#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 14163#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12958#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12959#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12993#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13830#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13831#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13943#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13944#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12777#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12778#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13980#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13302#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13303#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13884#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14150#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 14040#L1286-2 assume !(0 == ~T1_E~0); 12686#L1291-1 assume !(0 == ~T2_E~0); 12687#L1296-1 assume !(0 == ~T3_E~0); 13392#L1301-1 assume !(0 == ~T4_E~0); 13393#L1306-1 assume !(0 == ~T5_E~0); 13893#L1311-1 assume !(0 == ~T6_E~0); 12646#L1316-1 assume !(0 == ~T7_E~0); 12647#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13412#L1326-1 assume !(0 == ~T9_E~0); 12461#L1331-1 assume !(0 == ~T10_E~0); 12167#L1336-1 assume !(0 == ~T11_E~0); 12168#L1341-1 assume !(0 == ~T12_E~0); 12219#L1346-1 assume !(0 == ~T13_E~0); 12220#L1351-1 assume !(0 == ~E_M~0); 12593#L1356-1 assume !(0 == ~E_1~0); 12594#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14113#L1366-1 assume !(0 == ~E_3~0); 12639#L1371-1 assume !(0 == ~E_4~0); 12640#L1376-1 assume !(0 == ~E_5~0); 13453#L1381-1 assume !(0 == ~E_6~0); 13454#L1386-1 assume !(0 == ~E_7~0); 14141#L1391-1 assume !(0 == ~E_8~0); 14154#L1396-1 assume !(0 == ~E_9~0); 13336#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13337#L1406-1 assume !(0 == ~E_11~0); 13639#L1411-1 assume !(0 == ~E_12~0); 13640#L1416-1 assume !(0 == ~E_13~0); 13260#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13098#L635 assume !(1 == ~m_pc~0); 12237#L635-2 is_master_triggered_~__retres1~0#1 := 0; 12238#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12588#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13224#L1598 assume !(0 != activate_threads_~tmp~1#1); 12416#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12417#L654 assume 1 == ~t1_pc~0; 13122#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13123#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14138#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13204#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 13205#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12464#L673 assume 1 == ~t2_pc~0; 12465#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13609#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13610#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14168#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 14175#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13283#L692 assume !(1 == ~t3_pc~0); 13100#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13101#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12960#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12928#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12929#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12489#L711 assume 1 == ~t4_pc~0; 12490#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12973#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13430#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12192#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 12193#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14161#L730 assume !(1 == ~t5_pc~0); 13543#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12371#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12372#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12499#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 12500#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12842#L749 assume 1 == ~t6_pc~0; 12616#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12376#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12808#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12809#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 13031#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12172#L768 assume !(1 == ~t7_pc~0); 12173#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13477#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12409#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12410#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 13496#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12648#L787 assume 1 == ~t8_pc~0; 12649#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13844#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14008#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14009#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 12217#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12218#L806 assume 1 == ~t9_pc~0; 13855#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12252#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12253#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12501#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 12502#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13838#L825 assume !(1 == ~t10_pc~0); 13839#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13444#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13445#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12589#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12590#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13173#L844 assume 1 == ~t11_pc~0; 12863#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12864#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13230#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13231#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 13826#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13827#L863 assume !(1 == ~t12_pc~0); 12352#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12351#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12579#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13918#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 13919#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13297#L882 assume 1 == ~t13_pc~0; 13298#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13582#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 14083#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13886#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 13569#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13570#L1434 assume !(1 == ~M_E~0); 14091#L1434-2 assume !(1 == ~T1_E~0); 14167#L1439-1 assume !(1 == ~T2_E~0); 12482#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12483#L1449-1 assume !(1 == ~T4_E~0); 12925#L1454-1 assume !(1 == ~T5_E~0); 12926#L1459-1 assume !(1 == ~T6_E~0); 13497#L1464-1 assume !(1 == ~T7_E~0); 13498#L1469-1 assume !(1 == ~T8_E~0); 13583#L1474-1 assume !(1 == ~T9_E~0); 13261#L1479-1 assume !(1 == ~T10_E~0); 13262#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13505#L1489-1 assume !(1 == ~T12_E~0); 13139#L1494-1 assume !(1 == ~T13_E~0); 13140#L1499-1 assume !(1 == ~E_M~0); 13321#L1504-1 assume !(1 == ~E_1~0); 13322#L1509-1 assume !(1 == ~E_2~0); 13935#L1514-1 assume !(1 == ~E_3~0); 13620#L1519-1 assume !(1 == ~E_4~0); 13621#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14125#L1529-1 assume !(1 == ~E_6~0); 14126#L1534-1 assume !(1 == ~E_7~0); 12272#L1539-1 assume !(1 == ~E_8~0); 12273#L1544-1 assume !(1 == ~E_9~0); 12703#L1549-1 assume !(1 == ~E_10~0); 14103#L1554-1 assume !(1 == ~E_11~0); 14101#L1559-1 assume !(1 == ~E_12~0); 13963#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 13964#L1569-1 assume { :end_inline_reset_delta_events } true; 14119#L1935-2 [2022-11-16 11:07:08,873 INFO L750 eck$LassoCheckResult]: Loop: 14119#L1935-2 assume !false; 12281#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12282#L1261 assume !false; 13509#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13510#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12412#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12582#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12583#L1074 assume !(0 != eval_~tmp~0#1); 12940#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13538#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13939#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13995#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13714#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13715#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14151#L1301-3 assume !(0 == ~T4_E~0); 14109#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13217#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12516#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12517#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12622#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13358#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13623#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13624#L1341-3 assume !(0 == ~T12_E~0); 12918#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12909#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12853#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12854#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13434#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12207#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12208#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13950#L1381-3 assume !(0 == ~E_6~0); 13799#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13800#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13981#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13982#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12587#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12418#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 12419#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13046#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12296#L635-45 assume 1 == ~m_pc~0; 12297#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13091#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13571#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13825#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12605#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12606#L654-45 assume 1 == ~t1_pc~0; 13426#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13774#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12259#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12260#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12285#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13112#L673-45 assume !(1 == ~t2_pc~0); 13113#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 13437#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13438#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14063#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 13883#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12730#L692-45 assume !(1 == ~t3_pc~0); 12456#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 12457#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13501#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12784#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12785#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13097#L711-45 assume 1 == ~t4_pc~0; 13221#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13222#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13074#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13075#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13478#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12629#L730-45 assume 1 == ~t5_pc~0; 12467#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12468#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12877#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12878#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13629#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12440#L749-45 assume !(1 == ~t6_pc~0); 12441#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 13841#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13604#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13605#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13756#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12756#L768-45 assume 1 == ~t7_pc~0; 12757#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12896#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13700#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13701#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13740#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13741#L787-45 assume 1 == ~t8_pc~0; 13909#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12902#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12903#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13319#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13320#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13628#L806-45 assume 1 == ~t9_pc~0; 14104#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12316#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13141#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12969#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12881#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12882#L825-45 assume 1 == ~t10_pc~0; 13493#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13406#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13511#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13512#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13664#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12524#L844-45 assume !(1 == ~t11_pc~0); 12525#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 13047#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13048#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13064#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 13475#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12564#L863-45 assume 1 == ~t12_pc~0; 12565#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12165#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12166#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12681#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12682#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13481#L882-45 assume !(1 == ~t13_pc~0); 13011#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 12184#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12185#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12793#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 13972#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13588#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13589#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13773#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12478#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12479#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12641#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13578#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13579#L1464-3 assume !(1 == ~T7_E~0); 14025#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13952#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13953#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14027#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13219#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13220#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13880#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13515#L1504-3 assume !(1 == ~E_1~0); 13516#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13961#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14001#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13142#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13143#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14048#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13443#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12897#L1544-3 assume !(1 == ~E_9~0); 12898#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13413#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12529#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12530#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13679#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13680#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12414#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12979#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13650#L1954 assume !(0 == start_simulation_~tmp~3#1); 13652#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13902#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12697#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13738#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13868#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13869#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13959#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14021#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 14119#L1935-2 [2022-11-16 11:07:08,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:08,875 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2022-11-16 11:07:08,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:08,875 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801306054] [2022-11-16 11:07:08,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:08,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:08,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:08,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:08,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:08,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801306054] [2022-11-16 11:07:08,978 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801306054] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:08,978 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:08,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:08,983 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387073940] [2022-11-16 11:07:08,983 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:08,984 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:08,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:08,985 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 3 times [2022-11-16 11:07:08,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:08,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784403639] [2022-11-16 11:07:08,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:08,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:09,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:09,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:09,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:09,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784403639] [2022-11-16 11:07:09,109 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784403639] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:09,109 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:09,110 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:09,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308362091] [2022-11-16 11:07:09,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:09,111 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:09,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:09,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:09,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:09,114 INFO L87 Difference]: Start difference. First operand 2021 states and 2990 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:09,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:09,171 INFO L93 Difference]: Finished difference Result 2021 states and 2989 transitions. [2022-11-16 11:07:09,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2989 transitions. [2022-11-16 11:07:09,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:09,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2989 transitions. [2022-11-16 11:07:09,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:09,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:09,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2989 transitions. [2022-11-16 11:07:09,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:09,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2022-11-16 11:07:09,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2989 transitions. [2022-11-16 11:07:09,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:09,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.47897080653142) internal successors, (2989), 2020 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:09,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2989 transitions. [2022-11-16 11:07:09,289 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2022-11-16 11:07:09,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:09,291 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2989 transitions. [2022-11-16 11:07:09,292 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 11:07:09,292 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2989 transitions. [2022-11-16 11:07:09,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:09,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:09,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:09,308 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:09,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:09,309 INFO L748 eck$LassoCheckResult]: Stem: 17088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 17089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16820#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16821#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18211#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 18212#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17007#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17008#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17042#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17879#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17880#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17992#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17993#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16826#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16827#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18029#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17351#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17352#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17933#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18199#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 18089#L1286-2 assume !(0 == ~T1_E~0); 16735#L1291-1 assume !(0 == ~T2_E~0); 16736#L1296-1 assume !(0 == ~T3_E~0); 17441#L1301-1 assume !(0 == ~T4_E~0); 17442#L1306-1 assume !(0 == ~T5_E~0); 17942#L1311-1 assume !(0 == ~T6_E~0); 16695#L1316-1 assume !(0 == ~T7_E~0); 16696#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17461#L1326-1 assume !(0 == ~T9_E~0); 16510#L1331-1 assume !(0 == ~T10_E~0); 16216#L1336-1 assume !(0 == ~T11_E~0); 16217#L1341-1 assume !(0 == ~T12_E~0); 16268#L1346-1 assume !(0 == ~T13_E~0); 16269#L1351-1 assume !(0 == ~E_M~0); 16642#L1356-1 assume !(0 == ~E_1~0); 16643#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 18162#L1366-1 assume !(0 == ~E_3~0); 16688#L1371-1 assume !(0 == ~E_4~0); 16689#L1376-1 assume !(0 == ~E_5~0); 17502#L1381-1 assume !(0 == ~E_6~0); 17503#L1386-1 assume !(0 == ~E_7~0); 18190#L1391-1 assume !(0 == ~E_8~0); 18203#L1396-1 assume !(0 == ~E_9~0); 17385#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17386#L1406-1 assume !(0 == ~E_11~0); 17688#L1411-1 assume !(0 == ~E_12~0); 17689#L1416-1 assume !(0 == ~E_13~0); 17309#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17147#L635 assume !(1 == ~m_pc~0); 16286#L635-2 is_master_triggered_~__retres1~0#1 := 0; 16287#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16637#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17273#L1598 assume !(0 != activate_threads_~tmp~1#1); 16465#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16466#L654 assume 1 == ~t1_pc~0; 17171#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17172#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18187#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17253#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 17254#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16513#L673 assume 1 == ~t2_pc~0; 16514#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17658#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17659#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18217#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 18224#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17332#L692 assume !(1 == ~t3_pc~0); 17149#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17150#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17009#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16977#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16978#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16538#L711 assume 1 == ~t4_pc~0; 16539#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17022#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17479#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16241#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 16242#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18210#L730 assume !(1 == ~t5_pc~0); 17592#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16420#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16421#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16548#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 16549#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16891#L749 assume 1 == ~t6_pc~0; 16665#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16425#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16857#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16858#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 17080#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16221#L768 assume !(1 == ~t7_pc~0); 16222#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17526#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16458#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16459#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 17545#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16697#L787 assume 1 == ~t8_pc~0; 16698#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17893#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18057#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18058#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 16266#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16267#L806 assume 1 == ~t9_pc~0; 17904#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16301#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16302#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16550#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 16551#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17887#L825 assume !(1 == ~t10_pc~0); 17888#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17493#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17494#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16638#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16639#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17222#L844 assume 1 == ~t11_pc~0; 16912#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16913#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17279#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17280#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 17875#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17876#L863 assume !(1 == ~t12_pc~0); 16401#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 16400#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16628#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17967#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 17968#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17346#L882 assume 1 == ~t13_pc~0; 17347#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17631#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 18132#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17935#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 17618#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17619#L1434 assume !(1 == ~M_E~0); 18140#L1434-2 assume !(1 == ~T1_E~0); 18216#L1439-1 assume !(1 == ~T2_E~0); 16531#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16532#L1449-1 assume !(1 == ~T4_E~0); 16974#L1454-1 assume !(1 == ~T5_E~0); 16975#L1459-1 assume !(1 == ~T6_E~0); 17546#L1464-1 assume !(1 == ~T7_E~0); 17547#L1469-1 assume !(1 == ~T8_E~0); 17632#L1474-1 assume !(1 == ~T9_E~0); 17310#L1479-1 assume !(1 == ~T10_E~0); 17311#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17554#L1489-1 assume !(1 == ~T12_E~0); 17188#L1494-1 assume !(1 == ~T13_E~0); 17189#L1499-1 assume !(1 == ~E_M~0); 17370#L1504-1 assume !(1 == ~E_1~0); 17371#L1509-1 assume !(1 == ~E_2~0); 17984#L1514-1 assume !(1 == ~E_3~0); 17669#L1519-1 assume !(1 == ~E_4~0); 17670#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18174#L1529-1 assume !(1 == ~E_6~0); 18175#L1534-1 assume !(1 == ~E_7~0); 16321#L1539-1 assume !(1 == ~E_8~0); 16322#L1544-1 assume !(1 == ~E_9~0); 16752#L1549-1 assume !(1 == ~E_10~0); 18152#L1554-1 assume !(1 == ~E_11~0); 18150#L1559-1 assume !(1 == ~E_12~0); 18012#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18013#L1569-1 assume { :end_inline_reset_delta_events } true; 18168#L1935-2 [2022-11-16 11:07:09,310 INFO L750 eck$LassoCheckResult]: Loop: 18168#L1935-2 assume !false; 16330#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16331#L1261 assume !false; 17558#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17559#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16461#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16631#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16632#L1074 assume !(0 != eval_~tmp~0#1); 16989#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17587#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17988#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18044#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17763#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17764#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18200#L1301-3 assume !(0 == ~T4_E~0); 18158#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17266#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16565#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16566#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16671#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17407#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17672#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17673#L1341-3 assume !(0 == ~T12_E~0); 16967#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 16958#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16902#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16903#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17483#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16256#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16257#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17999#L1381-3 assume !(0 == ~E_6~0); 17848#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17849#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18030#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18031#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16636#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16467#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 16468#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17095#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16345#L635-45 assume 1 == ~m_pc~0; 16346#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17140#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17620#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17874#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16654#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16655#L654-45 assume 1 == ~t1_pc~0; 17475#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17823#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16308#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16309#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16334#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17161#L673-45 assume !(1 == ~t2_pc~0); 17162#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 17486#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17487#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18112#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 17932#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16779#L692-45 assume !(1 == ~t3_pc~0); 16505#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 16506#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17550#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16833#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16834#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17146#L711-45 assume 1 == ~t4_pc~0; 17270#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17271#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17123#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17124#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17527#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16678#L730-45 assume 1 == ~t5_pc~0; 16516#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16517#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16926#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16927#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17678#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16489#L749-45 assume !(1 == ~t6_pc~0); 16490#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 17890#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17653#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17654#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17805#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16805#L768-45 assume 1 == ~t7_pc~0; 16806#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16945#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17749#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17750#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17789#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17790#L787-45 assume 1 == ~t8_pc~0; 17958#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16951#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16952#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17368#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17369#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17677#L806-45 assume 1 == ~t9_pc~0; 18153#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16365#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17190#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17018#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16930#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16931#L825-45 assume 1 == ~t10_pc~0; 17542#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17455#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17560#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17561#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17713#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16573#L844-45 assume !(1 == ~t11_pc~0); 16574#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 17096#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17097#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17113#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 17524#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16613#L863-45 assume 1 == ~t12_pc~0; 16614#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16214#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16215#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16730#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16731#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17530#L882-45 assume !(1 == ~t13_pc~0); 17060#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 16233#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16234#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16842#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18021#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17637#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17638#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17822#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16527#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16528#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16690#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17627#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17628#L1464-3 assume !(1 == ~T7_E~0); 18074#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18001#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18002#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18076#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17268#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 17269#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17929#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17564#L1504-3 assume !(1 == ~E_1~0); 17565#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18010#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18050#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17191#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17192#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18097#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17492#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16946#L1544-3 assume !(1 == ~E_9~0); 16947#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17462#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16578#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16579#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17728#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17729#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16463#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17028#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17699#L1954 assume !(0 == start_simulation_~tmp~3#1); 17701#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17951#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16746#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17787#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17917#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17918#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18008#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18070#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 18168#L1935-2 [2022-11-16 11:07:09,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:09,311 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2022-11-16 11:07:09,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:09,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428210342] [2022-11-16 11:07:09,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:09,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:09,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:09,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:09,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:09,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428210342] [2022-11-16 11:07:09,388 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [428210342] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:09,388 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:09,388 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:09,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [106025790] [2022-11-16 11:07:09,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:09,389 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:09,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:09,390 INFO L85 PathProgramCache]: Analyzing trace with hash 766080739, now seen corresponding path program 4 times [2022-11-16 11:07:09,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:09,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850495489] [2022-11-16 11:07:09,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:09,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:09,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:09,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:09,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:09,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850495489] [2022-11-16 11:07:09,506 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1850495489] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:09,506 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:09,506 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:09,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [287900936] [2022-11-16 11:07:09,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:09,507 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:09,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:09,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:09,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:09,508 INFO L87 Difference]: Start difference. First operand 2021 states and 2989 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:09,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:09,561 INFO L93 Difference]: Finished difference Result 2021 states and 2988 transitions. [2022-11-16 11:07:09,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2988 transitions. [2022-11-16 11:07:09,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:09,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2988 transitions. [2022-11-16 11:07:09,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:09,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:09,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2988 transitions. [2022-11-16 11:07:09,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:09,595 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2022-11-16 11:07:09,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2988 transitions. [2022-11-16 11:07:09,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:09,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4784760019792182) internal successors, (2988), 2020 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:09,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2988 transitions. [2022-11-16 11:07:09,640 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2022-11-16 11:07:09,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:09,644 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2988 transitions. [2022-11-16 11:07:09,644 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 11:07:09,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2988 transitions. [2022-11-16 11:07:09,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:09,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:09,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:09,658 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:09,658 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:09,659 INFO L748 eck$LassoCheckResult]: Stem: 21137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 21138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20869#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20870#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22260#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 22261#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21056#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21057#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21091#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21928#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21929#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22041#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22042#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20875#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20876#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22078#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21400#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21401#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21982#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22248#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 22138#L1286-2 assume !(0 == ~T1_E~0); 20784#L1291-1 assume !(0 == ~T2_E~0); 20785#L1296-1 assume !(0 == ~T3_E~0); 21490#L1301-1 assume !(0 == ~T4_E~0); 21491#L1306-1 assume !(0 == ~T5_E~0); 21991#L1311-1 assume !(0 == ~T6_E~0); 20744#L1316-1 assume !(0 == ~T7_E~0); 20745#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21510#L1326-1 assume !(0 == ~T9_E~0); 20559#L1331-1 assume !(0 == ~T10_E~0); 20265#L1336-1 assume !(0 == ~T11_E~0); 20266#L1341-1 assume !(0 == ~T12_E~0); 20317#L1346-1 assume !(0 == ~T13_E~0); 20318#L1351-1 assume !(0 == ~E_M~0); 20691#L1356-1 assume !(0 == ~E_1~0); 20692#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22211#L1366-1 assume !(0 == ~E_3~0); 20737#L1371-1 assume !(0 == ~E_4~0); 20738#L1376-1 assume !(0 == ~E_5~0); 21551#L1381-1 assume !(0 == ~E_6~0); 21552#L1386-1 assume !(0 == ~E_7~0); 22239#L1391-1 assume !(0 == ~E_8~0); 22252#L1396-1 assume !(0 == ~E_9~0); 21434#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21435#L1406-1 assume !(0 == ~E_11~0); 21737#L1411-1 assume !(0 == ~E_12~0); 21738#L1416-1 assume !(0 == ~E_13~0); 21358#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21196#L635 assume !(1 == ~m_pc~0); 20335#L635-2 is_master_triggered_~__retres1~0#1 := 0; 20336#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20686#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21322#L1598 assume !(0 != activate_threads_~tmp~1#1); 20514#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20515#L654 assume 1 == ~t1_pc~0; 21220#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21221#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22236#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21302#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 21303#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20562#L673 assume 1 == ~t2_pc~0; 20563#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21707#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21708#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22266#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 22273#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21381#L692 assume !(1 == ~t3_pc~0); 21198#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21199#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21058#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21026#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21027#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20587#L711 assume 1 == ~t4_pc~0; 20588#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21071#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21528#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20290#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 20291#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22259#L730 assume !(1 == ~t5_pc~0); 21641#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20469#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20470#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20597#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 20598#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20940#L749 assume 1 == ~t6_pc~0; 20714#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20474#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20906#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20907#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 21129#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20270#L768 assume !(1 == ~t7_pc~0); 20271#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21575#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20507#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20508#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 21594#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20746#L787 assume 1 == ~t8_pc~0; 20747#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21942#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22106#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22107#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 20315#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20316#L806 assume 1 == ~t9_pc~0; 21953#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20350#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20351#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20599#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 20600#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21936#L825 assume !(1 == ~t10_pc~0); 21937#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21542#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21543#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20687#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20688#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21271#L844 assume 1 == ~t11_pc~0; 20961#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20962#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21328#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21329#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 21924#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21925#L863 assume !(1 == ~t12_pc~0); 20450#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 20449#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20677#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22016#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 22017#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21395#L882 assume 1 == ~t13_pc~0; 21396#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21680#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 22181#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21984#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 21667#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21668#L1434 assume !(1 == ~M_E~0); 22189#L1434-2 assume !(1 == ~T1_E~0); 22265#L1439-1 assume !(1 == ~T2_E~0); 20580#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20581#L1449-1 assume !(1 == ~T4_E~0); 21023#L1454-1 assume !(1 == ~T5_E~0); 21024#L1459-1 assume !(1 == ~T6_E~0); 21595#L1464-1 assume !(1 == ~T7_E~0); 21596#L1469-1 assume !(1 == ~T8_E~0); 21681#L1474-1 assume !(1 == ~T9_E~0); 21359#L1479-1 assume !(1 == ~T10_E~0); 21360#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21603#L1489-1 assume !(1 == ~T12_E~0); 21237#L1494-1 assume !(1 == ~T13_E~0); 21238#L1499-1 assume !(1 == ~E_M~0); 21419#L1504-1 assume !(1 == ~E_1~0); 21420#L1509-1 assume !(1 == ~E_2~0); 22033#L1514-1 assume !(1 == ~E_3~0); 21718#L1519-1 assume !(1 == ~E_4~0); 21719#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22223#L1529-1 assume !(1 == ~E_6~0); 22224#L1534-1 assume !(1 == ~E_7~0); 20370#L1539-1 assume !(1 == ~E_8~0); 20371#L1544-1 assume !(1 == ~E_9~0); 20801#L1549-1 assume !(1 == ~E_10~0); 22201#L1554-1 assume !(1 == ~E_11~0); 22199#L1559-1 assume !(1 == ~E_12~0); 22061#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22062#L1569-1 assume { :end_inline_reset_delta_events } true; 22217#L1935-2 [2022-11-16 11:07:09,659 INFO L750 eck$LassoCheckResult]: Loop: 22217#L1935-2 assume !false; 20379#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20380#L1261 assume !false; 21607#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21608#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20510#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20680#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20681#L1074 assume !(0 != eval_~tmp~0#1); 21038#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21636#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22037#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22093#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21812#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21813#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22249#L1301-3 assume !(0 == ~T4_E~0); 22207#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21315#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20614#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20615#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20720#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21456#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21721#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21722#L1341-3 assume !(0 == ~T12_E~0); 21016#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21007#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20951#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20952#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21532#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20305#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20306#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22048#L1381-3 assume !(0 == ~E_6~0); 21897#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21898#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22079#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22080#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20685#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20516#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 20517#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21144#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20394#L635-45 assume 1 == ~m_pc~0; 20395#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21189#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21669#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21923#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20703#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20704#L654-45 assume 1 == ~t1_pc~0; 21524#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21872#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20357#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20358#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20383#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21210#L673-45 assume !(1 == ~t2_pc~0); 21211#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21535#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21536#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22161#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 21981#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20828#L692-45 assume !(1 == ~t3_pc~0); 20554#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 20555#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21599#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20882#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20883#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21195#L711-45 assume 1 == ~t4_pc~0; 21319#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21320#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21172#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21173#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21576#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20727#L730-45 assume 1 == ~t5_pc~0; 20565#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20566#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20975#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20976#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21727#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20538#L749-45 assume !(1 == ~t6_pc~0); 20539#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 21939#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21702#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21703#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21854#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20854#L768-45 assume 1 == ~t7_pc~0; 20855#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20994#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21798#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21799#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21838#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21839#L787-45 assume 1 == ~t8_pc~0; 22007#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21000#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21001#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21417#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21418#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21726#L806-45 assume 1 == ~t9_pc~0; 22202#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20414#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21239#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21067#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20979#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20980#L825-45 assume 1 == ~t10_pc~0; 21591#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21504#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21609#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21610#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21762#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20622#L844-45 assume 1 == ~t11_pc~0; 20624#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21145#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21146#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21162#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 21573#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20662#L863-45 assume 1 == ~t12_pc~0; 20663#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20263#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20264#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20779#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20780#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21579#L882-45 assume !(1 == ~t13_pc~0); 21109#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 20282#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20283#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 20891#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22070#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21686#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21687#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21871#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20576#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20577#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20739#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21676#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21677#L1464-3 assume !(1 == ~T7_E~0); 22123#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22050#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22051#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22125#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21317#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21318#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21978#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21613#L1504-3 assume !(1 == ~E_1~0); 21614#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22059#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22099#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21240#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21241#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22146#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21541#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20995#L1544-3 assume !(1 == ~E_9~0); 20996#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21511#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20627#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20628#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21777#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21778#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20512#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21077#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21748#L1954 assume !(0 == start_simulation_~tmp~3#1); 21750#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 22000#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20795#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21836#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21966#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21967#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22057#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22119#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 22217#L1935-2 [2022-11-16 11:07:09,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:09,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2022-11-16 11:07:09,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:09,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970228710] [2022-11-16 11:07:09,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:09,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:09,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:09,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:09,741 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:09,741 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970228710] [2022-11-16 11:07:09,742 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970228710] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:09,742 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:09,742 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:09,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894649064] [2022-11-16 11:07:09,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:09,750 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:09,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:09,753 INFO L85 PathProgramCache]: Analyzing trace with hash 1797411554, now seen corresponding path program 1 times [2022-11-16 11:07:09,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:09,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793471022] [2022-11-16 11:07:09,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:09,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:09,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:09,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:09,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:09,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793471022] [2022-11-16 11:07:09,867 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793471022] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:09,867 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:09,867 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:09,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920052973] [2022-11-16 11:07:09,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:09,868 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:09,869 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:09,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:09,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:09,870 INFO L87 Difference]: Start difference. First operand 2021 states and 2988 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:09,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:09,921 INFO L93 Difference]: Finished difference Result 2021 states and 2987 transitions. [2022-11-16 11:07:09,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2987 transitions. [2022-11-16 11:07:09,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:09,972 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2987 transitions. [2022-11-16 11:07:09,973 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:09,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:09,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2987 transitions. [2022-11-16 11:07:09,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:09,981 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2022-11-16 11:07:09,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2987 transitions. [2022-11-16 11:07:10,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:10,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4779811974270163) internal successors, (2987), 2020 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:10,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2987 transitions. [2022-11-16 11:07:10,023 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2022-11-16 11:07:10,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:10,025 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2987 transitions. [2022-11-16 11:07:10,026 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 11:07:10,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2987 transitions. [2022-11-16 11:07:10,035 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:10,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:10,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:10,039 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:10,039 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:10,040 INFO L748 eck$LassoCheckResult]: Stem: 25186#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 25187#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24918#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24919#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26309#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 26310#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25105#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25106#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25140#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25977#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25978#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26090#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26091#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24924#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24925#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26127#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25449#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25450#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 26031#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26297#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 26187#L1286-2 assume !(0 == ~T1_E~0); 24833#L1291-1 assume !(0 == ~T2_E~0); 24834#L1296-1 assume !(0 == ~T3_E~0); 25539#L1301-1 assume !(0 == ~T4_E~0); 25540#L1306-1 assume !(0 == ~T5_E~0); 26040#L1311-1 assume !(0 == ~T6_E~0); 24793#L1316-1 assume !(0 == ~T7_E~0); 24794#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25559#L1326-1 assume !(0 == ~T9_E~0); 24608#L1331-1 assume !(0 == ~T10_E~0); 24314#L1336-1 assume !(0 == ~T11_E~0); 24315#L1341-1 assume !(0 == ~T12_E~0); 24366#L1346-1 assume !(0 == ~T13_E~0); 24367#L1351-1 assume !(0 == ~E_M~0); 24740#L1356-1 assume !(0 == ~E_1~0); 24741#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 26260#L1366-1 assume !(0 == ~E_3~0); 24786#L1371-1 assume !(0 == ~E_4~0); 24787#L1376-1 assume !(0 == ~E_5~0); 25600#L1381-1 assume !(0 == ~E_6~0); 25601#L1386-1 assume !(0 == ~E_7~0); 26288#L1391-1 assume !(0 == ~E_8~0); 26301#L1396-1 assume !(0 == ~E_9~0); 25483#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 25484#L1406-1 assume !(0 == ~E_11~0); 25786#L1411-1 assume !(0 == ~E_12~0); 25787#L1416-1 assume !(0 == ~E_13~0); 25407#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25245#L635 assume !(1 == ~m_pc~0); 24384#L635-2 is_master_triggered_~__retres1~0#1 := 0; 24385#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24735#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25371#L1598 assume !(0 != activate_threads_~tmp~1#1); 24563#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24564#L654 assume 1 == ~t1_pc~0; 25269#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25270#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26285#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25351#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 25352#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24611#L673 assume 1 == ~t2_pc~0; 24612#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25756#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25757#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26315#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 26322#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25430#L692 assume !(1 == ~t3_pc~0); 25247#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25248#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25107#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25075#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25076#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24636#L711 assume 1 == ~t4_pc~0; 24637#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25120#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25577#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24339#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 24340#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26308#L730 assume !(1 == ~t5_pc~0); 25690#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24518#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24519#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24646#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 24647#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24989#L749 assume 1 == ~t6_pc~0; 24763#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24523#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24955#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24956#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 25178#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24319#L768 assume !(1 == ~t7_pc~0); 24320#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25624#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24556#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24557#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 25643#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24795#L787 assume 1 == ~t8_pc~0; 24796#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25991#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26155#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26156#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 24364#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24365#L806 assume 1 == ~t9_pc~0; 26002#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24399#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24400#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24648#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 24649#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25985#L825 assume !(1 == ~t10_pc~0); 25986#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25591#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25592#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24736#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24737#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25320#L844 assume 1 == ~t11_pc~0; 25010#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25011#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25377#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25378#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 25973#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25974#L863 assume !(1 == ~t12_pc~0); 24499#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 24498#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24726#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26065#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 26066#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25444#L882 assume 1 == ~t13_pc~0; 25445#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25729#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 26230#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26033#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 25716#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25717#L1434 assume !(1 == ~M_E~0); 26238#L1434-2 assume !(1 == ~T1_E~0); 26314#L1439-1 assume !(1 == ~T2_E~0); 24629#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24630#L1449-1 assume !(1 == ~T4_E~0); 25072#L1454-1 assume !(1 == ~T5_E~0); 25073#L1459-1 assume !(1 == ~T6_E~0); 25644#L1464-1 assume !(1 == ~T7_E~0); 25645#L1469-1 assume !(1 == ~T8_E~0); 25730#L1474-1 assume !(1 == ~T9_E~0); 25408#L1479-1 assume !(1 == ~T10_E~0); 25409#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25652#L1489-1 assume !(1 == ~T12_E~0); 25286#L1494-1 assume !(1 == ~T13_E~0); 25287#L1499-1 assume !(1 == ~E_M~0); 25468#L1504-1 assume !(1 == ~E_1~0); 25469#L1509-1 assume !(1 == ~E_2~0); 26082#L1514-1 assume !(1 == ~E_3~0); 25767#L1519-1 assume !(1 == ~E_4~0); 25768#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26272#L1529-1 assume !(1 == ~E_6~0); 26273#L1534-1 assume !(1 == ~E_7~0); 24419#L1539-1 assume !(1 == ~E_8~0); 24420#L1544-1 assume !(1 == ~E_9~0); 24850#L1549-1 assume !(1 == ~E_10~0); 26250#L1554-1 assume !(1 == ~E_11~0); 26248#L1559-1 assume !(1 == ~E_12~0); 26110#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26111#L1569-1 assume { :end_inline_reset_delta_events } true; 26266#L1935-2 [2022-11-16 11:07:10,040 INFO L750 eck$LassoCheckResult]: Loop: 26266#L1935-2 assume !false; 24428#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24429#L1261 assume !false; 25656#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25657#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24559#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24729#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 24730#L1074 assume !(0 != eval_~tmp~0#1); 25087#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25685#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26086#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26142#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25861#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25862#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26298#L1301-3 assume !(0 == ~T4_E~0); 26256#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25364#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24663#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24664#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24769#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25505#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25770#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25771#L1341-3 assume !(0 == ~T12_E~0); 25065#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25056#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25000#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25001#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25581#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24354#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24355#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26097#L1381-3 assume !(0 == ~E_6~0); 25946#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25947#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26128#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26129#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24734#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24565#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24566#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25193#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24443#L635-45 assume 1 == ~m_pc~0; 24444#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25238#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25718#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25972#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24752#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24753#L654-45 assume 1 == ~t1_pc~0; 25573#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25921#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24406#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24407#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24432#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25259#L673-45 assume !(1 == ~t2_pc~0); 25260#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 25584#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25585#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26210#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 26030#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24877#L692-45 assume !(1 == ~t3_pc~0); 24603#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 24604#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25648#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24931#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24932#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25244#L711-45 assume 1 == ~t4_pc~0; 25368#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25369#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25221#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25222#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25625#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24776#L730-45 assume 1 == ~t5_pc~0; 24614#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24615#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25024#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25025#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25776#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24587#L749-45 assume !(1 == ~t6_pc~0); 24588#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 25988#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25751#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25752#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25903#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24903#L768-45 assume 1 == ~t7_pc~0; 24904#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25043#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25847#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25848#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25887#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25888#L787-45 assume 1 == ~t8_pc~0; 26056#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25049#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25050#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25466#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25467#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25775#L806-45 assume 1 == ~t9_pc~0; 26251#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24463#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25288#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25116#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25028#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25029#L825-45 assume !(1 == ~t10_pc~0); 25552#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 25553#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25658#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25659#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25811#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24671#L844-45 assume !(1 == ~t11_pc~0); 24672#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 25194#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25195#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25211#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 25622#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24711#L863-45 assume 1 == ~t12_pc~0; 24712#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24312#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24313#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24828#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24829#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25628#L882-45 assume !(1 == ~t13_pc~0); 25158#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 24331#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 24332#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 24940#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 26119#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25735#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25736#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25920#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24625#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24626#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24788#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25725#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25726#L1464-3 assume !(1 == ~T7_E~0); 26172#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26099#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26100#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26174#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25366#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25367#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 26027#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25662#L1504-3 assume !(1 == ~E_1~0); 25663#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26108#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26148#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25289#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25290#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26195#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25590#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25044#L1544-3 assume !(1 == ~E_9~0); 25045#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25560#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24676#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24677#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25826#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25827#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24561#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25126#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 25797#L1954 assume !(0 == start_simulation_~tmp~3#1); 25799#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 26049#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24844#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25885#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 26015#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26016#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26106#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26168#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 26266#L1935-2 [2022-11-16 11:07:10,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:10,042 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2022-11-16 11:07:10,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:10,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766780302] [2022-11-16 11:07:10,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:10,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:10,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:10,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:10,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:10,111 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [766780302] [2022-11-16 11:07:10,111 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [766780302] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:10,111 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:10,111 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:10,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028168825] [2022-11-16 11:07:10,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:10,112 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:10,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:10,113 INFO L85 PathProgramCache]: Analyzing trace with hash 1143723556, now seen corresponding path program 1 times [2022-11-16 11:07:10,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:10,113 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089094742] [2022-11-16 11:07:10,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:10,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:10,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:10,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:10,201 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:10,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089094742] [2022-11-16 11:07:10,202 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089094742] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:10,202 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:10,202 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:10,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027584081] [2022-11-16 11:07:10,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:10,203 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:10,204 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:10,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:10,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:10,205 INFO L87 Difference]: Start difference. First operand 2021 states and 2987 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:10,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:10,259 INFO L93 Difference]: Finished difference Result 2021 states and 2986 transitions. [2022-11-16 11:07:10,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2986 transitions. [2022-11-16 11:07:10,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:10,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2986 transitions. [2022-11-16 11:07:10,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:10,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:10,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2986 transitions. [2022-11-16 11:07:10,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:10,288 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2022-11-16 11:07:10,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2986 transitions. [2022-11-16 11:07:10,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:10,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4774863928748145) internal successors, (2986), 2020 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:10,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2986 transitions. [2022-11-16 11:07:10,340 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2022-11-16 11:07:10,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:10,343 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2986 transitions. [2022-11-16 11:07:10,344 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 11:07:10,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2986 transitions. [2022-11-16 11:07:10,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:10,353 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:10,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:10,357 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:10,357 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:10,360 INFO L748 eck$LassoCheckResult]: Stem: 29235#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 29236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28967#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28968#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30358#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 30359#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29154#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29155#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29189#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30026#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30027#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30139#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30140#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28973#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28974#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30176#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29498#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29499#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 30080#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30346#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 30236#L1286-2 assume !(0 == ~T1_E~0); 28882#L1291-1 assume !(0 == ~T2_E~0); 28883#L1296-1 assume !(0 == ~T3_E~0); 29588#L1301-1 assume !(0 == ~T4_E~0); 29589#L1306-1 assume !(0 == ~T5_E~0); 30089#L1311-1 assume !(0 == ~T6_E~0); 28842#L1316-1 assume !(0 == ~T7_E~0); 28843#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29608#L1326-1 assume !(0 == ~T9_E~0); 28657#L1331-1 assume !(0 == ~T10_E~0); 28363#L1336-1 assume !(0 == ~T11_E~0); 28364#L1341-1 assume !(0 == ~T12_E~0); 28415#L1346-1 assume !(0 == ~T13_E~0); 28416#L1351-1 assume !(0 == ~E_M~0); 28789#L1356-1 assume !(0 == ~E_1~0); 28790#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 30309#L1366-1 assume !(0 == ~E_3~0); 28835#L1371-1 assume !(0 == ~E_4~0); 28836#L1376-1 assume !(0 == ~E_5~0); 29649#L1381-1 assume !(0 == ~E_6~0); 29650#L1386-1 assume !(0 == ~E_7~0); 30337#L1391-1 assume !(0 == ~E_8~0); 30350#L1396-1 assume !(0 == ~E_9~0); 29532#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29533#L1406-1 assume !(0 == ~E_11~0); 29835#L1411-1 assume !(0 == ~E_12~0); 29836#L1416-1 assume !(0 == ~E_13~0); 29456#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29294#L635 assume !(1 == ~m_pc~0); 28433#L635-2 is_master_triggered_~__retres1~0#1 := 0; 28434#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28784#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29420#L1598 assume !(0 != activate_threads_~tmp~1#1); 28612#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28613#L654 assume 1 == ~t1_pc~0; 29318#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29319#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30334#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29400#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 29401#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28660#L673 assume 1 == ~t2_pc~0; 28661#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29805#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29806#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30364#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 30371#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29479#L692 assume !(1 == ~t3_pc~0); 29296#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29297#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29156#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29124#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29125#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28685#L711 assume 1 == ~t4_pc~0; 28686#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29169#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29626#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28388#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 28389#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30357#L730 assume !(1 == ~t5_pc~0); 29739#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28567#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28568#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28695#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 28696#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29038#L749 assume 1 == ~t6_pc~0; 28812#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28572#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29004#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29005#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 29227#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28368#L768 assume !(1 == ~t7_pc~0); 28369#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 29673#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28605#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28606#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 29692#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28844#L787 assume 1 == ~t8_pc~0; 28845#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30040#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30204#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30205#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 28413#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28414#L806 assume 1 == ~t9_pc~0; 30051#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28448#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28449#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28697#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 28698#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30034#L825 assume !(1 == ~t10_pc~0); 30035#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29640#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29641#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28785#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28786#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29369#L844 assume 1 == ~t11_pc~0; 29059#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29060#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29426#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29427#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 30022#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30023#L863 assume !(1 == ~t12_pc~0); 28548#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 28547#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28775#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30114#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 30115#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29493#L882 assume 1 == ~t13_pc~0; 29494#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29778#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30279#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30082#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 29765#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29766#L1434 assume !(1 == ~M_E~0); 30287#L1434-2 assume !(1 == ~T1_E~0); 30363#L1439-1 assume !(1 == ~T2_E~0); 28678#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28679#L1449-1 assume !(1 == ~T4_E~0); 29121#L1454-1 assume !(1 == ~T5_E~0); 29122#L1459-1 assume !(1 == ~T6_E~0); 29693#L1464-1 assume !(1 == ~T7_E~0); 29694#L1469-1 assume !(1 == ~T8_E~0); 29779#L1474-1 assume !(1 == ~T9_E~0); 29457#L1479-1 assume !(1 == ~T10_E~0); 29458#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29701#L1489-1 assume !(1 == ~T12_E~0); 29335#L1494-1 assume !(1 == ~T13_E~0); 29336#L1499-1 assume !(1 == ~E_M~0); 29517#L1504-1 assume !(1 == ~E_1~0); 29518#L1509-1 assume !(1 == ~E_2~0); 30131#L1514-1 assume !(1 == ~E_3~0); 29816#L1519-1 assume !(1 == ~E_4~0); 29817#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30321#L1529-1 assume !(1 == ~E_6~0); 30322#L1534-1 assume !(1 == ~E_7~0); 28468#L1539-1 assume !(1 == ~E_8~0); 28469#L1544-1 assume !(1 == ~E_9~0); 28899#L1549-1 assume !(1 == ~E_10~0); 30299#L1554-1 assume !(1 == ~E_11~0); 30297#L1559-1 assume !(1 == ~E_12~0); 30159#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30160#L1569-1 assume { :end_inline_reset_delta_events } true; 30315#L1935-2 [2022-11-16 11:07:10,360 INFO L750 eck$LassoCheckResult]: Loop: 30315#L1935-2 assume !false; 28477#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28478#L1261 assume !false; 29705#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29706#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28608#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28778#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28779#L1074 assume !(0 != eval_~tmp~0#1); 29136#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29734#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30135#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30191#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29910#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29911#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30347#L1301-3 assume !(0 == ~T4_E~0); 30305#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29413#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28712#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28713#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28818#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29554#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29819#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29820#L1341-3 assume !(0 == ~T12_E~0); 29114#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29105#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29049#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29050#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29630#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28403#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28404#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30146#L1381-3 assume !(0 == ~E_6~0); 29995#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29996#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30177#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30178#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28783#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28614#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28615#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29242#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28492#L635-45 assume 1 == ~m_pc~0; 28493#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29287#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29767#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30021#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28801#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28802#L654-45 assume 1 == ~t1_pc~0; 29622#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29970#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28455#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28456#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28481#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29308#L673-45 assume !(1 == ~t2_pc~0); 29309#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29633#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29634#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30259#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 30079#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28926#L692-45 assume !(1 == ~t3_pc~0); 28652#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 28653#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29697#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28980#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28981#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29293#L711-45 assume 1 == ~t4_pc~0; 29417#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29418#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29270#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29271#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29674#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28825#L730-45 assume 1 == ~t5_pc~0; 28663#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28664#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29073#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29074#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29825#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28636#L749-45 assume !(1 == ~t6_pc~0); 28637#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 30037#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29800#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29801#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29952#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28952#L768-45 assume 1 == ~t7_pc~0; 28953#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29092#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29896#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29897#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29936#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29937#L787-45 assume 1 == ~t8_pc~0; 30105#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29098#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29099#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29515#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29516#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29824#L806-45 assume 1 == ~t9_pc~0; 30300#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28512#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29337#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29165#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29077#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29078#L825-45 assume !(1 == ~t10_pc~0); 29601#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 29602#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29707#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29708#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29860#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28720#L844-45 assume !(1 == ~t11_pc~0); 28721#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29243#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29244#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29260#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 29671#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28760#L863-45 assume 1 == ~t12_pc~0; 28761#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28361#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28362#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28877#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28878#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29677#L882-45 assume !(1 == ~t13_pc~0); 29207#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 28380#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 28381#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 28989#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30168#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29784#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29785#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29969#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28674#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28675#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28837#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29774#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29775#L1464-3 assume !(1 == ~T7_E~0); 30221#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30148#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30149#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30223#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29415#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29416#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 30076#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29711#L1504-3 assume !(1 == ~E_1~0); 29712#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30157#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30197#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29338#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29339#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30244#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29639#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29093#L1544-3 assume !(1 == ~E_9~0); 29094#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29609#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28725#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28726#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29875#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29876#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28610#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29175#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29846#L1954 assume !(0 == start_simulation_~tmp~3#1); 29848#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30098#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28893#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29934#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 30064#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30065#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30155#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30217#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 30315#L1935-2 [2022-11-16 11:07:10,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:10,361 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2022-11-16 11:07:10,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:10,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052571615] [2022-11-16 11:07:10,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:10,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:10,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:10,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:10,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:10,424 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052571615] [2022-11-16 11:07:10,424 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052571615] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:10,424 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:10,425 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:10,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1513161368] [2022-11-16 11:07:10,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:10,426 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:10,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:10,426 INFO L85 PathProgramCache]: Analyzing trace with hash 1143723556, now seen corresponding path program 2 times [2022-11-16 11:07:10,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:10,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707556309] [2022-11-16 11:07:10,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:10,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:10,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:10,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:10,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:10,525 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707556309] [2022-11-16 11:07:10,527 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707556309] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:10,528 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:10,528 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:10,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306919337] [2022-11-16 11:07:10,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:10,530 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:10,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:10,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:10,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:10,531 INFO L87 Difference]: Start difference. First operand 2021 states and 2986 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:10,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:10,607 INFO L93 Difference]: Finished difference Result 2021 states and 2985 transitions. [2022-11-16 11:07:10,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2985 transitions. [2022-11-16 11:07:10,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:10,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2985 transitions. [2022-11-16 11:07:10,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:10,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:10,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2985 transitions. [2022-11-16 11:07:10,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:10,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2022-11-16 11:07:10,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2985 transitions. [2022-11-16 11:07:10,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:10,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4769915883226126) internal successors, (2985), 2020 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:10,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2985 transitions. [2022-11-16 11:07:10,678 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2022-11-16 11:07:10,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:10,682 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2985 transitions. [2022-11-16 11:07:10,682 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 11:07:10,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2985 transitions. [2022-11-16 11:07:10,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:10,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:10,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:10,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:10,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:10,696 INFO L748 eck$LassoCheckResult]: Stem: 33284#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 33285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33016#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33017#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34407#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 34408#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33203#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33204#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33238#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34075#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34076#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34188#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34189#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33022#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33023#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 34225#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33547#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33548#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 34129#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34395#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 34285#L1286-2 assume !(0 == ~T1_E~0); 32931#L1291-1 assume !(0 == ~T2_E~0); 32932#L1296-1 assume !(0 == ~T3_E~0); 33637#L1301-1 assume !(0 == ~T4_E~0); 33638#L1306-1 assume !(0 == ~T5_E~0); 34138#L1311-1 assume !(0 == ~T6_E~0); 32891#L1316-1 assume !(0 == ~T7_E~0); 32892#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33657#L1326-1 assume !(0 == ~T9_E~0); 32706#L1331-1 assume !(0 == ~T10_E~0); 32412#L1336-1 assume !(0 == ~T11_E~0); 32413#L1341-1 assume !(0 == ~T12_E~0); 32464#L1346-1 assume !(0 == ~T13_E~0); 32465#L1351-1 assume !(0 == ~E_M~0); 32838#L1356-1 assume !(0 == ~E_1~0); 32839#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 34358#L1366-1 assume !(0 == ~E_3~0); 32884#L1371-1 assume !(0 == ~E_4~0); 32885#L1376-1 assume !(0 == ~E_5~0); 33698#L1381-1 assume !(0 == ~E_6~0); 33699#L1386-1 assume !(0 == ~E_7~0); 34386#L1391-1 assume !(0 == ~E_8~0); 34399#L1396-1 assume !(0 == ~E_9~0); 33581#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 33582#L1406-1 assume !(0 == ~E_11~0); 33884#L1411-1 assume !(0 == ~E_12~0); 33885#L1416-1 assume !(0 == ~E_13~0); 33505#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33343#L635 assume !(1 == ~m_pc~0); 32482#L635-2 is_master_triggered_~__retres1~0#1 := 0; 32483#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32833#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33469#L1598 assume !(0 != activate_threads_~tmp~1#1); 32661#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32662#L654 assume 1 == ~t1_pc~0; 33367#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33368#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34383#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33449#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 33450#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32709#L673 assume 1 == ~t2_pc~0; 32710#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33854#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33855#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34413#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 34420#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33528#L692 assume !(1 == ~t3_pc~0); 33345#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33346#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33205#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33173#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33174#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32734#L711 assume 1 == ~t4_pc~0; 32735#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33218#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33675#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32437#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 32438#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34406#L730 assume !(1 == ~t5_pc~0); 33788#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32616#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32617#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32744#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 32745#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33087#L749 assume 1 == ~t6_pc~0; 32861#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32621#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33053#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33054#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 33276#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32417#L768 assume !(1 == ~t7_pc~0); 32418#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33722#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32654#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32655#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 33741#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32893#L787 assume 1 == ~t8_pc~0; 32894#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34089#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34253#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34254#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 32462#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32463#L806 assume 1 == ~t9_pc~0; 34100#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32497#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32498#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32746#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 32747#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34083#L825 assume !(1 == ~t10_pc~0); 34084#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33689#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33690#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32834#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32835#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33418#L844 assume 1 == ~t11_pc~0; 33108#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33109#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33475#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33476#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 34071#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34072#L863 assume !(1 == ~t12_pc~0); 32597#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 32596#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32824#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34163#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 34164#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33542#L882 assume 1 == ~t13_pc~0; 33543#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33827#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34328#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34131#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 33814#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33815#L1434 assume !(1 == ~M_E~0); 34336#L1434-2 assume !(1 == ~T1_E~0); 34412#L1439-1 assume !(1 == ~T2_E~0); 32727#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32728#L1449-1 assume !(1 == ~T4_E~0); 33170#L1454-1 assume !(1 == ~T5_E~0); 33171#L1459-1 assume !(1 == ~T6_E~0); 33742#L1464-1 assume !(1 == ~T7_E~0); 33743#L1469-1 assume !(1 == ~T8_E~0); 33828#L1474-1 assume !(1 == ~T9_E~0); 33506#L1479-1 assume !(1 == ~T10_E~0); 33507#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33750#L1489-1 assume !(1 == ~T12_E~0); 33384#L1494-1 assume !(1 == ~T13_E~0); 33385#L1499-1 assume !(1 == ~E_M~0); 33566#L1504-1 assume !(1 == ~E_1~0); 33567#L1509-1 assume !(1 == ~E_2~0); 34180#L1514-1 assume !(1 == ~E_3~0); 33865#L1519-1 assume !(1 == ~E_4~0); 33866#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34370#L1529-1 assume !(1 == ~E_6~0); 34371#L1534-1 assume !(1 == ~E_7~0); 32517#L1539-1 assume !(1 == ~E_8~0); 32518#L1544-1 assume !(1 == ~E_9~0); 32948#L1549-1 assume !(1 == ~E_10~0); 34348#L1554-1 assume !(1 == ~E_11~0); 34346#L1559-1 assume !(1 == ~E_12~0); 34208#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 34209#L1569-1 assume { :end_inline_reset_delta_events } true; 34364#L1935-2 [2022-11-16 11:07:10,696 INFO L750 eck$LassoCheckResult]: Loop: 34364#L1935-2 assume !false; 32526#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32527#L1261 assume !false; 33754#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33755#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32657#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32827#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32828#L1074 assume !(0 != eval_~tmp~0#1); 33185#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33783#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34184#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34240#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33959#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33960#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34396#L1301-3 assume !(0 == ~T4_E~0); 34354#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33462#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32761#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32762#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32867#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33603#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33868#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33869#L1341-3 assume !(0 == ~T12_E~0); 33163#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33154#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33098#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33099#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33679#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32452#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32453#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34195#L1381-3 assume !(0 == ~E_6~0); 34044#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34045#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34226#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34227#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32832#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32663#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32664#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33291#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32541#L635-45 assume 1 == ~m_pc~0; 32542#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33336#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33816#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34070#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32850#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32851#L654-45 assume 1 == ~t1_pc~0; 33671#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34019#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32504#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32505#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32530#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33357#L673-45 assume !(1 == ~t2_pc~0); 33358#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 33682#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33683#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34308#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 34128#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32975#L692-45 assume 1 == ~t3_pc~0; 32976#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32702#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33746#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33029#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33030#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33342#L711-45 assume 1 == ~t4_pc~0; 33466#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33467#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33319#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33320#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33723#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32874#L730-45 assume 1 == ~t5_pc~0; 32712#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32713#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33122#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33123#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33874#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32685#L749-45 assume !(1 == ~t6_pc~0); 32686#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 34086#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33849#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33850#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34001#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33001#L768-45 assume 1 == ~t7_pc~0; 33002#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33141#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33945#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33946#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33985#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33986#L787-45 assume 1 == ~t8_pc~0; 34154#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33147#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33148#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33564#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33565#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33873#L806-45 assume !(1 == ~t9_pc~0); 32560#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 32561#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33386#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33214#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33126#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33127#L825-45 assume !(1 == ~t10_pc~0); 33650#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 33651#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33756#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33757#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33909#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32769#L844-45 assume !(1 == ~t11_pc~0); 32770#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 33292#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33293#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33309#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 33720#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32809#L863-45 assume 1 == ~t12_pc~0; 32810#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32410#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32411#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 32926#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32927#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33726#L882-45 assume 1 == ~t13_pc~0; 34080#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 32429#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 32430#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33038#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34217#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33833#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33834#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34018#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32723#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32724#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32886#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33823#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33824#L1464-3 assume !(1 == ~T7_E~0); 34270#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34197#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34198#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34272#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33464#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33465#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34125#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33760#L1504-3 assume !(1 == ~E_1~0); 33761#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34206#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34246#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33387#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33388#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34293#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33688#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33142#L1544-3 assume !(1 == ~E_9~0); 33143#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33658#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32774#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32775#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33924#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33925#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32659#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33224#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33895#L1954 assume !(0 == start_simulation_~tmp~3#1); 33897#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34147#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32942#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33983#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34113#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34114#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34204#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34266#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 34364#L1935-2 [2022-11-16 11:07:10,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:10,698 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2022-11-16 11:07:10,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:10,698 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751367437] [2022-11-16 11:07:10,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:10,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:10,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:10,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:10,757 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:10,757 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751367437] [2022-11-16 11:07:10,757 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751367437] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:10,757 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:10,758 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:10,758 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103238687] [2022-11-16 11:07:10,758 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:10,759 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:10,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:10,759 INFO L85 PathProgramCache]: Analyzing trace with hash -289217245, now seen corresponding path program 1 times [2022-11-16 11:07:10,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:10,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035314337] [2022-11-16 11:07:10,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:10,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:10,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:10,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:10,843 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:10,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035314337] [2022-11-16 11:07:10,844 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2035314337] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:10,844 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:10,844 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:10,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140403686] [2022-11-16 11:07:10,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:10,845 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:10,845 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:10,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:10,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:10,846 INFO L87 Difference]: Start difference. First operand 2021 states and 2985 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:10,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:10,898 INFO L93 Difference]: Finished difference Result 2021 states and 2984 transitions. [2022-11-16 11:07:10,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2984 transitions. [2022-11-16 11:07:10,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:10,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2984 transitions. [2022-11-16 11:07:10,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:10,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:10,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2984 transitions. [2022-11-16 11:07:10,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:10,939 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2022-11-16 11:07:10,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2984 transitions. [2022-11-16 11:07:10,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:10,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4764967837704106) internal successors, (2984), 2020 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:10,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2984 transitions. [2022-11-16 11:07:10,998 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2022-11-16 11:07:10,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:10,999 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2984 transitions. [2022-11-16 11:07:11,000 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 11:07:11,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2984 transitions. [2022-11-16 11:07:11,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:11,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:11,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:11,013 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:11,013 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:11,014 INFO L748 eck$LassoCheckResult]: Stem: 37333#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 37334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37065#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37066#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38456#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 38457#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37252#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37253#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37287#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38124#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38125#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38237#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38238#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37071#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37072#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 38274#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37596#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37597#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38178#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38444#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 38334#L1286-2 assume !(0 == ~T1_E~0); 36980#L1291-1 assume !(0 == ~T2_E~0); 36981#L1296-1 assume !(0 == ~T3_E~0); 37686#L1301-1 assume !(0 == ~T4_E~0); 37687#L1306-1 assume !(0 == ~T5_E~0); 38187#L1311-1 assume !(0 == ~T6_E~0); 36940#L1316-1 assume !(0 == ~T7_E~0); 36941#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37706#L1326-1 assume !(0 == ~T9_E~0); 36755#L1331-1 assume !(0 == ~T10_E~0); 36461#L1336-1 assume !(0 == ~T11_E~0); 36462#L1341-1 assume !(0 == ~T12_E~0); 36513#L1346-1 assume !(0 == ~T13_E~0); 36514#L1351-1 assume !(0 == ~E_M~0); 36887#L1356-1 assume !(0 == ~E_1~0); 36888#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 38407#L1366-1 assume !(0 == ~E_3~0); 36933#L1371-1 assume !(0 == ~E_4~0); 36934#L1376-1 assume !(0 == ~E_5~0); 37747#L1381-1 assume !(0 == ~E_6~0); 37748#L1386-1 assume !(0 == ~E_7~0); 38435#L1391-1 assume !(0 == ~E_8~0); 38448#L1396-1 assume !(0 == ~E_9~0); 37630#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 37631#L1406-1 assume !(0 == ~E_11~0); 37933#L1411-1 assume !(0 == ~E_12~0); 37934#L1416-1 assume !(0 == ~E_13~0); 37554#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37392#L635 assume !(1 == ~m_pc~0); 36531#L635-2 is_master_triggered_~__retres1~0#1 := 0; 36532#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36882#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37518#L1598 assume !(0 != activate_threads_~tmp~1#1); 36710#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36711#L654 assume 1 == ~t1_pc~0; 37416#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37417#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38432#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37498#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 37499#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36758#L673 assume 1 == ~t2_pc~0; 36759#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37903#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37904#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38462#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 38469#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37577#L692 assume !(1 == ~t3_pc~0); 37394#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37395#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37254#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37222#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37223#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36783#L711 assume 1 == ~t4_pc~0; 36784#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37267#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37724#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36486#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 36487#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38455#L730 assume !(1 == ~t5_pc~0); 37837#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36665#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36666#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36793#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 36794#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37136#L749 assume 1 == ~t6_pc~0; 36910#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36670#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37102#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37103#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 37325#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36466#L768 assume !(1 == ~t7_pc~0); 36467#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37771#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36703#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36704#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 37790#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36942#L787 assume 1 == ~t8_pc~0; 36943#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38138#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38302#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38303#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 36511#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36512#L806 assume 1 == ~t9_pc~0; 38149#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36546#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36547#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36795#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 36796#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38132#L825 assume !(1 == ~t10_pc~0); 38133#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37738#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37739#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36883#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36884#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37467#L844 assume 1 == ~t11_pc~0; 37157#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37158#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37524#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37525#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 38120#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38121#L863 assume !(1 == ~t12_pc~0); 36646#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36645#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36873#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38212#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 38213#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37591#L882 assume 1 == ~t13_pc~0; 37592#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37876#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38377#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38180#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 37863#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37864#L1434 assume !(1 == ~M_E~0); 38385#L1434-2 assume !(1 == ~T1_E~0); 38461#L1439-1 assume !(1 == ~T2_E~0); 36776#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36777#L1449-1 assume !(1 == ~T4_E~0); 37219#L1454-1 assume !(1 == ~T5_E~0); 37220#L1459-1 assume !(1 == ~T6_E~0); 37791#L1464-1 assume !(1 == ~T7_E~0); 37792#L1469-1 assume !(1 == ~T8_E~0); 37877#L1474-1 assume !(1 == ~T9_E~0); 37555#L1479-1 assume !(1 == ~T10_E~0); 37556#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37799#L1489-1 assume !(1 == ~T12_E~0); 37433#L1494-1 assume !(1 == ~T13_E~0); 37434#L1499-1 assume !(1 == ~E_M~0); 37615#L1504-1 assume !(1 == ~E_1~0); 37616#L1509-1 assume !(1 == ~E_2~0); 38229#L1514-1 assume !(1 == ~E_3~0); 37914#L1519-1 assume !(1 == ~E_4~0); 37915#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38419#L1529-1 assume !(1 == ~E_6~0); 38420#L1534-1 assume !(1 == ~E_7~0); 36566#L1539-1 assume !(1 == ~E_8~0); 36567#L1544-1 assume !(1 == ~E_9~0); 36997#L1549-1 assume !(1 == ~E_10~0); 38397#L1554-1 assume !(1 == ~E_11~0); 38395#L1559-1 assume !(1 == ~E_12~0); 38257#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38258#L1569-1 assume { :end_inline_reset_delta_events } true; 38413#L1935-2 [2022-11-16 11:07:11,015 INFO L750 eck$LassoCheckResult]: Loop: 38413#L1935-2 assume !false; 36575#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36576#L1261 assume !false; 37803#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37804#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36706#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36876#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36877#L1074 assume !(0 != eval_~tmp~0#1); 37234#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37832#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38233#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38289#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38008#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38009#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38445#L1301-3 assume !(0 == ~T4_E~0); 38403#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37511#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36810#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36811#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36916#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37652#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37917#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37918#L1341-3 assume !(0 == ~T12_E~0); 37212#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37203#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37147#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37148#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37728#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36501#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36502#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38244#L1381-3 assume !(0 == ~E_6~0); 38093#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38094#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38275#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38276#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36881#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36712#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36713#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37340#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36590#L635-45 assume !(1 == ~m_pc~0); 36592#L635-47 is_master_triggered_~__retres1~0#1 := 0; 37385#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37865#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38119#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36899#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36900#L654-45 assume 1 == ~t1_pc~0; 37720#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38068#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36553#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36554#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36579#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37406#L673-45 assume 1 == ~t2_pc~0; 37408#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37731#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37732#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38357#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 38177#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37024#L692-45 assume 1 == ~t3_pc~0; 37025#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36751#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37795#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37078#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37079#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37391#L711-45 assume 1 == ~t4_pc~0; 37515#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37516#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37368#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37369#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37772#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36923#L730-45 assume 1 == ~t5_pc~0; 36761#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36762#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37171#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37172#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37923#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36734#L749-45 assume 1 == ~t6_pc~0; 36736#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38135#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37898#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37899#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38050#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37050#L768-45 assume 1 == ~t7_pc~0; 37051#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37190#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37994#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37995#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38034#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38035#L787-45 assume 1 == ~t8_pc~0; 38203#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37196#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37197#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37613#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37614#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37922#L806-45 assume !(1 == ~t9_pc~0); 36609#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 36610#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37435#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37263#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37175#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37176#L825-45 assume !(1 == ~t10_pc~0); 37699#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 37700#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37805#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37806#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37958#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36818#L844-45 assume !(1 == ~t11_pc~0); 36819#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37341#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37342#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37358#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 37769#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36858#L863-45 assume 1 == ~t12_pc~0; 36859#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36459#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36460#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 36975#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36976#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37775#L882-45 assume 1 == ~t13_pc~0; 38129#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 36478#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 36479#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37087#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38266#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37882#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37883#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38067#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36772#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36773#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36935#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37872#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37873#L1464-3 assume !(1 == ~T7_E~0); 38319#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38246#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38247#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38321#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37513#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37514#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38174#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37809#L1504-3 assume !(1 == ~E_1~0); 37810#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38255#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38295#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37436#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37437#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38342#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37737#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37191#L1544-3 assume !(1 == ~E_9~0); 37192#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37707#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36823#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 36824#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37973#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37974#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36708#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37273#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37944#L1954 assume !(0 == start_simulation_~tmp~3#1); 37946#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38196#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36991#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38032#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38162#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38163#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38253#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38315#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 38413#L1935-2 [2022-11-16 11:07:11,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:11,016 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2022-11-16 11:07:11,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:11,016 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235127165] [2022-11-16 11:07:11,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:11,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:11,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:11,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:11,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:11,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1235127165] [2022-11-16 11:07:11,077 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1235127165] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:11,077 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:11,077 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:11,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010924946] [2022-11-16 11:07:11,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:11,078 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:11,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:11,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1698619550, now seen corresponding path program 1 times [2022-11-16 11:07:11,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:11,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294570036] [2022-11-16 11:07:11,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:11,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:11,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:11,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:11,156 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:11,156 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294570036] [2022-11-16 11:07:11,156 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294570036] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:11,157 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:11,157 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:11,157 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346420025] [2022-11-16 11:07:11,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:11,158 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:11,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:11,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:11,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:11,160 INFO L87 Difference]: Start difference. First operand 2021 states and 2984 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:11,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:11,259 INFO L93 Difference]: Finished difference Result 2021 states and 2983 transitions. [2022-11-16 11:07:11,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2983 transitions. [2022-11-16 11:07:11,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:11,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2983 transitions. [2022-11-16 11:07:11,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:11,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:11,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2983 transitions. [2022-11-16 11:07:11,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:11,291 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2022-11-16 11:07:11,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2983 transitions. [2022-11-16 11:07:11,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:11,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4760019792182089) internal successors, (2983), 2020 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:11,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2983 transitions. [2022-11-16 11:07:11,343 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2022-11-16 11:07:11,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:11,344 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2983 transitions. [2022-11-16 11:07:11,345 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 11:07:11,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2983 transitions. [2022-11-16 11:07:11,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:11,357 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:11,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:11,360 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:11,361 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:11,361 INFO L748 eck$LassoCheckResult]: Stem: 41382#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 41383#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 41114#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41115#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42505#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 42506#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41301#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41302#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41336#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42173#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42174#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42286#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42287#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41120#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41121#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42323#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41645#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41646#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42227#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42493#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 42383#L1286-2 assume !(0 == ~T1_E~0); 41029#L1291-1 assume !(0 == ~T2_E~0); 41030#L1296-1 assume !(0 == ~T3_E~0); 41735#L1301-1 assume !(0 == ~T4_E~0); 41736#L1306-1 assume !(0 == ~T5_E~0); 42236#L1311-1 assume !(0 == ~T6_E~0); 40989#L1316-1 assume !(0 == ~T7_E~0); 40990#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41755#L1326-1 assume !(0 == ~T9_E~0); 40804#L1331-1 assume !(0 == ~T10_E~0); 40510#L1336-1 assume !(0 == ~T11_E~0); 40511#L1341-1 assume !(0 == ~T12_E~0); 40562#L1346-1 assume !(0 == ~T13_E~0); 40563#L1351-1 assume !(0 == ~E_M~0); 40936#L1356-1 assume !(0 == ~E_1~0); 40937#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 42456#L1366-1 assume !(0 == ~E_3~0); 40982#L1371-1 assume !(0 == ~E_4~0); 40983#L1376-1 assume !(0 == ~E_5~0); 41796#L1381-1 assume !(0 == ~E_6~0); 41797#L1386-1 assume !(0 == ~E_7~0); 42484#L1391-1 assume !(0 == ~E_8~0); 42497#L1396-1 assume !(0 == ~E_9~0); 41679#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 41680#L1406-1 assume !(0 == ~E_11~0); 41982#L1411-1 assume !(0 == ~E_12~0); 41983#L1416-1 assume !(0 == ~E_13~0); 41603#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41441#L635 assume !(1 == ~m_pc~0); 40580#L635-2 is_master_triggered_~__retres1~0#1 := 0; 40581#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40931#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41567#L1598 assume !(0 != activate_threads_~tmp~1#1); 40759#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40760#L654 assume 1 == ~t1_pc~0; 41465#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41466#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42481#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41547#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 41548#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40807#L673 assume 1 == ~t2_pc~0; 40808#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41952#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41953#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42511#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 42518#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41626#L692 assume !(1 == ~t3_pc~0); 41443#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41444#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41303#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41271#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41272#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40832#L711 assume 1 == ~t4_pc~0; 40833#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41316#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41773#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40535#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 40536#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42504#L730 assume !(1 == ~t5_pc~0); 41886#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40714#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40715#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40842#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 40843#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41185#L749 assume 1 == ~t6_pc~0; 40959#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40719#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41151#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41152#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 41374#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40515#L768 assume !(1 == ~t7_pc~0); 40516#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41820#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40752#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40753#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 41839#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40991#L787 assume 1 == ~t8_pc~0; 40992#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42187#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42351#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42352#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 40560#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40561#L806 assume 1 == ~t9_pc~0; 42198#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40595#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40596#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40844#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 40845#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42181#L825 assume !(1 == ~t10_pc~0); 42182#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41787#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41788#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40932#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40933#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41516#L844 assume 1 == ~t11_pc~0; 41206#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41207#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41573#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41574#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 42169#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42170#L863 assume !(1 == ~t12_pc~0); 40695#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40694#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40922#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42261#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 42262#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41640#L882 assume 1 == ~t13_pc~0; 41641#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41925#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42426#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42229#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 41912#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41913#L1434 assume !(1 == ~M_E~0); 42434#L1434-2 assume !(1 == ~T1_E~0); 42510#L1439-1 assume !(1 == ~T2_E~0); 40825#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40826#L1449-1 assume !(1 == ~T4_E~0); 41268#L1454-1 assume !(1 == ~T5_E~0); 41269#L1459-1 assume !(1 == ~T6_E~0); 41840#L1464-1 assume !(1 == ~T7_E~0); 41841#L1469-1 assume !(1 == ~T8_E~0); 41926#L1474-1 assume !(1 == ~T9_E~0); 41604#L1479-1 assume !(1 == ~T10_E~0); 41605#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41848#L1489-1 assume !(1 == ~T12_E~0); 41482#L1494-1 assume !(1 == ~T13_E~0); 41483#L1499-1 assume !(1 == ~E_M~0); 41664#L1504-1 assume !(1 == ~E_1~0); 41665#L1509-1 assume !(1 == ~E_2~0); 42278#L1514-1 assume !(1 == ~E_3~0); 41963#L1519-1 assume !(1 == ~E_4~0); 41964#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42468#L1529-1 assume !(1 == ~E_6~0); 42469#L1534-1 assume !(1 == ~E_7~0); 40615#L1539-1 assume !(1 == ~E_8~0); 40616#L1544-1 assume !(1 == ~E_9~0); 41046#L1549-1 assume !(1 == ~E_10~0); 42446#L1554-1 assume !(1 == ~E_11~0); 42444#L1559-1 assume !(1 == ~E_12~0); 42306#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 42307#L1569-1 assume { :end_inline_reset_delta_events } true; 42462#L1935-2 [2022-11-16 11:07:11,362 INFO L750 eck$LassoCheckResult]: Loop: 42462#L1935-2 assume !false; 40624#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40625#L1261 assume !false; 41852#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41853#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40755#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40925#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40926#L1074 assume !(0 != eval_~tmp~0#1); 41283#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41881#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42282#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42338#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42057#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42058#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42494#L1301-3 assume !(0 == ~T4_E~0); 42452#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41560#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40859#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40860#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40965#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41701#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41966#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41967#L1341-3 assume !(0 == ~T12_E~0); 41261#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41252#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41196#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41197#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41777#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40550#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40551#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42293#L1381-3 assume !(0 == ~E_6~0); 42142#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42143#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42324#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42325#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40930#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40761#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40762#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41389#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40639#L635-45 assume 1 == ~m_pc~0; 40640#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41434#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41914#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42168#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40948#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40949#L654-45 assume 1 == ~t1_pc~0; 41769#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42117#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40602#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40603#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40628#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41455#L673-45 assume !(1 == ~t2_pc~0); 41456#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 41780#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41781#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42406#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 42226#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41073#L692-45 assume 1 == ~t3_pc~0; 41074#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40800#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41844#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41127#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41128#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41440#L711-45 assume 1 == ~t4_pc~0; 41564#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41565#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41417#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41418#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41821#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40972#L730-45 assume 1 == ~t5_pc~0; 40810#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40811#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41220#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41221#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41972#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40783#L749-45 assume !(1 == ~t6_pc~0); 40784#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 42184#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41947#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41948#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42099#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41099#L768-45 assume 1 == ~t7_pc~0; 41100#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41239#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42043#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42044#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42083#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42084#L787-45 assume 1 == ~t8_pc~0; 42252#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41245#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41246#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41662#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41663#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41971#L806-45 assume !(1 == ~t9_pc~0); 40658#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 40659#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41484#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41312#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41224#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41225#L825-45 assume !(1 == ~t10_pc~0); 41748#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 41749#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41854#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41855#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42007#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40867#L844-45 assume !(1 == ~t11_pc~0); 40868#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41390#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41391#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41407#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 41818#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40907#L863-45 assume 1 == ~t12_pc~0; 40908#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40508#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40509#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41024#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41025#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41824#L882-45 assume 1 == ~t13_pc~0; 42178#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 40527#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 40528#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41136#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42315#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41931#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41932#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42116#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40821#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40822#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40984#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41921#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41922#L1464-3 assume !(1 == ~T7_E~0); 42368#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42295#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42296#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42370#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41562#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41563#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42223#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41858#L1504-3 assume !(1 == ~E_1~0); 41859#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42304#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42344#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41485#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41486#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42391#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41786#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41240#L1544-3 assume !(1 == ~E_9~0); 41241#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41756#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40872#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40873#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42022#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42023#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40757#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41322#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41993#L1954 assume !(0 == start_simulation_~tmp~3#1); 41995#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42245#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41040#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42081#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42211#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42212#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42302#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42364#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 42462#L1935-2 [2022-11-16 11:07:11,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:11,364 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2022-11-16 11:07:11,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:11,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566168582] [2022-11-16 11:07:11,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:11,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:11,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:11,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:11,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:11,442 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1566168582] [2022-11-16 11:07:11,443 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1566168582] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:11,443 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:11,443 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:11,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511179961] [2022-11-16 11:07:11,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:11,444 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:11,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:11,445 INFO L85 PathProgramCache]: Analyzing trace with hash -289217245, now seen corresponding path program 2 times [2022-11-16 11:07:11,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:11,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31146019] [2022-11-16 11:07:11,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:11,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:11,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:11,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:11,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:11,585 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31146019] [2022-11-16 11:07:11,585 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [31146019] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:11,585 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:11,585 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:11,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [178446267] [2022-11-16 11:07:11,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:11,587 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:11,587 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:11,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:11,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:11,588 INFO L87 Difference]: Start difference. First operand 2021 states and 2983 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:11,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:11,653 INFO L93 Difference]: Finished difference Result 2021 states and 2982 transitions. [2022-11-16 11:07:11,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2982 transitions. [2022-11-16 11:07:11,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:11,678 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2982 transitions. [2022-11-16 11:07:11,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:11,681 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:11,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2982 transitions. [2022-11-16 11:07:11,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:11,686 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2022-11-16 11:07:11,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2982 transitions. [2022-11-16 11:07:11,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:11,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.475507174666007) internal successors, (2982), 2020 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:11,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2982 transitions. [2022-11-16 11:07:11,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2022-11-16 11:07:11,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:11,730 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2982 transitions. [2022-11-16 11:07:11,731 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 11:07:11,731 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2982 transitions. [2022-11-16 11:07:11,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:11,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:11,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:11,744 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:11,744 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:11,745 INFO L748 eck$LassoCheckResult]: Stem: 45431#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 45432#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 45163#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45164#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46554#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 46555#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45350#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45351#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45385#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46222#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46223#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46335#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46336#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45169#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45170#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46372#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45694#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45695#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46276#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46542#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 46432#L1286-2 assume !(0 == ~T1_E~0); 45078#L1291-1 assume !(0 == ~T2_E~0); 45079#L1296-1 assume !(0 == ~T3_E~0); 45784#L1301-1 assume !(0 == ~T4_E~0); 45785#L1306-1 assume !(0 == ~T5_E~0); 46285#L1311-1 assume !(0 == ~T6_E~0); 45038#L1316-1 assume !(0 == ~T7_E~0); 45039#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45804#L1326-1 assume !(0 == ~T9_E~0); 44853#L1331-1 assume !(0 == ~T10_E~0); 44559#L1336-1 assume !(0 == ~T11_E~0); 44560#L1341-1 assume !(0 == ~T12_E~0); 44611#L1346-1 assume !(0 == ~T13_E~0); 44612#L1351-1 assume !(0 == ~E_M~0); 44985#L1356-1 assume !(0 == ~E_1~0); 44986#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 46505#L1366-1 assume !(0 == ~E_3~0); 45031#L1371-1 assume !(0 == ~E_4~0); 45032#L1376-1 assume !(0 == ~E_5~0); 45845#L1381-1 assume !(0 == ~E_6~0); 45846#L1386-1 assume !(0 == ~E_7~0); 46533#L1391-1 assume !(0 == ~E_8~0); 46546#L1396-1 assume !(0 == ~E_9~0); 45728#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 45729#L1406-1 assume !(0 == ~E_11~0); 46031#L1411-1 assume !(0 == ~E_12~0); 46032#L1416-1 assume !(0 == ~E_13~0); 45652#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45490#L635 assume !(1 == ~m_pc~0); 44629#L635-2 is_master_triggered_~__retres1~0#1 := 0; 44630#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44980#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45616#L1598 assume !(0 != activate_threads_~tmp~1#1); 44808#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44809#L654 assume 1 == ~t1_pc~0; 45514#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45515#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46530#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45596#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 45597#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44856#L673 assume 1 == ~t2_pc~0; 44857#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46001#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46002#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46560#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 46567#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45675#L692 assume !(1 == ~t3_pc~0); 45492#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45493#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45352#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45320#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45321#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44881#L711 assume 1 == ~t4_pc~0; 44882#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45365#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45822#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44584#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 44585#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46553#L730 assume !(1 == ~t5_pc~0); 45935#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 44763#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44764#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44891#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 44892#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45234#L749 assume 1 == ~t6_pc~0; 45008#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44768#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45200#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45201#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 45423#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44564#L768 assume !(1 == ~t7_pc~0); 44565#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45869#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44801#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44802#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 45888#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45040#L787 assume 1 == ~t8_pc~0; 45041#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46236#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46400#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46401#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 44609#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44610#L806 assume 1 == ~t9_pc~0; 46247#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44644#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44645#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44893#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 44894#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46230#L825 assume !(1 == ~t10_pc~0); 46231#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45836#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45837#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44981#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44982#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45565#L844 assume 1 == ~t11_pc~0; 45255#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45256#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45622#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45623#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 46218#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46219#L863 assume !(1 == ~t12_pc~0); 44744#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44743#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44971#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46310#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 46311#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45689#L882 assume 1 == ~t13_pc~0; 45690#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45974#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46475#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46278#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 45961#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45962#L1434 assume !(1 == ~M_E~0); 46483#L1434-2 assume !(1 == ~T1_E~0); 46559#L1439-1 assume !(1 == ~T2_E~0); 44874#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44875#L1449-1 assume !(1 == ~T4_E~0); 45317#L1454-1 assume !(1 == ~T5_E~0); 45318#L1459-1 assume !(1 == ~T6_E~0); 45889#L1464-1 assume !(1 == ~T7_E~0); 45890#L1469-1 assume !(1 == ~T8_E~0); 45975#L1474-1 assume !(1 == ~T9_E~0); 45653#L1479-1 assume !(1 == ~T10_E~0); 45654#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45897#L1489-1 assume !(1 == ~T12_E~0); 45531#L1494-1 assume !(1 == ~T13_E~0); 45532#L1499-1 assume !(1 == ~E_M~0); 45713#L1504-1 assume !(1 == ~E_1~0); 45714#L1509-1 assume !(1 == ~E_2~0); 46327#L1514-1 assume !(1 == ~E_3~0); 46012#L1519-1 assume !(1 == ~E_4~0); 46013#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46517#L1529-1 assume !(1 == ~E_6~0); 46518#L1534-1 assume !(1 == ~E_7~0); 44664#L1539-1 assume !(1 == ~E_8~0); 44665#L1544-1 assume !(1 == ~E_9~0); 45095#L1549-1 assume !(1 == ~E_10~0); 46495#L1554-1 assume !(1 == ~E_11~0); 46493#L1559-1 assume !(1 == ~E_12~0); 46355#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46356#L1569-1 assume { :end_inline_reset_delta_events } true; 46511#L1935-2 [2022-11-16 11:07:11,745 INFO L750 eck$LassoCheckResult]: Loop: 46511#L1935-2 assume !false; 44673#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44674#L1261 assume !false; 45901#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45902#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44804#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44974#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44975#L1074 assume !(0 != eval_~tmp~0#1); 45332#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45930#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46331#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46387#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46106#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46107#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46543#L1301-3 assume !(0 == ~T4_E~0); 46501#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45609#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44908#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44909#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45014#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45750#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46015#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46016#L1341-3 assume !(0 == ~T12_E~0); 45310#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45301#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45245#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45246#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45826#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44599#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44600#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46342#L1381-3 assume !(0 == ~E_6~0); 46191#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46192#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46373#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46374#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44979#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44810#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44811#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45438#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44688#L635-45 assume 1 == ~m_pc~0; 44689#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45483#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45963#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46217#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44997#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44998#L654-45 assume 1 == ~t1_pc~0; 45818#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46166#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44651#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44652#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44677#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45504#L673-45 assume !(1 == ~t2_pc~0); 45505#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45829#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45830#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46455#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 46275#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45122#L692-45 assume !(1 == ~t3_pc~0); 44848#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 44849#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45893#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45176#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45177#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45489#L711-45 assume 1 == ~t4_pc~0; 45613#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45614#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45466#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45467#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45870#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45021#L730-45 assume 1 == ~t5_pc~0; 44859#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44860#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45269#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45270#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46021#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44832#L749-45 assume !(1 == ~t6_pc~0); 44833#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 46233#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45996#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45997#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46148#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45148#L768-45 assume 1 == ~t7_pc~0; 45149#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45288#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46092#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46093#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46132#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46133#L787-45 assume 1 == ~t8_pc~0; 46301#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45294#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45295#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45711#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45712#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46020#L806-45 assume 1 == ~t9_pc~0; 46496#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44708#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45533#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45361#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45273#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45274#L825-45 assume !(1 == ~t10_pc~0); 45797#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 45798#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45903#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45904#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46056#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44916#L844-45 assume !(1 == ~t11_pc~0); 44917#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45439#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45440#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45456#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 45867#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44956#L863-45 assume 1 == ~t12_pc~0; 44957#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44557#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44558#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45073#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45074#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45873#L882-45 assume 1 == ~t13_pc~0; 46227#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 44576#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 44577#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45185#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46364#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45980#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45981#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46165#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44870#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44871#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45033#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45970#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45971#L1464-3 assume !(1 == ~T7_E~0); 46417#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46344#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46345#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46419#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45611#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45612#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46272#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45907#L1504-3 assume !(1 == ~E_1~0); 45908#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46353#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46393#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45534#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45535#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46440#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45835#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45289#L1544-3 assume !(1 == ~E_9~0); 45290#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 45805#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44921#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44922#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46071#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46072#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44806#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45371#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46042#L1954 assume !(0 == start_simulation_~tmp~3#1); 46044#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46294#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45089#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46130#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46260#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46261#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46351#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46413#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 46511#L1935-2 [2022-11-16 11:07:11,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:11,747 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2022-11-16 11:07:11,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:11,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284527696] [2022-11-16 11:07:11,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:11,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:11,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:11,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:11,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:11,805 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284527696] [2022-11-16 11:07:11,805 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1284527696] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:11,805 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:11,806 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:11,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949679628] [2022-11-16 11:07:11,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:11,807 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:11,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:11,807 INFO L85 PathProgramCache]: Analyzing trace with hash -1257801565, now seen corresponding path program 1 times [2022-11-16 11:07:11,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:11,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995150089] [2022-11-16 11:07:11,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:11,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:11,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:11,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:11,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:11,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [995150089] [2022-11-16 11:07:11,885 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [995150089] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:11,885 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:11,885 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:11,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819246630] [2022-11-16 11:07:11,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:11,886 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:11,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:11,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:11,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:11,887 INFO L87 Difference]: Start difference. First operand 2021 states and 2982 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:11,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:11,938 INFO L93 Difference]: Finished difference Result 2021 states and 2981 transitions. [2022-11-16 11:07:11,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2981 transitions. [2022-11-16 11:07:11,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:11,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2981 transitions. [2022-11-16 11:07:11,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:11,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:11,962 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2981 transitions. [2022-11-16 11:07:11,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:11,965 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2022-11-16 11:07:11,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2981 transitions. [2022-11-16 11:07:11,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:12,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4750123701138051) internal successors, (2981), 2020 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:12,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2981 transitions. [2022-11-16 11:07:12,006 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2022-11-16 11:07:12,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:12,007 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2981 transitions. [2022-11-16 11:07:12,007 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 11:07:12,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2981 transitions. [2022-11-16 11:07:12,017 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:12,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:12,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:12,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:12,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:12,021 INFO L748 eck$LassoCheckResult]: Stem: 49480#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 49481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 49212#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49213#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50603#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 50604#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49399#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49400#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49434#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50271#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50272#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50384#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50385#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49218#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49219#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50421#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49743#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49744#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50325#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50591#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 50481#L1286-2 assume !(0 == ~T1_E~0); 49127#L1291-1 assume !(0 == ~T2_E~0); 49128#L1296-1 assume !(0 == ~T3_E~0); 49833#L1301-1 assume !(0 == ~T4_E~0); 49834#L1306-1 assume !(0 == ~T5_E~0); 50334#L1311-1 assume !(0 == ~T6_E~0); 49087#L1316-1 assume !(0 == ~T7_E~0); 49088#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49853#L1326-1 assume !(0 == ~T9_E~0); 48902#L1331-1 assume !(0 == ~T10_E~0); 48608#L1336-1 assume !(0 == ~T11_E~0); 48609#L1341-1 assume !(0 == ~T12_E~0); 48660#L1346-1 assume !(0 == ~T13_E~0); 48661#L1351-1 assume !(0 == ~E_M~0); 49034#L1356-1 assume !(0 == ~E_1~0); 49035#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 50554#L1366-1 assume !(0 == ~E_3~0); 49080#L1371-1 assume !(0 == ~E_4~0); 49081#L1376-1 assume !(0 == ~E_5~0); 49894#L1381-1 assume !(0 == ~E_6~0); 49895#L1386-1 assume !(0 == ~E_7~0); 50582#L1391-1 assume !(0 == ~E_8~0); 50595#L1396-1 assume !(0 == ~E_9~0); 49777#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 49778#L1406-1 assume !(0 == ~E_11~0); 50080#L1411-1 assume !(0 == ~E_12~0); 50081#L1416-1 assume !(0 == ~E_13~0); 49701#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49539#L635 assume !(1 == ~m_pc~0); 48678#L635-2 is_master_triggered_~__retres1~0#1 := 0; 48679#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49029#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49665#L1598 assume !(0 != activate_threads_~tmp~1#1); 48857#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48858#L654 assume 1 == ~t1_pc~0; 49563#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49564#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50579#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49645#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 49646#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48905#L673 assume 1 == ~t2_pc~0; 48906#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50050#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50051#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50609#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 50616#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49724#L692 assume !(1 == ~t3_pc~0); 49541#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49542#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49401#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49369#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49370#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48930#L711 assume 1 == ~t4_pc~0; 48931#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49414#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49871#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48633#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 48634#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50602#L730 assume !(1 == ~t5_pc~0); 49984#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48812#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48813#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48940#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 48941#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49283#L749 assume 1 == ~t6_pc~0; 49057#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48817#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49249#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49250#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 49472#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48613#L768 assume !(1 == ~t7_pc~0); 48614#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49918#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48850#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48851#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 49937#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49089#L787 assume 1 == ~t8_pc~0; 49090#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50285#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50449#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50450#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 48658#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48659#L806 assume 1 == ~t9_pc~0; 50296#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48693#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48694#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48942#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 48943#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50279#L825 assume !(1 == ~t10_pc~0); 50280#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49885#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49886#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49030#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49031#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49614#L844 assume 1 == ~t11_pc~0; 49304#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49305#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49671#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49672#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 50267#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50268#L863 assume !(1 == ~t12_pc~0); 48793#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 48792#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49020#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50359#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 50360#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49738#L882 assume 1 == ~t13_pc~0; 49739#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50023#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50524#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50327#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 50010#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50011#L1434 assume !(1 == ~M_E~0); 50532#L1434-2 assume !(1 == ~T1_E~0); 50608#L1439-1 assume !(1 == ~T2_E~0); 48923#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48924#L1449-1 assume !(1 == ~T4_E~0); 49366#L1454-1 assume !(1 == ~T5_E~0); 49367#L1459-1 assume !(1 == ~T6_E~0); 49938#L1464-1 assume !(1 == ~T7_E~0); 49939#L1469-1 assume !(1 == ~T8_E~0); 50024#L1474-1 assume !(1 == ~T9_E~0); 49702#L1479-1 assume !(1 == ~T10_E~0); 49703#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49946#L1489-1 assume !(1 == ~T12_E~0); 49580#L1494-1 assume !(1 == ~T13_E~0); 49581#L1499-1 assume !(1 == ~E_M~0); 49762#L1504-1 assume !(1 == ~E_1~0); 49763#L1509-1 assume !(1 == ~E_2~0); 50376#L1514-1 assume !(1 == ~E_3~0); 50061#L1519-1 assume !(1 == ~E_4~0); 50062#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50566#L1529-1 assume !(1 == ~E_6~0); 50567#L1534-1 assume !(1 == ~E_7~0); 48713#L1539-1 assume !(1 == ~E_8~0); 48714#L1544-1 assume !(1 == ~E_9~0); 49144#L1549-1 assume !(1 == ~E_10~0); 50544#L1554-1 assume !(1 == ~E_11~0); 50542#L1559-1 assume !(1 == ~E_12~0); 50404#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 50405#L1569-1 assume { :end_inline_reset_delta_events } true; 50560#L1935-2 [2022-11-16 11:07:12,022 INFO L750 eck$LassoCheckResult]: Loop: 50560#L1935-2 assume !false; 48722#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48723#L1261 assume !false; 49950#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49951#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48853#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49023#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49024#L1074 assume !(0 != eval_~tmp~0#1); 49381#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49979#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50380#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50436#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50155#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50156#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50592#L1301-3 assume !(0 == ~T4_E~0); 50550#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49658#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48957#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 48958#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49063#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49799#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50064#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50065#L1341-3 assume !(0 == ~T12_E~0); 49359#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49350#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49294#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49295#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49875#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48648#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48649#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50391#L1381-3 assume !(0 == ~E_6~0); 50240#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50241#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50422#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50423#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49028#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48859#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 48860#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49487#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48737#L635-45 assume 1 == ~m_pc~0; 48738#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49532#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50012#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50266#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49046#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49047#L654-45 assume 1 == ~t1_pc~0; 49867#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50215#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48700#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48701#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48726#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49553#L673-45 assume !(1 == ~t2_pc~0); 49554#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 49878#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49879#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50504#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 50324#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49171#L692-45 assume !(1 == ~t3_pc~0); 48897#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 48898#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49942#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49225#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49226#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49538#L711-45 assume !(1 == ~t4_pc~0); 49664#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 49663#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49515#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49516#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49919#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49070#L730-45 assume 1 == ~t5_pc~0; 48908#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48909#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49318#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49319#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50070#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48881#L749-45 assume !(1 == ~t6_pc~0); 48882#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 50282#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50045#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50046#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50197#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49197#L768-45 assume 1 == ~t7_pc~0; 49198#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49337#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50141#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50142#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50181#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50182#L787-45 assume 1 == ~t8_pc~0; 50350#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49343#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49344#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49760#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49761#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50069#L806-45 assume 1 == ~t9_pc~0; 50545#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48757#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49582#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49410#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49322#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49323#L825-45 assume !(1 == ~t10_pc~0); 49846#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 49847#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49952#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49953#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50105#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48965#L844-45 assume !(1 == ~t11_pc~0); 48966#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49488#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49489#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49505#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 49916#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49005#L863-45 assume 1 == ~t12_pc~0; 49006#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48606#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48607#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49122#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49123#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49922#L882-45 assume 1 == ~t13_pc~0; 50276#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 48625#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 48626#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 49234#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50413#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50029#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50030#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50214#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48919#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48920#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49082#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50019#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50020#L1464-3 assume !(1 == ~T7_E~0); 50466#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50393#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50394#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50468#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49660#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49661#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50321#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49956#L1504-3 assume !(1 == ~E_1~0); 49957#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50402#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50442#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49583#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49584#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50489#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49884#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49338#L1544-3 assume !(1 == ~E_9~0); 49339#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49854#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48970#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48971#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50120#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50121#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48855#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49420#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50091#L1954 assume !(0 == start_simulation_~tmp~3#1); 50093#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50343#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49138#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50179#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 50309#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50310#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50400#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 50462#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 50560#L1935-2 [2022-11-16 11:07:12,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:12,023 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2022-11-16 11:07:12,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:12,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629733922] [2022-11-16 11:07:12,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:12,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:12,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:12,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:12,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:12,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1629733922] [2022-11-16 11:07:12,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1629733922] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:12,084 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:12,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:12,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302616437] [2022-11-16 11:07:12,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:12,085 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:12,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:12,086 INFO L85 PathProgramCache]: Analyzing trace with hash 2007173988, now seen corresponding path program 1 times [2022-11-16 11:07:12,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:12,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597398451] [2022-11-16 11:07:12,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:12,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:12,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:12,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:12,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:12,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597398451] [2022-11-16 11:07:12,215 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1597398451] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:12,215 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:12,215 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:12,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708254238] [2022-11-16 11:07:12,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:12,216 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:12,217 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:12,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:12,217 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:12,217 INFO L87 Difference]: Start difference. First operand 2021 states and 2981 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:12,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:12,267 INFO L93 Difference]: Finished difference Result 2021 states and 2980 transitions. [2022-11-16 11:07:12,268 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2980 transitions. [2022-11-16 11:07:12,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:12,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2980 transitions. [2022-11-16 11:07:12,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2022-11-16 11:07:12,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2022-11-16 11:07:12,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2980 transitions. [2022-11-16 11:07:12,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:12,309 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2022-11-16 11:07:12,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2980 transitions. [2022-11-16 11:07:12,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 2021. [2022-11-16 11:07:12,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2021 states, 2021 states have (on average 1.4745175655616032) internal successors, (2980), 2020 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:12,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2021 states to 2021 states and 2980 transitions. [2022-11-16 11:07:12,351 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2022-11-16 11:07:12,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:12,353 INFO L428 stractBuchiCegarLoop]: Abstraction has 2021 states and 2980 transitions. [2022-11-16 11:07:12,354 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 11:07:12,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2021 states and 2980 transitions. [2022-11-16 11:07:12,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1846 [2022-11-16 11:07:12,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:12,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:12,367 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:12,367 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:12,368 INFO L748 eck$LassoCheckResult]: Stem: 53529#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 53530#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 53261#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53262#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54652#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 54653#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53448#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53449#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53483#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54320#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54321#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54433#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54434#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53267#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53268#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54470#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53792#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53793#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54374#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54640#L1286 assume 0 == ~M_E~0;~M_E~0 := 1; 54530#L1286-2 assume !(0 == ~T1_E~0); 53176#L1291-1 assume !(0 == ~T2_E~0); 53177#L1296-1 assume !(0 == ~T3_E~0); 53882#L1301-1 assume !(0 == ~T4_E~0); 53883#L1306-1 assume !(0 == ~T5_E~0); 54383#L1311-1 assume !(0 == ~T6_E~0); 53136#L1316-1 assume !(0 == ~T7_E~0); 53137#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53902#L1326-1 assume !(0 == ~T9_E~0); 52951#L1331-1 assume !(0 == ~T10_E~0); 52657#L1336-1 assume !(0 == ~T11_E~0); 52658#L1341-1 assume !(0 == ~T12_E~0); 52709#L1346-1 assume !(0 == ~T13_E~0); 52710#L1351-1 assume !(0 == ~E_M~0); 53083#L1356-1 assume !(0 == ~E_1~0); 53084#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 54603#L1366-1 assume !(0 == ~E_3~0); 53129#L1371-1 assume !(0 == ~E_4~0); 53130#L1376-1 assume !(0 == ~E_5~0); 53943#L1381-1 assume !(0 == ~E_6~0); 53944#L1386-1 assume !(0 == ~E_7~0); 54631#L1391-1 assume !(0 == ~E_8~0); 54644#L1396-1 assume !(0 == ~E_9~0); 53826#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 53827#L1406-1 assume !(0 == ~E_11~0); 54129#L1411-1 assume !(0 == ~E_12~0); 54130#L1416-1 assume !(0 == ~E_13~0); 53750#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53588#L635 assume !(1 == ~m_pc~0); 52727#L635-2 is_master_triggered_~__retres1~0#1 := 0; 52728#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53078#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53714#L1598 assume !(0 != activate_threads_~tmp~1#1); 52906#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52907#L654 assume 1 == ~t1_pc~0; 53612#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53613#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54628#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53694#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 53695#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52954#L673 assume 1 == ~t2_pc~0; 52955#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54099#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54100#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54658#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 54665#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53773#L692 assume !(1 == ~t3_pc~0); 53590#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53591#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53450#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53418#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53419#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52979#L711 assume 1 == ~t4_pc~0; 52980#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53463#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53920#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52682#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 52683#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54651#L730 assume !(1 == ~t5_pc~0); 54033#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52861#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52862#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52989#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 52990#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53332#L749 assume 1 == ~t6_pc~0; 53106#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52866#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53298#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53299#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 53521#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52662#L768 assume !(1 == ~t7_pc~0); 52663#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53967#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52899#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52900#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 53986#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53138#L787 assume 1 == ~t8_pc~0; 53139#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54334#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54498#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54499#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 52707#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52708#L806 assume 1 == ~t9_pc~0; 54345#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52742#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52743#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52991#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 52992#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54328#L825 assume !(1 == ~t10_pc~0); 54329#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53934#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53935#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53079#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53080#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53663#L844 assume 1 == ~t11_pc~0; 53353#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53354#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53720#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53721#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 54316#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54317#L863 assume !(1 == ~t12_pc~0); 52842#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52841#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53069#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54408#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 54409#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53787#L882 assume 1 == ~t13_pc~0; 53788#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54072#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54573#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54376#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 54059#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54060#L1434 assume !(1 == ~M_E~0); 54581#L1434-2 assume !(1 == ~T1_E~0); 54657#L1439-1 assume !(1 == ~T2_E~0); 52972#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52973#L1449-1 assume !(1 == ~T4_E~0); 53415#L1454-1 assume !(1 == ~T5_E~0); 53416#L1459-1 assume !(1 == ~T6_E~0); 53987#L1464-1 assume !(1 == ~T7_E~0); 53988#L1469-1 assume !(1 == ~T8_E~0); 54073#L1474-1 assume !(1 == ~T9_E~0); 53751#L1479-1 assume !(1 == ~T10_E~0); 53752#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53995#L1489-1 assume !(1 == ~T12_E~0); 53629#L1494-1 assume !(1 == ~T13_E~0); 53630#L1499-1 assume !(1 == ~E_M~0); 53811#L1504-1 assume !(1 == ~E_1~0); 53812#L1509-1 assume !(1 == ~E_2~0); 54425#L1514-1 assume !(1 == ~E_3~0); 54110#L1519-1 assume !(1 == ~E_4~0); 54111#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54615#L1529-1 assume !(1 == ~E_6~0); 54616#L1534-1 assume !(1 == ~E_7~0); 52762#L1539-1 assume !(1 == ~E_8~0); 52763#L1544-1 assume !(1 == ~E_9~0); 53193#L1549-1 assume !(1 == ~E_10~0); 54593#L1554-1 assume !(1 == ~E_11~0); 54591#L1559-1 assume !(1 == ~E_12~0); 54453#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 54454#L1569-1 assume { :end_inline_reset_delta_events } true; 54609#L1935-2 [2022-11-16 11:07:12,368 INFO L750 eck$LassoCheckResult]: Loop: 54609#L1935-2 assume !false; 52771#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52772#L1261 assume !false; 53999#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54000#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52902#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53072#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53073#L1074 assume !(0 != eval_~tmp~0#1); 53430#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54028#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54429#L1286-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54485#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54204#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54205#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54641#L1301-3 assume !(0 == ~T4_E~0); 54599#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53707#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53006#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53007#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53112#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53848#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54113#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54114#L1341-3 assume !(0 == ~T12_E~0); 53408#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53399#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53343#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53344#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53924#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52697#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52698#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54440#L1381-3 assume !(0 == ~E_6~0); 54289#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54290#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54471#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54472#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53077#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52908#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52909#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53536#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52786#L635-45 assume 1 == ~m_pc~0; 52787#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53581#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54061#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54315#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53095#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53096#L654-45 assume 1 == ~t1_pc~0; 53916#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54264#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52749#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52750#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52775#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53602#L673-45 assume !(1 == ~t2_pc~0); 53603#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 53927#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53928#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54553#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 54373#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53220#L692-45 assume !(1 == ~t3_pc~0); 52946#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 52947#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53991#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53274#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53275#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53587#L711-45 assume !(1 == ~t4_pc~0); 53713#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 53712#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53564#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53565#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53968#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53119#L730-45 assume 1 == ~t5_pc~0; 52957#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 52958#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53367#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53368#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54119#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52930#L749-45 assume !(1 == ~t6_pc~0); 52931#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 54331#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54094#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54095#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54246#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53246#L768-45 assume !(1 == ~t7_pc~0); 53248#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53386#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54190#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54191#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54230#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54231#L787-45 assume !(1 == ~t8_pc~0); 54400#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 53392#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53393#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53809#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53810#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54118#L806-45 assume 1 == ~t9_pc~0; 54594#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52806#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53631#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53459#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53371#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53372#L825-45 assume !(1 == ~t10_pc~0); 53895#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 53896#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54001#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54002#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54154#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53014#L844-45 assume !(1 == ~t11_pc~0); 53015#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53537#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53538#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53554#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 53965#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53054#L863-45 assume !(1 == ~t12_pc~0); 53056#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 52655#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52656#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53171#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53172#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53971#L882-45 assume 1 == ~t13_pc~0; 54325#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 52674#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 52675#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 53283#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54462#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54078#L1434-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54079#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54263#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52968#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52969#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53131#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54068#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54069#L1464-3 assume !(1 == ~T7_E~0); 54515#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54442#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54443#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54517#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53709#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53710#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54370#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54005#L1504-3 assume !(1 == ~E_1~0); 54006#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54451#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54491#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53632#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53633#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54538#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53933#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53387#L1544-3 assume !(1 == ~E_9~0); 53388#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53903#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53019#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53020#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54169#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54170#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52904#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53469#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54140#L1954 assume !(0 == start_simulation_~tmp~3#1); 54142#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54392#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53187#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54228#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54358#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54359#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54449#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54511#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 54609#L1935-2 [2022-11-16 11:07:12,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:12,369 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2022-11-16 11:07:12,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:12,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100152166] [2022-11-16 11:07:12,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:12,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:12,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:12,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:12,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:12,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100152166] [2022-11-16 11:07:12,455 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100152166] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:12,455 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:12,456 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:07:12,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546332279] [2022-11-16 11:07:12,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:12,457 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:12,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:12,457 INFO L85 PathProgramCache]: Analyzing trace with hash -1509066009, now seen corresponding path program 1 times [2022-11-16 11:07:12,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:12,458 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709985951] [2022-11-16 11:07:12,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:12,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:12,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:12,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:12,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:12,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709985951] [2022-11-16 11:07:12,538 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709985951] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:12,538 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:12,538 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:12,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734489685] [2022-11-16 11:07:12,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:12,539 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:12,540 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:12,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:12,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:12,541 INFO L87 Difference]: Start difference. First operand 2021 states and 2980 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:12,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:12,748 INFO L93 Difference]: Finished difference Result 3767 states and 5538 transitions. [2022-11-16 11:07:12,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3767 states and 5538 transitions. [2022-11-16 11:07:12,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2022-11-16 11:07:12,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3767 states to 3767 states and 5538 transitions. [2022-11-16 11:07:12,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3767 [2022-11-16 11:07:12,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3767 [2022-11-16 11:07:12,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3767 states and 5538 transitions. [2022-11-16 11:07:12,808 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:12,808 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2022-11-16 11:07:12,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3767 states and 5538 transitions. [2022-11-16 11:07:12,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3767 to 3767. [2022-11-16 11:07:12,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3767 states, 3767 states have (on average 1.4701353862490045) internal successors, (5538), 3766 states have internal predecessors, (5538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:12,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3767 states to 3767 states and 5538 transitions. [2022-11-16 11:07:12,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2022-11-16 11:07:12,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:12,906 INFO L428 stractBuchiCegarLoop]: Abstraction has 3767 states and 5538 transitions. [2022-11-16 11:07:12,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 11:07:12,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3767 states and 5538 transitions. [2022-11-16 11:07:12,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3592 [2022-11-16 11:07:12,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:12,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:12,931 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:12,931 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:12,932 INFO L748 eck$LassoCheckResult]: Stem: 59327#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 59328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 59056#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59057#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60502#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 60503#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59244#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59245#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59279#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60128#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60129#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60246#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60247#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59062#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59063#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60286#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59590#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59591#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 60185#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60487#L1286 assume !(0 == ~M_E~0); 60350#L1286-2 assume !(0 == ~T1_E~0); 58971#L1291-1 assume !(0 == ~T2_E~0); 58972#L1296-1 assume !(0 == ~T3_E~0); 59682#L1301-1 assume !(0 == ~T4_E~0); 59683#L1306-1 assume !(0 == ~T5_E~0); 60194#L1311-1 assume !(0 == ~T6_E~0); 58931#L1316-1 assume !(0 == ~T7_E~0); 58932#L1321-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59702#L1326-1 assume !(0 == ~T9_E~0); 58746#L1331-1 assume !(0 == ~T10_E~0); 58452#L1336-1 assume !(0 == ~T11_E~0); 58453#L1341-1 assume !(0 == ~T12_E~0); 58504#L1346-1 assume !(0 == ~T13_E~0); 58505#L1351-1 assume !(0 == ~E_M~0); 58878#L1356-1 assume !(0 == ~E_1~0); 58879#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 60437#L1366-1 assume !(0 == ~E_3~0); 58924#L1371-1 assume !(0 == ~E_4~0); 58925#L1376-1 assume !(0 == ~E_5~0); 59745#L1381-1 assume !(0 == ~E_6~0); 59746#L1386-1 assume !(0 == ~E_7~0); 60475#L1391-1 assume !(0 == ~E_8~0); 60493#L1396-1 assume !(0 == ~E_9~0); 59624#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 59625#L1406-1 assume !(0 == ~E_11~0); 59933#L1411-1 assume !(0 == ~E_12~0); 59934#L1416-1 assume !(0 == ~E_13~0); 59548#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59386#L635 assume !(1 == ~m_pc~0); 58522#L635-2 is_master_triggered_~__retres1~0#1 := 0; 58523#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58875#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59512#L1598 assume !(0 != activate_threads_~tmp~1#1); 58701#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58702#L654 assume 1 == ~t1_pc~0; 59410#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59411#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60471#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59492#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 59493#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58752#L673 assume 1 == ~t2_pc~0; 58753#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59902#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59903#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60508#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 60516#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59571#L692 assume !(1 == ~t3_pc~0); 59388#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59389#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59248#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59213#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59214#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58774#L711 assume 1 == ~t4_pc~0; 58775#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59259#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59720#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58477#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 58478#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60501#L730 assume !(1 == ~t5_pc~0); 59836#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58656#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58657#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58784#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 58785#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59127#L749 assume 1 == ~t6_pc~0; 58901#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58664#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59093#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59094#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 59319#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58459#L768 assume !(1 == ~t7_pc~0); 58460#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59769#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58694#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58695#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 59788#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58933#L787 assume 1 == ~t8_pc~0; 58934#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60145#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60315#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60316#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 58502#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58503#L806 assume 1 == ~t9_pc~0; 60156#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58537#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58538#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58786#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 58787#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60139#L825 assume !(1 == ~t10_pc~0); 60140#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 59735#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59736#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58876#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58877#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59461#L844 assume 1 == ~t11_pc~0; 59150#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59151#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59518#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59519#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 60124#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60125#L863 assume !(1 == ~t12_pc~0); 58639#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58638#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58864#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60221#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 60222#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59585#L882 assume 1 == ~t13_pc~0; 59586#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59875#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60397#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60187#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 59862#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59863#L1434 assume !(1 == ~M_E~0); 60410#L1434-2 assume !(1 == ~T1_E~0); 60507#L1439-1 assume !(1 == ~T2_E~0); 58767#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58768#L1449-1 assume !(1 == ~T4_E~0); 59211#L1454-1 assume !(1 == ~T5_E~0); 59212#L1459-1 assume !(1 == ~T6_E~0); 59789#L1464-1 assume !(1 == ~T7_E~0); 59790#L1469-1 assume !(1 == ~T8_E~0); 59876#L1474-1 assume !(1 == ~T9_E~0); 59549#L1479-1 assume !(1 == ~T10_E~0); 59550#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59797#L1489-1 assume !(1 == ~T12_E~0); 59427#L1494-1 assume !(1 == ~T13_E~0); 59428#L1499-1 assume !(1 == ~E_M~0); 59609#L1504-1 assume !(1 == ~E_1~0); 59610#L1509-1 assume !(1 == ~E_2~0); 60238#L1514-1 assume !(1 == ~E_3~0); 59913#L1519-1 assume !(1 == ~E_4~0); 59914#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60456#L1529-1 assume !(1 == ~E_6~0); 60457#L1534-1 assume !(1 == ~E_7~0); 58557#L1539-1 assume !(1 == ~E_8~0); 58558#L1544-1 assume !(1 == ~E_9~0); 58988#L1549-1 assume !(1 == ~E_10~0); 60425#L1554-1 assume !(1 == ~E_11~0); 60423#L1559-1 assume !(1 == ~E_12~0); 60269#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60270#L1569-1 assume { :end_inline_reset_delta_events } true; 60449#L1935-2 [2022-11-16 11:07:12,932 INFO L750 eck$LassoCheckResult]: Loop: 60449#L1935-2 assume !false; 60556#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60469#L1261 assume !false; 59804#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59805#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58697#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58868#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 58869#L1074 assume !(0 != eval_~tmp~0#1); 59225#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59831#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60242#L1286-3 assume !(0 == ~M_E~0); 60303#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62201#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62200#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62199#L1301-3 assume !(0 == ~T4_E~0); 62198#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62197#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62196#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62195#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62194#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62193#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62192#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62191#L1341-3 assume !(0 == ~T12_E~0); 62190#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62189#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62188#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62187#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62186#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62185#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62184#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62183#L1381-3 assume !(0 == ~E_6~0); 62182#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62181#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62180#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62179#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62178#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62177#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62176#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 62175#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62174#L635-45 assume 1 == ~m_pc~0; 62172#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62171#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62170#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62169#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62168#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62167#L654-45 assume !(1 == ~t1_pc~0); 62165#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 62164#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62163#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62162#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62161#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62160#L673-45 assume 1 == ~t2_pc~0; 62158#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62157#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62156#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62155#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 62154#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62153#L692-45 assume 1 == ~t3_pc~0; 62151#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62150#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62149#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62148#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62147#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62146#L711-45 assume 1 == ~t4_pc~0; 62144#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62143#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62142#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62141#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62140#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62139#L730-45 assume 1 == ~t5_pc~0; 62137#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62136#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62135#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62134#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62133#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62132#L749-45 assume !(1 == ~t6_pc~0); 62130#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 62129#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62128#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62127#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62126#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62125#L768-45 assume 1 == ~t7_pc~0; 62123#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62122#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62121#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62120#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62119#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62118#L787-45 assume !(1 == ~t8_pc~0); 62116#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 62115#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62114#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62113#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62112#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62111#L806-45 assume 1 == ~t9_pc~0; 62109#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62108#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62107#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62106#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61679#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61678#L825-45 assume !(1 == ~t10_pc~0); 61676#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 61675#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61674#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61673#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61672#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61671#L844-45 assume 1 == ~t11_pc~0; 61669#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61668#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61667#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61666#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 61665#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61664#L863-45 assume 1 == ~t12_pc~0; 61662#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61661#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61660#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 61659#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61658#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61657#L882-45 assume !(1 == ~t13_pc~0); 61655#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 61654#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 61653#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 61652#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 61651#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59881#L1434-3 assume !(1 == ~M_E~0); 59882#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60069#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58763#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58764#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58926#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 59871#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 59872#L1464-3 assume !(1 == ~T7_E~0); 60335#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60255#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60256#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60337#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59507#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59508#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 60181#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59808#L1504-3 assume !(1 == ~E_1~0); 59809#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60265#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60307#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59430#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59431#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60358#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59731#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59182#L1544-3 assume !(1 == ~E_9~0); 59183#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 59703#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58814#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58815#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 60201#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61482#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61472#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61471#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 61470#L1954 assume !(0 == start_simulation_~tmp~3#1); 61467#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60853#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60843#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60626#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 60587#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60579#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60573#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 60565#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 60449#L1935-2 [2022-11-16 11:07:12,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:12,934 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2022-11-16 11:07:12,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:12,934 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308361062] [2022-11-16 11:07:12,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:12,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:12,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:13,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:13,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:13,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308361062] [2022-11-16 11:07:13,077 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308361062] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:13,077 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:13,077 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:13,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031395730] [2022-11-16 11:07:13,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:13,078 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:13,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:13,079 INFO L85 PathProgramCache]: Analyzing trace with hash 627302755, now seen corresponding path program 1 times [2022-11-16 11:07:13,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:13,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882026529] [2022-11-16 11:07:13,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:13,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:13,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:13,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:13,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:13,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882026529] [2022-11-16 11:07:13,159 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882026529] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:13,159 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:13,160 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:13,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848102823] [2022-11-16 11:07:13,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:13,161 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:13,161 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:13,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:07:13,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:07:13,164 INFO L87 Difference]: Start difference. First operand 3767 states and 5538 transitions. cyclomatic complexity: 1772 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:13,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:13,435 INFO L93 Difference]: Finished difference Result 7385 states and 10846 transitions. [2022-11-16 11:07:13,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7385 states and 10846 transitions. [2022-11-16 11:07:13,476 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2022-11-16 11:07:13,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7385 states to 7385 states and 10846 transitions. [2022-11-16 11:07:13,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7385 [2022-11-16 11:07:13,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7385 [2022-11-16 11:07:13,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7385 states and 10846 transitions. [2022-11-16 11:07:13,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:13,527 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7385 states and 10846 transitions. [2022-11-16 11:07:13,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7385 states and 10846 transitions. [2022-11-16 11:07:13,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7385 to 7385. [2022-11-16 11:07:13,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7385 states, 7385 states have (on average 1.4686526743398782) internal successors, (10846), 7384 states have internal predecessors, (10846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:13,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7385 states to 7385 states and 10846 transitions. [2022-11-16 11:07:13,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7385 states and 10846 transitions. [2022-11-16 11:07:13,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:07:13,712 INFO L428 stractBuchiCegarLoop]: Abstraction has 7385 states and 10846 transitions. [2022-11-16 11:07:13,712 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 11:07:13,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7385 states and 10846 transitions. [2022-11-16 11:07:13,744 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2022-11-16 11:07:13,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:13,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:13,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:13,751 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:13,751 INFO L748 eck$LassoCheckResult]: Stem: 70490#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 70491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 70218#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70219#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71728#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 71729#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70407#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70408#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70443#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71312#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71313#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 71446#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 71447#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70224#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70225#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 71487#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 70755#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 70756#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 71375#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71711#L1286 assume !(0 == ~M_E~0); 71558#L1286-2 assume !(0 == ~T1_E~0); 70133#L1291-1 assume !(0 == ~T2_E~0); 70134#L1296-1 assume !(0 == ~T3_E~0); 70848#L1301-1 assume !(0 == ~T4_E~0); 70849#L1306-1 assume !(0 == ~T5_E~0); 71384#L1311-1 assume !(0 == ~T6_E~0); 70093#L1316-1 assume !(0 == ~T7_E~0); 70094#L1321-1 assume !(0 == ~T8_E~0); 70868#L1326-1 assume !(0 == ~T9_E~0); 69908#L1331-1 assume !(0 == ~T10_E~0); 69614#L1336-1 assume !(0 == ~T11_E~0); 69615#L1341-1 assume !(0 == ~T12_E~0); 69666#L1346-1 assume !(0 == ~T13_E~0); 69667#L1351-1 assume !(0 == ~E_M~0); 70040#L1356-1 assume !(0 == ~E_1~0); 70041#L1361-1 assume 0 == ~E_2~0;~E_2~0 := 1; 71660#L1366-1 assume !(0 == ~E_3~0); 70086#L1371-1 assume !(0 == ~E_4~0); 70087#L1376-1 assume !(0 == ~E_5~0); 70911#L1381-1 assume !(0 == ~E_6~0); 70912#L1386-1 assume !(0 == ~E_7~0); 71700#L1391-1 assume !(0 == ~E_8~0); 71717#L1396-1 assume !(0 == ~E_9~0); 70790#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 70791#L1406-1 assume !(0 == ~E_11~0); 71107#L1411-1 assume !(0 == ~E_12~0); 71108#L1416-1 assume !(0 == ~E_13~0); 70713#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70551#L635 assume !(1 == ~m_pc~0); 69686#L635-2 is_master_triggered_~__retres1~0#1 := 0; 69687#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70037#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70677#L1598 assume !(0 != activate_threads_~tmp~1#1); 69863#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69864#L654 assume 1 == ~t1_pc~0; 70575#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 70576#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71696#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70657#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 70658#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69914#L673 assume 1 == ~t2_pc~0; 69915#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 71072#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71073#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 71737#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 71746#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70736#L692 assume !(1 == ~t3_pc~0); 70553#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70554#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70411#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70376#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70377#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69936#L711 assume 1 == ~t4_pc~0; 69937#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70422#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70886#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69639#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 69640#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71727#L730 assume !(1 == ~t5_pc~0); 71003#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69818#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69819#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69946#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 69947#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70290#L749 assume 1 == ~t6_pc~0; 70063#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69828#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70256#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70257#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 70482#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69621#L768 assume !(1 == ~t7_pc~0); 69622#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 70934#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69856#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69857#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 70953#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70095#L787 assume 1 == ~t8_pc~0; 70096#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 71330#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 71518#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 71519#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 69664#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69665#L806 assume 1 == ~t9_pc~0; 71342#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69699#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69700#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69948#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 69949#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 71323#L825 assume !(1 == ~t10_pc~0); 71324#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 70900#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70901#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70038#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 70039#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 70626#L844 assume 1 == ~t11_pc~0; 70313#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 70314#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70683#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 70684#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 71306#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 71307#L863 assume !(1 == ~t12_pc~0); 69803#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69802#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70028#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 71410#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 71411#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70750#L882 assume 1 == ~t13_pc~0; 70751#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 71043#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 71610#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 71377#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 71030#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71031#L1434 assume !(1 == ~M_E~0); 71621#L1434-2 assume !(1 == ~T1_E~0); 71734#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69929#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69930#L1449-1 assume !(1 == ~T4_E~0); 70374#L1454-1 assume !(1 == ~T5_E~0); 70375#L1459-1 assume !(1 == ~T6_E~0); 70954#L1464-1 assume !(1 == ~T7_E~0); 70955#L1469-1 assume !(1 == ~T8_E~0); 71046#L1474-1 assume !(1 == ~T9_E~0); 70714#L1479-1 assume !(1 == ~T10_E~0); 70715#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70962#L1489-1 assume !(1 == ~T12_E~0); 70592#L1494-1 assume !(1 == ~T13_E~0); 70593#L1499-1 assume !(1 == ~E_M~0); 70775#L1504-1 assume !(1 == ~E_1~0); 70776#L1509-1 assume !(1 == ~E_2~0); 71431#L1514-1 assume !(1 == ~E_3~0); 71083#L1519-1 assume !(1 == ~E_4~0); 71084#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 71677#L1529-1 assume !(1 == ~E_6~0); 71678#L1534-1 assume !(1 == ~E_7~0); 69721#L1539-1 assume !(1 == ~E_8~0); 69722#L1544-1 assume !(1 == ~E_9~0); 70150#L1549-1 assume !(1 == ~E_10~0); 71639#L1554-1 assume !(1 == ~E_11~0); 71636#L1559-1 assume !(1 == ~E_12~0); 71637#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 71669#L1569-1 assume { :end_inline_reset_delta_events } true; 71670#L1935-2 [2022-11-16 11:07:13,752 INFO L750 eck$LassoCheckResult]: Loop: 71670#L1935-2 assume !false; 71797#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71693#L1261 assume !false; 70968#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 70969#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 71310#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 71311#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 70387#L1074 assume !(0 != eval_~tmp~0#1); 70389#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 71439#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 71440#L1286-3 assume !(0 == ~M_E~0); 73270#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 73268#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 71738#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71712#L1301-3 assume !(0 == ~T4_E~0); 71653#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70670#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69963#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69964#L1321-3 assume !(0 == ~T8_E~0); 70069#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70812#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 71086#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 71087#L1341-3 assume !(0 == ~T12_E~0); 70366#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 70357#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 70301#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 70302#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70890#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69654#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69655#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71453#L1381-3 assume !(0 == ~E_6~0); 71276#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71277#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 71488#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 71489#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 70034#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69865#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 69866#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 70497#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69743#L635-45 assume !(1 == ~m_pc~0); 69745#L635-47 is_master_triggered_~__retres1~0#1 := 0; 70542#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71032#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71305#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70052#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70053#L654-45 assume !(1 == ~t1_pc~0); 70883#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 71249#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69706#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69707#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69732#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70565#L673-45 assume 1 == ~t2_pc~0; 70567#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 70893#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70894#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 71586#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 71374#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70177#L692-45 assume 1 == ~t3_pc~0; 70178#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69907#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70958#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70231#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70232#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70550#L711-45 assume 1 == ~t4_pc~0; 70674#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70675#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70526#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70527#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 71679#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75232#L730-45 assume 1 == ~t5_pc~0; 75229#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75228#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75227#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75226#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 75225#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75224#L749-45 assume 1 == ~t6_pc~0; 75223#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 75220#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75219#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75218#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 75217#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75215#L768-45 assume 1 == ~t7_pc~0; 75213#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75212#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75211#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75210#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75209#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75208#L787-45 assume 1 == ~t8_pc~0; 75205#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 75203#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75202#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75201#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75198#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75196#L806-45 assume 1 == ~t9_pc~0; 75193#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75191#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75189#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75188#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 75187#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75186#L825-45 assume 1 == ~t10_pc~0; 75184#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 75181#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75179#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75177#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 75174#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75172#L844-45 assume 1 == ~t11_pc~0; 75169#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75167#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75165#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75163#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 75160#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75158#L863-45 assume 1 == ~t12_pc~0; 75155#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 75153#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75151#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75149#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 75146#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 75144#L882-45 assume !(1 == ~t13_pc~0); 75141#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 75139#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 75137#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 75135#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 75132#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75130#L1434-3 assume !(1 == ~M_E~0); 75126#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 75124#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75120#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75118#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75115#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75113#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 75111#L1464-3 assume !(1 == ~T7_E~0); 75109#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75105#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 75103#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75100#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 75098#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 75096#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 75094#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 75092#L1504-3 assume !(1 == ~E_1~0); 75089#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75087#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75085#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75084#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75083#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 75082#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 75081#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 75080#L1544-3 assume !(1 == ~E_9~0); 75079#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 75078#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 75077#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 75076#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 75075#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 73800#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73791#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 73790#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 73787#L1954 assume !(0 == start_simulation_~tmp~3#1); 73785#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 71905#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 71895#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 71856#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 71846#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 71821#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 71820#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 71816#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 71670#L1935-2 [2022-11-16 11:07:13,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:13,753 INFO L85 PathProgramCache]: Analyzing trace with hash -113531325, now seen corresponding path program 1 times [2022-11-16 11:07:13,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:13,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933908568] [2022-11-16 11:07:13,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:13,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:13,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:13,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:13,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:13,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [933908568] [2022-11-16 11:07:13,844 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [933908568] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:13,844 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:13,845 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:07:13,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080334104] [2022-11-16 11:07:13,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:13,845 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:13,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:13,846 INFO L85 PathProgramCache]: Analyzing trace with hash 376017951, now seen corresponding path program 1 times [2022-11-16 11:07:13,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:13,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985485541] [2022-11-16 11:07:13,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:13,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:13,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:13,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:13,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:13,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [985485541] [2022-11-16 11:07:13,936 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [985485541] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:13,936 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:13,936 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:13,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078617176] [2022-11-16 11:07:13,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:13,937 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:13,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:13,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:13,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:13,938 INFO L87 Difference]: Start difference. First operand 7385 states and 10846 transitions. cyclomatic complexity: 3463 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:14,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:14,079 INFO L93 Difference]: Finished difference Result 7385 states and 10772 transitions. [2022-11-16 11:07:14,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7385 states and 10772 transitions. [2022-11-16 11:07:14,121 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2022-11-16 11:07:14,224 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7385 states to 7385 states and 10772 transitions. [2022-11-16 11:07:14,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7385 [2022-11-16 11:07:14,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7385 [2022-11-16 11:07:14,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7385 states and 10772 transitions. [2022-11-16 11:07:14,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:14,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7385 states and 10772 transitions. [2022-11-16 11:07:14,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7385 states and 10772 transitions. [2022-11-16 11:07:14,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7385 to 7385. [2022-11-16 11:07:14,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7385 states, 7385 states have (on average 1.4586323628977658) internal successors, (10772), 7384 states have internal predecessors, (10772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:14,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7385 states to 7385 states and 10772 transitions. [2022-11-16 11:07:14,402 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7385 states and 10772 transitions. [2022-11-16 11:07:14,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:14,403 INFO L428 stractBuchiCegarLoop]: Abstraction has 7385 states and 10772 transitions. [2022-11-16 11:07:14,403 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 11:07:14,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7385 states and 10772 transitions. [2022-11-16 11:07:14,434 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7184 [2022-11-16 11:07:14,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:14,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:14,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:14,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:14,439 INFO L748 eck$LassoCheckResult]: Stem: 85272#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 85273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 85001#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85002#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86597#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 86598#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85190#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85191#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85225#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86110#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86111#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86245#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86246#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85007#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 85008#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86292#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 85541#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 85542#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86171#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86569#L1286 assume !(0 == ~M_E~0); 86377#L1286-2 assume !(0 == ~T1_E~0); 84914#L1291-1 assume !(0 == ~T2_E~0); 84915#L1296-1 assume !(0 == ~T3_E~0); 85636#L1301-1 assume !(0 == ~T4_E~0); 85637#L1306-1 assume !(0 == ~T5_E~0); 86180#L1311-1 assume !(0 == ~T6_E~0); 84874#L1316-1 assume !(0 == ~T7_E~0); 84875#L1321-1 assume !(0 == ~T8_E~0); 85656#L1326-1 assume !(0 == ~T9_E~0); 84687#L1331-1 assume !(0 == ~T10_E~0); 84391#L1336-1 assume !(0 == ~T11_E~0); 84392#L1341-1 assume !(0 == ~T12_E~0); 84444#L1346-1 assume !(0 == ~T13_E~0); 84445#L1351-1 assume !(0 == ~E_M~0); 84820#L1356-1 assume !(0 == ~E_1~0); 84821#L1361-1 assume !(0 == ~E_2~0); 86501#L1366-1 assume !(0 == ~E_3~0); 84867#L1371-1 assume !(0 == ~E_4~0); 84868#L1376-1 assume !(0 == ~E_5~0); 85700#L1381-1 assume !(0 == ~E_6~0); 85701#L1386-1 assume !(0 == ~E_7~0); 86551#L1391-1 assume !(0 == ~E_8~0); 86580#L1396-1 assume !(0 == ~E_9~0); 85576#L1401-1 assume 0 == ~E_10~0;~E_10~0 := 1; 85577#L1406-1 assume !(0 == ~E_11~0); 85895#L1411-1 assume !(0 == ~E_12~0); 85896#L1416-1 assume !(0 == ~E_13~0); 85499#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85335#L635 assume !(1 == ~m_pc~0); 84462#L635-2 is_master_triggered_~__retres1~0#1 := 0; 84463#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84817#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85462#L1598 assume !(0 != activate_threads_~tmp~1#1); 84642#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84643#L654 assume 1 == ~t1_pc~0; 85358#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85359#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86546#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85440#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 85441#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84693#L673 assume !(1 == ~t2_pc~0); 84695#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85864#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85865#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86607#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 86616#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85522#L692 assume !(1 == ~t3_pc~0); 85337#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85338#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85194#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85160#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85161#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84715#L711 assume 1 == ~t4_pc~0; 84716#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85205#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85675#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84416#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 84417#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86594#L730 assume !(1 == ~t5_pc~0); 85794#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 84597#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84598#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84725#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 84726#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85072#L749 assume 1 == ~t6_pc~0; 84843#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84605#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85038#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85039#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 85264#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84398#L768 assume !(1 == ~t7_pc~0); 84399#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85724#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84635#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 84636#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 85743#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84876#L787 assume 1 == ~t8_pc~0; 84877#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86125#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86334#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86335#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 84442#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84443#L806 assume 1 == ~t9_pc~0; 86138#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84477#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84478#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84727#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 84728#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86119#L825 assume !(1 == ~t10_pc~0); 86120#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 85690#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85691#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84818#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84819#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85409#L844 assume 1 == ~t11_pc~0; 85095#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85096#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85469#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85470#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 86104#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86105#L863 assume !(1 == ~t12_pc~0); 84580#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 84579#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84805#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86213#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 86214#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85536#L882 assume 1 == ~t13_pc~0; 85537#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85834#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86441#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86173#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 85820#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85821#L1434 assume !(1 == ~M_E~0); 86457#L1434-2 assume !(1 == ~T1_E~0); 86605#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84708#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84709#L1449-1 assume !(1 == ~T4_E~0); 85158#L1454-1 assume !(1 == ~T5_E~0); 85159#L1459-1 assume !(1 == ~T6_E~0); 85744#L1464-1 assume !(1 == ~T7_E~0); 85745#L1469-1 assume !(1 == ~T8_E~0); 85837#L1474-1 assume !(1 == ~T9_E~0); 85500#L1479-1 assume !(1 == ~T10_E~0); 85501#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85755#L1489-1 assume !(1 == ~T12_E~0); 85375#L1494-1 assume !(1 == ~T13_E~0); 85376#L1499-1 assume !(1 == ~E_M~0); 85560#L1504-1 assume !(1 == ~E_1~0); 85561#L1509-1 assume !(1 == ~E_2~0); 86234#L1514-1 assume !(1 == ~E_3~0); 85875#L1519-1 assume !(1 == ~E_4~0); 85876#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86519#L1529-1 assume !(1 == ~E_6~0); 86520#L1534-1 assume !(1 == ~E_7~0); 84497#L1539-1 assume !(1 == ~E_8~0); 84498#L1544-1 assume !(1 == ~E_9~0); 84931#L1549-1 assume !(1 == ~E_10~0); 86478#L1554-1 assume !(1 == ~E_11~0); 86492#L1559-1 assume !(1 == ~E_12~0); 88405#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 86511#L1569-1 assume { :end_inline_reset_delta_events } true; 86512#L1935-2 [2022-11-16 11:07:14,440 INFO L750 eck$LassoCheckResult]: Loop: 86512#L1935-2 assume !false; 86676#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86541#L1261 assume !false; 85761#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85762#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84638#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 88364#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 88362#L1074 assume !(0 != eval_~tmp~0#1); 88361#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86240#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86241#L1286-3 assume !(0 == ~M_E~0); 88360#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88357#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88355#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88356#L1301-3 assume !(0 == ~T4_E~0); 86490#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86491#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 84742#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 84743#L1321-3 assume !(0 == ~T8_E~0); 85599#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 85600#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 85879#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85880#L1341-3 assume !(0 == ~T12_E~0); 85148#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85139#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85085#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85086#L1361-3 assume !(0 == ~E_2~0); 85679#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 90010#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 90008#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 90003#L1381-3 assume !(0 == ~E_6~0); 90002#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 90000#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 89998#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 89996#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 89818#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 89817#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 89816#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 89814#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89810#L635-45 assume !(1 == ~m_pc~0); 89809#L635-47 is_master_triggered_~__retres1~0#1 := 0; 89807#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89806#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89805#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 89804#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89803#L654-45 assume !(1 == ~t1_pc~0); 88263#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 88264#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88259#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88260#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88255#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88256#L673-45 assume !(1 == ~t2_pc~0); 89797#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 89796#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89795#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89794#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 89793#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89792#L692-45 assume !(1 == ~t3_pc~0); 89791#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 89789#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89788#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89787#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89786#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89785#L711-45 assume 1 == ~t4_pc~0; 89783#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 89782#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89781#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 89780#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89779#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89778#L730-45 assume 1 == ~t5_pc~0; 88229#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 88228#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85107#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85108#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 85885#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84666#L749-45 assume !(1 == ~t6_pc~0); 84667#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 86122#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85858#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85859#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86022#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84985#L768-45 assume !(1 == ~t7_pc~0); 84987#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 85126#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85962#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85963#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86003#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86004#L787-45 assume !(1 == ~t8_pc~0); 86621#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 89758#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86515#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85558#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85559#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89731#L806-45 assume !(1 == ~t9_pc~0); 84541#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 84542#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85377#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85201#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85111#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85112#L825-45 assume !(1 == ~t10_pc~0); 85649#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 85650#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85759#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85760#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85923#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84750#L844-45 assume 1 == ~t11_pc~0; 84752#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85280#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85281#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85297#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 85722#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 89699#L863-45 assume 1 == ~t12_pc~0; 86137#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 84389#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84390#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 84909#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 84910#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85727#L882-45 assume 1 == ~t13_pc~0; 86114#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85244#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85022#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 85023#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86331#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86332#L1434-3 assume !(1 == ~M_E~0); 89676#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89675#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87947#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89674#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89673#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89672#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 89671#L1464-3 assume !(1 == ~T7_E~0); 89670#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 87940#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 89669#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 89668#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 89667#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 89666#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 89665#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 89664#L1504-3 assume !(1 == ~E_1~0); 89663#L1509-3 assume !(1 == ~E_2~0); 89662#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 89661#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89660#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89659#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 89658#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87924#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 87923#L1544-3 assume !(1 == ~E_9~0); 87921#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 87922#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 87917#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 87918#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 87913#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 87914#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 87897#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 87896#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 86967#L1954 assume !(0 == start_simulation_~tmp~3#1); 86963#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86964#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 88411#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 88410#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 88409#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88408#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88407#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 86688#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 86512#L1935-2 [2022-11-16 11:07:14,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:14,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1573181374, now seen corresponding path program 1 times [2022-11-16 11:07:14,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:14,442 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81526967] [2022-11-16 11:07:14,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:14,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:14,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:14,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:14,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:14,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81526967] [2022-11-16 11:07:14,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [81526967] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:14,547 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:14,547 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:14,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79620325] [2022-11-16 11:07:14,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:14,548 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:14,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:14,549 INFO L85 PathProgramCache]: Analyzing trace with hash 749958885, now seen corresponding path program 1 times [2022-11-16 11:07:14,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:14,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [661701227] [2022-11-16 11:07:14,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:14,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:14,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:14,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:14,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:14,621 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [661701227] [2022-11-16 11:07:14,621 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [661701227] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:14,621 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:14,622 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:14,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280734879] [2022-11-16 11:07:14,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:14,622 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:14,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:14,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:07:14,623 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:07:14,624 INFO L87 Difference]: Start difference. First operand 7385 states and 10772 transitions. cyclomatic complexity: 3389 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:14,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:14,974 INFO L93 Difference]: Finished difference Result 14197 states and 20700 transitions. [2022-11-16 11:07:14,974 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14197 states and 20700 transitions. [2022-11-16 11:07:15,159 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13968 [2022-11-16 11:07:15,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14197 states to 14197 states and 20700 transitions. [2022-11-16 11:07:15,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14197 [2022-11-16 11:07:15,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14197 [2022-11-16 11:07:15,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14197 states and 20700 transitions. [2022-11-16 11:07:15,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:15,265 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14197 states and 20700 transitions. [2022-11-16 11:07:15,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14197 states and 20700 transitions. [2022-11-16 11:07:15,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14197 to 14193. [2022-11-16 11:07:15,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14193 states, 14193 states have (on average 1.4581836116395406) internal successors, (20696), 14192 states have internal predecessors, (20696), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:15,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14193 states to 14193 states and 20696 transitions. [2022-11-16 11:07:15,656 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14193 states and 20696 transitions. [2022-11-16 11:07:15,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:07:15,657 INFO L428 stractBuchiCegarLoop]: Abstraction has 14193 states and 20696 transitions. [2022-11-16 11:07:15,658 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 11:07:15,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14193 states and 20696 transitions. [2022-11-16 11:07:15,727 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13968 [2022-11-16 11:07:15,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:15,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:15,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:15,732 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:15,733 INFO L748 eck$LassoCheckResult]: Stem: 106862#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 106863#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 106589#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 106590#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108201#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 108202#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106781#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 106782#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 106816#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 107718#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 107719#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 107862#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 107863#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 106595#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 106596#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 107906#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 107145#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 107146#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 107782#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108182#L1286 assume !(0 == ~M_E~0); 107989#L1286-2 assume !(0 == ~T1_E~0); 106503#L1291-1 assume !(0 == ~T2_E~0); 106504#L1296-1 assume !(0 == ~T3_E~0); 107240#L1301-1 assume !(0 == ~T4_E~0); 107241#L1306-1 assume !(0 == ~T5_E~0); 107795#L1311-1 assume !(0 == ~T6_E~0); 106463#L1316-1 assume !(0 == ~T7_E~0); 106464#L1321-1 assume !(0 == ~T8_E~0); 107261#L1326-1 assume !(0 == ~T9_E~0); 106278#L1331-1 assume !(0 == ~T10_E~0); 105983#L1336-1 assume !(0 == ~T11_E~0); 105984#L1341-1 assume !(0 == ~T12_E~0); 106035#L1346-1 assume !(0 == ~T13_E~0); 106036#L1351-1 assume !(0 == ~E_M~0); 106410#L1356-1 assume !(0 == ~E_1~0); 106411#L1361-1 assume !(0 == ~E_2~0); 108115#L1366-1 assume !(0 == ~E_3~0); 106456#L1371-1 assume !(0 == ~E_4~0); 106457#L1376-1 assume !(0 == ~E_5~0); 107305#L1381-1 assume !(0 == ~E_6~0); 107306#L1386-1 assume !(0 == ~E_7~0); 108165#L1391-1 assume !(0 == ~E_8~0); 108190#L1396-1 assume !(0 == ~E_9~0); 107179#L1401-1 assume !(0 == ~E_10~0); 107180#L1406-1 assume !(0 == ~E_11~0); 107501#L1411-1 assume !(0 == ~E_12~0); 107502#L1416-1 assume !(0 == ~E_13~0); 107102#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106925#L635 assume !(1 == ~m_pc~0); 106055#L635-2 is_master_triggered_~__retres1~0#1 := 0; 106056#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106407#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 107063#L1598 assume !(0 != activate_threads_~tmp~1#1); 106232#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106233#L654 assume 1 == ~t1_pc~0; 106949#L655 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 106950#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108161#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 107041#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 107042#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106284#L673 assume !(1 == ~t2_pc~0); 106286#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 107470#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107471#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108212#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 108225#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107125#L692 assume !(1 == ~t3_pc~0); 106927#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 106928#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106785#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106750#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 106751#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106306#L711 assume 1 == ~t4_pc~0; 106307#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 106796#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107279#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 106008#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 106009#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108200#L730 assume !(1 == ~t5_pc~0); 107399#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 106187#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106188#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 106316#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 106317#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 106660#L749 assume 1 == ~t6_pc~0; 106433#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 106197#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 106626#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 106627#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 106854#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 105990#L768 assume !(1 == ~t7_pc~0); 105991#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 107328#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 106225#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 106226#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 107348#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 106465#L787 assume 1 == ~t8_pc~0; 106466#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 107734#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 107945#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 107946#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 106033#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 106034#L806 assume 1 == ~t9_pc~0; 107745#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 106068#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 106069#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 106318#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 106319#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 107727#L825 assume !(1 == ~t10_pc~0); 107728#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 107293#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 107294#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 106408#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 106409#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 107005#L844 assume 1 == ~t11_pc~0; 106683#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 106684#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 107070#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 107071#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 107714#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 107715#L863 assume !(1 == ~t12_pc~0); 106172#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 106171#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 106398#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 107828#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 107829#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 107140#L882 assume 1 == ~t13_pc~0; 107141#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 107443#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 108055#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 107784#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 107428#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107429#L1434 assume !(1 == ~M_E~0); 108067#L1434-2 assume !(1 == ~T1_E~0); 108209#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 108210#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 107506#L1449-1 assume !(1 == ~T4_E~0); 106748#L1454-1 assume !(1 == ~T5_E~0); 106749#L1459-1 assume !(1 == ~T6_E~0); 107349#L1464-1 assume !(1 == ~T7_E~0); 107350#L1469-1 assume !(1 == ~T8_E~0); 107446#L1474-1 assume !(1 == ~T9_E~0); 108158#L1479-1 assume !(1 == ~T10_E~0); 110117#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 107850#L1489-1 assume !(1 == ~T12_E~0); 106966#L1494-1 assume !(1 == ~T13_E~0); 106967#L1499-1 assume !(1 == ~E_M~0); 107164#L1504-1 assume !(1 == ~E_1~0); 107165#L1509-1 assume !(1 == ~E_2~0); 107849#L1514-1 assume !(1 == ~E_3~0); 107481#L1519-1 assume !(1 == ~E_4~0); 107482#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 108136#L1529-1 assume !(1 == ~E_6~0); 108137#L1534-1 assume !(1 == ~E_7~0); 108183#L1539-1 assume !(1 == ~E_8~0); 106520#L1544-1 assume !(1 == ~E_9~0); 106521#L1549-1 assume !(1 == ~E_10~0); 110010#L1554-1 assume !(1 == ~E_11~0); 110007#L1559-1 assume !(1 == ~E_12~0); 110004#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 109999#L1569-1 assume { :end_inline_reset_delta_events } true; 109992#L1935-2 [2022-11-16 11:07:15,734 INFO L750 eck$LassoCheckResult]: Loop: 109992#L1935-2 assume !false; 109986#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109981#L1261 assume !false; 109980#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 109973#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 109965#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 109964#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 109962#L1074 assume !(0 != eval_~tmp~0#1); 109961#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 109960#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 109959#L1286-3 assume !(0 == ~M_E~0); 109958#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 109956#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 109957#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 115626#L1301-3 assume !(0 == ~T4_E~0); 115624#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 109951#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 109950#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 109949#L1321-3 assume !(0 == ~T8_E~0); 109948#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 109947#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 109946#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 109945#L1341-3 assume !(0 == ~T12_E~0); 109944#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 109943#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 109942#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 109941#L1361-3 assume !(0 == ~E_2~0); 109939#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 109940#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 111916#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 109935#L1381-3 assume !(0 == ~E_6~0); 109934#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 109933#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 109932#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 109931#L1401-3 assume !(0 == ~E_10~0); 109930#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 109929#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 109928#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 109927#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109924#L635-45 assume 1 == ~m_pc~0; 109925#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 111618#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111617#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 111616#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 111615#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111614#L654-45 assume 1 == ~t1_pc~0; 111613#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 111611#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111610#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 111609#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 111608#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111607#L673-45 assume !(1 == ~t2_pc~0); 111605#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 111604#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111603#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 111602#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 111601#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111598#L692-45 assume !(1 == ~t3_pc~0); 111600#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 114247#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114246#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114245#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 114244#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114243#L711-45 assume 1 == ~t4_pc~0; 114241#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 114240#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114239#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114238#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 114237#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114235#L730-45 assume !(1 == ~t5_pc~0); 111583#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 111580#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111581#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112089#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 112086#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112084#L749-45 assume !(1 == ~t6_pc~0); 112081#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 111565#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111562#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111563#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 111555#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 111556#L768-45 assume 1 == ~t7_pc~0; 111777#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 109819#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109820#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 111657#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 111656#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 111498#L787-45 assume !(1 == ~t8_pc~0); 111495#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 111493#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 111491#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 111440#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 111363#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 111361#L806-45 assume !(1 == ~t9_pc~0); 111299#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 111296#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111294#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111291#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 111289#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111288#L825-45 assume !(1 == ~t10_pc~0); 111229#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 111227#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111132#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111129#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111127#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111026#L844-45 assume !(1 == ~t11_pc~0); 111023#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 111020#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 110975#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 110973#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 110935#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 110934#L863-45 assume !(1 == ~t12_pc~0); 110933#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 110881#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110804#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 106495#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 106496#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 107331#L882-45 assume !(1 == ~t13_pc~0); 106834#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 106000#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 106001#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 106611#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 107897#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107449#L1434-3 assume !(1 == ~M_E~0); 107450#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 109687#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106295#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 106296#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106458#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 107438#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107439#L1464-3 assume !(1 == ~T7_E~0); 108249#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 109306#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 110270#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 110246#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 110244#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 110219#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 110217#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 110193#L1504-3 assume !(1 == ~E_1~0); 110191#L1509-3 assume !(1 == ~E_2~0); 110173#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 110171#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 110168#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 110166#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 110164#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 110148#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 110131#L1544-3 assume !(1 == ~E_9~0); 110122#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 110114#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 110110#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 110105#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 110103#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110078#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 110068#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 110066#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 110048#L1954 assume !(0 == start_simulation_~tmp~3#1); 110045#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110029#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 110017#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 110014#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 110011#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 110008#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 110005#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 110000#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 109992#L1935-2 [2022-11-16 11:07:15,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:15,737 INFO L85 PathProgramCache]: Analyzing trace with hash 879310208, now seen corresponding path program 1 times [2022-11-16 11:07:15,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:15,737 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215956338] [2022-11-16 11:07:15,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:15,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:15,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:15,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:15,877 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:15,877 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215956338] [2022-11-16 11:07:15,877 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215956338] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:15,877 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:15,878 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:15,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [327836567] [2022-11-16 11:07:15,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:15,879 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:15,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:15,879 INFO L85 PathProgramCache]: Analyzing trace with hash -1590774876, now seen corresponding path program 1 times [2022-11-16 11:07:15,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:15,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725409860] [2022-11-16 11:07:15,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:15,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:15,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:15,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:15,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:15,990 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725409860] [2022-11-16 11:07:15,990 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725409860] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:15,990 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:15,990 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:15,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657897962] [2022-11-16 11:07:15,991 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:15,992 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:15,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:15,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:07:15,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:07:15,993 INFO L87 Difference]: Start difference. First operand 14193 states and 20696 transitions. cyclomatic complexity: 6507 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:16,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:16,857 INFO L93 Difference]: Finished difference Result 40855 states and 58998 transitions. [2022-11-16 11:07:16,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40855 states and 58998 transitions. [2022-11-16 11:07:17,059 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 39792 [2022-11-16 11:07:17,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40855 states to 40855 states and 58998 transitions. [2022-11-16 11:07:17,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40855 [2022-11-16 11:07:17,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40855 [2022-11-16 11:07:17,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40855 states and 58998 transitions. [2022-11-16 11:07:17,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:17,306 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40855 states and 58998 transitions. [2022-11-16 11:07:17,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40855 states and 58998 transitions. [2022-11-16 11:07:18,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40855 to 39319. [2022-11-16 11:07:18,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39319 states, 39319 states have (on average 1.4461710623362751) internal successors, (56862), 39318 states have internal predecessors, (56862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:18,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39319 states to 39319 states and 56862 transitions. [2022-11-16 11:07:18,444 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39319 states and 56862 transitions. [2022-11-16 11:07:18,445 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:07:18,445 INFO L428 stractBuchiCegarLoop]: Abstraction has 39319 states and 56862 transitions. [2022-11-16 11:07:18,445 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 11:07:18,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39319 states and 56862 transitions. [2022-11-16 11:07:18,616 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 39056 [2022-11-16 11:07:18,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:18,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:18,621 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:18,621 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:18,622 INFO L748 eck$LassoCheckResult]: Stem: 161915#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 161916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 161644#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 161645#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 163192#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 163193#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 161833#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 161834#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 161868#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 162759#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 162760#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 162899#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 162900#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 161650#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 161651#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 162944#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 162181#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 162182#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 162829#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 163174#L1286 assume !(0 == ~M_E~0); 163024#L1286-2 assume !(0 == ~T1_E~0); 161559#L1291-1 assume !(0 == ~T2_E~0); 161560#L1296-1 assume !(0 == ~T3_E~0); 162279#L1301-1 assume !(0 == ~T4_E~0); 162280#L1306-1 assume !(0 == ~T5_E~0); 162838#L1311-1 assume !(0 == ~T6_E~0); 161518#L1316-1 assume !(0 == ~T7_E~0); 161519#L1321-1 assume !(0 == ~T8_E~0); 162298#L1326-1 assume !(0 == ~T9_E~0); 161334#L1331-1 assume !(0 == ~T10_E~0); 161041#L1336-1 assume !(0 == ~T11_E~0); 161042#L1341-1 assume !(0 == ~T12_E~0); 161093#L1346-1 assume !(0 == ~T13_E~0); 161094#L1351-1 assume !(0 == ~E_M~0); 161463#L1356-1 assume !(0 == ~E_1~0); 161464#L1361-1 assume !(0 == ~E_2~0); 163125#L1366-1 assume !(0 == ~E_3~0); 161510#L1371-1 assume !(0 == ~E_4~0); 161511#L1376-1 assume !(0 == ~E_5~0); 162347#L1381-1 assume !(0 == ~E_6~0); 162348#L1386-1 assume !(0 == ~E_7~0); 163158#L1391-1 assume !(0 == ~E_8~0); 163180#L1396-1 assume !(0 == ~E_9~0); 162215#L1401-1 assume !(0 == ~E_10~0); 162216#L1406-1 assume !(0 == ~E_11~0); 162547#L1411-1 assume !(0 == ~E_12~0); 162548#L1416-1 assume !(0 == ~E_13~0); 162138#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 161979#L635 assume !(1 == ~m_pc~0); 161113#L635-2 is_master_triggered_~__retres1~0#1 := 0; 161114#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161460#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 162102#L1598 assume !(0 != activate_threads_~tmp~1#1); 161289#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161290#L654 assume !(1 == ~t1_pc~0); 162084#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 162946#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163154#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 162080#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 162081#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 161340#L673 assume !(1 == ~t2_pc~0); 161342#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 162511#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 162512#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 163205#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 163214#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162162#L692 assume !(1 == ~t3_pc~0); 161980#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 161981#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161837#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 161804#L1622 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 161805#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161362#L711 assume 1 == ~t4_pc~0; 161363#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 161848#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162319#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 161066#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 161067#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163191#L730 assume !(1 == ~t5_pc~0); 162442#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 161245#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 161246#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 161372#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 161373#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 161716#L749 assume 1 == ~t6_pc~0; 161486#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 161255#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 161682#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 161683#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 161907#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 161048#L768 assume !(1 == ~t7_pc~0); 161049#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 162373#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 161282#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 161283#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 162394#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 161520#L787 assume 1 == ~t8_pc~0; 161521#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 162777#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 162976#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 162977#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 161091#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 161092#L806 assume 1 == ~t9_pc~0; 162789#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 161126#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 161127#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 161374#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 161375#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 162768#L825 assume !(1 == ~t10_pc~0); 162769#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 162336#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 162337#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 161461#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 161462#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 162049#L844 assume 1 == ~t11_pc~0; 161739#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 161740#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 162108#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 162109#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 162753#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 162754#L863 assume !(1 == ~t12_pc~0); 161230#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 161229#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 161451#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 162869#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 162870#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 162176#L882 assume 1 == ~t13_pc~0; 162177#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 162482#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 163083#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 162831#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 162468#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 162469#L1434 assume !(1 == ~M_E~0); 163096#L1434-2 assume !(1 == ~T1_E~0); 163203#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 161355#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 161356#L1449-1 assume !(1 == ~T4_E~0); 161802#L1454-1 assume !(1 == ~T5_E~0); 161803#L1459-1 assume !(1 == ~T6_E~0); 162395#L1464-1 assume !(1 == ~T7_E~0); 162396#L1469-1 assume !(1 == ~T8_E~0); 162485#L1474-1 assume !(1 == ~T9_E~0); 162139#L1479-1 assume !(1 == ~T10_E~0); 162140#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 162403#L1489-1 assume !(1 == ~T12_E~0); 162015#L1494-1 assume !(1 == ~T13_E~0); 162016#L1499-1 assume !(1 == ~E_M~0); 162200#L1504-1 assume !(1 == ~E_1~0); 162201#L1509-1 assume !(1 == ~E_2~0); 162888#L1514-1 assume !(1 == ~E_3~0); 162524#L1519-1 assume !(1 == ~E_4~0); 162525#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 163139#L1529-1 assume !(1 == ~E_6~0); 163140#L1534-1 assume !(1 == ~E_7~0); 161148#L1539-1 assume !(1 == ~E_8~0); 161149#L1544-1 assume !(1 == ~E_9~0); 161576#L1549-1 assume !(1 == ~E_10~0); 163112#L1554-1 assume !(1 == ~E_11~0); 195261#L1559-1 assume !(1 == ~E_12~0); 195259#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 176867#L1569-1 assume { :end_inline_reset_delta_events } true; 176862#L1935-2 [2022-11-16 11:07:18,623 INFO L750 eck$LassoCheckResult]: Loop: 176862#L1935-2 assume !false; 176861#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 176856#L1261 assume !false; 176855#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 176847#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 176838#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 176834#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 176831#L1074 assume !(0 != eval_~tmp~0#1); 176832#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 195236#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 195234#L1286-3 assume !(0 == ~M_E~0); 195232#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 195230#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 195228#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 195226#L1301-3 assume !(0 == ~T4_E~0); 195224#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 195223#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 195221#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 195219#L1321-3 assume !(0 == ~T8_E~0); 195218#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 195217#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 195216#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 195215#L1341-3 assume !(0 == ~T12_E~0); 195214#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 195213#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 195212#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 195211#L1361-3 assume !(0 == ~E_2~0); 195210#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 195209#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 195208#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 195207#L1381-3 assume !(0 == ~E_6~0); 195206#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 195205#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 195204#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 195203#L1401-3 assume !(0 == ~E_10~0); 195202#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 195201#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 195200#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 195199#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 195198#L635-45 assume !(1 == ~m_pc~0); 195197#L635-47 is_master_triggered_~__retres1~0#1 := 0; 195196#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 195195#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 195194#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 195193#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 195192#L654-45 assume !(1 == ~t1_pc~0); 195191#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 195190#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 195189#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 195188#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 195186#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 195184#L673-45 assume !(1 == ~t2_pc~0); 195181#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 195179#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 195178#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 195177#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 195176#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 195175#L692-45 assume !(1 == ~t3_pc~0); 195174#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 195172#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 195171#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 195170#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 195164#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 195162#L711-45 assume 1 == ~t4_pc~0; 195159#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 195157#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 195154#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 195152#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 195150#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 195148#L730-45 assume !(1 == ~t5_pc~0); 195146#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 195143#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 195142#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 195140#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 195138#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 195136#L749-45 assume 1 == ~t6_pc~0; 195134#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 195130#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 195128#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 195126#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 195124#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 195122#L768-45 assume !(1 == ~t7_pc~0); 195120#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 195117#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 195114#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 195112#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 195110#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 195108#L787-45 assume 1 == ~t8_pc~0; 195106#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 195103#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 195100#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 195098#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 195096#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 195094#L806-45 assume 1 == ~t9_pc~0; 195091#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 195089#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 195086#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 195084#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 195082#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 195080#L825-45 assume !(1 == ~t10_pc~0); 195006#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 195003#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 195001#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 194999#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 194997#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 194995#L844-45 assume 1 == ~t11_pc~0; 194992#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 194989#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 194987#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 194985#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 194983#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 194981#L863-45 assume 1 == ~t12_pc~0; 194978#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 194975#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 194973#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 194971#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 194969#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 194967#L882-45 assume !(1 == ~t13_pc~0); 194964#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 194961#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 194959#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 194957#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 194955#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194953#L1434-3 assume !(1 == ~M_E~0); 183750#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 194949#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 162692#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 194946#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 194944#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 194942#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 194940#L1464-3 assume !(1 == ~T7_E~0); 194937#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 163002#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 194934#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 194932#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 194930#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 194928#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 194925#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 194923#L1504-3 assume !(1 == ~E_1~0); 194921#L1509-3 assume !(1 == ~E_2~0); 194919#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 194917#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 194915#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 194912#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 194910#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 194908#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 194906#L1544-3 assume !(1 == ~E_9~0); 194904#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 179676#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 194900#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 194898#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 194896#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 176925#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 176915#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 176913#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 176909#L1954 assume !(0 == start_simulation_~tmp~3#1); 176906#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 176890#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 176881#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 176878#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 176876#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 176874#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 176873#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 176868#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 176862#L1935-2 [2022-11-16 11:07:18,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:18,624 INFO L85 PathProgramCache]: Analyzing trace with hash -2044595327, now seen corresponding path program 1 times [2022-11-16 11:07:18,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:18,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [963730648] [2022-11-16 11:07:18,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:18,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:18,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:18,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:18,881 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:18,881 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [963730648] [2022-11-16 11:07:18,881 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [963730648] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:18,882 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:18,882 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:07:18,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014461210] [2022-11-16 11:07:18,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:18,884 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:18,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:18,884 INFO L85 PathProgramCache]: Analyzing trace with hash 293949346, now seen corresponding path program 1 times [2022-11-16 11:07:18,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:18,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628052183] [2022-11-16 11:07:18,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:18,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:18,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:18,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:18,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:18,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628052183] [2022-11-16 11:07:18,958 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628052183] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:18,958 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:18,958 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:18,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723143312] [2022-11-16 11:07:18,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:18,960 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:18,960 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:18,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:07:18,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:07:18,961 INFO L87 Difference]: Start difference. First operand 39319 states and 56862 transitions. cyclomatic complexity: 17551 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:20,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:20,016 INFO L93 Difference]: Finished difference Result 108046 states and 156539 transitions. [2022-11-16 11:07:20,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108046 states and 156539 transitions. [2022-11-16 11:07:20,934 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 107408 [2022-11-16 11:07:21,526 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108046 states to 108046 states and 156539 transitions. [2022-11-16 11:07:21,527 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108046 [2022-11-16 11:07:21,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108046 [2022-11-16 11:07:21,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108046 states and 156539 transitions. [2022-11-16 11:07:21,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:21,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108046 states and 156539 transitions. [2022-11-16 11:07:22,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108046 states and 156539 transitions. [2022-11-16 11:07:22,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108046 to 40330. [2022-11-16 11:07:22,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40330 states, 40330 states have (on average 1.4349863625092982) internal successors, (57873), 40329 states have internal predecessors, (57873), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:23,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40330 states to 40330 states and 57873 transitions. [2022-11-16 11:07:23,123 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40330 states and 57873 transitions. [2022-11-16 11:07:23,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 11:07:23,124 INFO L428 stractBuchiCegarLoop]: Abstraction has 40330 states and 57873 transitions. [2022-11-16 11:07:23,124 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 11:07:23,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40330 states and 57873 transitions. [2022-11-16 11:07:23,292 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 40064 [2022-11-16 11:07:23,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:23,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:23,296 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:23,297 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:23,298 INFO L748 eck$LassoCheckResult]: Stem: 309295#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 309296#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 309024#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 309025#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 310681#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 310682#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 309211#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 309212#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 309247#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 310180#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 310181#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 310331#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 310332#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 309030#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 309031#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 310374#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 309563#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 309564#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 310251#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 310650#L1286 assume !(0 == ~M_E~0); 310463#L1286-2 assume !(0 == ~T1_E~0); 308939#L1291-1 assume !(0 == ~T2_E~0); 308940#L1296-1 assume !(0 == ~T3_E~0); 309672#L1301-1 assume !(0 == ~T4_E~0); 309673#L1306-1 assume !(0 == ~T5_E~0); 310263#L1311-1 assume !(0 == ~T6_E~0); 308897#L1316-1 assume !(0 == ~T7_E~0); 308898#L1321-1 assume !(0 == ~T8_E~0); 309692#L1326-1 assume !(0 == ~T9_E~0); 308714#L1331-1 assume !(0 == ~T10_E~0); 308419#L1336-1 assume !(0 == ~T11_E~0); 308420#L1341-1 assume !(0 == ~T12_E~0); 308471#L1346-1 assume !(0 == ~T13_E~0); 308472#L1351-1 assume !(0 == ~E_M~0); 308842#L1356-1 assume !(0 == ~E_1~0); 308843#L1361-1 assume !(0 == ~E_2~0); 310576#L1366-1 assume !(0 == ~E_3~0); 308889#L1371-1 assume !(0 == ~E_4~0); 308890#L1376-1 assume !(0 == ~E_5~0); 309741#L1381-1 assume !(0 == ~E_6~0); 309742#L1386-1 assume !(0 == ~E_7~0); 310631#L1391-1 assume !(0 == ~E_8~0); 310658#L1396-1 assume !(0 == ~E_9~0); 309602#L1401-1 assume !(0 == ~E_10~0); 309603#L1406-1 assume !(0 == ~E_11~0); 309951#L1411-1 assume !(0 == ~E_12~0); 309952#L1416-1 assume !(0 == ~E_13~0); 309520#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 309358#L635 assume !(1 == ~m_pc~0); 308491#L635-2 is_master_triggered_~__retres1~0#1 := 0; 308492#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 308839#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 309483#L1598 assume !(0 != activate_threads_~tmp~1#1); 308668#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 308669#L654 assume !(1 == ~t1_pc~0); 309467#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 310376#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 310624#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 309463#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 309464#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 308720#L673 assume !(1 == ~t2_pc~0); 308722#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 309912#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 309913#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 310695#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 310706#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 309543#L692 assume !(1 == ~t3_pc~0); 309359#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 309360#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 310653#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 309182#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 309183#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 308742#L711 assume 1 == ~t4_pc~0; 308743#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 309227#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 309710#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 308444#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 308445#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 310680#L730 assume !(1 == ~t5_pc~0); 309842#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 308624#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 308625#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 308752#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 308753#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 309096#L749 assume 1 == ~t6_pc~0; 308865#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 308634#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 309062#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 309063#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 309287#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 308426#L768 assume !(1 == ~t7_pc~0); 308427#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 309768#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 308661#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 308662#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 309787#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 308899#L787 assume 1 == ~t8_pc~0; 308900#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 310199#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 310413#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 310414#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 308469#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 308470#L806 assume 1 == ~t9_pc~0; 310211#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 308504#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 308505#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 308754#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 308755#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 310190#L825 assume !(1 == ~t10_pc~0); 310191#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 309729#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 309730#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 308840#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 308841#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 309430#L844 assume 1 == ~t11_pc~0; 309119#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 309120#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 309490#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 309491#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 310174#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 310175#L863 assume !(1 == ~t12_pc~0); 308608#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 308607#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 308830#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 310298#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 310299#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 309558#L882 assume 1 == ~t13_pc~0; 309559#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 309884#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 310522#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 310254#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 309869#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309870#L1434 assume !(1 == ~M_E~0); 310538#L1434-2 assume !(1 == ~T1_E~0); 310693#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 308735#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 308736#L1449-1 assume !(1 == ~T4_E~0); 309180#L1454-1 assume !(1 == ~T5_E~0); 309181#L1459-1 assume !(1 == ~T6_E~0); 309788#L1464-1 assume !(1 == ~T7_E~0); 309789#L1469-1 assume !(1 == ~T8_E~0); 309887#L1474-1 assume !(1 == ~T9_E~0); 336302#L1479-1 assume !(1 == ~T10_E~0); 336300#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 336298#L1489-1 assume !(1 == ~T12_E~0); 336295#L1494-1 assume !(1 == ~T13_E~0); 336293#L1499-1 assume !(1 == ~E_M~0); 336291#L1504-1 assume !(1 == ~E_1~0); 336289#L1509-1 assume !(1 == ~E_2~0); 336287#L1514-1 assume !(1 == ~E_3~0); 336285#L1519-1 assume !(1 == ~E_4~0); 336282#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 336280#L1529-1 assume !(1 == ~E_6~0); 336278#L1534-1 assume !(1 == ~E_7~0); 336276#L1539-1 assume !(1 == ~E_8~0); 336274#L1544-1 assume !(1 == ~E_9~0); 336272#L1549-1 assume !(1 == ~E_10~0); 310560#L1554-1 assume !(1 == ~E_11~0); 336271#L1559-1 assume !(1 == ~E_12~0); 334407#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 315526#L1569-1 assume { :end_inline_reset_delta_events } true; 315524#L1935-2 [2022-11-16 11:07:23,298 INFO L750 eck$LassoCheckResult]: Loop: 315524#L1935-2 assume !false; 313671#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 313665#L1261 assume !false; 313663#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 313382#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 313373#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 313372#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 313371#L1074 assume !(0 != eval_~tmp~0#1); 309836#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 309837#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 310325#L1286-3 assume !(0 == ~M_E~0); 310396#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 310035#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 310036#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 310651#L1301-3 assume !(0 == ~T4_E~0); 310568#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 309476#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 308766#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 308767#L1321-3 assume !(0 == ~T8_E~0); 309627#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 309628#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 348609#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 348608#L1341-3 assume !(0 == ~T12_E~0); 348607#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 348606#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 348605#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 348604#L1361-3 assume !(0 == ~E_2~0); 348603#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 348602#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 348601#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 348600#L1381-3 assume !(0 == ~E_6~0); 348599#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 348598#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 348597#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 348596#L1401-3 assume !(0 == ~E_10~0); 348595#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 348594#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 348593#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 348592#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 308549#L635-45 assume !(1 == ~m_pc~0); 308550#L635-47 is_master_triggered_~__retres1~0#1 := 0; 309871#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 309872#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 310172#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 310173#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 309706#L654-45 assume !(1 == ~t1_pc~0); 309707#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 310110#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 310111#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 308537#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 308538#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 348591#L673-45 assume !(1 == ~t2_pc~0); 310392#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 310393#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 348589#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 310491#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 310249#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 310250#L692-45 assume 1 == ~t3_pc~0; 348053#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 348054#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 348045#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 348046#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 348587#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 348586#L711-45 assume !(1 == ~t4_pc~0); 348585#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 348583#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 348582#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 348581#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 348580#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 348579#L730-45 assume 1 == ~t5_pc~0; 348577#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 348576#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 348575#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 348574#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 348573#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 348572#L749-45 assume 1 == ~t6_pc~0; 348571#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 348569#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 348568#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 348567#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 348566#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 348565#L768-45 assume !(1 == ~t7_pc~0); 348564#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 348562#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 348561#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 348560#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 348559#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 348558#L787-45 assume 1 == ~t8_pc~0; 348557#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 348555#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 348554#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 348553#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 347999#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 348000#L806-45 assume !(1 == ~t9_pc~0); 348532#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 348529#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 347993#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 309223#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 309135#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 309136#L825-45 assume !(1 == ~t10_pc~0); 309685#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 309686#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 309806#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 309807#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 309979#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 308777#L844-45 assume !(1 == ~t11_pc~0); 308778#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 309304#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 309305#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 309321#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 309766#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 308815#L863-45 assume 1 == ~t12_pc~0; 308816#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 308417#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 308418#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 308934#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 308935#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 309772#L882-45 assume !(1 == ~t13_pc~0); 310186#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 348409#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 348407#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 348405#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 348403#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 348402#L1434-3 assume !(1 == ~M_E~0); 310143#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 310108#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 308731#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 308732#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 308891#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 309879#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 309880#L1464-3 assume !(1 == ~T7_E~0); 310443#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 310444#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 310572#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 310446#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 310447#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 348069#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 348068#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 309810#L1504-3 assume !(1 == ~E_1~0); 309811#L1509-3 assume !(1 == ~E_2~0); 310352#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 347257#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 347256#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 347255#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 347254#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 347105#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 347104#L1544-3 assume !(1 == ~E_9~0); 347103#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 310451#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 347102#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 347101#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 347100#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 337159#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 337148#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 337146#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 337143#L1954 assume !(0 == start_simulation_~tmp~3#1); 337140#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 337128#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 337119#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 337118#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 337117#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 337116#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 334408#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 315527#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 315524#L1935-2 [2022-11-16 11:07:23,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:23,300 INFO L85 PathProgramCache]: Analyzing trace with hash 309789955, now seen corresponding path program 1 times [2022-11-16 11:07:23,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:23,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085848826] [2022-11-16 11:07:23,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:23,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:23,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:23,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:23,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:23,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085848826] [2022-11-16 11:07:23,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085848826] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:23,421 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:23,421 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:07:23,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071832281] [2022-11-16 11:07:23,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:23,422 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:23,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:23,423 INFO L85 PathProgramCache]: Analyzing trace with hash -671712413, now seen corresponding path program 1 times [2022-11-16 11:07:23,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:23,423 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623308274] [2022-11-16 11:07:23,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:23,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:23,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:23,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:23,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:23,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623308274] [2022-11-16 11:07:23,523 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [623308274] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:23,524 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:23,524 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:23,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649544278] [2022-11-16 11:07:23,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:23,525 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:23,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:23,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:23,526 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:23,526 INFO L87 Difference]: Start difference. First operand 40330 states and 57873 transitions. cyclomatic complexity: 17551 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:24,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:24,021 INFO L93 Difference]: Finished difference Result 77649 states and 111016 transitions. [2022-11-16 11:07:24,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77649 states and 111016 transitions. [2022-11-16 11:07:24,803 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 77296 [2022-11-16 11:07:25,051 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77649 states to 77649 states and 111016 transitions. [2022-11-16 11:07:25,051 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77649 [2022-11-16 11:07:25,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77649 [2022-11-16 11:07:25,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77649 states and 111016 transitions. [2022-11-16 11:07:25,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:25,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77649 states and 111016 transitions. [2022-11-16 11:07:25,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77649 states and 111016 transitions. [2022-11-16 11:07:26,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77649 to 77601. [2022-11-16 11:07:26,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77601 states, 77601 states have (on average 1.4299815724024174) internal successors, (110968), 77600 states have internal predecessors, (110968), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:26,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77601 states to 77601 states and 110968 transitions. [2022-11-16 11:07:26,449 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77601 states and 110968 transitions. [2022-11-16 11:07:26,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:26,727 INFO L428 stractBuchiCegarLoop]: Abstraction has 77601 states and 110968 transitions. [2022-11-16 11:07:26,727 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-16 11:07:26,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77601 states and 110968 transitions. [2022-11-16 11:07:26,939 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 77248 [2022-11-16 11:07:26,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:26,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:26,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:26,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:26,943 INFO L748 eck$LassoCheckResult]: Stem: 427294#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 427295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 427018#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 427019#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 428638#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 428639#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 427213#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 427214#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 427249#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 428158#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 428159#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 428297#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 428298#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 427024#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 427025#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 428345#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 427568#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 427569#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 428222#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 428611#L1286 assume !(0 == ~M_E~0); 428432#L1286-2 assume !(0 == ~T1_E~0); 426928#L1291-1 assume !(0 == ~T2_E~0); 426929#L1296-1 assume !(0 == ~T3_E~0); 427671#L1301-1 assume !(0 == ~T4_E~0); 427672#L1306-1 assume !(0 == ~T5_E~0); 428233#L1311-1 assume !(0 == ~T6_E~0); 426886#L1316-1 assume !(0 == ~T7_E~0); 426887#L1321-1 assume !(0 == ~T8_E~0); 427690#L1326-1 assume !(0 == ~T9_E~0); 426704#L1331-1 assume !(0 == ~T10_E~0); 426405#L1336-1 assume !(0 == ~T11_E~0); 426406#L1341-1 assume !(0 == ~T12_E~0); 426458#L1346-1 assume !(0 == ~T13_E~0); 426459#L1351-1 assume !(0 == ~E_M~0); 426834#L1356-1 assume !(0 == ~E_1~0); 426835#L1361-1 assume !(0 == ~E_2~0); 428544#L1366-1 assume !(0 == ~E_3~0); 426879#L1371-1 assume !(0 == ~E_4~0); 426880#L1376-1 assume !(0 == ~E_5~0); 427739#L1381-1 assume !(0 == ~E_6~0); 427740#L1386-1 assume !(0 == ~E_7~0); 428594#L1391-1 assume !(0 == ~E_8~0); 428618#L1396-1 assume !(0 == ~E_9~0); 427605#L1401-1 assume !(0 == ~E_10~0); 427606#L1406-1 assume !(0 == ~E_11~0); 427939#L1411-1 assume !(0 == ~E_12~0); 427940#L1416-1 assume !(0 == ~E_13~0); 427523#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 427355#L635 assume !(1 == ~m_pc~0); 426478#L635-2 is_master_triggered_~__retres1~0#1 := 0; 426479#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 426831#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 427484#L1598 assume !(0 != activate_threads_~tmp~1#1); 426658#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 426659#L654 assume !(1 == ~t1_pc~0); 427466#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 428347#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 428588#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 427462#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 427463#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 426710#L673 assume !(1 == ~t2_pc~0); 426712#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 427905#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 427906#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 428654#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 428665#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 427547#L692 assume !(1 == ~t3_pc~0); 427356#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 427357#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 427217#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 427180#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 427181#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 426732#L711 assume !(1 == ~t4_pc~0); 426733#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 428336#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 427710#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 426430#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 426431#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 428635#L730 assume !(1 == ~t5_pc~0); 427835#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 426613#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 426614#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 426741#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 426742#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 427091#L749 assume 1 == ~t6_pc~0; 426857#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 426623#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 427055#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 427056#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 427286#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 426412#L768 assume !(1 == ~t7_pc~0); 426413#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 427763#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 426651#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 426652#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 427782#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 426888#L787 assume 1 == ~t8_pc~0; 426889#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 428174#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 428379#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 428380#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 426456#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 426457#L806 assume 1 == ~t9_pc~0; 428186#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 426491#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 426492#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 426743#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 426744#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 428166#L825 assume !(1 == ~t10_pc~0); 428167#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 427728#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 427729#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 426832#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 426833#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 427427#L844 assume 1 == ~t11_pc~0; 427115#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 427116#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 427490#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 427491#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 428154#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 428155#L863 assume !(1 == ~t12_pc~0); 426596#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 426595#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 426822#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 428259#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 428260#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 427563#L882 assume 1 == ~t13_pc~0; 427564#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 427876#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 428490#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 428224#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 427863#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 427864#L1434 assume !(1 == ~M_E~0); 428505#L1434-2 assume !(1 == ~T1_E~0); 428650#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 428651#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 427944#L1449-1 assume !(1 == ~T4_E~0); 427945#L1454-1 assume !(1 == ~T5_E~0); 428455#L1459-1 assume !(1 == ~T6_E~0); 428456#L1464-1 assume !(1 == ~T7_E~0); 427879#L1469-1 assume !(1 == ~T8_E~0); 427880#L1474-1 assume !(1 == ~T9_E~0); 449632#L1479-1 assume !(1 == ~T10_E~0); 449631#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 428281#L1489-1 assume !(1 == ~T12_E~0); 428282#L1494-1 assume !(1 == ~T13_E~0); 428641#L1499-1 assume !(1 == ~E_M~0); 427588#L1504-1 assume !(1 == ~E_1~0); 427589#L1509-1 assume !(1 == ~E_2~0); 428485#L1514-1 assume !(1 == ~E_3~0); 427918#L1519-1 assume !(1 == ~E_4~0); 427919#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 428562#L1529-1 assume !(1 == ~E_6~0); 428563#L1534-1 assume !(1 == ~E_7~0); 426513#L1539-1 assume !(1 == ~E_8~0); 426514#L1544-1 assume !(1 == ~E_9~0); 426947#L1549-1 assume !(1 == ~E_10~0); 428523#L1554-1 assume !(1 == ~E_11~0); 428521#L1559-1 assume !(1 == ~E_12~0); 428324#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 428325#L1569-1 assume { :end_inline_reset_delta_events } true; 428554#L1935-2 [2022-11-16 11:07:26,943 INFO L750 eck$LassoCheckResult]: Loop: 428554#L1935-2 assume !false; 450666#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 450660#L1261 assume !false; 450658#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 450638#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 450629#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 450627#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 450624#L1074 assume !(0 != eval_~tmp~0#1); 450625#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 451066#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 451064#L1286-3 assume !(0 == ~M_E~0); 451062#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 451060#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 451058#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 451056#L1301-3 assume !(0 == ~T4_E~0); 451054#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 451052#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 451050#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 451048#L1321-3 assume !(0 == ~T8_E~0); 451046#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 451044#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 451042#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 451040#L1341-3 assume !(0 == ~T12_E~0); 451038#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 451036#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 451034#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 451032#L1361-3 assume !(0 == ~E_2~0); 451030#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 451028#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 451026#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 451024#L1381-3 assume !(0 == ~E_6~0); 451022#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 451020#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 451018#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 451016#L1401-3 assume !(0 == ~E_10~0); 451014#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 451012#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 451010#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 451008#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 451006#L635-45 assume !(1 == ~m_pc~0); 451004#L635-47 is_master_triggered_~__retres1~0#1 := 0; 451002#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 451000#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 450998#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 450996#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 450994#L654-45 assume !(1 == ~t1_pc~0); 450992#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 450990#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 450988#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 450986#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 450984#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 450982#L673-45 assume !(1 == ~t2_pc~0); 450978#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 450976#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 450974#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 450972#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 450970#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 450968#L692-45 assume !(1 == ~t3_pc~0); 450966#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 450962#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 450958#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 450954#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 450950#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 450948#L711-45 assume !(1 == ~t4_pc~0); 450946#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 450944#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 450942#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 450940#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 450938#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 450936#L730-45 assume !(1 == ~t5_pc~0); 450934#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 450930#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 450928#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 450926#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 450924#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 450922#L749-45 assume !(1 == ~t6_pc~0); 450919#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 450916#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 450914#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 450912#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 450910#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 450908#L768-45 assume !(1 == ~t7_pc~0); 450906#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 450902#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 450900#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 450898#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 450896#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 450894#L787-45 assume 1 == ~t8_pc~0; 450892#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 450888#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 450886#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 450884#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 450882#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 450880#L806-45 assume !(1 == ~t9_pc~0); 450878#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 450874#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 450872#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 450870#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 450868#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 450866#L825-45 assume 1 == ~t10_pc~0; 450864#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 450860#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 450858#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 450856#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 450854#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 450852#L844-45 assume !(1 == ~t11_pc~0); 450850#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 450846#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 450844#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 450842#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 450839#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 450836#L863-45 assume 1 == ~t12_pc~0; 450832#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 450828#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 450825#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 450822#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 450819#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 450816#L882-45 assume !(1 == ~t13_pc~0); 450812#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 450808#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 450805#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 450802#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 450799#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 450796#L1434-3 assume !(1 == ~M_E~0); 450791#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 450789#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 441999#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 450786#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 450784#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 450782#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 450780#L1464-3 assume !(1 == ~T7_E~0); 450777#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 446491#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 450772#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 450769#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 450767#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 450765#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 450762#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 450760#L1504-3 assume !(1 == ~E_1~0); 450758#L1509-3 assume !(1 == ~E_2~0); 450756#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 450754#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 450752#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 450749#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 450747#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 450745#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 450743#L1544-3 assume !(1 == ~E_9~0); 450741#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 441897#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 450737#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 450735#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 450733#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 450726#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 450716#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 450714#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 450710#L1954 assume !(0 == start_simulation_~tmp~3#1); 450707#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 450691#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 450681#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 450678#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 450676#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 450674#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 450672#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 450670#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 428554#L1935-2 [2022-11-16 11:07:26,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:26,944 INFO L85 PathProgramCache]: Analyzing trace with hash -1076891324, now seen corresponding path program 1 times [2022-11-16 11:07:26,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:26,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926940125] [2022-11-16 11:07:26,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:26,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:26,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:27,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:27,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:27,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926940125] [2022-11-16 11:07:27,048 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926940125] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:27,048 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:27,049 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:27,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955929442] [2022-11-16 11:07:27,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:27,050 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:27,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:27,050 INFO L85 PathProgramCache]: Analyzing trace with hash 1069522023, now seen corresponding path program 1 times [2022-11-16 11:07:27,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:27,051 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94767905] [2022-11-16 11:07:27,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:27,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:27,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:27,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:27,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:27,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94767905] [2022-11-16 11:07:27,159 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94767905] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:27,159 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:27,159 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:27,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202256449] [2022-11-16 11:07:27,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:27,160 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:27,161 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:27,161 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:07:27,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:07:27,162 INFO L87 Difference]: Start difference. First operand 77601 states and 110968 transitions. cyclomatic complexity: 33383 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:28,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:28,722 INFO L93 Difference]: Finished difference Result 223376 states and 317197 transitions. [2022-11-16 11:07:28,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223376 states and 317197 transitions. [2022-11-16 11:07:30,336 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 219280 [2022-11-16 11:07:30,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223376 states to 223376 states and 317197 transitions. [2022-11-16 11:07:30,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 223376 [2022-11-16 11:07:30,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 223376 [2022-11-16 11:07:30,874 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223376 states and 317197 transitions. [2022-11-16 11:07:31,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:31,009 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223376 states and 317197 transitions. [2022-11-16 11:07:31,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223376 states and 317197 transitions. [2022-11-16 11:07:33,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223376 to 217152. [2022-11-16 11:07:33,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 217152 states, 217152 states have (on average 1.421663166814029) internal successors, (308717), 217151 states have internal predecessors, (308717), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:34,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217152 states to 217152 states and 308717 transitions. [2022-11-16 11:07:34,985 INFO L240 hiAutomatonCegarLoop]: Abstraction has 217152 states and 308717 transitions. [2022-11-16 11:07:34,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:07:34,986 INFO L428 stractBuchiCegarLoop]: Abstraction has 217152 states and 308717 transitions. [2022-11-16 11:07:34,986 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-16 11:07:34,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217152 states and 308717 transitions. [2022-11-16 11:07:35,750 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 216544 [2022-11-16 11:07:35,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:35,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:35,754 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:35,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:35,755 INFO L748 eck$LassoCheckResult]: Stem: 728264#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 728265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 727995#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 727996#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 729610#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 729611#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 728185#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 728186#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 728219#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 729128#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 729129#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 729272#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 729273#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 728001#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 728002#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 729319#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 728534#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 728535#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 729200#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 729574#L1286 assume !(0 == ~M_E~0); 729399#L1286-2 assume !(0 == ~T1_E~0); 727910#L1291-1 assume !(0 == ~T2_E~0); 727911#L1296-1 assume !(0 == ~T3_E~0); 728634#L1301-1 assume !(0 == ~T4_E~0); 728635#L1306-1 assume !(0 == ~T5_E~0); 729209#L1311-1 assume !(0 == ~T6_E~0); 727869#L1316-1 assume !(0 == ~T7_E~0); 727870#L1321-1 assume !(0 == ~T8_E~0); 728653#L1326-1 assume !(0 == ~T9_E~0); 727683#L1331-1 assume !(0 == ~T10_E~0); 727392#L1336-1 assume !(0 == ~T11_E~0); 727393#L1341-1 assume !(0 == ~T12_E~0); 727444#L1346-1 assume !(0 == ~T13_E~0); 727445#L1351-1 assume !(0 == ~E_M~0); 727811#L1356-1 assume !(0 == ~E_1~0); 727812#L1361-1 assume !(0 == ~E_2~0); 729510#L1366-1 assume !(0 == ~E_3~0); 727861#L1371-1 assume !(0 == ~E_4~0); 727862#L1376-1 assume !(0 == ~E_5~0); 728699#L1381-1 assume !(0 == ~E_6~0); 728700#L1386-1 assume !(0 == ~E_7~0); 729557#L1391-1 assume !(0 == ~E_8~0); 729589#L1396-1 assume !(0 == ~E_9~0); 728570#L1401-1 assume !(0 == ~E_10~0); 728571#L1406-1 assume !(0 == ~E_11~0); 728909#L1411-1 assume !(0 == ~E_12~0); 728910#L1416-1 assume !(0 == ~E_13~0); 728490#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728325#L635 assume !(1 == ~m_pc~0); 727464#L635-2 is_master_triggered_~__retres1~0#1 := 0; 727465#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 727808#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 728453#L1598 assume !(0 != activate_threads_~tmp~1#1); 727639#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 727640#L654 assume !(1 == ~t1_pc~0); 728434#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 729321#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 729552#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 728430#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 728431#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 727689#L673 assume !(1 == ~t2_pc~0); 727691#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 728872#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 728873#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 729626#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 729641#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 728515#L692 assume !(1 == ~t3_pc~0); 728326#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 728327#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 728189#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 728153#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 728154#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 727711#L711 assume !(1 == ~t4_pc~0); 727712#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 729311#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 728672#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 727417#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 727418#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 729609#L730 assume !(1 == ~t5_pc~0); 728800#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 727596#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 727597#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 727720#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 727721#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 728064#L749 assume !(1 == ~t6_pc~0); 727605#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 727606#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 728032#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 728033#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 728256#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 727399#L768 assume !(1 == ~t7_pc~0); 727400#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 728726#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 727632#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 727633#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 728748#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 727871#L787 assume 1 == ~t8_pc~0; 727872#L788 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 729150#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 729352#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 729353#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 727442#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 727443#L806 assume 1 == ~t9_pc~0; 729164#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 727477#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 727478#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 727722#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 727723#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 729137#L825 assume !(1 == ~t10_pc~0); 729138#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 728689#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 728690#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 727809#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 727810#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 728396#L844 assume 1 == ~t11_pc~0; 728087#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 728088#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 728459#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 728460#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 729124#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 729125#L863 assume !(1 == ~t12_pc~0); 727580#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 727579#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 727798#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 729240#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 729241#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 728529#L882 assume 1 == ~t13_pc~0; 728530#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 728844#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 729461#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 729202#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 728830#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728831#L1434 assume !(1 == ~M_E~0); 729475#L1434-2 assume !(1 == ~T1_E~0); 729624#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 729625#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 874559#L1449-1 assume !(1 == ~T4_E~0); 728151#L1454-1 assume !(1 == ~T5_E~0); 728152#L1459-1 assume !(1 == ~T6_E~0); 728749#L1464-1 assume !(1 == ~T7_E~0); 728750#L1469-1 assume !(1 == ~T8_E~0); 728847#L1474-1 assume !(1 == ~T9_E~0); 728491#L1479-1 assume !(1 == ~T10_E~0); 728492#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 728758#L1489-1 assume !(1 == ~T12_E~0); 728361#L1494-1 assume !(1 == ~T13_E~0); 728362#L1499-1 assume !(1 == ~E_M~0); 728553#L1504-1 assume !(1 == ~E_1~0); 728554#L1509-1 assume !(1 == ~E_2~0); 729258#L1514-1 assume !(1 == ~E_3~0); 728886#L1519-1 assume !(1 == ~E_4~0); 728887#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 729530#L1529-1 assume !(1 == ~E_6~0); 729531#L1534-1 assume !(1 == ~E_7~0); 727499#L1539-1 assume !(1 == ~E_8~0); 727500#L1544-1 assume !(1 == ~E_9~0); 727928#L1549-1 assume !(1 == ~E_10~0); 729491#L1554-1 assume !(1 == ~E_11~0); 729489#L1559-1 assume !(1 == ~E_12~0); 729301#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 729302#L1569-1 assume { :end_inline_reset_delta_events } true; 729522#L1935-2 [2022-11-16 11:07:35,756 INFO L750 eck$LassoCheckResult]: Loop: 729522#L1935-2 assume !false; 727506#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 727507#L1261 assume !false; 728765#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 728766#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 727635#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 727800#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 727801#L1074 assume !(0 != eval_~tmp~0#1); 728166#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 932271#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 932270#L1286-3 assume !(0 == ~M_E~0); 932268#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 932267#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 932266#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 932265#L1301-3 assume !(0 == ~T4_E~0); 932264#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 932263#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 932261#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 932259#L1321-3 assume !(0 == ~T8_E~0); 932257#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 932254#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 932252#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 932250#L1341-3 assume !(0 == ~T12_E~0); 932248#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 932246#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 932244#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 932240#L1361-3 assume !(0 == ~E_2~0); 932238#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 932236#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 932234#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 932231#L1381-3 assume !(0 == ~E_6~0); 932229#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 932227#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 932224#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 932222#L1401-3 assume !(0 == ~E_10~0); 932220#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 932218#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 932216#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 932214#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 932213#L635-45 assume !(1 == ~m_pc~0); 932212#L635-47 is_master_triggered_~__retres1~0#1 := 0; 932211#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 932210#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 932209#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 932208#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 932207#L654-45 assume !(1 == ~t1_pc~0); 932206#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 932205#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 932204#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 932203#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 932202#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 932201#L673-45 assume !(1 == ~t2_pc~0); 932199#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 932198#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 932196#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 932195#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 932194#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 727955#L692-45 assume !(1 == ~t3_pc~0); 727678#L692-47 is_transmit3_triggered_~__retres1~3#1 := 0; 727679#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 728754#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 728009#L1622-45 assume !(0 != activate_threads_~tmp___2~0#1); 728010#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 728324#L711-45 assume !(1 == ~t4_pc~0); 729683#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 932000#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 931999#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 931997#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 931998#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 932160#L730-45 assume !(1 == ~t5_pc~0); 932158#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 932155#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 932152#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 932150#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 932148#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 932146#L749-45 assume !(1 == ~t6_pc~0); 932144#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 932142#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 932141#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 932139#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 729042#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 727981#L768-45 assume !(1 == ~t7_pc~0); 727983#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 728116#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 728979#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 728980#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 729021#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 729022#L787-45 assume !(1 == ~t8_pc~0); 729229#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 728124#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 728125#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 728551#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 728552#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 728894#L806-45 assume !(1 == ~t9_pc~0); 727539#L806-47 is_transmit9_triggered_~__retres1~9#1 := 0; 727540#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 728363#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 728196#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 728102#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 728103#L825-45 assume 1 == ~t10_pc~0; 932030#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 932027#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 932024#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 728937#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 728938#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 727745#L844-45 assume 1 == ~t11_pc~0; 727747#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 728273#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 728274#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 728290#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 728724#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 727783#L863-45 assume !(1 == ~t12_pc~0); 727785#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 727390#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 727391#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 727905#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 727906#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 728729#L882-45 assume !(1 == ~t13_pc~0); 728237#L882-47 is_transmit13_triggered_~__retres1~13#1 := 0; 727409#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 727410#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 728017#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 729310#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728850#L1434-3 assume !(1 == ~M_E~0); 728851#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 729061#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 729062#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 941443#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 941442#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 941441#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 941440#L1464-3 assume !(1 == ~T7_E~0); 941436#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 873503#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 941433#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 941431#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 941428#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 941426#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 941424#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 941422#L1504-3 assume !(1 == ~E_1~0); 941420#L1509-3 assume !(1 == ~E_2~0); 941419#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 941418#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 941417#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 941416#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 941415#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 728688#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 728117#L1544-3 assume !(1 == ~E_9~0); 728118#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 728654#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 727750#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 727751#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 728955#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 728956#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 929405#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 929404#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 929402#L1954 assume !(0 == start_simulation_~tmp~3#1); 929403#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 940322#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 940314#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 942248#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 942246#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 942244#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 942241#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 942239#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 729522#L1935-2 [2022-11-16 11:07:35,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:35,757 INFO L85 PathProgramCache]: Analyzing trace with hash 1375762181, now seen corresponding path program 1 times [2022-11-16 11:07:35,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:35,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159227722] [2022-11-16 11:07:35,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:35,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:35,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:35,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:35,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:35,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159227722] [2022-11-16 11:07:35,855 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1159227722] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:35,855 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:35,855 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:07:35,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243142392] [2022-11-16 11:07:35,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:35,856 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:35,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:35,857 INFO L85 PathProgramCache]: Analyzing trace with hash -15239448, now seen corresponding path program 1 times [2022-11-16 11:07:35,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:35,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956273708] [2022-11-16 11:07:35,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:35,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:35,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:35,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:35,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:35,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956273708] [2022-11-16 11:07:35,940 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956273708] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:35,940 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:35,941 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:35,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170420369] [2022-11-16 11:07:35,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:35,942 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:35,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:35,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:07:35,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:07:35,948 INFO L87 Difference]: Start difference. First operand 217152 states and 308717 transitions. cyclomatic complexity: 91597 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:38,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:07:38,343 INFO L93 Difference]: Finished difference Result 417775 states and 592070 transitions. [2022-11-16 11:07:38,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417775 states and 592070 transitions. [2022-11-16 11:07:40,675 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 416496 [2022-11-16 11:07:42,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417775 states to 417775 states and 592070 transitions. [2022-11-16 11:07:42,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 417775 [2022-11-16 11:07:42,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 417775 [2022-11-16 11:07:42,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 417775 states and 592070 transitions. [2022-11-16 11:07:42,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:07:42,428 INFO L218 hiAutomatonCegarLoop]: Abstraction has 417775 states and 592070 transitions. [2022-11-16 11:07:42,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 417775 states and 592070 transitions. [2022-11-16 11:07:47,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 417775 to 417487. [2022-11-16 11:07:47,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 417487 states, 417487 states have (on average 1.417486053457952) internal successors, (591782), 417486 states have internal predecessors, (591782), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:07:49,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417487 states to 417487 states and 591782 transitions. [2022-11-16 11:07:49,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 417487 states and 591782 transitions. [2022-11-16 11:07:49,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:07:49,084 INFO L428 stractBuchiCegarLoop]: Abstraction has 417487 states and 591782 transitions. [2022-11-16 11:07:49,084 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-16 11:07:49,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 417487 states and 591782 transitions. [2022-11-16 11:07:51,176 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 416208 [2022-11-16 11:07:51,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:07:51,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:07:51,179 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:51,179 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:07:51,180 INFO L748 eck$LassoCheckResult]: Stem: 1363204#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~local~0 := 0;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~E_M~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~token~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1363205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1362937#L1898 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1362938#L902 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1364680#L909 assume 1 == ~m_i~0;~m_st~0 := 0; 1364681#L909-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1363123#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1363124#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1363156#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1364122#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1364123#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1364279#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1364280#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1362943#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1362944#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1364337#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1363483#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1363484#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1364202#L974-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1364642#L1286 assume !(0 == ~M_E~0); 1364430#L1286-2 assume !(0 == ~T1_E~0); 1362848#L1291-1 assume !(0 == ~T2_E~0); 1362849#L1296-1 assume !(0 == ~T3_E~0); 1363585#L1301-1 assume !(0 == ~T4_E~0); 1363586#L1306-1 assume !(0 == ~T5_E~0); 1364212#L1311-1 assume !(0 == ~T6_E~0); 1362807#L1316-1 assume !(0 == ~T7_E~0); 1362808#L1321-1 assume !(0 == ~T8_E~0); 1363605#L1326-1 assume !(0 == ~T9_E~0); 1362618#L1331-1 assume !(0 == ~T10_E~0); 1362326#L1336-1 assume !(0 == ~T11_E~0); 1362327#L1341-1 assume !(0 == ~T12_E~0); 1362378#L1346-1 assume !(0 == ~T13_E~0); 1362379#L1351-1 assume !(0 == ~E_M~0); 1362749#L1356-1 assume !(0 == ~E_1~0); 1362750#L1361-1 assume !(0 == ~E_2~0); 1364572#L1366-1 assume !(0 == ~E_3~0); 1362799#L1371-1 assume !(0 == ~E_4~0); 1362800#L1376-1 assume !(0 == ~E_5~0); 1363651#L1381-1 assume !(0 == ~E_6~0); 1363652#L1386-1 assume !(0 == ~E_7~0); 1364625#L1391-1 assume !(0 == ~E_8~0); 1364656#L1396-1 assume !(0 == ~E_9~0); 1363520#L1401-1 assume !(0 == ~E_10~0); 1363521#L1406-1 assume !(0 == ~E_11~0); 1363872#L1411-1 assume !(0 == ~E_12~0); 1363873#L1416-1 assume !(0 == ~E_13~0); 1363440#L1421-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1363268#L635 assume !(1 == ~m_pc~0); 1362398#L635-2 is_master_triggered_~__retres1~0#1 := 0; 1362399#L646 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1362746#L647 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1363403#L1598 assume !(0 != activate_threads_~tmp~1#1); 1362574#L1598-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1362575#L654 assume !(1 == ~t1_pc~0); 1363386#L654-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1364339#L665 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1364619#L666 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1363382#L1606 assume !(0 != activate_threads_~tmp___0~0#1); 1363383#L1606-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1362624#L673 assume !(1 == ~t2_pc~0); 1362626#L673-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1363833#L684 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1363834#L685 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1364694#L1614 assume !(0 != activate_threads_~tmp___1~0#1); 1364707#L1614-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1363462#L692 assume !(1 == ~t3_pc~0); 1363269#L692-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1363270#L703 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1363127#L704 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1363091#L1622 assume !(0 != activate_threads_~tmp___2~0#1); 1363092#L1622-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1362646#L711 assume !(1 == ~t4_pc~0); 1362647#L711-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1364329#L722 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1363624#L723 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1362351#L1630 assume !(0 != activate_threads_~tmp___3~0#1); 1362352#L1630-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1364678#L730 assume !(1 == ~t5_pc~0); 1363760#L730-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1362532#L741 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1362533#L742 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1362655#L1638 assume !(0 != activate_threads_~tmp___4~0#1); 1362656#L1638-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1363006#L749 assume !(1 == ~t6_pc~0); 1362540#L749-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1362541#L760 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1362974#L761 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1362975#L1646 assume !(0 != activate_threads_~tmp___5~0#1); 1363196#L1646-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1362333#L768 assume !(1 == ~t7_pc~0); 1362334#L768-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1363679#L779 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1362567#L780 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1362568#L1654 assume !(0 != activate_threads_~tmp___6~0#1); 1363701#L1654-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1362809#L787 assume !(1 == ~t8_pc~0); 1362810#L787-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1364447#L798 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1364375#L799 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1364376#L1662 assume !(0 != activate_threads_~tmp___7~0#1); 1362376#L1662-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1362377#L806 assume 1 == ~t9_pc~0; 1364155#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1362411#L817 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1362412#L818 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1362657#L1670 assume !(0 != activate_threads_~tmp___8~0#1); 1362658#L1670-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1364132#L825 assume !(1 == ~t10_pc~0); 1364133#L825-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1363640#L836 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1363641#L837 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1362747#L1678 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1362748#L1678-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1363343#L844 assume 1 == ~t11_pc~0; 1363030#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1363031#L855 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1363409#L856 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1363410#L1686 assume !(0 != activate_threads_~tmp___10~0#1); 1364115#L1686-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1364116#L863 assume !(1 == ~t12_pc~0); 1362517#L863-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1362516#L874 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1362736#L875 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1364243#L1694 assume !(0 != activate_threads_~tmp___11~0#1); 1364244#L1694-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1363478#L882 assume 1 == ~t13_pc~0; 1363479#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1363803#L893 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1364509#L894 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1364204#L1702 assume !(0 != activate_threads_~tmp___12~0#1); 1363789#L1702-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1363790#L1434 assume !(1 == ~M_E~0); 1364526#L1434-2 assume !(1 == ~T1_E~0); 1364692#L1439-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1362639#L1444-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1362640#L1449-1 assume !(1 == ~T4_E~0); 1363089#L1454-1 assume !(1 == ~T5_E~0); 1363090#L1459-1 assume !(1 == ~T6_E~0); 1363702#L1464-1 assume !(1 == ~T7_E~0); 1363703#L1469-1 assume !(1 == ~T8_E~0); 1363806#L1474-1 assume !(1 == ~T9_E~0); 1477512#L1479-1 assume !(1 == ~T10_E~0); 1477509#L1484-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1477507#L1489-1 assume !(1 == ~T12_E~0); 1477505#L1494-1 assume !(1 == ~T13_E~0); 1477503#L1499-1 assume !(1 == ~E_M~0); 1477501#L1504-1 assume !(1 == ~E_1~0); 1477499#L1509-1 assume !(1 == ~E_2~0); 1477498#L1514-1 assume !(1 == ~E_3~0); 1477495#L1519-1 assume !(1 == ~E_4~0); 1477493#L1524-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1477491#L1529-1 assume !(1 == ~E_6~0); 1477489#L1534-1 assume !(1 == ~E_7~0); 1477487#L1539-1 assume !(1 == ~E_8~0); 1477485#L1544-1 assume !(1 == ~E_9~0); 1364550#L1549-1 assume !(1 == ~E_10~0); 1364551#L1554-1 assume !(1 == ~E_11~0); 1477304#L1559-1 assume !(1 == ~E_12~0); 1477302#L1564-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1364585#L1569-1 assume { :end_inline_reset_delta_events } true; 1364586#L1935-2 [2022-11-16 11:07:51,180 INFO L750 eck$LassoCheckResult]: Loop: 1364586#L1935-2 assume !false; 1468009#L1936 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1468003#L1261 assume !false; 1468001#L1070 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1462055#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1462047#L1059 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1462043#L1060 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1462040#L1074 assume !(0 != eval_~tmp~0#1); 1462041#L1276 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1484769#L902-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1484767#L1286-3 assume !(0 == ~M_E~0); 1484765#L1286-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1484762#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1484760#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1484758#L1301-3 assume !(0 == ~T4_E~0); 1484756#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1484754#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1484752#L1316-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1484749#L1321-3 assume !(0 == ~T8_E~0); 1484747#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1484745#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1484743#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1484741#L1341-3 assume !(0 == ~T12_E~0); 1484739#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1484736#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1484734#L1356-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1484732#L1361-3 assume !(0 == ~E_2~0); 1484730#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1484728#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1484726#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1484723#L1381-3 assume !(0 == ~E_6~0); 1484721#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1484719#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1484717#L1396-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1484715#L1401-3 assume !(0 == ~E_10~0); 1484713#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1484710#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1484708#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1484706#L1421-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1484704#L635-45 assume !(1 == ~m_pc~0); 1484702#L635-47 is_master_triggered_~__retres1~0#1 := 0; 1484698#L646-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1484696#L647-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1484694#L1598-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1484693#L1598-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1484692#L654-45 assume !(1 == ~t1_pc~0); 1484691#L654-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1484690#L665-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1484689#L666-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1484688#L1606-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1484687#L1606-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1484686#L673-45 assume !(1 == ~t2_pc~0); 1484684#L673-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1484683#L684-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1484682#L685-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1484681#L1614-45 assume !(0 != activate_threads_~tmp___1~0#1); 1484680#L1614-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1484679#L692-45 assume 1 == ~t3_pc~0; 1484678#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1484676#L703-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1484674#L704-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1484671#L1622-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1484670#L1622-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1484669#L711-45 assume !(1 == ~t4_pc~0); 1484668#L711-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1484667#L722-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1484666#L723-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1484665#L1630-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1484664#L1630-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1484663#L730-45 assume !(1 == ~t5_pc~0); 1484662#L730-47 is_transmit5_triggered_~__retres1~5#1 := 0; 1484659#L741-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1484658#L742-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1484657#L1638-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1484656#L1638-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1484655#L749-45 assume !(1 == ~t6_pc~0); 1484654#L749-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1484652#L760-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1484650#L761-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1484648#L1646-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1484646#L1646-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1484644#L768-45 assume !(1 == ~t7_pc~0); 1484642#L768-47 is_transmit7_triggered_~__retres1~7#1 := 0; 1484639#L779-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1484637#L780-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1484635#L1654-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1484633#L1654-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1484631#L787-45 assume !(1 == ~t8_pc~0); 1484629#L787-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1484628#L798-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1484625#L799-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1484623#L1662-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1484621#L1662-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1484619#L806-45 assume 1 == ~t9_pc~0; 1484616#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1484614#L817-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1484610#L818-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1484608#L1670-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1484606#L1670-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1484604#L825-45 assume !(1 == ~t10_pc~0); 1484600#L825-47 is_transmit10_triggered_~__retres1~10#1 := 0; 1484598#L836-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1484596#L837-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1484594#L1678-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1484592#L1678-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1484590#L844-45 assume !(1 == ~t11_pc~0); 1484588#L844-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1484585#L855-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1484583#L856-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1484580#L1686-45 assume !(0 != activate_threads_~tmp___10~0#1); 1484578#L1686-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1484576#L863-45 assume !(1 == ~t12_pc~0); 1484574#L863-47 is_transmit12_triggered_~__retres1~12#1 := 0; 1484571#L874-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1484569#L875-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1484568#L1694-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1484566#L1694-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1484564#L882-45 assume 1 == ~t13_pc~0; 1484562#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1484559#L893-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1484557#L894-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1484554#L1702-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1484552#L1702-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1484550#L1434-3 assume !(1 == ~M_E~0); 1464447#L1434-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1484547#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1463346#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1484544#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1484542#L1454-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1484540#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1484538#L1464-3 assume !(1 == ~T7_E~0); 1484536#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1484534#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1484531#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1484529#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1484527#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1484525#L1494-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1484523#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1484521#L1504-3 assume !(1 == ~E_1~0); 1484518#L1509-3 assume !(1 == ~E_2~0); 1484516#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1484514#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1484512#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1484510#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1484508#L1534-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1484505#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1484503#L1544-3 assume !(1 == ~E_9~0); 1484501#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1463295#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1484498#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1484495#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1484496#L1569-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1484475#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1484465#L1059-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1484461#L1060-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1484458#L1954 assume !(0 == start_simulation_~tmp~3#1); 1484459#L1954-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1736059#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1736050#L1059-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1736047#L1060-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1736045#L1909 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1736043#L1916 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1736041#L1917 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1736039#L1967 assume !(0 != start_simulation_~tmp___0~1#1); 1364586#L1935-2 [2022-11-16 11:07:51,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:51,181 INFO L85 PathProgramCache]: Analyzing trace with hash 1753404998, now seen corresponding path program 1 times [2022-11-16 11:07:51,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:51,182 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442960002] [2022-11-16 11:07:51,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:51,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:51,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:51,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:51,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:51,277 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442960002] [2022-11-16 11:07:51,277 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1442960002] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:51,277 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:51,278 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:51,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1968809157] [2022-11-16 11:07:51,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:51,278 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:07:51,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:07:51,279 INFO L85 PathProgramCache]: Analyzing trace with hash -452799067, now seen corresponding path program 1 times [2022-11-16 11:07:51,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:07:51,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012170244] [2022-11-16 11:07:51,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:07:51,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:07:51,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:07:51,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:07:51,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:07:51,342 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2012170244] [2022-11-16 11:07:51,342 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2012170244] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:07:51,342 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:07:51,342 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:07:51,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1887168284] [2022-11-16 11:07:51,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:07:51,343 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:07:51,344 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:07:51,344 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:07:51,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:07:51,345 INFO L87 Difference]: Start difference. First operand 417487 states and 591782 transitions. cyclomatic complexity: 174359 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)