./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:36:39,464 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:36:39,468 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:36:39,496 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:36:39,497 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:36:39,501 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:36:39,504 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:36:39,507 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:36:39,509 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:36:39,510 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:36:39,511 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:36:39,512 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:36:39,513 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:36:39,523 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:36:39,525 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:36:39,527 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:36:39,529 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:36:39,530 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:36:39,532 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:36:39,535 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:36:39,540 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:36:39,541 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:36:39,542 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:36:39,543 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:36:39,546 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:36:39,546 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:36:39,546 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:36:39,547 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:36:39,548 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:36:39,549 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:36:39,549 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:36:39,550 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:36:39,550 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:36:39,551 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:36:39,552 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:36:39,552 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:36:39,553 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:36:39,553 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:36:39,554 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:36:39,555 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:36:39,555 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:36:39,556 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 11:36:39,580 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:36:39,581 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:36:39,581 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:36:39,581 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:36:39,582 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:36:39,583 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:36:39,583 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:36:39,583 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 11:36:39,583 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 11:36:39,584 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 11:36:39,584 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 11:36:39,584 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 11:36:39,584 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 11:36:39,584 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:36:39,585 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 11:36:39,585 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 11:36:39,585 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:36:39,585 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 11:36:39,585 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:36:39,585 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 11:36:39,586 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 11:36:39,586 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 11:36:39,586 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 11:36:39,586 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:36:39,586 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 11:36:39,586 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:36:39,587 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 11:36:39,587 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:36:39,587 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:36:39,587 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:36:39,587 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:36:39,588 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 11:36:39,589 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2022-11-16 11:36:39,895 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:36:39,916 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:36:39,919 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:36:39,920 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:36:39,921 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:36:39,923 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/transmitter.01.cil.c [2022-11-16 11:36:39,984 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/data/e8ef92cea/d3d2071d48c7407aa3b1f28ee14a75f7/FLAG4a3953057 [2022-11-16 11:36:40,402 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:36:40,406 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/sv-benchmarks/c/systemc/transmitter.01.cil.c [2022-11-16 11:36:40,421 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/data/e8ef92cea/d3d2071d48c7407aa3b1f28ee14a75f7/FLAG4a3953057 [2022-11-16 11:36:40,796 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/data/e8ef92cea/d3d2071d48c7407aa3b1f28ee14a75f7 [2022-11-16 11:36:40,799 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:36:40,800 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:36:40,802 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:36:40,802 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:36:40,812 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:36:40,813 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:36:40" (1/1) ... [2022-11-16 11:36:40,815 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@67710845 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:40, skipping insertion in model container [2022-11-16 11:36:40,815 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:36:40" (1/1) ... [2022-11-16 11:36:40,829 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:36:40,871 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:36:41,032 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/sv-benchmarks/c/systemc/transmitter.01.cil.c[706,719] [2022-11-16 11:36:41,072 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:36:41,082 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:36:41,095 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/sv-benchmarks/c/systemc/transmitter.01.cil.c[706,719] [2022-11-16 11:36:41,115 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:36:41,130 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:36:41,131 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41 WrapperNode [2022-11-16 11:36:41,131 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:36:41,132 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:36:41,133 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:36:41,133 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:36:41,141 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,149 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,179 INFO L138 Inliner]: procedures = 30, calls = 33, calls flagged for inlining = 28, calls inlined = 34, statements flattened = 357 [2022-11-16 11:36:41,181 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:36:41,182 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:36:41,182 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:36:41,183 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:36:41,191 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,192 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,204 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,212 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,217 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,235 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,237 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,238 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,241 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:36:41,242 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:36:41,249 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:36:41,249 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:36:41,250 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (1/1) ... [2022-11-16 11:36:41,258 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:36:41,269 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:36:41,292 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:36:41,315 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 11:36:41,335 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 11:36:41,336 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 11:36:41,336 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:36:41,336 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:36:41,410 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:36:41,412 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:36:41,864 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:36:41,880 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:36:41,881 INFO L300 CfgBuilder]: Removed 5 assume(true) statements. [2022-11-16 11:36:41,883 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:36:41 BoogieIcfgContainer [2022-11-16 11:36:41,883 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:36:41,890 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 11:36:41,890 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 11:36:41,894 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 11:36:41,895 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:36:41,895 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 11:36:40" (1/3) ... [2022-11-16 11:36:41,896 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ddbb013 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:36:41, skipping insertion in model container [2022-11-16 11:36:41,896 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:36:41,896 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:36:41" (2/3) ... [2022-11-16 11:36:41,896 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ddbb013 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:36:41, skipping insertion in model container [2022-11-16 11:36:41,896 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:36:41,897 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:36:41" (3/3) ... [2022-11-16 11:36:41,898 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2022-11-16 11:36:41,955 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 11:36:41,955 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 11:36:41,956 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 11:36:41,956 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 11:36:41,956 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 11:36:41,956 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 11:36:41,956 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 11:36:41,957 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 11:36:41,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:41,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2022-11-16 11:36:41,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:36:41,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:36:42,007 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:42,007 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:42,007 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 11:36:42,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:42,019 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2022-11-16 11:36:42,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:36:42,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:36:42,021 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:42,022 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:42,037 INFO L748 eck$LassoCheckResult]: Stem: 116#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t1_st~0 := 0;~t1_pc~0 := 0; 45#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 14#L367true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 91#L154true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11#L161true assume !(1 == ~m_i~0);~m_st~0 := 2; 6#L161-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 77#L166-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86#L250true assume !(0 == ~M_E~0); 104#L250-2true assume !(0 == ~T1_E~0); 37#L255-1true assume !(0 == ~E_1~0); 78#L260-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51#L115true assume !(1 == ~m_pc~0); 55#L115-2true is_master_triggered_~__retres1~0#1 := 0; 66#L126true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 120#L127true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 62#L300true assume !(0 != activate_threads_~tmp~1#1); 103#L300-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118#L134true assume 1 == ~t1_pc~0; 105#L135true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53#L145true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84#L146true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10#L308true assume !(0 != activate_threads_~tmp___0~0#1); 58#L308-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56#L273true assume !(1 == ~M_E~0); 108#L273-2true assume !(1 == ~T1_E~0); 98#L278-1true assume !(1 == ~E_1~0); 68#L283-1true assume { :end_inline_reset_delta_events } true; 54#L404-2true [2022-11-16 11:36:42,042 INFO L750 eck$LassoCheckResult]: Loop: 54#L404-2true assume !false; 79#L405true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42#L225true assume !true; 24#L240true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 113#L154-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117#L250-3true assume 0 == ~M_E~0;~M_E~0 := 1; 95#L250-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 100#L255-3true assume 0 == ~E_1~0;~E_1~0 := 1; 7#L260-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47#L115-6true assume 1 == ~m_pc~0; 112#L116-2true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 132#L126-2true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57#L127-2true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 71#L300-6true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 114#L300-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130#L134-6true assume 1 == ~t1_pc~0; 44#L135-2true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50#L145-2true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111#L146-2true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 48#L308-6true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8#L308-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126#L273-3true assume 1 == ~M_E~0;~M_E~0 := 2; 43#L273-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 34#L278-3true assume 1 == ~E_1~0;~E_1~0 := 2; 92#L283-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 74#L179-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 109#L191-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 131#L192-1true start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 18#L423true assume !(0 == start_simulation_~tmp~3#1); 17#L423-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21#L179-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 69#L191-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 93#L192-2true stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 13#L378true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15#L385true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75#L386true start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 41#L436true assume !(0 != start_simulation_~tmp___0~1#1); 54#L404-2true [2022-11-16 11:36:42,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:42,054 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2022-11-16 11:36:42,062 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:42,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940996616] [2022-11-16 11:36:42,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:42,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:42,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:42,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:42,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:42,346 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940996616] [2022-11-16 11:36:42,347 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1940996616] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:36:42,347 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:36:42,347 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:36:42,349 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [865319938] [2022-11-16 11:36:42,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:36:42,354 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:36:42,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:42,359 INFO L85 PathProgramCache]: Analyzing trace with hash 591500370, now seen corresponding path program 1 times [2022-11-16 11:36:42,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:42,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178080569] [2022-11-16 11:36:42,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:42,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:42,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:42,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:42,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:42,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178080569] [2022-11-16 11:36:42,419 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178080569] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:36:42,419 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:36:42,419 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:36:42,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471886851] [2022-11-16 11:36:42,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:36:42,421 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:36:42,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:36:42,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:36:42,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:36:42,462 INFO L87 Difference]: Start difference. First operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:42,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:36:42,511 INFO L93 Difference]: Finished difference Result 132 states and 188 transitions. [2022-11-16 11:36:42,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132 states and 188 transitions. [2022-11-16 11:36:42,526 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-11-16 11:36:42,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132 states to 126 states and 182 transitions. [2022-11-16 11:36:42,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126 [2022-11-16 11:36:42,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126 [2022-11-16 11:36:42,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126 states and 182 transitions. [2022-11-16 11:36:42,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:36:42,546 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126 states and 182 transitions. [2022-11-16 11:36:42,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states and 182 transitions. [2022-11-16 11:36:42,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 126. [2022-11-16 11:36:42,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126 states, 126 states have (on average 1.4444444444444444) internal successors, (182), 125 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:42,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 182 transitions. [2022-11-16 11:36:42,580 INFO L240 hiAutomatonCegarLoop]: Abstraction has 126 states and 182 transitions. [2022-11-16 11:36:42,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:36:42,601 INFO L428 stractBuchiCegarLoop]: Abstraction has 126 states and 182 transitions. [2022-11-16 11:36:42,602 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 11:36:42,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126 states and 182 transitions. [2022-11-16 11:36:42,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-11-16 11:36:42,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:36:42,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:36:42,605 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:42,605 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:42,606 INFO L748 eck$LassoCheckResult]: Stem: 398#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t1_st~0 := 0;~t1_pc~0 := 0; 341#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 293#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 294#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 287#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 278#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 279#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 375#L250 assume !(0 == ~M_E~0); 382#L250-2 assume !(0 == ~T1_E~0); 331#L255-1 assume !(0 == ~E_1~0); 332#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 347#L115 assume !(1 == ~m_pc~0); 318#L115-2 is_master_triggered_~__retres1~0#1 := 0; 319#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 362#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 359#L300 assume !(0 != activate_threads_~tmp~1#1); 360#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 391#L134 assume 1 == ~t1_pc~0; 392#L135 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 349#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 285#L308 assume !(0 != activate_threads_~tmp___0~0#1); 286#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 352#L273 assume !(1 == ~M_E~0); 353#L273-2 assume !(1 == ~T1_E~0); 389#L278-1 assume !(1 == ~E_1~0); 365#L283-1 assume { :end_inline_reset_delta_events } true; 337#L404-2 [2022-11-16 11:36:42,606 INFO L750 eck$LassoCheckResult]: Loop: 337#L404-2 assume !false; 351#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 301#L225 assume !false; 338#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 379#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 321#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 374#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 329#L206 assume !(0 != eval_~tmp~0#1); 310#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 311#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 396#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 387#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 388#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 280#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281#L115-6 assume 1 == ~m_pc~0; 342#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 395#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 354#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 355#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 368#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 397#L134-6 assume !(1 == ~t1_pc~0); 322#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 323#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 346#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 344#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 282#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 283#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 339#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 325#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 326#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 371#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 372#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 393#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 298#L423 assume !(0 == start_simulation_~tmp~3#1); 296#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 297#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 304#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 366#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 291#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 292#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 295#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 336#L436 assume !(0 != start_simulation_~tmp___0~1#1); 337#L404-2 [2022-11-16 11:36:42,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:42,607 INFO L85 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2022-11-16 11:36:42,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:42,608 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276213136] [2022-11-16 11:36:42,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:42,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:42,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:42,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:42,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:42,778 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276213136] [2022-11-16 11:36:42,778 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276213136] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:36:42,778 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:36:42,778 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:36:42,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900497487] [2022-11-16 11:36:42,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:36:42,779 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:36:42,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:42,780 INFO L85 PathProgramCache]: Analyzing trace with hash -445215682, now seen corresponding path program 1 times [2022-11-16 11:36:42,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:42,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867497441] [2022-11-16 11:36:42,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:42,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:42,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:42,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:42,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:42,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867497441] [2022-11-16 11:36:42,863 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867497441] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:36:42,863 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:36:42,863 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:36:42,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34021856] [2022-11-16 11:36:42,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:36:42,865 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:36:42,865 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:36:42,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:36:42,868 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:36:42,869 INFO L87 Difference]: Start difference. First operand 126 states and 182 transitions. cyclomatic complexity: 57 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:43,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:36:43,025 INFO L93 Difference]: Finished difference Result 304 states and 423 transitions. [2022-11-16 11:36:43,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304 states and 423 transitions. [2022-11-16 11:36:43,029 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 254 [2022-11-16 11:36:43,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304 states to 304 states and 423 transitions. [2022-11-16 11:36:43,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304 [2022-11-16 11:36:43,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304 [2022-11-16 11:36:43,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304 states and 423 transitions. [2022-11-16 11:36:43,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:36:43,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 304 states and 423 transitions. [2022-11-16 11:36:43,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states and 423 transitions. [2022-11-16 11:36:43,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 284. [2022-11-16 11:36:43,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4049295774647887) internal successors, (399), 283 states have internal predecessors, (399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:43,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 399 transitions. [2022-11-16 11:36:43,058 INFO L240 hiAutomatonCegarLoop]: Abstraction has 284 states and 399 transitions. [2022-11-16 11:36:43,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:36:43,059 INFO L428 stractBuchiCegarLoop]: Abstraction has 284 states and 399 transitions. [2022-11-16 11:36:43,060 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 11:36:43,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 399 transitions. [2022-11-16 11:36:43,065 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 252 [2022-11-16 11:36:43,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:36:43,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:36:43,067 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:43,067 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:43,067 INFO L748 eck$LassoCheckResult]: Stem: 853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t1_st~0 := 0;~t1_pc~0 := 0; 783#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 735#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 736#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 729#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 720#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 721#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 824#L250 assume !(0 == ~M_E~0); 834#L250-2 assume !(0 == ~T1_E~0); 773#L255-1 assume !(0 == ~E_1~0); 774#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 789#L115 assume !(1 == ~m_pc~0); 790#L115-2 is_master_triggered_~__retres1~0#1 := 0; 794#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 808#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 804#L300 assume !(0 != activate_threads_~tmp~1#1); 805#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 844#L134 assume !(1 == ~t1_pc~0); 802#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 791#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 792#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 727#L308 assume !(0 != activate_threads_~tmp___0~0#1); 728#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 795#L273 assume !(1 == ~M_E~0); 796#L273-2 assume !(1 == ~T1_E~0); 840#L278-1 assume !(1 == ~E_1~0); 812#L283-1 assume { :end_inline_reset_delta_events } true; 813#L404-2 [2022-11-16 11:36:43,067 INFO L750 eck$LassoCheckResult]: Loop: 813#L404-2 assume !false; 969#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 966#L225 assume !false; 964#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 857#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 761#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 823#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 959#L206 assume !(0 != eval_~tmp~0#1); 753#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 754#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 851#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 854#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 842#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 722#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 723#L115-6 assume !(1 == ~m_pc~0); 784#L115-8 is_master_triggered_~__retres1~0#1 := 0; 856#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 797#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 798#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 815#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 852#L134-6 assume !(1 == ~t1_pc~0); 861#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 985#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 982#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 980#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 978#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 977#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 976#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 974#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 973#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 818#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 819#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 846#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 740#L423 assume !(0 == start_simulation_~tmp~3#1); 742#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 983#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 981#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 979#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 975#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 972#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 821#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 822#L436 assume !(0 != start_simulation_~tmp___0~1#1); 813#L404-2 [2022-11-16 11:36:43,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:43,068 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2022-11-16 11:36:43,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:43,069 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103971923] [2022-11-16 11:36:43,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:43,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:43,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,081 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:43,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:36:43,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:43,112 INFO L85 PathProgramCache]: Analyzing trace with hash -753654691, now seen corresponding path program 1 times [2022-11-16 11:36:43,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:43,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181974948] [2022-11-16 11:36:43,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:43,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:43,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:43,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:43,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:43,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181974948] [2022-11-16 11:36:43,183 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [181974948] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:36:43,183 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:36:43,184 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:36:43,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245184586] [2022-11-16 11:36:43,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:36:43,184 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:36:43,185 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:36:43,185 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:36:43,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:36:43,186 INFO L87 Difference]: Start difference. First operand 284 states and 399 transitions. cyclomatic complexity: 117 Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:43,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:36:43,276 INFO L93 Difference]: Finished difference Result 478 states and 654 transitions. [2022-11-16 11:36:43,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 654 transitions. [2022-11-16 11:36:43,281 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 441 [2022-11-16 11:36:43,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 654 transitions. [2022-11-16 11:36:43,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2022-11-16 11:36:43,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2022-11-16 11:36:43,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 654 transitions. [2022-11-16 11:36:43,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:36:43,288 INFO L218 hiAutomatonCegarLoop]: Abstraction has 478 states and 654 transitions. [2022-11-16 11:36:43,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 654 transitions. [2022-11-16 11:36:43,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 293. [2022-11-16 11:36:43,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 293 states, 293 states have (on average 1.3924914675767919) internal successors, (408), 292 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:43,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 293 states to 293 states and 408 transitions. [2022-11-16 11:36:43,303 INFO L240 hiAutomatonCegarLoop]: Abstraction has 293 states and 408 transitions. [2022-11-16 11:36:43,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 11:36:43,304 INFO L428 stractBuchiCegarLoop]: Abstraction has 293 states and 408 transitions. [2022-11-16 11:36:43,305 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 11:36:43,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 293 states and 408 transitions. [2022-11-16 11:36:43,307 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 261 [2022-11-16 11:36:43,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:36:43,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:36:43,308 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:43,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:43,309 INFO L748 eck$LassoCheckResult]: Stem: 1643#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t1_st~0 := 0;~t1_pc~0 := 0; 1564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1513#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1514#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1507#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1498#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1499#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1608#L250 assume !(0 == ~M_E~0); 1620#L250-2 assume !(0 == ~T1_E~0); 1552#L255-1 assume !(0 == ~E_1~0); 1553#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1572#L115 assume !(1 == ~m_pc~0); 1573#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1577#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1591#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1587#L300 assume !(0 != activate_threads_~tmp~1#1); 1588#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1631#L134 assume !(1 == ~t1_pc~0); 1582#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1574#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1575#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1505#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1506#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1578#L273 assume !(1 == ~M_E~0); 1579#L273-2 assume !(1 == ~T1_E~0); 1627#L278-1 assume !(1 == ~E_1~0); 1594#L283-1 assume { :end_inline_reset_delta_events } true; 1595#L404-2 [2022-11-16 11:36:43,309 INFO L750 eck$LassoCheckResult]: Loop: 1595#L404-2 assume !false; 1751#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1744#L225 assume !false; 1694#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1690#L179 assume !(0 == ~m_st~0); 1685#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 1682#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1679#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1676#L206 assume !(0 != eval_~tmp~0#1); 1674#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1672#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1670#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1668#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1665#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1666#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1565#L115-6 assume !(1 == ~m_pc~0); 1566#L115-8 is_master_triggered_~__retres1~0#1 := 0; 1645#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1728#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1599#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1600#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1649#L134-6 assume !(1 == ~t1_pc~0); 1543#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1544#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1569#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1636#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1725#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1724#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1560#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1546#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1547#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1604#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1605#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1634#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1518#L423 assume !(0 == start_simulation_~tmp~3#1); 1520#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1763#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1762#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1760#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1758#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1756#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1754#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1752#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1595#L404-2 [2022-11-16 11:36:43,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:43,310 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2022-11-16 11:36:43,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:43,310 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416995630] [2022-11-16 11:36:43,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:43,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:43,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,321 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:43,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,349 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:36:43,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:43,350 INFO L85 PathProgramCache]: Analyzing trace with hash -682345966, now seen corresponding path program 1 times [2022-11-16 11:36:43,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:43,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397624762] [2022-11-16 11:36:43,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:43,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:43,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:43,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:43,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:43,484 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397624762] [2022-11-16 11:36:43,484 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1397624762] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:36:43,484 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:36:43,485 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:36:43,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242096941] [2022-11-16 11:36:43,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:36:43,485 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:36:43,486 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:36:43,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:36:43,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:36:43,487 INFO L87 Difference]: Start difference. First operand 293 states and 408 transitions. cyclomatic complexity: 117 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:43,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:36:43,610 INFO L93 Difference]: Finished difference Result 623 states and 857 transitions. [2022-11-16 11:36:43,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 623 states and 857 transitions. [2022-11-16 11:36:43,617 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 591 [2022-11-16 11:36:43,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 623 states to 623 states and 857 transitions. [2022-11-16 11:36:43,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 623 [2022-11-16 11:36:43,622 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 623 [2022-11-16 11:36:43,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 623 states and 857 transitions. [2022-11-16 11:36:43,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:36:43,624 INFO L218 hiAutomatonCegarLoop]: Abstraction has 623 states and 857 transitions. [2022-11-16 11:36:43,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 623 states and 857 transitions. [2022-11-16 11:36:43,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 623 to 311. [2022-11-16 11:36:43,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311 states, 311 states have (on average 1.360128617363344) internal successors, (423), 310 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:43,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 423 transitions. [2022-11-16 11:36:43,661 INFO L240 hiAutomatonCegarLoop]: Abstraction has 311 states and 423 transitions. [2022-11-16 11:36:43,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 11:36:43,663 INFO L428 stractBuchiCegarLoop]: Abstraction has 311 states and 423 transitions. [2022-11-16 11:36:43,665 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 11:36:43,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 311 states and 423 transitions. [2022-11-16 11:36:43,668 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 279 [2022-11-16 11:36:43,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:36:43,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:36:43,669 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:43,669 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:43,670 INFO L748 eck$LassoCheckResult]: Stem: 2561#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t1_st~0 := 0;~t1_pc~0 := 0; 2492#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2442#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2443#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2436#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2427#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2428#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2533#L250 assume !(0 == ~M_E~0); 2544#L250-2 assume !(0 == ~T1_E~0); 2480#L255-1 assume !(0 == ~E_1~0); 2481#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2500#L115 assume !(1 == ~m_pc~0); 2501#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2505#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2518#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2515#L300 assume !(0 != activate_threads_~tmp~1#1); 2516#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2552#L134 assume !(1 == ~t1_pc~0); 2513#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2502#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2503#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2434#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2435#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2506#L273 assume !(1 == ~M_E~0); 2507#L273-2 assume !(1 == ~T1_E~0); 2548#L278-1 assume !(1 == ~E_1~0); 2522#L283-1 assume { :end_inline_reset_delta_events } true; 2523#L404-2 [2022-11-16 11:36:43,670 INFO L750 eck$LassoCheckResult]: Loop: 2523#L404-2 assume !false; 2604#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2602#L225 assume !false; 2601#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2599#L179 assume !(0 == ~m_st~0); 2600#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2598#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2596#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2594#L206 assume !(0 != eval_~tmp~0#1); 2592#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2590#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2587#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2584#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2582#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2579#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2493#L115-6 assume !(1 == ~m_pc~0); 2494#L115-8 is_master_triggered_~__retres1~0#1 := 0; 2647#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2646#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2645#L300-6 assume !(0 != activate_threads_~tmp~1#1); 2644#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2643#L134-6 assume !(1 == ~t1_pc~0); 2641#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2639#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2637#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2635#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2633#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2631#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2629#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2627#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2625#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2622#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2620#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2618#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2615#L423 assume !(0 == start_simulation_~tmp~3#1); 2613#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2611#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2610#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2609#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2608#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2607#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2606#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2605#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2523#L404-2 [2022-11-16 11:36:43,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:43,676 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2022-11-16 11:36:43,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:43,676 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941293345] [2022-11-16 11:36:43,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:43,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:43,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,685 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:43,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,711 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:36:43,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:43,713 INFO L85 PathProgramCache]: Analyzing trace with hash -816359472, now seen corresponding path program 1 times [2022-11-16 11:36:43,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:43,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479800148] [2022-11-16 11:36:43,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:43,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:43,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:43,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:43,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:43,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1479800148] [2022-11-16 11:36:43,750 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1479800148] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:36:43,751 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:36:43,751 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:36:43,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791092414] [2022-11-16 11:36:43,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:36:43,752 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:36:43,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:36:43,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:36:43,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:36:43,763 INFO L87 Difference]: Start difference. First operand 311 states and 423 transitions. cyclomatic complexity: 114 Second operand has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:43,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:36:43,803 INFO L93 Difference]: Finished difference Result 460 states and 611 transitions. [2022-11-16 11:36:43,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 460 states and 611 transitions. [2022-11-16 11:36:43,808 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 426 [2022-11-16 11:36:43,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 460 states to 460 states and 611 transitions. [2022-11-16 11:36:43,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 460 [2022-11-16 11:36:43,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 460 [2022-11-16 11:36:43,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 460 states and 611 transitions. [2022-11-16 11:36:43,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:36:43,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 460 states and 611 transitions. [2022-11-16 11:36:43,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states and 611 transitions. [2022-11-16 11:36:43,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 439. [2022-11-16 11:36:43,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 439 states, 439 states have (on average 1.3348519362186788) internal successors, (586), 438 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:43,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 439 states to 439 states and 586 transitions. [2022-11-16 11:36:43,829 INFO L240 hiAutomatonCegarLoop]: Abstraction has 439 states and 586 transitions. [2022-11-16 11:36:43,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:36:43,833 INFO L428 stractBuchiCegarLoop]: Abstraction has 439 states and 586 transitions. [2022-11-16 11:36:43,833 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 11:36:43,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 439 states and 586 transitions. [2022-11-16 11:36:43,836 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 405 [2022-11-16 11:36:43,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:36:43,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:36:43,838 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:43,838 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:43,839 INFO L748 eck$LassoCheckResult]: Stem: 3337#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t1_st~0 := 0;~t1_pc~0 := 0; 3268#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3219#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3220#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3213#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 3204#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3205#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3304#L250 assume !(0 == ~M_E~0); 3314#L250-2 assume !(0 == ~T1_E~0); 3256#L255-1 assume !(0 == ~E_1~0); 3257#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3273#L115 assume !(1 == ~m_pc~0); 3274#L115-2 is_master_triggered_~__retres1~0#1 := 0; 3278#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3290#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3286#L300 assume !(0 != activate_threads_~tmp~1#1); 3287#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3327#L134 assume !(1 == ~t1_pc~0); 3285#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3275#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3276#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3211#L308 assume !(0 != activate_threads_~tmp___0~0#1); 3212#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3279#L273 assume !(1 == ~M_E~0); 3280#L273-2 assume !(1 == ~T1_E~0); 3322#L278-1 assume !(1 == ~E_1~0); 3294#L283-1 assume { :end_inline_reset_delta_events } true; 3295#L404-2 assume !false; 3541#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3539#L225 [2022-11-16 11:36:43,840 INFO L750 eck$LassoCheckResult]: Loop: 3539#L225 assume !false; 3538#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3536#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3534#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3532#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3530#L206 assume 0 != eval_~tmp~0#1; 3528#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 3525#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 3526#L211 assume !(0 == ~t1_st~0); 3539#L225 [2022-11-16 11:36:43,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:43,841 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 1 times [2022-11-16 11:36:43,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:43,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508377170] [2022-11-16 11:36:43,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:43,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:43,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,850 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:43,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,870 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:36:43,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:43,871 INFO L85 PathProgramCache]: Analyzing trace with hash 438949112, now seen corresponding path program 1 times [2022-11-16 11:36:43,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:43,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574440308] [2022-11-16 11:36:43,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:43,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:43,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,876 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:43,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:43,880 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:36:43,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:43,881 INFO L85 PathProgramCache]: Analyzing trace with hash -1724815409, now seen corresponding path program 1 times [2022-11-16 11:36:43,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:43,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948594329] [2022-11-16 11:36:43,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:43,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:43,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:43,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:43,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:43,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948594329] [2022-11-16 11:36:43,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948594329] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:36:43,969 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:36:43,969 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:36:43,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582695263] [2022-11-16 11:36:43,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:36:44,053 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:36:44,053 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:36:44,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:36:44,054 INFO L87 Difference]: Start difference. First operand 439 states and 586 transitions. cyclomatic complexity: 150 Second operand has 3 states, 2 states have (on average 19.0) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:44,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:36:44,090 INFO L93 Difference]: Finished difference Result 765 states and 1008 transitions. [2022-11-16 11:36:44,090 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 765 states and 1008 transitions. [2022-11-16 11:36:44,096 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 665 [2022-11-16 11:36:44,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 765 states to 765 states and 1008 transitions. [2022-11-16 11:36:44,106 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 765 [2022-11-16 11:36:44,107 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 765 [2022-11-16 11:36:44,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 765 states and 1008 transitions. [2022-11-16 11:36:44,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:36:44,109 INFO L218 hiAutomatonCegarLoop]: Abstraction has 765 states and 1008 transitions. [2022-11-16 11:36:44,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 765 states and 1008 transitions. [2022-11-16 11:36:44,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 765 to 690. [2022-11-16 11:36:44,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 690 states, 690 states have (on average 1.3333333333333333) internal successors, (920), 689 states have internal predecessors, (920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:44,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 920 transitions. [2022-11-16 11:36:44,123 INFO L240 hiAutomatonCegarLoop]: Abstraction has 690 states and 920 transitions. [2022-11-16 11:36:44,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:36:44,125 INFO L428 stractBuchiCegarLoop]: Abstraction has 690 states and 920 transitions. [2022-11-16 11:36:44,125 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 11:36:44,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 920 transitions. [2022-11-16 11:36:44,129 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 616 [2022-11-16 11:36:44,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:36:44,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:36:44,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:44,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:44,133 INFO L748 eck$LassoCheckResult]: Stem: 4567#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t1_st~0 := 0;~t1_pc~0 := 0; 4481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4433#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4434#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4427#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 4416#L161-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 4417#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4537#L250 assume !(0 == ~M_E~0); 4538#L250-2 assume !(0 == ~T1_E~0); 4468#L255-1 assume !(0 == ~E_1~0); 4469#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4489#L115 assume !(1 == ~m_pc~0); 4490#L115-2 is_master_triggered_~__retres1~0#1 := 0; 4509#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4510#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4505#L300 assume !(0 != activate_threads_~tmp~1#1); 4506#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4570#L134 assume !(1 == ~t1_pc~0); 4571#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4491#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4492#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4424#L308 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4425#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4500#L273 assume !(1 == ~M_E~0); 4556#L273-2 assume !(1 == ~T1_E~0); 4557#L278-1 assume !(1 == ~E_1~0); 4514#L283-1 assume { :end_inline_reset_delta_events } true; 4515#L404-2 assume !false; 5101#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4531#L225 [2022-11-16 11:36:44,133 INFO L750 eck$LassoCheckResult]: Loop: 4531#L225 assume !false; 5098#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5097#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5095#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5092#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5089#L206 assume 0 != eval_~tmp~0#1; 5086#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4577#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 4578#L211 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4529#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 4531#L225 [2022-11-16 11:36:44,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:44,134 INFO L85 PathProgramCache]: Analyzing trace with hash -1113894070, now seen corresponding path program 1 times [2022-11-16 11:36:44,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:44,135 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179596302] [2022-11-16 11:36:44,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:44,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:44,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:36:44,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:36:44,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:36:44,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179596302] [2022-11-16 11:36:44,173 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179596302] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:36:44,173 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:36:44,173 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:36:44,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835561199] [2022-11-16 11:36:44,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:36:44,174 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:36:44,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:44,176 INFO L85 PathProgramCache]: Analyzing trace with hash 722519635, now seen corresponding path program 1 times [2022-11-16 11:36:44,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:44,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448171714] [2022-11-16 11:36:44,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:44,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:44,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:44,183 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:44,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:44,198 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:36:44,315 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:36:44,315 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:36:44,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:36:44,316 INFO L87 Difference]: Start difference. First operand 690 states and 920 transitions. cyclomatic complexity: 234 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:44,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:36:44,324 INFO L93 Difference]: Finished difference Result 577 states and 772 transitions. [2022-11-16 11:36:44,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 577 states and 772 transitions. [2022-11-16 11:36:44,328 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 543 [2022-11-16 11:36:44,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 577 states to 577 states and 772 transitions. [2022-11-16 11:36:44,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 577 [2022-11-16 11:36:44,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 577 [2022-11-16 11:36:44,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 577 states and 772 transitions. [2022-11-16 11:36:44,334 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:36:44,334 INFO L218 hiAutomatonCegarLoop]: Abstraction has 577 states and 772 transitions. [2022-11-16 11:36:44,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577 states and 772 transitions. [2022-11-16 11:36:44,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577 to 577. [2022-11-16 11:36:44,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 577 states, 577 states have (on average 1.3379549393414212) internal successors, (772), 576 states have internal predecessors, (772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:36:44,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 577 states to 577 states and 772 transitions. [2022-11-16 11:36:44,345 INFO L240 hiAutomatonCegarLoop]: Abstraction has 577 states and 772 transitions. [2022-11-16 11:36:44,346 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:36:44,348 INFO L428 stractBuchiCegarLoop]: Abstraction has 577 states and 772 transitions. [2022-11-16 11:36:44,348 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 11:36:44,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 577 states and 772 transitions. [2022-11-16 11:36:44,352 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 543 [2022-11-16 11:36:44,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:36:44,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:36:44,354 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:44,354 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:36:44,356 INFO L748 eck$LassoCheckResult]: Stem: 5825#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t1_st~0 := 0;~t1_pc~0 := 0; 5752#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 5704#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5705#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5698#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 5689#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5690#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5793#L250 assume !(0 == ~M_E~0); 5804#L250-2 assume !(0 == ~T1_E~0); 5739#L255-1 assume !(0 == ~E_1~0); 5740#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5762#L115 assume !(1 == ~m_pc~0); 5763#L115-2 is_master_triggered_~__retres1~0#1 := 0; 5767#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5779#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5775#L300 assume !(0 != activate_threads_~tmp~1#1); 5776#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5815#L134 assume !(1 == ~t1_pc~0); 5772#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5764#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5765#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5696#L308 assume !(0 != activate_threads_~tmp___0~0#1); 5697#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5768#L273 assume !(1 == ~M_E~0); 5769#L273-2 assume !(1 == ~T1_E~0); 5808#L278-1 assume !(1 == ~E_1~0); 5782#L283-1 assume { :end_inline_reset_delta_events } true; 5783#L404-2 assume !false; 6088#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6086#L225 [2022-11-16 11:36:44,356 INFO L750 eck$LassoCheckResult]: Loop: 6086#L225 assume !false; 6085#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6084#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6083#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6082#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6081#L206 assume 0 != eval_~tmp~0#1; 6080#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 6078#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 6079#L211 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 6087#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 6086#L225 [2022-11-16 11:36:44,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:44,357 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 2 times [2022-11-16 11:36:44,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:44,357 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710260986] [2022-11-16 11:36:44,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:44,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:44,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:44,364 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:44,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:44,371 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:36:44,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:44,372 INFO L85 PathProgramCache]: Analyzing trace with hash 722519635, now seen corresponding path program 2 times [2022-11-16 11:36:44,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:44,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448015310] [2022-11-16 11:36:44,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:44,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:44,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:44,376 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:44,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:44,380 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:36:44,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:36:44,380 INFO L85 PathProgramCache]: Analyzing trace with hash -1929671076, now seen corresponding path program 1 times [2022-11-16 11:36:44,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:36:44,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468007761] [2022-11-16 11:36:44,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:36:44,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:36:44,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:44,388 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:44,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:44,409 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:36:45,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:45,030 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:36:45,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:36:45,143 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.11 11:36:45 BoogieIcfgContainer [2022-11-16 11:36:45,143 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-16 11:36:45,143 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-16 11:36:45,143 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-16 11:36:45,144 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-16 11:36:45,144 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:36:41" (3/4) ... [2022-11-16 11:36:45,147 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-16 11:36:45,225 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/witness.graphml [2022-11-16 11:36:45,227 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-16 11:36:45,228 INFO L158 Benchmark]: Toolchain (without parser) took 4427.58ms. Allocated memory was 117.4MB in the beginning and 165.7MB in the end (delta: 48.2MB). Free memory was 76.0MB in the beginning and 89.4MB in the end (delta: -13.3MB). Peak memory consumption was 38.5MB. Max. memory is 16.1GB. [2022-11-16 11:36:45,229 INFO L158 Benchmark]: CDTParser took 0.31ms. Allocated memory is still 117.4MB. Free memory was 92.7MB in the beginning and 92.6MB in the end (delta: 140.4kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-16 11:36:45,229 INFO L158 Benchmark]: CACSL2BoogieTranslator took 329.75ms. Allocated memory is still 117.4MB. Free memory was 75.9MB in the beginning and 90.7MB in the end (delta: -14.8MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2022-11-16 11:36:45,230 INFO L158 Benchmark]: Boogie Procedure Inliner took 48.65ms. Allocated memory is still 117.4MB. Free memory was 90.7MB in the beginning and 88.2MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-16 11:36:45,230 INFO L158 Benchmark]: Boogie Preprocessor took 59.63ms. Allocated memory is still 117.4MB. Free memory was 88.2MB in the beginning and 86.6MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-16 11:36:45,230 INFO L158 Benchmark]: RCFGBuilder took 641.81ms. Allocated memory is still 117.4MB. Free memory was 86.6MB in the beginning and 66.6MB in the end (delta: 20.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-11-16 11:36:45,231 INFO L158 Benchmark]: BuchiAutomizer took 3252.81ms. Allocated memory was 117.4MB in the beginning and 165.7MB in the end (delta: 48.2MB). Free memory was 66.6MB in the beginning and 92.5MB in the end (delta: -25.9MB). Peak memory consumption was 23.9MB. Max. memory is 16.1GB. [2022-11-16 11:36:45,231 INFO L158 Benchmark]: Witness Printer took 83.96ms. Allocated memory is still 165.7MB. Free memory was 92.5MB in the beginning and 89.4MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-16 11:36:45,234 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31ms. Allocated memory is still 117.4MB. Free memory was 92.7MB in the beginning and 92.6MB in the end (delta: 140.4kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 329.75ms. Allocated memory is still 117.4MB. Free memory was 75.9MB in the beginning and 90.7MB in the end (delta: -14.8MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 48.65ms. Allocated memory is still 117.4MB. Free memory was 90.7MB in the beginning and 88.2MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 59.63ms. Allocated memory is still 117.4MB. Free memory was 88.2MB in the beginning and 86.6MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 641.81ms. Allocated memory is still 117.4MB. Free memory was 86.6MB in the beginning and 66.6MB in the end (delta: 20.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 3252.81ms. Allocated memory was 117.4MB in the beginning and 165.7MB in the end (delta: 48.2MB). Free memory was 66.6MB in the beginning and 92.5MB in the end (delta: -25.9MB). Peak memory consumption was 23.9MB. Max. memory is 16.1GB. * Witness Printer took 83.96ms. Allocated memory is still 165.7MB. Free memory was 92.5MB in the beginning and 89.4MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 7 terminating modules (7 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.7 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 577 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.1s and 8 iterations. TraceHistogramMax:1. Analysis of lassos took 2.1s. Construction of modules took 0.2s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 7. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 7 MinimizatonAttempts, 613 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1700 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1700 mSDsluCounter, 3003 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1724 mSDsCounter, 62 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 173 IncrementalHoareTripleChecker+Invalid, 235 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 62 mSolverCounterUnsat, 1279 mSDtfsCounter, 173 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN1 SILU0 SILI2 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 201]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L27] int m_st ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L29] int m_i ; [L33] int E_1 = 2; [L25] int m_pc = 0; [L28] int t1_st ; [L26] int t1_pc = 0; VAL [E_1=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [__retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [__retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 201]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L27] int m_st ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L29] int m_i ; [L33] int E_1 = 2; [L25] int m_pc = 0; [L28] int t1_st ; [L26] int t1_pc = 0; VAL [E_1=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [__retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [__retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-16 11:36:45,303 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_506ac0b4-ecb2-478c-a5c0-942af8075d46/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)