./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 10:54:08,843 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 10:54:08,846 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 10:54:08,876 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 10:54:08,879 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 10:54:08,883 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 10:54:08,886 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 10:54:08,891 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 10:54:08,894 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 10:54:08,900 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 10:54:08,902 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 10:54:08,905 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 10:54:08,905 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 10:54:08,909 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 10:54:08,911 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 10:54:08,914 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 10:54:08,916 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 10:54:08,917 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 10:54:08,919 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 10:54:08,923 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 10:54:08,924 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 10:54:08,926 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 10:54:08,927 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 10:54:08,928 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 10:54:08,932 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 10:54:08,932 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 10:54:08,933 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 10:54:08,934 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 10:54:08,934 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 10:54:08,935 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 10:54:08,936 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 10:54:08,937 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 10:54:08,937 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 10:54:08,938 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 10:54:08,939 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 10:54:08,940 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 10:54:08,941 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 10:54:08,941 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 10:54:08,941 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 10:54:08,942 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 10:54:08,943 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 10:54:08,944 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 10:54:08,969 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 10:54:08,970 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 10:54:08,970 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 10:54:08,970 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 10:54:08,971 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 10:54:08,972 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 10:54:08,972 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 10:54:08,972 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 10:54:08,972 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 10:54:08,973 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 10:54:08,973 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 10:54:08,973 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 10:54:08,973 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 10:54:08,973 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 10:54:08,974 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 10:54:08,974 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 10:54:08,974 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 10:54:08,974 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 10:54:08,974 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 10:54:08,975 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 10:54:08,975 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 10:54:08,975 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 10:54:08,975 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 10:54:08,975 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 10:54:08,976 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 10:54:08,976 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 10:54:08,976 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 10:54:08,976 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 10:54:08,976 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 10:54:08,977 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 10:54:08,977 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 10:54:08,978 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 10:54:08,978 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2022-11-16 10:54:09,305 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 10:54:09,329 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 10:54:09,332 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 10:54:09,333 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 10:54:09,334 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 10:54:09,336 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2022-11-16 10:54:09,425 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/data/4b7de4a36/2a972843a5d44949912a04d18214db10/FLAGeba439ca2 [2022-11-16 10:54:10,044 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 10:54:10,045 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/sv-benchmarks/c/systemc/transmitter.03.cil.c [2022-11-16 10:54:10,060 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/data/4b7de4a36/2a972843a5d44949912a04d18214db10/FLAGeba439ca2 [2022-11-16 10:54:10,374 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/data/4b7de4a36/2a972843a5d44949912a04d18214db10 [2022-11-16 10:54:10,376 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 10:54:10,378 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 10:54:10,379 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 10:54:10,380 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 10:54:10,383 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 10:54:10,384 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,386 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5044993b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10, skipping insertion in model container [2022-11-16 10:54:10,386 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,394 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 10:54:10,424 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 10:54:10,608 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/sv-benchmarks/c/systemc/transmitter.03.cil.c[706,719] [2022-11-16 10:54:10,668 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 10:54:10,679 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 10:54:10,692 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/sv-benchmarks/c/systemc/transmitter.03.cil.c[706,719] [2022-11-16 10:54:10,725 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 10:54:10,741 INFO L208 MainTranslator]: Completed translation [2022-11-16 10:54:10,742 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10 WrapperNode [2022-11-16 10:54:10,742 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 10:54:10,743 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 10:54:10,744 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 10:54:10,744 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 10:54:10,753 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,774 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,820 INFO L138 Inliner]: procedures = 34, calls = 39, calls flagged for inlining = 34, calls inlined = 56, statements flattened = 733 [2022-11-16 10:54:10,826 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 10:54:10,827 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 10:54:10,828 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 10:54:10,828 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 10:54:10,837 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,838 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,854 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,867 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,877 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,901 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,905 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,921 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,926 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 10:54:10,927 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 10:54:10,928 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 10:54:10,928 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 10:54:10,929 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (1/1) ... [2022-11-16 10:54:10,949 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 10:54:10,962 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 10:54:10,977 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 10:54:10,985 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 10:54:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 10:54:11,025 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 10:54:11,026 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 10:54:11,026 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 10:54:11,124 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 10:54:11,127 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 10:54:11,903 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 10:54:11,914 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 10:54:11,914 INFO L300 CfgBuilder]: Removed 7 assume(true) statements. [2022-11-16 10:54:11,918 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 10:54:11 BoogieIcfgContainer [2022-11-16 10:54:11,918 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 10:54:11,919 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 10:54:11,919 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 10:54:11,924 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 10:54:11,925 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 10:54:11,925 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 10:54:10" (1/3) ... [2022-11-16 10:54:11,926 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7d1b688 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 10:54:11, skipping insertion in model container [2022-11-16 10:54:11,926 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 10:54:11,927 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:54:10" (2/3) ... [2022-11-16 10:54:11,927 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7d1b688 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 10:54:11, skipping insertion in model container [2022-11-16 10:54:11,927 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 10:54:11,928 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 10:54:11" (3/3) ... [2022-11-16 10:54:11,929 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2022-11-16 10:54:11,998 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 10:54:11,998 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 10:54:11,998 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 10:54:11,999 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 10:54:11,999 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 10:54:11,999 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 10:54:11,999 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 10:54:12,000 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 10:54:12,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 291 states, 290 states have (on average 1.5413793103448277) internal successors, (447), 290 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:12,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 234 [2022-11-16 10:54:12,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:12,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:12,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:12,098 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:12,099 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 10:54:12,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 291 states, 290 states have (on average 1.5413793103448277) internal successors, (447), 290 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:12,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 234 [2022-11-16 10:54:12,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:12,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:12,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:12,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:12,145 INFO L748 eck$LassoCheckResult]: Stem: 281#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 192#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 160#L615true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112#L274true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 168#L281true assume !(1 == ~m_i~0);~m_st~0 := 2; 226#L281-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 33#L286-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 205#L291-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 220#L296-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14#L418true assume !(0 == ~M_E~0); 167#L418-2true assume !(0 == ~T1_E~0); 213#L423-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 223#L428-1true assume !(0 == ~T3_E~0); 210#L433-1true assume !(0 == ~E_1~0); 196#L438-1true assume !(0 == ~E_2~0); 126#L443-1true assume !(0 == ~E_3~0); 122#L448-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91#L197true assume !(1 == ~m_pc~0); 258#L197-2true is_master_triggered_~__retres1~0#1 := 0; 262#L208true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270#L209true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 232#L510true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6#L510-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 259#L216true assume 1 == ~t1_pc~0; 25#L217true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 117#L227true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109#L228true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7#L518true assume !(0 != activate_threads_~tmp___0~0#1); 134#L518-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 273#L235true assume !(1 == ~t2_pc~0); 202#L235-2true is_transmit2_triggered_~__retres1~2#1 := 0; 80#L246true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131#L247true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 244#L526true assume !(0 != activate_threads_~tmp___1~0#1); 254#L526-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71#L254true assume 1 == ~t3_pc~0; 18#L255true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 87#L265true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#L266true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 110#L534true assume !(0 != activate_threads_~tmp___2~0#1); 76#L534-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2#L461true assume !(1 == ~M_E~0); 34#L461-2true assume !(1 == ~T1_E~0); 221#L466-1true assume !(1 == ~T2_E~0); 266#L471-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 46#L476-1true assume !(1 == ~E_1~0); 271#L481-1true assume !(1 == ~E_2~0); 146#L486-1true assume !(1 == ~E_3~0); 54#L491-1true assume { :end_inline_reset_delta_events } true; 10#L652-2true [2022-11-16 10:54:12,154 INFO L750 eck$LassoCheckResult]: Loop: 10#L652-2true assume !false; 62#L653true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 171#L393true assume false; 263#L408true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 230#L274-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 289#L418-3true assume 0 == ~M_E~0;~M_E~0 := 1; 133#L418-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 154#L423-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 129#L428-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 90#L433-3true assume 0 == ~E_1~0;~E_1~0 := 1; 176#L438-3true assume !(0 == ~E_2~0); 183#L443-3true assume 0 == ~E_3~0;~E_3~0 := 1; 3#L448-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 185#L197-12true assume 1 == ~m_pc~0; 190#L198-4true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 68#L208-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 268#L209-4true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9#L510-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 105#L510-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67#L216-12true assume 1 == ~t1_pc~0; 283#L217-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 102#L227-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44#L228-4true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 73#L518-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32#L518-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 277#L235-12true assume 1 == ~t2_pc~0; 194#L236-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 245#L246-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 240#L247-4true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 285#L526-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123#L526-14true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 235#L254-12true assume !(1 == ~t3_pc~0); 241#L254-14true is_transmit3_triggered_~__retres1~3#1 := 0; 125#L265-4true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132#L266-4true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 107#L534-12true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 147#L534-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69#L461-3true assume 1 == ~M_E~0;~M_E~0 := 2; 290#L461-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 138#L466-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 231#L471-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 64#L476-3true assume 1 == ~E_1~0;~E_1~0 := 2; 130#L481-3true assume 1 == ~E_2~0;~E_2~0 := 2; 86#L486-3true assume !(1 == ~E_3~0); 251#L491-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20#L309-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 35#L331-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 48#L332-1true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 139#L671true assume !(0 == start_simulation_~tmp~3#1); 173#L671-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 291#L309-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 145#L331-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 111#L332-2true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 218#L626true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 149#L633true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 243#L634true start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 158#L684true assume !(0 != start_simulation_~tmp___0~1#1); 10#L652-2true [2022-11-16 10:54:12,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:12,169 INFO L85 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2022-11-16 10:54:12,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:12,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686215960] [2022-11-16 10:54:12,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:12,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:12,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:12,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:12,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:12,513 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686215960] [2022-11-16 10:54:12,514 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686215960] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:12,514 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:12,514 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:12,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953402572] [2022-11-16 10:54:12,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:12,521 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:12,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:12,523 INFO L85 PathProgramCache]: Analyzing trace with hash 213943049, now seen corresponding path program 1 times [2022-11-16 10:54:12,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:12,523 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170156945] [2022-11-16 10:54:12,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:12,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:12,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:12,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:12,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:12,558 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170156945] [2022-11-16 10:54:12,558 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170156945] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:12,558 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:12,558 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 10:54:12,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1743288915] [2022-11-16 10:54:12,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:12,560 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:12,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:12,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:12,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:12,596 INFO L87 Difference]: Start difference. First operand has 291 states, 290 states have (on average 1.5413793103448277) internal successors, (447), 290 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:12,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:12,640 INFO L93 Difference]: Finished difference Result 290 states and 430 transitions. [2022-11-16 10:54:12,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 290 states and 430 transitions. [2022-11-16 10:54:12,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2022-11-16 10:54:12,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 290 states to 284 states and 424 transitions. [2022-11-16 10:54:12,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2022-11-16 10:54:12,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2022-11-16 10:54:12,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 424 transitions. [2022-11-16 10:54:12,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:12,656 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 424 transitions. [2022-11-16 10:54:12,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 424 transitions. [2022-11-16 10:54:12,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2022-11-16 10:54:12,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4929577464788732) internal successors, (424), 283 states have internal predecessors, (424), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:12,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 424 transitions. [2022-11-16 10:54:12,700 INFO L240 hiAutomatonCegarLoop]: Abstraction has 284 states and 424 transitions. [2022-11-16 10:54:12,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:12,705 INFO L428 stractBuchiCegarLoop]: Abstraction has 284 states and 424 transitions. [2022-11-16 10:54:12,705 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 10:54:12,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 424 transitions. [2022-11-16 10:54:12,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2022-11-16 10:54:12,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:12,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:12,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:12,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:12,712 INFO L748 eck$LassoCheckResult]: Stem: 873#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 810#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 771#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 772#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 818#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 657#L286-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 658#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 850#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 614#L418 assume !(0 == ~M_E~0); 615#L418-2 assume !(0 == ~T1_E~0); 817#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 853#L428-1 assume !(0 == ~T3_E~0); 851#L433-1 assume !(0 == ~E_1~0); 843#L438-1 assume !(0 == ~E_2~0); 784#L443-1 assume !(0 == ~E_3~0); 779#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745#L197 assume !(1 == ~m_pc~0); 742#L197-2 is_master_triggered_~__retres1~0#1 := 0; 741#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 868#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 861#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 598#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 599#L216 assume 1 == ~t1_pc~0; 642#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 643#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 768#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 600#L518 assume !(0 != activate_threads_~tmp___0~0#1); 601#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 790#L235 assume !(1 == ~t2_pc~0); 847#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 731#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 732#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 786#L526 assume !(0 != activate_threads_~tmp___1~0#1); 864#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 720#L254 assume 1 == ~t3_pc~0; 624#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 625#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 610#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 611#L534 assume !(0 != activate_threads_~tmp___2~0#1); 726#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 590#L461 assume !(1 == ~M_E~0); 591#L461-2 assume !(1 == ~T1_E~0); 659#L466-1 assume !(1 == ~T2_E~0); 856#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 680#L476-1 assume !(1 == ~E_1~0); 681#L481-1 assume !(1 == ~E_2~0); 803#L486-1 assume !(1 == ~E_3~0); 694#L491-1 assume { :end_inline_reset_delta_events } true; 608#L652-2 [2022-11-16 10:54:12,712 INFO L750 eck$LassoCheckResult]: Loop: 608#L652-2 assume !false; 609#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 707#L393 assume !false; 674#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 675#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 653#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 813#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 697#L346 assume !(0 != eval_~tmp~0#1); 698#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 859#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 860#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 787#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 788#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 785#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 743#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 744#L438-3 assume !(0 == ~E_2~0); 825#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 592#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 593#L197-12 assume !(1 == ~m_pc~0); 833#L197-14 is_master_triggered_~__retres1~0#1 := 0; 714#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 715#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 604#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 605#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 711#L216-12 assume 1 == ~t1_pc~0; 712#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 759#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 676#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 677#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 655#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 656#L235-12 assume !(1 == ~t2_pc~0); 729#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 730#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 862#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 863#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 781#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 782#L254-12 assume 1 == ~t3_pc~0; 633#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 634#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 783#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 763#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 764#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 716#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 717#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 794#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 795#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 708#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 709#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 736#L486-3 assume !(1 == ~E_3~0); 737#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 627#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 628#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 660#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 685#L671 assume !(0 == start_simulation_~tmp~3#1); 613#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 820#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 705#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 769#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 770#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 804#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 805#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 808#L684 assume !(0 != start_simulation_~tmp___0~1#1); 608#L652-2 [2022-11-16 10:54:12,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:12,713 INFO L85 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2022-11-16 10:54:12,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:12,714 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388712068] [2022-11-16 10:54:12,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:12,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:12,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:12,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:12,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:12,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388712068] [2022-11-16 10:54:12,834 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388712068] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:12,834 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:12,834 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:12,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952868595] [2022-11-16 10:54:12,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:12,836 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:12,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:12,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1668488769, now seen corresponding path program 1 times [2022-11-16 10:54:12,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:12,840 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274475752] [2022-11-16 10:54:12,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:12,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:12,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:12,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:12,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:12,952 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274475752] [2022-11-16 10:54:12,953 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1274475752] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:12,953 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:12,953 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:12,953 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598163023] [2022-11-16 10:54:12,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:12,954 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:12,954 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:12,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:12,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:12,956 INFO L87 Difference]: Start difference. First operand 284 states and 424 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:12,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:12,987 INFO L93 Difference]: Finished difference Result 284 states and 423 transitions. [2022-11-16 10:54:12,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 423 transitions. [2022-11-16 10:54:12,990 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2022-11-16 10:54:13,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 423 transitions. [2022-11-16 10:54:13,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2022-11-16 10:54:13,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2022-11-16 10:54:13,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 423 transitions. [2022-11-16 10:54:13,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:13,011 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 423 transitions. [2022-11-16 10:54:13,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 423 transitions. [2022-11-16 10:54:13,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2022-11-16 10:54:13,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4894366197183098) internal successors, (423), 283 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:13,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 423 transitions. [2022-11-16 10:54:13,035 INFO L240 hiAutomatonCegarLoop]: Abstraction has 284 states and 423 transitions. [2022-11-16 10:54:13,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:13,036 INFO L428 stractBuchiCegarLoop]: Abstraction has 284 states and 423 transitions. [2022-11-16 10:54:13,037 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 10:54:13,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 423 transitions. [2022-11-16 10:54:13,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2022-11-16 10:54:13,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:13,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:13,043 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:13,044 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:13,044 INFO L748 eck$LassoCheckResult]: Stem: 1448#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 1415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1385#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1346#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1347#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1393#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1232#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1233#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1425#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1192#L418 assume !(0 == ~M_E~0); 1193#L418-2 assume !(0 == ~T1_E~0); 1392#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1428#L428-1 assume !(0 == ~T3_E~0); 1426#L433-1 assume !(0 == ~E_1~0); 1418#L438-1 assume !(0 == ~E_2~0); 1359#L443-1 assume !(0 == ~E_3~0); 1354#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1320#L197 assume !(1 == ~m_pc~0); 1317#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1316#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1443#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1436#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1173#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1174#L216 assume 1 == ~t1_pc~0; 1217#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1218#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1343#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1175#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1176#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1365#L235 assume !(1 == ~t2_pc~0); 1424#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1306#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1307#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1361#L526 assume !(0 != activate_threads_~tmp___1~0#1); 1439#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1295#L254 assume 1 == ~t3_pc~0; 1199#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1200#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1185#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1186#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1301#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1165#L461 assume !(1 == ~M_E~0); 1166#L461-2 assume !(1 == ~T1_E~0); 1234#L466-1 assume !(1 == ~T2_E~0); 1431#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1255#L476-1 assume !(1 == ~E_1~0); 1256#L481-1 assume !(1 == ~E_2~0); 1378#L486-1 assume !(1 == ~E_3~0); 1271#L491-1 assume { :end_inline_reset_delta_events } true; 1183#L652-2 [2022-11-16 10:54:13,045 INFO L750 eck$LassoCheckResult]: Loop: 1183#L652-2 assume !false; 1184#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1282#L393 assume !false; 1249#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1250#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1228#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1388#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1272#L346 assume !(0 != eval_~tmp~0#1); 1273#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1434#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1435#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1362#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1363#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1360#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1318#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1319#L438-3 assume !(0 == ~E_2~0); 1401#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1167#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1168#L197-12 assume !(1 == ~m_pc~0); 1408#L197-14 is_master_triggered_~__retres1~0#1 := 0; 1289#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1290#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1179#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1180#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1286#L216-12 assume 1 == ~t1_pc~0; 1287#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1334#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1251#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1252#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1230#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1231#L235-12 assume !(1 == ~t2_pc~0); 1304#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1305#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1437#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1438#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1355#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1356#L254-12 assume 1 == ~t3_pc~0; 1208#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1209#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1358#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1338#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1339#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1291#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1292#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1369#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1370#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1283#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1284#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1311#L486-3 assume !(1 == ~E_3~0); 1312#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1202#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1203#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1235#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1260#L671 assume !(0 == start_simulation_~tmp~3#1); 1188#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1395#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1280#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1344#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1345#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1379#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1380#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1383#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1183#L652-2 [2022-11-16 10:54:13,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:13,047 INFO L85 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2022-11-16 10:54:13,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:13,051 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [839306763] [2022-11-16 10:54:13,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:13,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:13,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:13,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:13,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:13,130 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [839306763] [2022-11-16 10:54:13,130 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [839306763] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:13,130 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:13,130 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:13,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987152688] [2022-11-16 10:54:13,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:13,147 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:13,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:13,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1668488769, now seen corresponding path program 2 times [2022-11-16 10:54:13,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:13,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290365371] [2022-11-16 10:54:13,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:13,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:13,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:13,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:13,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:13,233 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290365371] [2022-11-16 10:54:13,236 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290365371] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:13,236 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:13,236 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:13,237 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610570439] [2022-11-16 10:54:13,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:13,238 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:13,239 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:13,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:13,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:13,240 INFO L87 Difference]: Start difference. First operand 284 states and 423 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:13,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:13,288 INFO L93 Difference]: Finished difference Result 284 states and 422 transitions. [2022-11-16 10:54:13,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 422 transitions. [2022-11-16 10:54:13,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2022-11-16 10:54:13,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 422 transitions. [2022-11-16 10:54:13,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2022-11-16 10:54:13,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2022-11-16 10:54:13,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 422 transitions. [2022-11-16 10:54:13,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:13,307 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 422 transitions. [2022-11-16 10:54:13,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 422 transitions. [2022-11-16 10:54:13,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2022-11-16 10:54:13,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4859154929577465) internal successors, (422), 283 states have internal predecessors, (422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:13,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 422 transitions. [2022-11-16 10:54:13,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 284 states and 422 transitions. [2022-11-16 10:54:13,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:13,329 INFO L428 stractBuchiCegarLoop]: Abstraction has 284 states and 422 transitions. [2022-11-16 10:54:13,331 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 10:54:13,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 422 transitions. [2022-11-16 10:54:13,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2022-11-16 10:54:13,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:13,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:13,338 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:13,343 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:13,343 INFO L748 eck$LassoCheckResult]: Stem: 2023#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 1990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1960#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1921#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1922#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1968#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1807#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1808#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2000#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1769#L418 assume !(0 == ~M_E~0); 1770#L418-2 assume !(0 == ~T1_E~0); 1967#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2003#L428-1 assume !(0 == ~T3_E~0); 2001#L433-1 assume !(0 == ~E_1~0); 1993#L438-1 assume !(0 == ~E_2~0); 1934#L443-1 assume !(0 == ~E_3~0); 1929#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1895#L197 assume !(1 == ~m_pc~0); 1892#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1891#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2019#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2011#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1748#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1749#L216 assume 1 == ~t1_pc~0; 1792#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1793#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1918#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1750#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1751#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1941#L235 assume !(1 == ~t2_pc~0); 1999#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1882#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1883#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1936#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2014#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1873#L254 assume 1 == ~t3_pc~0; 1774#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1775#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1760#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1761#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1876#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1740#L461 assume !(1 == ~M_E~0); 1741#L461-2 assume !(1 == ~T1_E~0); 1809#L466-1 assume !(1 == ~T2_E~0); 2006#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1830#L476-1 assume !(1 == ~E_1~0); 1831#L481-1 assume !(1 == ~E_2~0); 1953#L486-1 assume !(1 == ~E_3~0); 1846#L491-1 assume { :end_inline_reset_delta_events } true; 1758#L652-2 [2022-11-16 10:54:13,344 INFO L750 eck$LassoCheckResult]: Loop: 1758#L652-2 assume !false; 1759#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1857#L393 assume !false; 1824#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1825#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1803#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1963#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1847#L346 assume !(0 != eval_~tmp~0#1); 1848#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2009#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2010#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1937#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1938#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1935#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1893#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1894#L438-3 assume !(0 == ~E_2~0); 1975#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1742#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1743#L197-12 assume 1 == ~m_pc~0; 1984#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1864#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1865#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1754#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1755#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1861#L216-12 assume 1 == ~t1_pc~0; 1862#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1909#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1826#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1827#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1805#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1806#L235-12 assume !(1 == ~t2_pc~0); 1879#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1880#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2012#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2013#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1930#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1931#L254-12 assume 1 == ~t3_pc~0; 1783#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1784#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1933#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1913#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1914#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1866#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1867#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1944#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1945#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1858#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1859#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1886#L486-3 assume !(1 == ~E_3~0); 1887#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1780#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1781#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1810#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1835#L671 assume !(0 == start_simulation_~tmp~3#1); 1763#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1970#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1855#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1919#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1920#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1954#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1955#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1958#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1758#L652-2 [2022-11-16 10:54:13,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:13,345 INFO L85 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2022-11-16 10:54:13,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:13,345 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206246892] [2022-11-16 10:54:13,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:13,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:13,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:13,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:13,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:13,421 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [206246892] [2022-11-16 10:54:13,422 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [206246892] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:13,422 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:13,422 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 10:54:13,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305222082] [2022-11-16 10:54:13,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:13,423 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:13,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:13,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1351375838, now seen corresponding path program 1 times [2022-11-16 10:54:13,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:13,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108893356] [2022-11-16 10:54:13,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:13,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:13,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:13,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:13,492 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:13,492 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108893356] [2022-11-16 10:54:13,492 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108893356] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:13,493 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:13,493 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:13,493 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123604417] [2022-11-16 10:54:13,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:13,494 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:13,494 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:13,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:13,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:13,495 INFO L87 Difference]: Start difference. First operand 284 states and 422 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:13,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:13,519 INFO L93 Difference]: Finished difference Result 284 states and 417 transitions. [2022-11-16 10:54:13,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 417 transitions. [2022-11-16 10:54:13,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2022-11-16 10:54:13,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 417 transitions. [2022-11-16 10:54:13,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2022-11-16 10:54:13,525 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2022-11-16 10:54:13,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 417 transitions. [2022-11-16 10:54:13,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:13,526 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 417 transitions. [2022-11-16 10:54:13,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 417 transitions. [2022-11-16 10:54:13,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2022-11-16 10:54:13,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4683098591549295) internal successors, (417), 283 states have internal predecessors, (417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:13,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 417 transitions. [2022-11-16 10:54:13,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 284 states and 417 transitions. [2022-11-16 10:54:13,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:13,536 INFO L428 stractBuchiCegarLoop]: Abstraction has 284 states and 417 transitions. [2022-11-16 10:54:13,536 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 10:54:13,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 417 transitions. [2022-11-16 10:54:13,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2022-11-16 10:54:13,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:13,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:13,552 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:13,552 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:13,552 INFO L748 eck$LassoCheckResult]: Stem: 2598#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 2565#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2535#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2496#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2497#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2543#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2382#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2383#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2575#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2344#L418 assume !(0 == ~M_E~0); 2345#L418-2 assume !(0 == ~T1_E~0); 2542#L423-1 assume !(0 == ~T2_E~0); 2578#L428-1 assume !(0 == ~T3_E~0); 2576#L433-1 assume !(0 == ~E_1~0); 2568#L438-1 assume !(0 == ~E_2~0); 2509#L443-1 assume !(0 == ~E_3~0); 2504#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2470#L197 assume !(1 == ~m_pc~0); 2467#L197-2 is_master_triggered_~__retres1~0#1 := 0; 2466#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2593#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2586#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2323#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2324#L216 assume 1 == ~t1_pc~0; 2367#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2368#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2493#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2325#L518 assume !(0 != activate_threads_~tmp___0~0#1); 2326#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2514#L235 assume !(1 == ~t2_pc~0); 2572#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2456#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2457#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2511#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2589#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2445#L254 assume 1 == ~t3_pc~0; 2349#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2350#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2335#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2336#L534 assume !(0 != activate_threads_~tmp___2~0#1); 2451#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2315#L461 assume !(1 == ~M_E~0); 2316#L461-2 assume !(1 == ~T1_E~0); 2384#L466-1 assume !(1 == ~T2_E~0); 2581#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2405#L476-1 assume !(1 == ~E_1~0); 2406#L481-1 assume !(1 == ~E_2~0); 2528#L486-1 assume !(1 == ~E_3~0); 2419#L491-1 assume { :end_inline_reset_delta_events } true; 2331#L652-2 [2022-11-16 10:54:13,552 INFO L750 eck$LassoCheckResult]: Loop: 2331#L652-2 assume !false; 2332#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2429#L393 assume !false; 2399#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2400#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2378#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2538#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2422#L346 assume !(0 != eval_~tmp~0#1); 2423#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2584#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2585#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2512#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2513#L423-3 assume !(0 == ~T2_E~0); 2510#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2468#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2469#L438-3 assume !(0 == ~E_2~0); 2550#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2317#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2318#L197-12 assume !(1 == ~m_pc~0); 2558#L197-14 is_master_triggered_~__retres1~0#1 := 0; 2439#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2440#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2329#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2330#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2436#L216-12 assume 1 == ~t1_pc~0; 2437#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2484#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2401#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2402#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2380#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2381#L235-12 assume !(1 == ~t2_pc~0); 2454#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 2455#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2587#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2588#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2505#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2506#L254-12 assume 1 == ~t3_pc~0; 2358#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2359#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2508#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2488#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2489#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2441#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2442#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2519#L466-3 assume !(1 == ~T2_E~0); 2520#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2433#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2434#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2462#L486-3 assume !(1 == ~E_3~0); 2463#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2355#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2356#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2385#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2410#L671 assume !(0 == start_simulation_~tmp~3#1); 2338#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2545#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2431#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2494#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 2495#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2529#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2530#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2534#L684 assume !(0 != start_simulation_~tmp___0~1#1); 2331#L652-2 [2022-11-16 10:54:13,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:13,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1247671284, now seen corresponding path program 1 times [2022-11-16 10:54:13,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:13,554 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663255948] [2022-11-16 10:54:13,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:13,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:13,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:13,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:13,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:13,671 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663255948] [2022-11-16 10:54:13,672 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1663255948] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:13,672 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:13,672 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 10:54:13,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830691593] [2022-11-16 10:54:13,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:13,673 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:13,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:13,673 INFO L85 PathProgramCache]: Analyzing trace with hash -806736195, now seen corresponding path program 1 times [2022-11-16 10:54:13,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:13,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207222280] [2022-11-16 10:54:13,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:13,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:13,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:13,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:13,765 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:13,765 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207222280] [2022-11-16 10:54:13,765 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207222280] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:13,766 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:13,766 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:13,766 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [230442075] [2022-11-16 10:54:13,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:13,767 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:13,767 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:13,767 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 10:54:13,767 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 10:54:13,768 INFO L87 Difference]: Start difference. First operand 284 states and 417 transitions. cyclomatic complexity: 134 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:13,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:13,959 INFO L93 Difference]: Finished difference Result 764 states and 1113 transitions. [2022-11-16 10:54:13,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 764 states and 1113 transitions. [2022-11-16 10:54:13,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 648 [2022-11-16 10:54:13,970 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 764 states to 764 states and 1113 transitions. [2022-11-16 10:54:13,971 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 764 [2022-11-16 10:54:13,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 764 [2022-11-16 10:54:13,974 INFO L73 IsDeterministic]: Start isDeterministic. Operand 764 states and 1113 transitions. [2022-11-16 10:54:13,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:13,976 INFO L218 hiAutomatonCegarLoop]: Abstraction has 764 states and 1113 transitions. [2022-11-16 10:54:13,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 764 states and 1113 transitions. [2022-11-16 10:54:14,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 764 to 302. [2022-11-16 10:54:14,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 302 states, 302 states have (on average 1.4403973509933774) internal successors, (435), 301 states have internal predecessors, (435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:14,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 435 transitions. [2022-11-16 10:54:14,006 INFO L240 hiAutomatonCegarLoop]: Abstraction has 302 states and 435 transitions. [2022-11-16 10:54:14,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 10:54:14,007 INFO L428 stractBuchiCegarLoop]: Abstraction has 302 states and 435 transitions. [2022-11-16 10:54:14,007 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 10:54:14,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 302 states and 435 transitions. [2022-11-16 10:54:14,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 246 [2022-11-16 10:54:14,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:14,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:14,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:14,011 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:14,011 INFO L748 eck$LassoCheckResult]: Stem: 3677#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 3631#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3599#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3557#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3558#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 3607#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3443#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3444#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3642#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3403#L418 assume !(0 == ~M_E~0); 3404#L418-2 assume !(0 == ~T1_E~0); 3606#L423-1 assume !(0 == ~T2_E~0); 3645#L428-1 assume !(0 == ~T3_E~0); 3643#L433-1 assume !(0 == ~E_1~0); 3634#L438-1 assume !(0 == ~E_2~0); 3571#L443-1 assume !(0 == ~E_3~0); 3566#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3531#L197 assume !(1 == ~m_pc~0); 3528#L197-2 is_master_triggered_~__retres1~0#1 := 0; 3666#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3667#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3653#L510 assume !(0 != activate_threads_~tmp~1#1); 3384#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3385#L216 assume 1 == ~t1_pc~0; 3428#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3429#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3554#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3386#L518 assume !(0 != activate_threads_~tmp___0~0#1); 3387#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3577#L235 assume !(1 == ~t2_pc~0); 3638#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3517#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3518#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3573#L526 assume !(0 != activate_threads_~tmp___1~0#1); 3657#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3506#L254 assume 1 == ~t3_pc~0; 3410#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3411#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3396#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3397#L534 assume !(0 != activate_threads_~tmp___2~0#1); 3512#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3376#L461 assume !(1 == ~M_E~0); 3377#L461-2 assume !(1 == ~T1_E~0); 3445#L466-1 assume !(1 == ~T2_E~0); 3648#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3466#L476-1 assume !(1 == ~E_1~0); 3467#L481-1 assume !(1 == ~E_2~0); 3591#L486-1 assume !(1 == ~E_3~0); 3480#L491-1 assume { :end_inline_reset_delta_events } true; 3394#L652-2 [2022-11-16 10:54:14,012 INFO L750 eck$LassoCheckResult]: Loop: 3394#L652-2 assume !false; 3395#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3493#L393 assume !false; 3460#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3461#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3439#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3602#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3483#L346 assume !(0 != eval_~tmp~0#1); 3484#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3651#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3652#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3574#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3575#L423-3 assume !(0 == ~T2_E~0); 3572#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3529#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3530#L438-3 assume !(0 == ~E_2~0); 3615#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3378#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3379#L197-12 assume !(1 == ~m_pc~0); 3623#L197-14 is_master_triggered_~__retres1~0#1 := 0; 3500#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3501#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3390#L510-12 assume !(0 != activate_threads_~tmp~1#1); 3391#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3497#L216-12 assume 1 == ~t1_pc~0; 3498#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3545#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3462#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3463#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3441#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3442#L235-12 assume 1 == ~t2_pc~0; 3633#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3516#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3655#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3656#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3567#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3568#L254-12 assume 1 == ~t3_pc~0; 3419#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3420#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3570#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3549#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3550#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3502#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3503#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3581#L466-3 assume !(1 == ~T2_E~0); 3582#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3494#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3495#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3522#L486-3 assume !(1 == ~E_3~0); 3523#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3413#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3414#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3446#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3471#L671 assume !(0 == start_simulation_~tmp~3#1); 3399#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3609#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3491#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3555#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 3556#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3592#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3593#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3597#L684 assume !(0 != start_simulation_~tmp___0~1#1); 3394#L652-2 [2022-11-16 10:54:14,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:14,012 INFO L85 PathProgramCache]: Analyzing trace with hash 738198194, now seen corresponding path program 1 times [2022-11-16 10:54:14,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:14,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493328918] [2022-11-16 10:54:14,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:14,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:14,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:14,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:14,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:14,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493328918] [2022-11-16 10:54:14,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493328918] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:14,136 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:14,136 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:14,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274510830] [2022-11-16 10:54:14,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:14,136 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:14,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:14,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1197449180, now seen corresponding path program 1 times [2022-11-16 10:54:14,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:14,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3243093] [2022-11-16 10:54:14,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:14,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:14,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:14,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:14,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:14,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3243093] [2022-11-16 10:54:14,222 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3243093] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:14,223 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:14,223 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:14,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [781741504] [2022-11-16 10:54:14,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:14,224 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:14,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:14,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:54:14,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:54:14,225 INFO L87 Difference]: Start difference. First operand 302 states and 435 transitions. cyclomatic complexity: 134 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:14,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:14,417 INFO L93 Difference]: Finished difference Result 716 states and 1012 transitions. [2022-11-16 10:54:14,417 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 716 states and 1012 transitions. [2022-11-16 10:54:14,423 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 628 [2022-11-16 10:54:14,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 716 states to 716 states and 1012 transitions. [2022-11-16 10:54:14,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 716 [2022-11-16 10:54:14,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 716 [2022-11-16 10:54:14,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 716 states and 1012 transitions. [2022-11-16 10:54:14,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:14,434 INFO L218 hiAutomatonCegarLoop]: Abstraction has 716 states and 1012 transitions. [2022-11-16 10:54:14,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states and 1012 transitions. [2022-11-16 10:54:14,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 662. [2022-11-16 10:54:14,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 662 states, 662 states have (on average 1.4244712990936557) internal successors, (943), 661 states have internal predecessors, (943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:14,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 943 transitions. [2022-11-16 10:54:14,460 INFO L240 hiAutomatonCegarLoop]: Abstraction has 662 states and 943 transitions. [2022-11-16 10:54:14,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 10:54:14,462 INFO L428 stractBuchiCegarLoop]: Abstraction has 662 states and 943 transitions. [2022-11-16 10:54:14,462 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 10:54:14,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 662 states and 943 transitions. [2022-11-16 10:54:14,466 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 606 [2022-11-16 10:54:14,467 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:14,467 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:14,470 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:14,470 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:14,472 INFO L748 eck$LassoCheckResult]: Stem: 4717#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 4664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4632#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4584#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4585#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 4641#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4470#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4471#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4676#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4430#L418 assume !(0 == ~M_E~0); 4431#L418-2 assume !(0 == ~T1_E~0); 4640#L423-1 assume !(0 == ~T2_E~0); 4682#L428-1 assume !(0 == ~T3_E~0); 4680#L433-1 assume !(0 == ~E_1~0); 4668#L438-1 assume !(0 == ~E_2~0); 4601#L443-1 assume !(0 == ~E_3~0); 4595#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4556#L197 assume !(1 == ~m_pc~0); 4557#L197-2 is_master_triggered_~__retres1~0#1 := 0; 4708#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4710#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4689#L510 assume !(0 != activate_threads_~tmp~1#1); 4412#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4413#L216 assume !(1 == ~t1_pc~0); 4466#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4467#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4581#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4414#L518 assume !(0 != activate_threads_~tmp___0~0#1); 4415#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4608#L235 assume !(1 == ~t2_pc~0); 4672#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4546#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4547#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4604#L526 assume !(0 != activate_threads_~tmp___1~0#1); 4698#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4537#L254 assume 1 == ~t3_pc~0; 4438#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4439#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4424#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4425#L534 assume !(0 != activate_threads_~tmp___2~0#1); 4540#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4404#L461 assume !(1 == ~M_E~0); 4405#L461-2 assume !(1 == ~T1_E~0); 4472#L466-1 assume !(1 == ~T2_E~0); 4685#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4493#L476-1 assume !(1 == ~E_1~0); 4494#L481-1 assume !(1 == ~E_2~0); 4624#L486-1 assume !(1 == ~E_3~0); 4507#L491-1 assume { :end_inline_reset_delta_events } true; 4508#L652-2 [2022-11-16 10:54:14,472 INFO L750 eck$LassoCheckResult]: Loop: 4508#L652-2 assume !false; 4988#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4987#L393 assume !false; 4986#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4985#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4981#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4980#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4975#L346 assume !(0 != eval_~tmp~0#1); 4974#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4973#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4972#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4971#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4970#L423-3 assume !(0 == ~T2_E~0); 4969#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4968#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4967#L438-3 assume !(0 == ~E_2~0); 4966#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4965#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4964#L197-12 assume !(1 == ~m_pc~0); 4963#L197-14 is_master_triggered_~__retres1~0#1 := 0; 4962#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4961#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4960#L510-12 assume !(0 != activate_threads_~tmp~1#1); 4959#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4958#L216-12 assume !(1 == ~t1_pc~0); 4956#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 4954#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4952#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4950#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4947#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4945#L235-12 assume !(1 == ~t2_pc~0); 4942#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 4940#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4938#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4936#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4932#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4929#L254-12 assume 1 == ~t3_pc~0; 4925#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4922#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4918#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4915#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4912#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4909#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4907#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4905#L466-3 assume !(1 == ~T2_E~0); 4903#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4884#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4881#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4879#L486-3 assume !(1 == ~E_3~0); 4877#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4859#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4856#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4849#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4612#L671 assume !(0 == start_simulation_~tmp~3#1); 4613#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4643#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4521#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4582#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 4583#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4625#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4626#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4697#L684 assume !(0 != start_simulation_~tmp___0~1#1); 4508#L652-2 [2022-11-16 10:54:14,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:14,474 INFO L85 PathProgramCache]: Analyzing trace with hash 1376982673, now seen corresponding path program 1 times [2022-11-16 10:54:14,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:14,475 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627807372] [2022-11-16 10:54:14,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:14,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:14,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:14,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:14,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:14,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627807372] [2022-11-16 10:54:14,579 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627807372] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:14,579 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:14,579 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:14,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719077594] [2022-11-16 10:54:14,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:14,580 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:14,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:14,581 INFO L85 PathProgramCache]: Analyzing trace with hash -1655222822, now seen corresponding path program 1 times [2022-11-16 10:54:14,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:14,581 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678632630] [2022-11-16 10:54:14,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:14,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:14,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:14,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:14,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:14,618 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678632630] [2022-11-16 10:54:14,618 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [678632630] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:14,618 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:14,619 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:14,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203824536] [2022-11-16 10:54:14,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:14,619 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:14,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:14,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:54:14,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:54:14,621 INFO L87 Difference]: Start difference. First operand 662 states and 943 transitions. cyclomatic complexity: 283 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:14,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:14,772 INFO L93 Difference]: Finished difference Result 1809 states and 2533 transitions. [2022-11-16 10:54:14,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1809 states and 2533 transitions. [2022-11-16 10:54:14,786 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1667 [2022-11-16 10:54:14,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1809 states to 1809 states and 2533 transitions. [2022-11-16 10:54:14,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1809 [2022-11-16 10:54:14,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1809 [2022-11-16 10:54:14,799 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1809 states and 2533 transitions. [2022-11-16 10:54:14,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:14,802 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1809 states and 2533 transitions. [2022-11-16 10:54:14,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1809 states and 2533 transitions. [2022-11-16 10:54:14,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1809 to 1726. [2022-11-16 10:54:14,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1726 states, 1726 states have (on average 1.4078794901506373) internal successors, (2430), 1725 states have internal predecessors, (2430), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:14,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1726 states to 1726 states and 2430 transitions. [2022-11-16 10:54:14,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1726 states and 2430 transitions. [2022-11-16 10:54:14,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 10:54:14,836 INFO L428 stractBuchiCegarLoop]: Abstraction has 1726 states and 2430 transitions. [2022-11-16 10:54:14,836 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 10:54:14,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1726 states and 2430 transitions. [2022-11-16 10:54:14,846 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1661 [2022-11-16 10:54:14,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:14,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:14,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:14,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:14,848 INFO L748 eck$LassoCheckResult]: Stem: 7202#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 7147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7114#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7061#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7062#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 7123#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6947#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6948#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7163#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6909#L418 assume !(0 == ~M_E~0); 6910#L418-2 assume !(0 == ~T1_E~0); 7122#L423-1 assume !(0 == ~T2_E~0); 7167#L428-1 assume !(0 == ~T3_E~0); 7165#L433-1 assume !(0 == ~E_1~0); 7150#L438-1 assume !(0 == ~E_2~0); 7080#L443-1 assume !(0 == ~E_3~0); 7074#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7033#L197 assume !(1 == ~m_pc~0); 7034#L197-2 is_master_triggered_~__retres1~0#1 := 0; 7195#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7196#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7176#L510 assume !(0 != activate_threads_~tmp~1#1); 6893#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6894#L216 assume !(1 == ~t1_pc~0); 6943#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6944#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7058#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6895#L518 assume !(0 != activate_threads_~tmp___0~0#1); 6896#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7086#L235 assume !(1 == ~t2_pc~0); 7159#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7022#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7023#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7083#L526 assume !(0 != activate_threads_~tmp___1~0#1); 7183#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7012#L254 assume !(1 == ~t3_pc~0); 6951#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6952#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6905#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6906#L534 assume !(0 != activate_threads_~tmp___2~0#1); 7017#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6885#L461 assume !(1 == ~M_E~0); 6886#L461-2 assume !(1 == ~T1_E~0); 6949#L466-1 assume !(1 == ~T2_E~0); 7170#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6972#L476-1 assume !(1 == ~E_1~0); 6973#L481-1 assume !(1 == ~E_2~0); 7102#L486-1 assume !(1 == ~E_3~0); 6985#L491-1 assume { :end_inline_reset_delta_events } true; 6986#L652-2 [2022-11-16 10:54:14,848 INFO L750 eck$LassoCheckResult]: Loop: 6986#L652-2 assume !false; 8329#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8327#L393 assume !false; 8325#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8323#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8320#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8313#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8314#L346 assume !(0 != eval_~tmp~0#1); 8476#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8473#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8470#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8467#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8464#L423-3 assume !(0 == ~T2_E~0); 8461#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8458#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8455#L438-3 assume !(0 == ~E_2~0); 8452#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8449#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8446#L197-12 assume !(1 == ~m_pc~0); 8443#L197-14 is_master_triggered_~__retres1~0#1 := 0; 8440#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8437#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8434#L510-12 assume !(0 != activate_threads_~tmp~1#1); 8431#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8428#L216-12 assume !(1 == ~t1_pc~0); 8427#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 8426#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8425#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8424#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8423#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8422#L235-12 assume !(1 == ~t2_pc~0); 8419#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 8417#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8415#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8413#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8411#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8409#L254-12 assume !(1 == ~t3_pc~0); 8407#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 8405#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8403#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8401#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8399#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8397#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8395#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8392#L466-3 assume !(1 == ~T2_E~0); 8390#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8388#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8386#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8384#L486-3 assume !(1 == ~E_3~0); 8382#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8378#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8374#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8372#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 8369#L671 assume !(0 == start_simulation_~tmp~3#1); 8367#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8363#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8362#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8360#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 8358#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8356#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8354#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 8352#L684 assume !(0 != start_simulation_~tmp___0~1#1); 6986#L652-2 [2022-11-16 10:54:14,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:14,849 INFO L85 PathProgramCache]: Analyzing trace with hash 372621552, now seen corresponding path program 1 times [2022-11-16 10:54:14,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:14,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619472129] [2022-11-16 10:54:14,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:14,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:14,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:14,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:14,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:14,904 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619472129] [2022-11-16 10:54:14,904 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619472129] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:14,904 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:14,904 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:14,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545637345] [2022-11-16 10:54:14,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:14,905 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:14,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:14,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1016438343, now seen corresponding path program 1 times [2022-11-16 10:54:14,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:14,906 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858412699] [2022-11-16 10:54:14,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:14,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:14,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:14,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:14,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:14,942 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858412699] [2022-11-16 10:54:14,942 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858412699] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:14,942 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:14,942 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:14,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952550695] [2022-11-16 10:54:14,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:14,943 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:14,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:14,944 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:54:14,944 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:54:14,944 INFO L87 Difference]: Start difference. First operand 1726 states and 2430 transitions. cyclomatic complexity: 708 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:15,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:15,025 INFO L93 Difference]: Finished difference Result 3758 states and 5248 transitions. [2022-11-16 10:54:15,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3758 states and 5248 transitions. [2022-11-16 10:54:15,052 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3641 [2022-11-16 10:54:15,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3758 states to 3758 states and 5248 transitions. [2022-11-16 10:54:15,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3758 [2022-11-16 10:54:15,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3758 [2022-11-16 10:54:15,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3758 states and 5248 transitions. [2022-11-16 10:54:15,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:15,083 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3758 states and 5248 transitions. [2022-11-16 10:54:15,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3758 states and 5248 transitions. [2022-11-16 10:54:15,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3758 to 2078. [2022-11-16 10:54:15,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2078 states, 2078 states have (on average 1.3941289701636188) internal successors, (2897), 2077 states have internal predecessors, (2897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:15,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2078 states to 2078 states and 2897 transitions. [2022-11-16 10:54:15,156 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2078 states and 2897 transitions. [2022-11-16 10:54:15,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 10:54:15,161 INFO L428 stractBuchiCegarLoop]: Abstraction has 2078 states and 2897 transitions. [2022-11-16 10:54:15,161 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 10:54:15,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2078 states and 2897 transitions. [2022-11-16 10:54:15,175 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1980 [2022-11-16 10:54:15,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:15,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:15,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:15,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:15,177 INFO L748 eck$LassoCheckResult]: Stem: 12720#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 12652#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12617#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12559#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12560#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 12625#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12441#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12442#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12667#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12403#L418 assume !(0 == ~M_E~0); 12404#L418-2 assume !(0 == ~T1_E~0); 12624#L423-1 assume !(0 == ~T2_E~0); 12672#L428-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12669#L433-1 assume !(0 == ~E_1~0); 12670#L438-1 assume !(0 == ~E_2~0); 12577#L443-1 assume !(0 == ~E_3~0); 12570#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12571#L197 assume !(1 == ~m_pc~0); 12749#L197-2 is_master_triggered_~__retres1~0#1 := 0; 12748#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12714#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12682#L510 assume !(0 != activate_threads_~tmp~1#1); 12683#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12746#L216 assume !(1 == ~t1_pc~0); 12745#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12744#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12743#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12742#L518 assume !(0 != activate_threads_~tmp___0~0#1); 12586#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12587#L235 assume !(1 == ~t2_pc~0); 12741#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12516#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12517#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12583#L526 assume !(0 != activate_threads_~tmp___1~0#1); 12693#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12702#L254 assume !(1 == ~t3_pc~0); 12445#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12446#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12399#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12400#L534 assume !(0 != activate_threads_~tmp___2~0#1); 12556#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12735#L461 assume !(1 == ~M_E~0); 12734#L461-2 assume !(1 == ~T1_E~0); 12733#L466-1 assume !(1 == ~T2_E~0); 12732#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12466#L476-1 assume !(1 == ~E_1~0); 12467#L481-1 assume !(1 == ~E_2~0); 12606#L486-1 assume !(1 == ~E_3~0); 12479#L491-1 assume { :end_inline_reset_delta_events } true; 12395#L652-2 [2022-11-16 10:54:15,177 INFO L750 eck$LassoCheckResult]: Loop: 12395#L652-2 assume !false; 12396#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13434#L393 assume !false; 13432#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13389#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13383#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13378#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13374#L346 assume !(0 != eval_~tmp~0#1); 13375#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14126#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14121#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14116#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14111#L423-3 assume !(0 == ~T2_E~0); 14073#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14072#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14071#L438-3 assume !(0 == ~E_2~0); 14070#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14069#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14068#L197-12 assume !(1 == ~m_pc~0); 14067#L197-14 is_master_triggered_~__retres1~0#1 := 0; 14066#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14065#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14064#L510-12 assume !(0 != activate_threads_~tmp~1#1); 14063#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14062#L216-12 assume !(1 == ~t1_pc~0); 14061#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 14060#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14059#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14058#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14057#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14056#L235-12 assume !(1 == ~t2_pc~0); 14054#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 14053#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14052#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14051#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14050#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14049#L254-12 assume !(1 == ~t3_pc~0); 14048#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 14047#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14046#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14045#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14044#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14043#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14042#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14041#L466-3 assume !(1 == ~T2_E~0); 14039#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14037#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12582#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12524#L486-3 assume !(1 == ~E_3~0); 12525#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12414#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12415#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12444#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 12470#L671 assume !(0 == start_simulation_~tmp~3#1); 12595#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 14315#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12605#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12557#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 12558#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12609#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12610#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 12616#L684 assume !(0 != start_simulation_~tmp___0~1#1); 12395#L652-2 [2022-11-16 10:54:15,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:15,178 INFO L85 PathProgramCache]: Analyzing trace with hash -286909970, now seen corresponding path program 1 times [2022-11-16 10:54:15,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:15,179 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [879690172] [2022-11-16 10:54:15,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:15,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:15,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:15,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:15,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:15,232 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [879690172] [2022-11-16 10:54:15,233 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [879690172] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:15,233 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:15,233 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:15,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940530684] [2022-11-16 10:54:15,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:15,234 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:15,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:15,235 INFO L85 PathProgramCache]: Analyzing trace with hash -1016438343, now seen corresponding path program 2 times [2022-11-16 10:54:15,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:15,235 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84940046] [2022-11-16 10:54:15,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:15,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:15,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:15,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:15,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:15,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84940046] [2022-11-16 10:54:15,294 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84940046] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:15,295 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:15,295 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:15,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996751549] [2022-11-16 10:54:15,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:15,296 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:15,296 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:15,296 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:54:15,296 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:54:15,297 INFO L87 Difference]: Start difference. First operand 2078 states and 2897 transitions. cyclomatic complexity: 823 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:15,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:15,330 INFO L93 Difference]: Finished difference Result 1726 states and 2401 transitions. [2022-11-16 10:54:15,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1726 states and 2401 transitions. [2022-11-16 10:54:15,341 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1661 [2022-11-16 10:54:15,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1726 states to 1726 states and 2401 transitions. [2022-11-16 10:54:15,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1726 [2022-11-16 10:54:15,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1726 [2022-11-16 10:54:15,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1726 states and 2401 transitions. [2022-11-16 10:54:15,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:15,355 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1726 states and 2401 transitions. [2022-11-16 10:54:15,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1726 states and 2401 transitions. [2022-11-16 10:54:15,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1726 to 1726. [2022-11-16 10:54:15,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1726 states, 1726 states have (on average 1.3910776361529549) internal successors, (2401), 1725 states have internal predecessors, (2401), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:15,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1726 states to 1726 states and 2401 transitions. [2022-11-16 10:54:15,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1726 states and 2401 transitions. [2022-11-16 10:54:15,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:15,387 INFO L428 stractBuchiCegarLoop]: Abstraction has 1726 states and 2401 transitions. [2022-11-16 10:54:15,387 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 10:54:15,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1726 states and 2401 transitions. [2022-11-16 10:54:15,397 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1661 [2022-11-16 10:54:15,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:15,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:15,404 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:15,404 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:15,405 INFO L748 eck$LassoCheckResult]: Stem: 16516#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 16459#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16424#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16369#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16370#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 16434#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16255#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16256#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16473#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16217#L418 assume !(0 == ~M_E~0); 16218#L418-2 assume !(0 == ~T1_E~0); 16433#L423-1 assume !(0 == ~T2_E~0); 16479#L428-1 assume !(0 == ~T3_E~0); 16477#L433-1 assume !(0 == ~E_1~0); 16462#L438-1 assume !(0 == ~E_2~0); 16387#L443-1 assume !(0 == ~E_3~0); 16381#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16342#L197 assume !(1 == ~m_pc~0); 16343#L197-2 is_master_triggered_~__retres1~0#1 := 0; 16508#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16509#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16488#L510 assume !(0 != activate_threads_~tmp~1#1); 16201#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16202#L216 assume !(1 == ~t1_pc~0); 16251#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16252#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16366#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16203#L518 assume !(0 != activate_threads_~tmp___0~0#1); 16204#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16395#L235 assume !(1 == ~t2_pc~0); 16469#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16329#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16330#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16392#L526 assume !(0 != activate_threads_~tmp___1~0#1); 16497#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16319#L254 assume !(1 == ~t3_pc~0); 16259#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16260#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16213#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16214#L534 assume !(0 != activate_threads_~tmp___2~0#1); 16324#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16193#L461 assume !(1 == ~M_E~0); 16194#L461-2 assume !(1 == ~T1_E~0); 16257#L466-1 assume !(1 == ~T2_E~0); 16482#L471-1 assume !(1 == ~T3_E~0); 16280#L476-1 assume !(1 == ~E_1~0); 16281#L481-1 assume !(1 == ~E_2~0); 16411#L486-1 assume !(1 == ~E_3~0); 16293#L491-1 assume { :end_inline_reset_delta_events } true; 16294#L652-2 [2022-11-16 10:54:15,405 INFO L750 eck$LassoCheckResult]: Loop: 16294#L652-2 assume !false; 17710#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16373#L393 assume !false; 17700#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17696#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16428#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16429#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16297#L346 assume !(0 != eval_~tmp~0#1); 16298#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16486#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16487#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16393#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16394#L423-3 assume !(0 == ~T2_E~0); 16391#L428-3 assume !(0 == ~T3_E~0); 16340#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16341#L438-3 assume !(0 == ~E_2~0); 16442#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16195#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16196#L197-12 assume !(1 == ~m_pc~0); 16449#L197-14 is_master_triggered_~__retres1~0#1 := 0; 16313#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16314#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16207#L510-12 assume !(0 != activate_threads_~tmp~1#1); 16208#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16311#L216-12 assume !(1 == ~t1_pc~0); 16312#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 16357#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16276#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16277#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16253#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16254#L235-12 assume !(1 == ~t2_pc~0); 16327#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 16328#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16494#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16495#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16382#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16383#L254-12 assume !(1 == ~t3_pc~0); 16489#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 16385#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16386#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16361#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16362#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16412#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17835#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17833#L466-3 assume !(1 == ~T2_E~0); 17831#L471-3 assume !(1 == ~T3_E~0); 17829#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17827#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17825#L486-3 assume !(1 == ~E_3~0); 17823#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17819#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17815#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17813#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 17786#L671 assume !(0 == start_simulation_~tmp~3#1); 17783#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17752#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17747#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17741#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 17736#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17727#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17722#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 17717#L684 assume !(0 != start_simulation_~tmp___0~1#1); 16294#L652-2 [2022-11-16 10:54:15,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:15,406 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2022-11-16 10:54:15,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:15,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988976871] [2022-11-16 10:54:15,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:15,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:15,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:15,419 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:15,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:15,466 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:15,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:15,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1674662333, now seen corresponding path program 1 times [2022-11-16 10:54:15,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:15,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082714377] [2022-11-16 10:54:15,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:15,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:15,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:15,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:15,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:15,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082714377] [2022-11-16 10:54:15,537 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082714377] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:15,537 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:15,538 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:15,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613438409] [2022-11-16 10:54:15,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:15,539 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:15,539 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:15,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:15,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:15,541 INFO L87 Difference]: Start difference. First operand 1726 states and 2401 transitions. cyclomatic complexity: 679 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:15,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:15,620 INFO L93 Difference]: Finished difference Result 2471 states and 3420 transitions. [2022-11-16 10:54:15,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2471 states and 3420 transitions. [2022-11-16 10:54:15,648 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2373 [2022-11-16 10:54:15,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2471 states to 2471 states and 3420 transitions. [2022-11-16 10:54:15,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2471 [2022-11-16 10:54:15,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2471 [2022-11-16 10:54:15,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2471 states and 3420 transitions. [2022-11-16 10:54:15,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:15,681 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2471 states and 3420 transitions. [2022-11-16 10:54:15,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2471 states and 3420 transitions. [2022-11-16 10:54:15,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2471 to 2467. [2022-11-16 10:54:15,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2467 states, 2467 states have (on average 1.3846777462505067) internal successors, (3416), 2466 states have internal predecessors, (3416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:15,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2467 states to 2467 states and 3416 transitions. [2022-11-16 10:54:15,744 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2467 states and 3416 transitions. [2022-11-16 10:54:15,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:15,746 INFO L428 stractBuchiCegarLoop]: Abstraction has 2467 states and 3416 transitions. [2022-11-16 10:54:15,746 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 10:54:15,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2467 states and 3416 transitions. [2022-11-16 10:54:15,757 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2369 [2022-11-16 10:54:15,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:15,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:15,758 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:15,758 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:15,759 INFO L748 eck$LassoCheckResult]: Stem: 20737#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 20663#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20628#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20574#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20575#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 20637#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20457#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20458#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20678#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20420#L418 assume !(0 == ~M_E~0); 20421#L418-2 assume !(0 == ~T1_E~0); 20636#L423-1 assume !(0 == ~T2_E~0); 20684#L428-1 assume !(0 == ~T3_E~0); 20682#L433-1 assume !(0 == ~E_1~0); 20666#L438-1 assume !(0 == ~E_2~0); 20593#L443-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20586#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20587#L197 assume !(1 == ~m_pc~0); 20716#L197-2 is_master_triggered_~__retres1~0#1 := 0; 20717#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20725#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20726#L510 assume !(0 != activate_threads_~tmp~1#1); 20404#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20405#L216 assume !(1 == ~t1_pc~0); 20453#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20454#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20570#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20571#L518 assume !(0 != activate_threads_~tmp___0~0#1); 20600#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20601#L235 assume !(1 == ~t2_pc~0); 20673#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20674#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20759#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20754#L526 assume !(0 != activate_threads_~tmp___1~0#1); 20753#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20522#L254 assume !(1 == ~t3_pc~0); 20461#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20462#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20416#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20417#L534 assume !(0 != activate_threads_~tmp___2~0#1); 20528#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20396#L461 assume !(1 == ~M_E~0); 20397#L461-2 assume !(1 == ~T1_E~0); 20459#L466-1 assume !(1 == ~T2_E~0); 20687#L471-1 assume !(1 == ~T3_E~0); 20482#L476-1 assume !(1 == ~E_1~0); 20483#L481-1 assume !(1 == ~E_2~0); 20617#L486-1 assume 1 == ~E_3~0;~E_3~0 := 2; 20495#L491-1 assume { :end_inline_reset_delta_events } true; 20412#L652-2 [2022-11-16 10:54:15,759 INFO L750 eck$LassoCheckResult]: Loop: 20412#L652-2 assume !false; 20413#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22634#L393 assume !false; 20476#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20477#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20451#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20631#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20498#L346 assume !(0 != eval_~tmp~0#1); 20499#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22633#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22632#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22631#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22630#L423-3 assume !(0 == ~T2_E~0); 22629#L428-3 assume !(0 == ~T3_E~0); 22628#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22627#L438-3 assume !(0 == ~E_2~0); 22626#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22624#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22622#L197-12 assume !(1 == ~m_pc~0); 22620#L197-14 is_master_triggered_~__retres1~0#1 := 0; 22618#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22616#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 22614#L510-12 assume !(0 != activate_threads_~tmp~1#1); 22612#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22610#L216-12 assume !(1 == ~t1_pc~0); 22608#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 22606#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22604#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22602#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22600#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22598#L235-12 assume !(1 == ~t2_pc~0); 22594#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 22592#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22590#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22588#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22586#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22584#L254-12 assume !(1 == ~t3_pc~0); 22582#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 22580#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22578#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22576#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22574#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22572#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22570#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22568#L466-3 assume !(1 == ~T2_E~0); 22566#L471-3 assume !(1 == ~T3_E~0); 22564#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22562#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22561#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22559#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20431#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20432#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20460#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 20486#L671 assume !(0 == start_simulation_~tmp~3#1); 20419#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20641#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20509#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20572#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 20573#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20620#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20621#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 20627#L684 assume !(0 != start_simulation_~tmp___0~1#1); 20412#L652-2 [2022-11-16 10:54:15,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:15,760 INFO L85 PathProgramCache]: Analyzing trace with hash -1676515466, now seen corresponding path program 1 times [2022-11-16 10:54:15,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:15,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918217404] [2022-11-16 10:54:15,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:15,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:15,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:15,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:15,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:15,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [918217404] [2022-11-16 10:54:15,811 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [918217404] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:15,811 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:15,812 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:15,812 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1630410508] [2022-11-16 10:54:15,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:15,812 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:15,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:15,813 INFO L85 PathProgramCache]: Analyzing trace with hash -1609187713, now seen corresponding path program 1 times [2022-11-16 10:54:15,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:15,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812107934] [2022-11-16 10:54:15,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:15,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:15,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:15,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:15,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:15,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812107934] [2022-11-16 10:54:15,876 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [812107934] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:15,877 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:15,877 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 10:54:15,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743958564] [2022-11-16 10:54:15,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:15,877 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:15,878 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:15,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:54:15,879 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:54:15,879 INFO L87 Difference]: Start difference. First operand 2467 states and 3416 transitions. cyclomatic complexity: 953 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:15,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:15,982 INFO L93 Difference]: Finished difference Result 4256 states and 5949 transitions. [2022-11-16 10:54:15,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4256 states and 5949 transitions. [2022-11-16 10:54:16,012 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 3936 [2022-11-16 10:54:16,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4256 states to 4256 states and 5949 transitions. [2022-11-16 10:54:16,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4256 [2022-11-16 10:54:16,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4256 [2022-11-16 10:54:16,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4256 states and 5949 transitions. [2022-11-16 10:54:16,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:16,100 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4256 states and 5949 transitions. [2022-11-16 10:54:16,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4256 states and 5949 transitions. [2022-11-16 10:54:16,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4256 to 2279. [2022-11-16 10:54:16,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2279 states, 2279 states have (on average 1.3892057920140413) internal successors, (3166), 2278 states have internal predecessors, (3166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:16,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2279 states to 2279 states and 3166 transitions. [2022-11-16 10:54:16,159 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2279 states and 3166 transitions. [2022-11-16 10:54:16,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 10:54:16,160 INFO L428 stractBuchiCegarLoop]: Abstraction has 2279 states and 3166 transitions. [2022-11-16 10:54:16,160 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 10:54:16,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2279 states and 3166 transitions. [2022-11-16 10:54:16,171 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2214 [2022-11-16 10:54:16,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:16,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:16,173 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:16,173 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:16,173 INFO L748 eck$LassoCheckResult]: Stem: 27477#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 27402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 27367#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27311#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27312#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 27376#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27191#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27192#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27419#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27159#L418 assume !(0 == ~M_E~0); 27160#L418-2 assume !(0 == ~T1_E~0); 27375#L423-1 assume !(0 == ~T2_E~0); 27424#L428-1 assume !(0 == ~T3_E~0); 27422#L433-1 assume !(0 == ~E_1~0); 27407#L438-1 assume !(0 == ~E_2~0); 27332#L443-1 assume !(0 == ~E_3~0); 27325#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27282#L197 assume !(1 == ~m_pc~0); 27283#L197-2 is_master_triggered_~__retres1~0#1 := 0; 27459#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27463#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 27436#L510 assume !(0 != activate_threads_~tmp~1#1); 27139#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27140#L216 assume !(1 == ~t1_pc~0); 27189#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27190#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27308#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27141#L518 assume !(0 != activate_threads_~tmp___0~0#1); 27142#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27340#L235 assume !(1 == ~t2_pc~0); 27415#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27273#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27274#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27335#L526 assume !(0 != activate_threads_~tmp___1~0#1); 27444#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27260#L254 assume !(1 == ~t3_pc~0); 27195#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 27196#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27151#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27152#L534 assume !(0 != activate_threads_~tmp___2~0#1); 27265#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27131#L461 assume !(1 == ~M_E~0); 27132#L461-2 assume !(1 == ~T1_E~0); 27193#L466-1 assume !(1 == ~T2_E~0); 27428#L471-1 assume !(1 == ~T3_E~0); 27217#L476-1 assume !(1 == ~E_1~0); 27218#L481-1 assume !(1 == ~E_2~0); 27356#L486-1 assume !(1 == ~E_3~0); 27232#L491-1 assume { :end_inline_reset_delta_events } true; 27233#L652-2 [2022-11-16 10:54:16,173 INFO L750 eck$LassoCheckResult]: Loop: 27233#L652-2 assume !false; 28088#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28085#L393 assume !false; 28065#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28059#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28044#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28040#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28035#L346 assume !(0 != eval_~tmp~0#1); 28036#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29312#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29311#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29309#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29307#L423-3 assume !(0 == ~T2_E~0); 29305#L428-3 assume !(0 == ~T3_E~0); 29303#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29302#L438-3 assume !(0 == ~E_2~0); 29301#L443-3 assume !(0 == ~E_3~0); 29300#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29299#L197-12 assume !(1 == ~m_pc~0); 29298#L197-14 is_master_triggered_~__retres1~0#1 := 0; 29297#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29296#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 29295#L510-12 assume !(0 != activate_threads_~tmp~1#1); 29294#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29293#L216-12 assume !(1 == ~t1_pc~0); 29292#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 29291#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29290#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29289#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29288#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29287#L235-12 assume !(1 == ~t2_pc~0); 29285#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 29284#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29283#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 29282#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29280#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29278#L254-12 assume !(1 == ~t3_pc~0); 29276#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 29274#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29272#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29270#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29267#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29265#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29263#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29261#L466-3 assume !(1 == ~T2_E~0); 29259#L471-3 assume !(1 == ~T3_E~0); 29258#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28908#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28157#L486-3 assume !(1 == ~E_3~0); 28152#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28148#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28144#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28142#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 28139#L671 assume !(0 == start_simulation_~tmp~3#1); 28136#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28125#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28122#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28119#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 28116#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28113#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28110#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 28107#L684 assume !(0 != start_simulation_~tmp___0~1#1); 27233#L652-2 [2022-11-16 10:54:16,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:16,174 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2022-11-16 10:54:16,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:16,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399358544] [2022-11-16 10:54:16,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:16,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:16,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:16,184 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:16,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:16,198 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:16,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:16,199 INFO L85 PathProgramCache]: Analyzing trace with hash -692032261, now seen corresponding path program 1 times [2022-11-16 10:54:16,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:16,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538619913] [2022-11-16 10:54:16,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:16,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:16,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:16,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:16,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:16,256 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538619913] [2022-11-16 10:54:16,260 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538619913] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:16,261 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:16,261 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 10:54:16,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814847238] [2022-11-16 10:54:16,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:16,262 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:16,262 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:16,262 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 10:54:16,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 10:54:16,262 INFO L87 Difference]: Start difference. First operand 2279 states and 3166 transitions. cyclomatic complexity: 891 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:16,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:16,379 INFO L93 Difference]: Finished difference Result 3900 states and 5349 transitions. [2022-11-16 10:54:16,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3900 states and 5349 transitions. [2022-11-16 10:54:16,399 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3820 [2022-11-16 10:54:16,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3900 states to 3900 states and 5349 transitions. [2022-11-16 10:54:16,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3900 [2022-11-16 10:54:16,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3900 [2022-11-16 10:54:16,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3900 states and 5349 transitions. [2022-11-16 10:54:16,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:16,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3900 states and 5349 transitions. [2022-11-16 10:54:16,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3900 states and 5349 transitions. [2022-11-16 10:54:16,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3900 to 2318. [2022-11-16 10:54:16,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2318 states, 2318 states have (on average 1.3826574633304574) internal successors, (3205), 2317 states have internal predecessors, (3205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:16,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2318 states to 2318 states and 3205 transitions. [2022-11-16 10:54:16,500 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2318 states and 3205 transitions. [2022-11-16 10:54:16,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 10:54:16,501 INFO L428 stractBuchiCegarLoop]: Abstraction has 2318 states and 3205 transitions. [2022-11-16 10:54:16,501 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 10:54:16,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2318 states and 3205 transitions. [2022-11-16 10:54:16,511 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2253 [2022-11-16 10:54:16,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:16,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:16,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:16,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:16,536 INFO L748 eck$LassoCheckResult]: Stem: 33685#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 33613#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 33573#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33511#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33512#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 33584#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33388#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33389#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33627#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33350#L418 assume !(0 == ~M_E~0); 33351#L418-2 assume !(0 == ~T1_E~0); 33583#L423-1 assume !(0 == ~T2_E~0); 33631#L428-1 assume !(0 == ~T3_E~0); 33629#L433-1 assume !(0 == ~E_1~0); 33616#L438-1 assume !(0 == ~E_2~0); 33530#L443-1 assume !(0 == ~E_3~0); 33522#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33480#L197 assume !(1 == ~m_pc~0); 33481#L197-2 is_master_triggered_~__retres1~0#1 := 0; 33671#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33674#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 33646#L510 assume !(0 != activate_threads_~tmp~1#1); 33334#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33335#L216 assume !(1 == ~t1_pc~0); 33386#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33387#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33508#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33336#L518 assume !(0 != activate_threads_~tmp___0~0#1); 33337#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33542#L235 assume !(1 == ~t2_pc~0); 33623#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33467#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33468#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33536#L526 assume !(0 != activate_threads_~tmp___1~0#1); 33658#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33457#L254 assume !(1 == ~t3_pc~0); 33392#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33393#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33346#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33347#L534 assume !(0 != activate_threads_~tmp___2~0#1); 33462#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33326#L461 assume !(1 == ~M_E~0); 33327#L461-2 assume !(1 == ~T1_E~0); 33390#L466-1 assume !(1 == ~T2_E~0); 33636#L471-1 assume !(1 == ~T3_E~0); 33413#L476-1 assume !(1 == ~E_1~0); 33414#L481-1 assume !(1 == ~E_2~0); 33557#L486-1 assume !(1 == ~E_3~0); 33429#L491-1 assume { :end_inline_reset_delta_events } true; 33430#L652-2 [2022-11-16 10:54:16,536 INFO L750 eck$LassoCheckResult]: Loop: 33430#L652-2 assume !false; 35374#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35373#L393 assume !false; 35372#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35366#L309 assume !(0 == ~m_st~0); 35362#L313 assume !(0 == ~t1_st~0); 35363#L317 assume !(0 == ~t2_st~0); 35364#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 35365#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 35243#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35244#L346 assume !(0 != eval_~tmp~0#1); 35354#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35485#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35484#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35483#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35482#L423-3 assume !(0 == ~T2_E~0); 35481#L428-3 assume !(0 == ~T3_E~0); 35480#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35479#L438-3 assume !(0 == ~E_2~0); 35478#L443-3 assume !(0 == ~E_3~0); 35477#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35476#L197-12 assume !(1 == ~m_pc~0); 35475#L197-14 is_master_triggered_~__retres1~0#1 := 0; 35474#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35473#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 35472#L510-12 assume !(0 != activate_threads_~tmp~1#1); 35471#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35470#L216-12 assume !(1 == ~t1_pc~0); 35469#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 35468#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35467#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35466#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35465#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35464#L235-12 assume !(1 == ~t2_pc~0); 35462#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 35461#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35460#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35459#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35458#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35457#L254-12 assume !(1 == ~t3_pc~0); 35456#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 35455#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35454#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35453#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35452#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35451#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35450#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35449#L466-3 assume !(1 == ~T2_E~0); 35448#L471-3 assume !(1 == ~T3_E~0); 35447#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35446#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35445#L486-3 assume !(1 == ~E_3~0); 35444#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35442#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 35437#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 35434#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 35432#L671 assume !(0 == start_simulation_~tmp~3#1); 35402#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35398#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 35397#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 35395#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 35393#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35391#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35389#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 35387#L684 assume !(0 != start_simulation_~tmp___0~1#1); 33430#L652-2 [2022-11-16 10:54:16,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:16,537 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2022-11-16 10:54:16,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:16,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665516386] [2022-11-16 10:54:16,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:16,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:16,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:16,549 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:16,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:16,576 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:16,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:16,579 INFO L85 PathProgramCache]: Analyzing trace with hash -922351627, now seen corresponding path program 1 times [2022-11-16 10:54:16,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:16,579 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478996131] [2022-11-16 10:54:16,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:16,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:16,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:16,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:16,617 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:16,617 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1478996131] [2022-11-16 10:54:16,617 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1478996131] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:16,618 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:16,618 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:16,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436518317] [2022-11-16 10:54:16,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:16,619 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:54:16,619 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:16,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:16,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:16,620 INFO L87 Difference]: Start difference. First operand 2318 states and 3205 transitions. cyclomatic complexity: 891 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:16,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:16,679 INFO L93 Difference]: Finished difference Result 3602 states and 4906 transitions. [2022-11-16 10:54:16,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3602 states and 4906 transitions. [2022-11-16 10:54:16,701 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3535 [2022-11-16 10:54:16,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3602 states to 3602 states and 4906 transitions. [2022-11-16 10:54:16,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3602 [2022-11-16 10:54:16,721 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3602 [2022-11-16 10:54:16,721 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3602 states and 4906 transitions. [2022-11-16 10:54:16,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:16,727 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3602 states and 4906 transitions. [2022-11-16 10:54:16,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3602 states and 4906 transitions. [2022-11-16 10:54:16,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3602 to 3416. [2022-11-16 10:54:16,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3416 states, 3416 states have (on average 1.3659250585480094) internal successors, (4666), 3415 states have internal predecessors, (4666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:16,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3416 states to 3416 states and 4666 transitions. [2022-11-16 10:54:16,797 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3416 states and 4666 transitions. [2022-11-16 10:54:16,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:16,798 INFO L428 stractBuchiCegarLoop]: Abstraction has 3416 states and 4666 transitions. [2022-11-16 10:54:16,799 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 10:54:16,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3416 states and 4666 transitions. [2022-11-16 10:54:16,814 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3349 [2022-11-16 10:54:16,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:16,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:16,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:16,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:16,816 INFO L748 eck$LassoCheckResult]: Stem: 39587#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 39519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 39480#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39428#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39429#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 39490#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39312#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39313#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39533#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39276#L418 assume !(0 == ~M_E~0); 39277#L418-2 assume !(0 == ~T1_E~0); 39489#L423-1 assume !(0 == ~T2_E~0); 39540#L428-1 assume !(0 == ~T3_E~0); 39538#L433-1 assume !(0 == ~E_1~0); 39522#L438-1 assume !(0 == ~E_2~0); 39448#L443-1 assume !(0 == ~E_3~0); 39442#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39400#L197 assume !(1 == ~m_pc~0); 39401#L197-2 is_master_triggered_~__retres1~0#1 := 0; 39574#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39577#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 39550#L510 assume !(0 != activate_threads_~tmp~1#1); 39260#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39261#L216 assume !(1 == ~t1_pc~0); 39308#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39309#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39425#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 39262#L518 assume !(0 != activate_threads_~tmp___0~0#1); 39263#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39454#L235 assume !(1 == ~t2_pc~0); 39529#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39389#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39390#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 39451#L526 assume !(0 != activate_threads_~tmp___1~0#1); 39558#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39378#L254 assume !(1 == ~t3_pc~0); 39317#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39318#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39272#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39273#L534 assume !(0 != activate_threads_~tmp___2~0#1); 39384#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39252#L461 assume !(1 == ~M_E~0); 39253#L461-2 assume !(1 == ~T1_E~0); 39314#L466-1 assume !(1 == ~T2_E~0); 39545#L471-1 assume !(1 == ~T3_E~0); 39338#L476-1 assume !(1 == ~E_1~0); 39339#L481-1 assume !(1 == ~E_2~0); 39470#L486-1 assume !(1 == ~E_3~0); 39352#L491-1 assume { :end_inline_reset_delta_events } true; 39353#L652-2 assume !false; 41357#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41355#L393 [2022-11-16 10:54:16,816 INFO L750 eck$LassoCheckResult]: Loop: 41355#L393 assume !false; 41353#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 41350#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 41348#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 41346#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 41343#L346 assume 0 != eval_~tmp~0#1; 41341#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 41135#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 41130#L351 assume !(0 == ~t1_st~0); 40829#L365 assume !(0 == ~t2_st~0); 41359#L379 assume !(0 == ~t3_st~0); 41355#L393 [2022-11-16 10:54:16,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:16,816 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 1 times [2022-11-16 10:54:16,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:16,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660896267] [2022-11-16 10:54:16,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:16,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:16,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:16,826 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:16,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:16,848 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:16,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:16,851 INFO L85 PathProgramCache]: Analyzing trace with hash 1064760425, now seen corresponding path program 1 times [2022-11-16 10:54:16,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:16,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540179871] [2022-11-16 10:54:16,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:16,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:16,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:16,857 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:16,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:16,861 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:16,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:16,862 INFO L85 PathProgramCache]: Analyzing trace with hash -787959978, now seen corresponding path program 1 times [2022-11-16 10:54:16,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:16,863 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28466046] [2022-11-16 10:54:16,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:16,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:16,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:16,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:16,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:16,908 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [28466046] [2022-11-16 10:54:16,909 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [28466046] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:16,909 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:16,909 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:16,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752674338] [2022-11-16 10:54:16,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:17,017 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:17,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:17,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:17,018 INFO L87 Difference]: Start difference. First operand 3416 states and 4666 transitions. cyclomatic complexity: 1257 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:17,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:17,171 INFO L93 Difference]: Finished difference Result 6131 states and 8279 transitions. [2022-11-16 10:54:17,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6131 states and 8279 transitions. [2022-11-16 10:54:17,204 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5763 [2022-11-16 10:54:17,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6131 states to 6131 states and 8279 transitions. [2022-11-16 10:54:17,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6131 [2022-11-16 10:54:17,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6131 [2022-11-16 10:54:17,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6131 states and 8279 transitions. [2022-11-16 10:54:17,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:17,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6131 states and 8279 transitions. [2022-11-16 10:54:17,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6131 states and 8279 transitions. [2022-11-16 10:54:17,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6131 to 5959. [2022-11-16 10:54:17,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5959 states, 5959 states have (on average 1.3527437489511662) internal successors, (8061), 5958 states have internal predecessors, (8061), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:17,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5959 states to 5959 states and 8061 transitions. [2022-11-16 10:54:17,383 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5959 states and 8061 transitions. [2022-11-16 10:54:17,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:17,384 INFO L428 stractBuchiCegarLoop]: Abstraction has 5959 states and 8061 transitions. [2022-11-16 10:54:17,385 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 10:54:17,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5959 states and 8061 transitions. [2022-11-16 10:54:17,409 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5591 [2022-11-16 10:54:17,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:17,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:17,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:17,415 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:17,415 INFO L748 eck$LassoCheckResult]: Stem: 49188#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 49090#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 49052#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48996#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48997#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 49064#L281-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 48866#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48867#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49120#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49121#L418 assume !(0 == ~M_E~0); 49062#L418-2 assume !(0 == ~T1_E~0); 49063#L423-1 assume !(0 == ~T2_E~0); 49124#L428-1 assume !(0 == ~T3_E~0); 49125#L433-1 assume !(0 == ~E_1~0); 49093#L438-1 assume !(0 == ~E_2~0); 49094#L443-1 assume !(0 == ~E_3~0); 49008#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49009#L197 assume !(1 == ~m_pc~0); 49161#L197-2 is_master_triggered_~__retres1~0#1 := 0; 49162#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49175#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 49176#L510 assume !(0 != activate_threads_~tmp~1#1); 48815#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48816#L216 assume !(1 == ~t1_pc~0); 48862#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48863#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48990#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 48991#L518 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48818#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49181#L235 assume !(1 == ~t2_pc~0); 49182#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48949#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48950#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 49147#L526 assume !(0 != activate_threads_~tmp___1~0#1); 49148#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48934#L254 assume !(1 == ~t3_pc~0); 48935#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48959#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48960#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48992#L534 assume !(0 != activate_threads_~tmp___2~0#1); 48993#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48807#L461 assume !(1 == ~M_E~0); 48808#L461-2 assume !(1 == ~T1_E~0); 49122#L466-1 assume !(1 == ~T2_E~0); 49123#L471-1 assume !(1 == ~T3_E~0); 48894#L476-1 assume !(1 == ~E_1~0); 48895#L481-1 assume !(1 == ~E_2~0); 49038#L486-1 assume !(1 == ~E_3~0); 49039#L491-1 assume { :end_inline_reset_delta_events } true; 49703#L652-2 assume !false; 49704#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49732#L393 [2022-11-16 10:54:17,415 INFO L750 eck$LassoCheckResult]: Loop: 49732#L393 assume !false; 49729#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 49730#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 49725#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 49726#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49723#L346 assume 0 != eval_~tmp~0#1; 49724#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 49718#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 49719#L351 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 49336#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 49337#L365 assume !(0 == ~t2_st~0); 49735#L379 assume !(0 == ~t3_st~0); 49732#L393 [2022-11-16 10:54:17,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:17,416 INFO L85 PathProgramCache]: Analyzing trace with hash 1149359284, now seen corresponding path program 1 times [2022-11-16 10:54:17,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:17,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688352794] [2022-11-16 10:54:17,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:17,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:17,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:17,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:17,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:17,442 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [688352794] [2022-11-16 10:54:17,442 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [688352794] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:17,442 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:17,443 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:17,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302298914] [2022-11-16 10:54:17,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:17,443 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:54:17,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:17,444 INFO L85 PathProgramCache]: Analyzing trace with hash -1356201070, now seen corresponding path program 1 times [2022-11-16 10:54:17,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:17,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74354992] [2022-11-16 10:54:17,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:17,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:17,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:17,450 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:17,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:17,456 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:17,619 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:17,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:17,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:17,620 INFO L87 Difference]: Start difference. First operand 5959 states and 8061 transitions. cyclomatic complexity: 2113 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:17,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:17,651 INFO L93 Difference]: Finished difference Result 5058 states and 6860 transitions. [2022-11-16 10:54:17,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5058 states and 6860 transitions. [2022-11-16 10:54:17,683 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4981 [2022-11-16 10:54:17,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5058 states to 5058 states and 6860 transitions. [2022-11-16 10:54:17,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5058 [2022-11-16 10:54:17,710 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5058 [2022-11-16 10:54:17,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5058 states and 6860 transitions. [2022-11-16 10:54:17,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:17,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5058 states and 6860 transitions. [2022-11-16 10:54:17,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5058 states and 6860 transitions. [2022-11-16 10:54:17,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5058 to 5058. [2022-11-16 10:54:17,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5058 states, 5058 states have (on average 1.3562672993277975) internal successors, (6860), 5057 states have internal predecessors, (6860), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:17,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5058 states to 5058 states and 6860 transitions. [2022-11-16 10:54:17,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5058 states and 6860 transitions. [2022-11-16 10:54:17,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:17,823 INFO L428 stractBuchiCegarLoop]: Abstraction has 5058 states and 6860 transitions. [2022-11-16 10:54:17,824 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 10:54:17,824 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5058 states and 6860 transitions. [2022-11-16 10:54:17,849 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4981 [2022-11-16 10:54:17,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:17,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:17,850 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:17,850 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:17,851 INFO L748 eck$LassoCheckResult]: Stem: 60168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 60098#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 60060#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60003#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60004#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 60072#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59888#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59889#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60114#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59858#L418 assume !(0 == ~M_E~0); 59859#L418-2 assume !(0 == ~T1_E~0); 60071#L423-1 assume !(0 == ~T2_E~0); 60121#L428-1 assume !(0 == ~T3_E~0); 60118#L433-1 assume !(0 == ~E_1~0); 60103#L438-1 assume !(0 == ~E_2~0); 60024#L443-1 assume !(0 == ~E_3~0); 60015#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59976#L197 assume !(1 == ~m_pc~0); 59977#L197-2 is_master_triggered_~__retres1~0#1 := 0; 60157#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60160#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 60134#L510 assume !(0 != activate_threads_~tmp~1#1); 59838#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59839#L216 assume !(1 == ~t1_pc~0); 59886#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 59887#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60000#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 59840#L518 assume !(0 != activate_threads_~tmp___0~0#1); 59841#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60030#L235 assume !(1 == ~t2_pc~0); 60113#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59967#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59968#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 60026#L526 assume !(0 != activate_threads_~tmp___1~0#1); 60145#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59956#L254 assume !(1 == ~t3_pc~0); 59893#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59894#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59850#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 59851#L534 assume !(0 != activate_threads_~tmp___2~0#1); 59960#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59830#L461 assume !(1 == ~M_E~0); 59831#L461-2 assume !(1 == ~T1_E~0); 59890#L466-1 assume !(1 == ~T2_E~0); 60127#L471-1 assume !(1 == ~T3_E~0); 59914#L476-1 assume !(1 == ~E_1~0); 59915#L481-1 assume !(1 == ~E_2~0); 60045#L486-1 assume !(1 == ~E_3~0); 59929#L491-1 assume { :end_inline_reset_delta_events } true; 59930#L652-2 assume !false; 64156#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64154#L393 [2022-11-16 10:54:17,851 INFO L750 eck$LassoCheckResult]: Loop: 64154#L393 assume !false; 64152#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 64149#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 64140#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 60705#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 60694#L346 assume 0 != eval_~tmp~0#1; 60695#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 63532#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 60681#L351 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 60563#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 60564#L365 assume !(0 == ~t2_st~0); 64158#L379 assume !(0 == ~t3_st~0); 64154#L393 [2022-11-16 10:54:17,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:17,852 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 2 times [2022-11-16 10:54:17,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:17,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232076965] [2022-11-16 10:54:17,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:17,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:17,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:17,862 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:17,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:17,887 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:17,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:17,888 INFO L85 PathProgramCache]: Analyzing trace with hash -1356201070, now seen corresponding path program 2 times [2022-11-16 10:54:17,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:17,888 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816357835] [2022-11-16 10:54:17,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:17,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:17,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:17,894 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:17,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:17,898 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:17,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:17,899 INFO L85 PathProgramCache]: Analyzing trace with hash 1339008581, now seen corresponding path program 1 times [2022-11-16 10:54:17,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:17,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073847243] [2022-11-16 10:54:17,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:17,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:17,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:17,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:17,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:17,945 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1073847243] [2022-11-16 10:54:17,945 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1073847243] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:17,945 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:17,946 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:54:17,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010210287] [2022-11-16 10:54:17,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:18,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:18,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:18,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:18,069 INFO L87 Difference]: Start difference. First operand 5058 states and 6860 transitions. cyclomatic complexity: 1809 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:18,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:18,149 INFO L93 Difference]: Finished difference Result 8623 states and 11591 transitions. [2022-11-16 10:54:18,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8623 states and 11591 transitions. [2022-11-16 10:54:18,193 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8521 [2022-11-16 10:54:18,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8623 states to 8623 states and 11591 transitions. [2022-11-16 10:54:18,224 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8623 [2022-11-16 10:54:18,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8623 [2022-11-16 10:54:18,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8623 states and 11591 transitions. [2022-11-16 10:54:18,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:18,242 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8623 states and 11591 transitions. [2022-11-16 10:54:18,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8623 states and 11591 transitions. [2022-11-16 10:54:18,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8623 to 8323. [2022-11-16 10:54:18,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8323 states, 8323 states have (on average 1.351796227321879) internal successors, (11251), 8322 states have internal predecessors, (11251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:18,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8323 states to 8323 states and 11251 transitions. [2022-11-16 10:54:18,440 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8323 states and 11251 transitions. [2022-11-16 10:54:18,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:18,441 INFO L428 stractBuchiCegarLoop]: Abstraction has 8323 states and 11251 transitions. [2022-11-16 10:54:18,441 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 10:54:18,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8323 states and 11251 transitions. [2022-11-16 10:54:18,471 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8221 [2022-11-16 10:54:18,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:18,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:18,472 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:18,472 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:18,473 INFO L748 eck$LassoCheckResult]: Stem: 73905#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 73812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 73762#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73703#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73704#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 73773#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 73577#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73578#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73832#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73547#L418 assume !(0 == ~M_E~0); 73548#L418-2 assume !(0 == ~T1_E~0); 73772#L423-1 assume !(0 == ~T2_E~0); 73839#L428-1 assume !(0 == ~T3_E~0); 73837#L433-1 assume !(0 == ~E_1~0); 73815#L438-1 assume !(0 == ~E_2~0); 73723#L443-1 assume !(0 == ~E_3~0); 73716#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73672#L197 assume !(1 == ~m_pc~0); 73673#L197-2 is_master_triggered_~__retres1~0#1 := 0; 73888#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73893#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 73854#L510 assume !(0 != activate_threads_~tmp~1#1); 73527#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73528#L216 assume !(1 == ~t1_pc~0); 73575#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73576#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73700#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 73529#L518 assume !(0 != activate_threads_~tmp___0~0#1); 73530#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73731#L235 assume !(1 == ~t2_pc~0); 73829#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 73661#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73662#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 73726#L526 assume !(0 != activate_threads_~tmp___1~0#1); 73871#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73649#L254 assume !(1 == ~t3_pc~0); 73582#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 73583#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73539#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 73540#L534 assume !(0 != activate_threads_~tmp___2~0#1); 73654#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73519#L461 assume !(1 == ~M_E~0); 73520#L461-2 assume !(1 == ~T1_E~0); 73579#L466-1 assume !(1 == ~T2_E~0); 73849#L471-1 assume !(1 == ~T3_E~0); 73604#L476-1 assume !(1 == ~E_1~0); 73605#L481-1 assume !(1 == ~E_2~0); 73747#L486-1 assume !(1 == ~E_3~0); 73620#L491-1 assume { :end_inline_reset_delta_events } true; 73621#L652-2 assume !false; 74632#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74633#L393 [2022-11-16 10:54:18,473 INFO L750 eck$LassoCheckResult]: Loop: 74633#L393 assume !false; 80662#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 80660#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 74624#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 74622#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 74616#L346 assume 0 != eval_~tmp~0#1; 74617#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 80577#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 80576#L351 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 80575#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 80574#L365 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 74639#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 74640#L379 assume !(0 == ~t3_st~0); 74633#L393 [2022-11-16 10:54:18,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:18,474 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 3 times [2022-11-16 10:54:18,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:18,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719517193] [2022-11-16 10:54:18,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:18,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:18,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:18,483 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:18,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:18,494 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:18,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:18,495 INFO L85 PathProgramCache]: Analyzing trace with hash 907313168, now seen corresponding path program 1 times [2022-11-16 10:54:18,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:18,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119333480] [2022-11-16 10:54:18,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:18,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:18,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:18,500 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:18,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:18,504 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:18,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:18,505 INFO L85 PathProgramCache]: Analyzing trace with hash -1440533571, now seen corresponding path program 1 times [2022-11-16 10:54:18,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:18,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619934109] [2022-11-16 10:54:18,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:18,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:18,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:54:18,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:54:18,541 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:54:18,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619934109] [2022-11-16 10:54:18,541 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619934109] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:54:18,541 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:54:18,542 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 10:54:18,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361293448] [2022-11-16 10:54:18,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:54:18,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:54:18,678 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:54:18,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:54:18,679 INFO L87 Difference]: Start difference. First operand 8323 states and 11251 transitions. cyclomatic complexity: 2935 Second operand has 3 states, 2 states have (on average 32.0) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:18,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:54:18,760 INFO L93 Difference]: Finished difference Result 13454 states and 18164 transitions. [2022-11-16 10:54:18,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13454 states and 18164 transitions. [2022-11-16 10:54:18,903 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 13332 [2022-11-16 10:54:18,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13454 states to 13454 states and 18164 transitions. [2022-11-16 10:54:18,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13454 [2022-11-16 10:54:18,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13454 [2022-11-16 10:54:18,962 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13454 states and 18164 transitions. [2022-11-16 10:54:18,973 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:54:18,973 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13454 states and 18164 transitions. [2022-11-16 10:54:18,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13454 states and 18164 transitions. [2022-11-16 10:54:19,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13454 to 13454. [2022-11-16 10:54:19,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13454 states, 13454 states have (on average 1.3500817600713542) internal successors, (18164), 13453 states have internal predecessors, (18164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:54:19,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13454 states to 13454 states and 18164 transitions. [2022-11-16 10:54:19,264 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13454 states and 18164 transitions. [2022-11-16 10:54:19,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:54:19,265 INFO L428 stractBuchiCegarLoop]: Abstraction has 13454 states and 18164 transitions. [2022-11-16 10:54:19,265 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 10:54:19,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13454 states and 18164 transitions. [2022-11-16 10:54:19,314 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 13332 [2022-11-16 10:54:19,315 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:54:19,315 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:54:19,316 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:19,316 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:54:19,316 INFO L748 eck$LassoCheckResult]: Stem: 95666#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0; 95586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 95544#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95483#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95484#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 95555#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95362#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95363#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95602#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95328#L418 assume !(0 == ~M_E~0); 95329#L418-2 assume !(0 == ~T1_E~0); 95554#L423-1 assume !(0 == ~T2_E~0); 95609#L428-1 assume !(0 == ~T3_E~0); 95607#L433-1 assume !(0 == ~E_1~0); 95589#L438-1 assume !(0 == ~E_2~0); 95503#L443-1 assume !(0 == ~E_3~0); 95496#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95452#L197 assume !(1 == ~m_pc~0); 95453#L197-2 is_master_triggered_~__retres1~0#1 := 0; 95650#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95651#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 95622#L510 assume !(0 != activate_threads_~tmp~1#1); 95312#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95313#L216 assume !(1 == ~t1_pc~0); 95358#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95359#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95480#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 95314#L518 assume !(0 != activate_threads_~tmp___0~0#1); 95315#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95513#L235 assume !(1 == ~t2_pc~0); 95598#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95440#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95441#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 95510#L526 assume !(0 != activate_threads_~tmp___1~0#1); 95636#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95427#L254 assume !(1 == ~t3_pc~0); 95367#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95368#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95324#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 95325#L534 assume !(0 != activate_threads_~tmp___2~0#1); 95435#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95304#L461 assume !(1 == ~M_E~0); 95305#L461-2 assume !(1 == ~T1_E~0); 95364#L466-1 assume !(1 == ~T2_E~0); 95615#L471-1 assume !(1 == ~T3_E~0); 95388#L476-1 assume !(1 == ~E_1~0); 95389#L481-1 assume !(1 == ~E_2~0); 95530#L486-1 assume !(1 == ~E_3~0); 95401#L491-1 assume { :end_inline_reset_delta_events } true; 95402#L652-2 assume !false; 108572#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100712#L393 [2022-11-16 10:54:19,316 INFO L750 eck$LassoCheckResult]: Loop: 100712#L393 assume !false; 108566#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 108567#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 95548#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 95549#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95405#L346 assume 0 != eval_~tmp~0#1; 95406#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 95604#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 95605#L351 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 95656#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 95657#L365 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 108070#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 104904#L379 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 100711#L396 assume !(0 != eval_~tmp_ndt_4~0#1); 100712#L393 [2022-11-16 10:54:19,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:19,317 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 4 times [2022-11-16 10:54:19,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:19,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314200990] [2022-11-16 10:54:19,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:19,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:19,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:19,332 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:19,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:19,346 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:19,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:19,348 INFO L85 PathProgramCache]: Analyzing trace with hash -1938063381, now seen corresponding path program 1 times [2022-11-16 10:54:19,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:19,349 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120120499] [2022-11-16 10:54:19,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:19,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:19,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:19,353 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:19,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:19,358 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:19,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:54:19,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1706868258, now seen corresponding path program 1 times [2022-11-16 10:54:19,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:54:19,359 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544829687] [2022-11-16 10:54:19,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:54:19,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:54:19,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:19,368 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:19,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:19,382 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 10:54:20,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:20,917 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 10:54:20,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 10:54:21,098 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.11 10:54:21 BoogieIcfgContainer [2022-11-16 10:54:21,098 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-16 10:54:21,102 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-16 10:54:21,103 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-16 10:54:21,103 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-16 10:54:21,103 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 10:54:11" (3/4) ... [2022-11-16 10:54:21,106 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-16 10:54:21,211 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/witness.graphml [2022-11-16 10:54:21,211 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-16 10:54:21,212 INFO L158 Benchmark]: Toolchain (without parser) took 10834.47ms. Allocated memory was 121.6MB in the beginning and 528.5MB in the end (delta: 406.8MB). Free memory was 85.9MB in the beginning and 348.4MB in the end (delta: -262.5MB). Peak memory consumption was 141.8MB. Max. memory is 16.1GB. [2022-11-16 10:54:21,213 INFO L158 Benchmark]: CDTParser took 0.30ms. Allocated memory is still 121.6MB. Free memory was 93.1MB in the beginning and 93.1MB in the end (delta: 21.3kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-16 10:54:21,213 INFO L158 Benchmark]: CACSL2BoogieTranslator took 363.28ms. Allocated memory is still 121.6MB. Free memory was 85.9MB in the beginning and 93.8MB in the end (delta: -7.8MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-16 10:54:21,214 INFO L158 Benchmark]: Boogie Procedure Inliner took 83.12ms. Allocated memory is still 121.6MB. Free memory was 93.8MB in the beginning and 91.0MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-16 10:54:21,214 INFO L158 Benchmark]: Boogie Preprocessor took 99.23ms. Allocated memory is still 121.6MB. Free memory was 91.0MB in the beginning and 87.5MB in the end (delta: 3.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-16 10:54:21,214 INFO L158 Benchmark]: RCFGBuilder took 990.68ms. Allocated memory is still 121.6MB. Free memory was 87.5MB in the beginning and 52.5MB in the end (delta: 34.9MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2022-11-16 10:54:21,215 INFO L158 Benchmark]: BuchiAutomizer took 9182.76ms. Allocated memory was 121.6MB in the beginning and 528.5MB in the end (delta: 406.8MB). Free memory was 51.8MB in the beginning and 354.7MB in the end (delta: -302.9MB). Peak memory consumption was 102.5MB. Max. memory is 16.1GB. [2022-11-16 10:54:21,215 INFO L158 Benchmark]: Witness Printer took 109.36ms. Allocated memory is still 528.5MB. Free memory was 354.7MB in the beginning and 348.4MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-16 10:54:21,218 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30ms. Allocated memory is still 121.6MB. Free memory was 93.1MB in the beginning and 93.1MB in the end (delta: 21.3kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 363.28ms. Allocated memory is still 121.6MB. Free memory was 85.9MB in the beginning and 93.8MB in the end (delta: -7.8MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 83.12ms. Allocated memory is still 121.6MB. Free memory was 93.8MB in the beginning and 91.0MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 99.23ms. Allocated memory is still 121.6MB. Free memory was 91.0MB in the beginning and 87.5MB in the end (delta: 3.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 990.68ms. Allocated memory is still 121.6MB. Free memory was 87.5MB in the beginning and 52.5MB in the end (delta: 34.9MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 9182.76ms. Allocated memory was 121.6MB in the beginning and 528.5MB in the end (delta: 406.8MB). Free memory was 51.8MB in the beginning and 354.7MB in the end (delta: -302.9MB). Peak memory consumption was 102.5MB. Max. memory is 16.1GB. * Witness Printer took 109.36ms. Allocated memory is still 528.5MB. Free memory was 354.7MB in the beginning and 348.4MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13454 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.9s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 4.7s. Construction of modules took 0.6s. Büchi inclusion checks took 3.1s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 1.3s AutomataMinimizationTime, 17 MinimizatonAttempts, 6500 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.7s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9538 SdHoareTripleChecker+Valid, 0.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9538 mSDsluCounter, 15149 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 7040 mSDsCounter, 180 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 460 IncrementalHoareTripleChecker+Invalid, 640 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 180 mSolverCounterUnsat, 8109 mSDtfsCounter, 460 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 341]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L29] int m_st ; [L39] int T2_E = 2; [L40] int T3_E = 2; [L38] int T1_E = 2; [L28] int t3_pc = 0; [L27] int t2_pc = 0; [L26] int t1_pc = 0; [L34] int t1_i ; [L37] int M_E = 2; [L33] int m_i ; [L41] int E_1 = 2; [L25] int m_pc = 0; [L31] int t2_st ; [L43] int E_3 = 2; [L30] int t1_st ; [L42] int E_2 = 2; [L32] int t3_st ; [L36] int t3_i ; [L35] int t2_i ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 341]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L29] int m_st ; [L39] int T2_E = 2; [L40] int T3_E = 2; [L38] int T1_E = 2; [L28] int t3_pc = 0; [L27] int t2_pc = 0; [L26] int t1_pc = 0; [L34] int t1_i ; [L37] int M_E = 2; [L33] int m_i ; [L41] int E_1 = 2; [L25] int m_pc = 0; [L31] int t2_st ; [L43] int E_3 = 2; [L30] int t1_st ; [L42] int E_2 = 2; [L32] int t3_st ; [L36] int t3_i ; [L35] int t2_i ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-16 10:54:21,341 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d859fdb5-f2e8-43bd-b8db-136e3909071f/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)