./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 12:16:09,409 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 12:16:09,411 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 12:16:09,456 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 12:16:09,457 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 12:16:09,458 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 12:16:09,459 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 12:16:09,462 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 12:16:09,469 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 12:16:09,475 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 12:16:09,478 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 12:16:09,481 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 12:16:09,482 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 12:16:09,484 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 12:16:09,488 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 12:16:09,491 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 12:16:09,493 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 12:16:09,494 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 12:16:09,498 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 12:16:09,505 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 12:16:09,507 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 12:16:09,509 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 12:16:09,513 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 12:16:09,515 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 12:16:09,524 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 12:16:09,525 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 12:16:09,525 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 12:16:09,527 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 12:16:09,528 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 12:16:09,529 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 12:16:09,531 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 12:16:09,533 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 12:16:09,535 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 12:16:09,536 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 12:16:09,538 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 12:16:09,538 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 12:16:09,539 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 12:16:09,539 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 12:16:09,540 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 12:16:09,541 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 12:16:09,542 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 12:16:09,543 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 12:16:09,590 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 12:16:09,590 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 12:16:09,591 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 12:16:09,592 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 12:16:09,593 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 12:16:09,594 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 12:16:09,594 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 12:16:09,595 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 12:16:09,595 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 12:16:09,595 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 12:16:09,596 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 12:16:09,597 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 12:16:09,597 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 12:16:09,597 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 12:16:09,598 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 12:16:09,598 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 12:16:09,598 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 12:16:09,599 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 12:16:09,599 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 12:16:09,599 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 12:16:09,600 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 12:16:09,600 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 12:16:09,600 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 12:16:09,600 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 12:16:09,601 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 12:16:09,601 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 12:16:09,601 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 12:16:09,602 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 12:16:09,602 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 12:16:09,602 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 12:16:09,603 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 12:16:09,604 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 12:16:09,604 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa [2022-11-16 12:16:09,970 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 12:16:10,004 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 12:16:10,007 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 12:16:10,008 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 12:16:10,009 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 12:16:10,011 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2022-11-16 12:16:10,112 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/data/c924f774c/da045f38927e4666aadea78220bc4713/FLAGf66f48585 [2022-11-16 12:16:10,659 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 12:16:10,659 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/sv-benchmarks/c/systemc/transmitter.04.cil.c [2022-11-16 12:16:10,676 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/data/c924f774c/da045f38927e4666aadea78220bc4713/FLAGf66f48585 [2022-11-16 12:16:10,992 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/data/c924f774c/da045f38927e4666aadea78220bc4713 [2022-11-16 12:16:10,995 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 12:16:10,998 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 12:16:11,004 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 12:16:11,005 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 12:16:11,009 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 12:16:11,010 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:16:10" (1/1) ... [2022-11-16 12:16:11,012 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@695e043e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11, skipping insertion in model container [2022-11-16 12:16:11,013 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:16:10" (1/1) ... [2022-11-16 12:16:11,021 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 12:16:11,057 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 12:16:11,264 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2022-11-16 12:16:11,342 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:16:11,355 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 12:16:11,370 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2022-11-16 12:16:11,441 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:16:11,472 INFO L208 MainTranslator]: Completed translation [2022-11-16 12:16:11,472 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11 WrapperNode [2022-11-16 12:16:11,472 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 12:16:11,474 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 12:16:11,474 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 12:16:11,474 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 12:16:11,483 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,494 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,545 INFO L138 Inliner]: procedures = 36, calls = 42, calls flagged for inlining = 37, calls inlined = 70, statements flattened = 966 [2022-11-16 12:16:11,545 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 12:16:11,546 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 12:16:11,546 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 12:16:11,547 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 12:16:11,560 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,560 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,566 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,567 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,590 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,603 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,606 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,609 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,617 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 12:16:11,618 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 12:16:11,618 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 12:16:11,618 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 12:16:11,619 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (1/1) ... [2022-11-16 12:16:11,633 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 12:16:11,652 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:16:11,669 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 12:16:11,677 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 12:16:11,735 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 12:16:11,735 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 12:16:11,735 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 12:16:11,736 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 12:16:11,836 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 12:16:11,838 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 12:16:13,214 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 12:16:13,237 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 12:16:13,241 INFO L300 CfgBuilder]: Removed 8 assume(true) statements. [2022-11-16 12:16:13,244 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:16:13 BoogieIcfgContainer [2022-11-16 12:16:13,248 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 12:16:13,249 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 12:16:13,249 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 12:16:13,255 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 12:16:13,256 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:16:13,256 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 12:16:10" (1/3) ... [2022-11-16 12:16:13,258 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@60cea326 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:16:13, skipping insertion in model container [2022-11-16 12:16:13,258 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:16:13,259 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:11" (2/3) ... [2022-11-16 12:16:13,259 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@60cea326 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:16:13, skipping insertion in model container [2022-11-16 12:16:13,259 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:16:13,259 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:16:13" (3/3) ... [2022-11-16 12:16:13,261 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2022-11-16 12:16:13,369 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 12:16:13,369 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 12:16:13,369 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 12:16:13,370 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 12:16:13,370 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 12:16:13,370 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 12:16:13,370 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 12:16:13,370 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 12:16:13,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:13,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2022-11-16 12:16:13,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:13,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:13,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:13,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:13,462 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 12:16:13,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:13,494 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2022-11-16 12:16:13,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:13,504 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:13,508 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:13,508 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:13,520 INFO L748 eck$LassoCheckResult]: Stem: 380#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 326#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 190#L739true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28#L334true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54#L341true assume !(1 == ~m_i~0);~m_st~0 := 2; 363#L341-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 211#L346-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 116#L351-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 23#L356-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 107#L361-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31#L502true assume !(0 == ~M_E~0); 82#L502-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 17#L507-1true assume !(0 == ~T2_E~0); 55#L512-1true assume !(0 == ~T3_E~0); 313#L517-1true assume !(0 == ~T4_E~0); 11#L522-1true assume !(0 == ~E_1~0); 276#L527-1true assume !(0 == ~E_2~0); 120#L532-1true assume !(0 == ~E_3~0); 357#L537-1true assume !(0 == ~E_4~0); 135#L542-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114#L238true assume 1 == ~m_pc~0; 319#L239true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 194#L249true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158#L250true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 100#L615true assume !(0 != activate_threads_~tmp~1#1); 199#L615-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88#L257true assume 1 == ~t1_pc~0; 322#L258true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 111#L268true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#L269true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 192#L623true assume !(0 != activate_threads_~tmp___0~0#1); 24#L623-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191#L276true assume !(1 == ~t2_pc~0); 278#L276-2true is_transmit2_triggered_~__retres1~2#1 := 0; 336#L287true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213#L288true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 339#L631true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 355#L631-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98#L295true assume 1 == ~t3_pc~0; 37#L296true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91#L306true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148#L307true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 324#L639true assume !(0 != activate_threads_~tmp___2~0#1); 317#L639-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 371#L314true assume !(1 == ~t4_pc~0); 344#L314-2true is_transmit4_triggered_~__retres1~4#1 := 0; 141#L325true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 320#L326true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 87#L647true assume !(0 != activate_threads_~tmp___3~0#1); 272#L647-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 385#L555true assume !(1 == ~M_E~0); 39#L555-2true assume !(1 == ~T1_E~0); 365#L560-1true assume !(1 == ~T2_E~0); 12#L565-1true assume !(1 == ~T3_E~0); 93#L570-1true assume !(1 == ~T4_E~0); 221#L575-1true assume !(1 == ~E_1~0); 291#L580-1true assume !(1 == ~E_2~0); 129#L585-1true assume 1 == ~E_3~0;~E_3~0 := 2; 30#L590-1true assume !(1 == ~E_4~0); 27#L595-1true assume { :end_inline_reset_delta_events } true; 178#L776-2true [2022-11-16 12:16:13,529 INFO L750 eck$LassoCheckResult]: Loop: 178#L776-2true assume !false; 19#L777true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117#L477true assume !true; 378#L492true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123#L334-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74#L502-3true assume !(0 == ~M_E~0); 299#L502-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 311#L507-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 52#L512-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 391#L517-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 49#L522-3true assume 0 == ~E_1~0;~E_1~0 := 1; 89#L527-3true assume 0 == ~E_2~0;~E_2~0 := 1; 139#L532-3true assume 0 == ~E_3~0;~E_3~0 := 1; 263#L537-3true assume !(0 == ~E_4~0); 58#L542-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83#L238-15true assume 1 == ~m_pc~0; 8#L239-5true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 308#L249-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 162#L250-5true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 229#L615-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 156#L615-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 209#L257-15true assume 1 == ~t1_pc~0; 168#L258-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 333#L268-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 361#L269-5true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 304#L623-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 312#L623-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 366#L276-15true assume 1 == ~t2_pc~0; 252#L277-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 245#L287-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187#L288-5true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 183#L631-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 287#L631-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25#L295-15true assume 1 == ~t3_pc~0; 303#L296-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 330#L306-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154#L307-5true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 164#L639-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122#L639-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163#L314-15true assume 1 == ~t4_pc~0; 281#L315-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 185#L325-5true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251#L326-5true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 316#L647-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 118#L647-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81#L555-3true assume 1 == ~M_E~0;~M_E~0 := 2; 195#L555-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 42#L560-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 305#L565-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 345#L570-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 288#L575-3true assume 1 == ~E_1~0;~E_1~0 := 2; 193#L580-3true assume !(1 == ~E_2~0); 389#L585-3true assume 1 == ~E_3~0;~E_3~0 := 2; 235#L590-3true assume 1 == ~E_4~0;~E_4~0 := 2; 270#L595-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 165#L374-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 70#L401-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 99#L402-1true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 97#L795true assume !(0 == start_simulation_~tmp~3#1); 318#L795-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 109#L374-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 265#L401-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 247#L402-2true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 170#L750true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40#L757true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 271#L758true start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 275#L808true assume !(0 != start_simulation_~tmp___0~1#1); 178#L776-2true [2022-11-16 12:16:13,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:13,548 INFO L85 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2022-11-16 12:16:13,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:13,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25045557] [2022-11-16 12:16:13,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:13,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:13,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:13,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:13,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:13,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25045557] [2022-11-16 12:16:13,862 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25045557] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:13,863 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:13,863 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:13,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007967843] [2022-11-16 12:16:13,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:13,872 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:13,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:13,874 INFO L85 PathProgramCache]: Analyzing trace with hash -1094417456, now seen corresponding path program 1 times [2022-11-16 12:16:13,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:13,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015815777] [2022-11-16 12:16:13,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:13,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:13,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:13,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:13,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:13,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015815777] [2022-11-16 12:16:13,934 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015815777] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:13,935 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:13,935 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:13,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428819179] [2022-11-16 12:16:13,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:13,937 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:13,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:13,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:13,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:13,987 INFO L87 Difference]: Start difference. First operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:14,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:14,067 INFO L93 Difference]: Finished difference Result 390 states and 581 transitions. [2022-11-16 12:16:14,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 390 states and 581 transitions. [2022-11-16 12:16:14,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:14,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 390 states to 384 states and 575 transitions. [2022-11-16 12:16:14,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-11-16 12:16:14,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-11-16 12:16:14,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 575 transitions. [2022-11-16 12:16:14,102 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:14,102 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 575 transitions. [2022-11-16 12:16:14,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 575 transitions. [2022-11-16 12:16:14,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-11-16 12:16:14,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:14,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 575 transitions. [2022-11-16 12:16:14,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 575 transitions. [2022-11-16 12:16:14,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:14,167 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2022-11-16 12:16:14,167 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 12:16:14,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 575 transitions. [2022-11-16 12:16:14,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:14,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:14,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:14,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:14,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:14,175 INFO L748 eck$LassoCheckResult]: Stem: 1171#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 1140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 790#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 791#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 915#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1021#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 874#L346-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 875#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 887#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 888#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 933#L502 assume !(0 == ~M_E~0); 934#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 862#L507-1 assume !(0 == ~T2_E~0); 863#L512-1 assume !(0 == ~T3_E~0); 1023#L517-1 assume !(0 == ~T4_E~0); 844#L522-1 assume !(0 == ~E_1~0); 845#L527-1 assume !(0 == ~E_2~0); 1040#L532-1 assume !(0 == ~E_3~0); 1134#L537-1 assume !(0 == ~E_4~0); 1148#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1124#L238 assume 1 == ~m_pc~0; 1125#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 803#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1104#L615 assume !(0 != activate_threads_~tmp~1#1); 826#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 827#L257 assume 1 == ~t1_pc~0; 1082#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 977#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 797#L623 assume !(0 != activate_threads_~tmp___0~0#1); 798#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 792#L276 assume !(1 == ~t2_pc~0); 793#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1051#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 889#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 890#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1159#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1103#L295 assume 1 == ~t3_pc~0; 953#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 908#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1088#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1135#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1128#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1129#L314 assume !(1 == ~t4_pc~0); 945#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 944#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1130#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1080#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1034#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1035#L555 assume !(1 == ~M_E~0); 958#L555-2 assume !(1 == ~T1_E~0); 959#L560-1 assume !(1 == ~T2_E~0); 846#L565-1 assume !(1 == ~T3_E~0); 847#L570-1 assume !(1 == ~T4_E~0); 918#L575-1 assume !(1 == ~E_1~0); 919#L580-1 assume !(1 == ~E_2~0); 1081#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 920#L590-1 assume !(1 == ~E_4~0); 909#L595-1 assume { :end_inline_reset_delta_events } true; 910#L776-2 [2022-11-16 12:16:14,176 INFO L750 eck$LassoCheckResult]: Loop: 910#L776-2 assume !false; 878#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 879#L477 assume !false; 969#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 970#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 811#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 812#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 850#L416 assume !(0 != eval_~tmp~0#1); 852#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1138#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1065#L502-3 assume !(0 == ~M_E~0); 1066#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1092#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1014#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1015#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1000#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1001#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1083#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1017#L537-3 assume !(0 == ~E_4~0); 1018#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1027#L238-15 assume 1 == ~m_pc~0; 828#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 829#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1113#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 939#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 940#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 869#L257-15 assume !(1 == ~t1_pc~0); 870#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1061#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1152#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1105#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1106#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1119#L276-15 assume 1 == ~t2_pc~0; 997#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 984#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 985#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1173#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1074#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 904#L295-15 assume !(1 == ~t3_pc~0); 905#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1102#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1146#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1167#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1136#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1137#L314-15 assume 1 == ~t4_pc~0; 1056#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1057#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 995#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 996#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1123#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1073#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 805#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 806#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 974#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1108#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1075#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 799#L580-3 assume !(1 == ~E_2~0); 800#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 956#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 957#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1032#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 883#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1059#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1098#L795 assume !(0 == start_simulation_~tmp~3#1); 1100#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1120#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 841#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 986#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 987#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 965#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 966#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1033#L808 assume !(0 != start_simulation_~tmp___0~1#1); 910#L776-2 [2022-11-16 12:16:14,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:14,177 INFO L85 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2022-11-16 12:16:14,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:14,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372669991] [2022-11-16 12:16:14,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:14,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:14,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:14,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:14,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:14,270 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372669991] [2022-11-16 12:16:14,270 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1372669991] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:14,270 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:14,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:14,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [205381169] [2022-11-16 12:16:14,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:14,272 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:14,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:14,273 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 1 times [2022-11-16 12:16:14,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:14,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140387884] [2022-11-16 12:16:14,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:14,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:14,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:14,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:14,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:14,441 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140387884] [2022-11-16 12:16:14,442 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1140387884] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:14,442 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:14,442 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:14,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331031444] [2022-11-16 12:16:14,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:14,443 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:14,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:14,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:14,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:14,445 INFO L87 Difference]: Start difference. First operand 384 states and 575 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:14,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:14,510 INFO L93 Difference]: Finished difference Result 384 states and 574 transitions. [2022-11-16 12:16:14,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 574 transitions. [2022-11-16 12:16:14,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:14,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 574 transitions. [2022-11-16 12:16:14,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-11-16 12:16:14,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-11-16 12:16:14,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 574 transitions. [2022-11-16 12:16:14,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:14,540 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 574 transitions. [2022-11-16 12:16:14,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 574 transitions. [2022-11-16 12:16:14,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-11-16 12:16:14,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:14,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 574 transitions. [2022-11-16 12:16:14,570 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 574 transitions. [2022-11-16 12:16:14,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:14,577 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2022-11-16 12:16:14,577 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 12:16:14,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 574 transitions. [2022-11-16 12:16:14,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:14,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:14,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:14,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:14,591 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:14,593 INFO L748 eck$LassoCheckResult]: Stem: 1946#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 1914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1565#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1566#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1688#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1794#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1649#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1650#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1662#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1663#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1708#L502 assume !(0 == ~M_E~0); 1709#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1637#L507-1 assume !(0 == ~T2_E~0); 1638#L512-1 assume !(0 == ~T3_E~0); 1797#L517-1 assume !(0 == ~T4_E~0); 1610#L522-1 assume !(0 == ~E_1~0); 1611#L527-1 assume !(0 == ~E_2~0); 1815#L532-1 assume !(0 == ~E_3~0); 1909#L537-1 assume !(0 == ~E_4~0); 1923#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1899#L238 assume 1 == ~m_pc~0; 1900#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1578#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1579#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1879#L615 assume !(0 != activate_threads_~tmp~1#1); 1597#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1598#L257 assume 1 == ~t1_pc~0; 1857#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1717#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1752#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1572#L623 assume !(0 != activate_threads_~tmp___0~0#1); 1573#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1567#L276 assume !(1 == ~t2_pc~0); 1568#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1825#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1664#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1665#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1933#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1876#L295 assume 1 == ~t3_pc~0; 1728#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1683#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1863#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1910#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1902#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1903#L314 assume !(1 == ~t4_pc~0); 1720#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1719#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1905#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1855#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1809#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1810#L555 assume !(1 == ~M_E~0); 1733#L555-2 assume !(1 == ~T1_E~0); 1734#L560-1 assume !(1 == ~T2_E~0); 1612#L565-1 assume !(1 == ~T3_E~0); 1613#L570-1 assume !(1 == ~T4_E~0); 1693#L575-1 assume !(1 == ~E_1~0); 1694#L580-1 assume !(1 == ~E_2~0); 1856#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1695#L590-1 assume !(1 == ~E_4~0); 1684#L595-1 assume { :end_inline_reset_delta_events } true; 1685#L776-2 [2022-11-16 12:16:14,593 INFO L750 eck$LassoCheckResult]: Loop: 1685#L776-2 assume !false; 1653#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1654#L477 assume !false; 1744#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1745#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1586#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1587#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1625#L416 assume !(0 != eval_~tmp~0#1); 1627#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1913#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1840#L502-3 assume !(0 == ~M_E~0); 1841#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1866#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1789#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1790#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1775#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1776#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1858#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1792#L537-3 assume !(0 == ~E_4~0); 1793#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1802#L238-15 assume 1 == ~m_pc~0; 1603#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1604#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1889#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1714#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1715#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1644#L257-15 assume !(1 == ~t1_pc~0); 1645#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1836#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1927#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1880#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1881#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1894#L276-15 assume 1 == ~t2_pc~0; 1772#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1759#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1760#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1948#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1849#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1679#L295-15 assume !(1 == ~t3_pc~0); 1680#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1878#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1921#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1942#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1911#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1912#L314-15 assume 1 == ~t4_pc~0; 1831#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1832#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1770#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1771#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1898#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1848#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1580#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1581#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1749#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1883#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1850#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1574#L580-3 assume !(1 == ~E_2~0); 1575#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1731#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1732#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1807#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1658#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1835#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1873#L795 assume !(0 == start_simulation_~tmp~3#1); 1875#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1895#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1620#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1761#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1762#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1742#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1743#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1808#L808 assume !(0 != start_simulation_~tmp___0~1#1); 1685#L776-2 [2022-11-16 12:16:14,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:14,594 INFO L85 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2022-11-16 12:16:14,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:14,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773240300] [2022-11-16 12:16:14,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:14,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:14,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:14,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:14,693 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:14,693 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773240300] [2022-11-16 12:16:14,693 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773240300] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:14,694 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:14,694 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:14,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119425398] [2022-11-16 12:16:14,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:14,695 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:14,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:14,696 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 2 times [2022-11-16 12:16:14,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:14,697 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135393786] [2022-11-16 12:16:14,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:14,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:14,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:14,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:14,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:14,775 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [135393786] [2022-11-16 12:16:14,775 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [135393786] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:14,776 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:14,776 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:14,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308538757] [2022-11-16 12:16:14,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:14,777 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:14,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:14,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:14,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:14,779 INFO L87 Difference]: Start difference. First operand 384 states and 574 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:14,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:14,798 INFO L93 Difference]: Finished difference Result 384 states and 573 transitions. [2022-11-16 12:16:14,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 573 transitions. [2022-11-16 12:16:14,802 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:14,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 573 transitions. [2022-11-16 12:16:14,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-11-16 12:16:14,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-11-16 12:16:14,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 573 transitions. [2022-11-16 12:16:14,808 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:14,808 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 573 transitions. [2022-11-16 12:16:14,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 573 transitions. [2022-11-16 12:16:14,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-11-16 12:16:14,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:14,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 573 transitions. [2022-11-16 12:16:14,823 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 573 transitions. [2022-11-16 12:16:14,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:14,825 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2022-11-16 12:16:14,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 12:16:14,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 573 transitions. [2022-11-16 12:16:14,829 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:14,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:14,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:14,831 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:14,831 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:14,831 INFO L748 eck$LassoCheckResult]: Stem: 2721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 2690#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2340#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2341#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2465#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 2571#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2424#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2425#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2437#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2438#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2483#L502 assume !(0 == ~M_E~0); 2484#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2415#L507-1 assume !(0 == ~T2_E~0); 2416#L512-1 assume !(0 == ~T3_E~0); 2573#L517-1 assume !(0 == ~T4_E~0); 2394#L522-1 assume !(0 == ~E_1~0); 2395#L527-1 assume !(0 == ~E_2~0); 2590#L532-1 assume !(0 == ~E_3~0); 2684#L537-1 assume !(0 == ~E_4~0); 2698#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2674#L238 assume 1 == ~m_pc~0; 2675#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2353#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2354#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2654#L615 assume !(0 != activate_threads_~tmp~1#1); 2376#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2377#L257 assume 1 == ~t1_pc~0; 2632#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2492#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2527#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2347#L623 assume !(0 != activate_threads_~tmp___0~0#1); 2348#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2342#L276 assume !(1 == ~t2_pc~0); 2343#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2603#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2439#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2440#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2709#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2653#L295 assume 1 == ~t3_pc~0; 2503#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2458#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2638#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2685#L639 assume !(0 != activate_threads_~tmp___2~0#1); 2678#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2679#L314 assume !(1 == ~t4_pc~0); 2495#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2494#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2680#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2630#L647 assume !(0 != activate_threads_~tmp___3~0#1); 2584#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2585#L555 assume !(1 == ~M_E~0); 2508#L555-2 assume !(1 == ~T1_E~0); 2509#L560-1 assume !(1 == ~T2_E~0); 2396#L565-1 assume !(1 == ~T3_E~0); 2397#L570-1 assume !(1 == ~T4_E~0); 2468#L575-1 assume !(1 == ~E_1~0); 2469#L580-1 assume !(1 == ~E_2~0); 2631#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2470#L590-1 assume !(1 == ~E_4~0); 2459#L595-1 assume { :end_inline_reset_delta_events } true; 2460#L776-2 [2022-11-16 12:16:14,832 INFO L750 eck$LassoCheckResult]: Loop: 2460#L776-2 assume !false; 2428#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2429#L477 assume !false; 2519#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2520#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2361#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2362#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2400#L416 assume !(0 != eval_~tmp~0#1); 2402#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2688#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2615#L502-3 assume !(0 == ~M_E~0); 2616#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2642#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2564#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2565#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2550#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2551#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2633#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2567#L537-3 assume !(0 == ~E_4~0); 2568#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2577#L238-15 assume 1 == ~m_pc~0; 2378#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2379#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2663#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2489#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2490#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2419#L257-15 assume !(1 == ~t1_pc~0); 2420#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2611#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2702#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2655#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2656#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2669#L276-15 assume 1 == ~t2_pc~0; 2547#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2534#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2535#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2723#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2624#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2454#L295-15 assume !(1 == ~t3_pc~0); 2455#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2652#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2696#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2717#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2686#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2687#L314-15 assume !(1 == ~t4_pc~0); 2608#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 2607#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2545#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2546#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2673#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2623#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2355#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2356#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2524#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2658#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2625#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2349#L580-3 assume !(1 == ~E_2~0); 2350#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2506#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2507#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2582#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2433#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2609#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2648#L795 assume !(0 == start_simulation_~tmp~3#1); 2650#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2670#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2391#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2536#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2537#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2515#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2516#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2583#L808 assume !(0 != start_simulation_~tmp___0~1#1); 2460#L776-2 [2022-11-16 12:16:14,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:14,833 INFO L85 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2022-11-16 12:16:14,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:14,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36489337] [2022-11-16 12:16:14,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:14,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:14,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:14,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:14,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:14,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36489337] [2022-11-16 12:16:14,883 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [36489337] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:14,883 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:14,883 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:14,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794997832] [2022-11-16 12:16:14,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:14,884 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:14,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:14,885 INFO L85 PathProgramCache]: Analyzing trace with hash -2012547652, now seen corresponding path program 1 times [2022-11-16 12:16:14,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:14,886 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287029043] [2022-11-16 12:16:14,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:14,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:14,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:14,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:14,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:14,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287029043] [2022-11-16 12:16:14,951 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287029043] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:14,951 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:14,952 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:14,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753808846] [2022-11-16 12:16:14,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:14,953 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:14,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:14,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:14,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:14,954 INFO L87 Difference]: Start difference. First operand 384 states and 573 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:14,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:14,970 INFO L93 Difference]: Finished difference Result 384 states and 572 transitions. [2022-11-16 12:16:14,970 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 572 transitions. [2022-11-16 12:16:14,974 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:14,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 572 transitions. [2022-11-16 12:16:14,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-11-16 12:16:14,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-11-16 12:16:14,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 572 transitions. [2022-11-16 12:16:14,979 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:14,979 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 572 transitions. [2022-11-16 12:16:14,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 572 transitions. [2022-11-16 12:16:14,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-11-16 12:16:14,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:14,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 572 transitions. [2022-11-16 12:16:14,991 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 572 transitions. [2022-11-16 12:16:14,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:14,993 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2022-11-16 12:16:14,993 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 12:16:14,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 572 transitions. [2022-11-16 12:16:14,996 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:14,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:14,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:14,998 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:14,998 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:14,999 INFO L748 eck$LassoCheckResult]: Stem: 3496#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 3464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3115#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3116#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3238#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 3346#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3199#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3200#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3212#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3213#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3258#L502 assume !(0 == ~M_E~0); 3259#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3187#L507-1 assume !(0 == ~T2_E~0); 3188#L512-1 assume !(0 == ~T3_E~0); 3347#L517-1 assume !(0 == ~T4_E~0); 3162#L522-1 assume !(0 == ~E_1~0); 3163#L527-1 assume !(0 == ~E_2~0); 3365#L532-1 assume !(0 == ~E_3~0); 3459#L537-1 assume !(0 == ~E_4~0); 3473#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3449#L238 assume 1 == ~m_pc~0; 3450#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3128#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3129#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3429#L615 assume !(0 != activate_threads_~tmp~1#1); 3147#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3148#L257 assume 1 == ~t1_pc~0; 3407#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3267#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3302#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3122#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3123#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3117#L276 assume !(1 == ~t2_pc~0); 3118#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3375#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3214#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3215#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3483#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3426#L295 assume 1 == ~t3_pc~0; 3278#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3233#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3413#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3460#L639 assume !(0 != activate_threads_~tmp___2~0#1); 3452#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3453#L314 assume !(1 == ~t4_pc~0); 3270#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3269#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3455#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3405#L647 assume !(0 != activate_threads_~tmp___3~0#1); 3359#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3360#L555 assume !(1 == ~M_E~0); 3283#L555-2 assume !(1 == ~T1_E~0); 3284#L560-1 assume !(1 == ~T2_E~0); 3164#L565-1 assume !(1 == ~T3_E~0); 3165#L570-1 assume !(1 == ~T4_E~0); 3243#L575-1 assume !(1 == ~E_1~0); 3244#L580-1 assume !(1 == ~E_2~0); 3406#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3245#L590-1 assume !(1 == ~E_4~0); 3234#L595-1 assume { :end_inline_reset_delta_events } true; 3235#L776-2 [2022-11-16 12:16:14,999 INFO L750 eck$LassoCheckResult]: Loop: 3235#L776-2 assume !false; 3203#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3204#L477 assume !false; 3294#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3295#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3136#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3137#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3175#L416 assume !(0 != eval_~tmp~0#1); 3177#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3463#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3390#L502-3 assume !(0 == ~M_E~0); 3391#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3416#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3339#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3340#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3325#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3326#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3408#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3342#L537-3 assume !(0 == ~E_4~0); 3343#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3352#L238-15 assume 1 == ~m_pc~0; 3153#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3154#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3439#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3264#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3265#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3194#L257-15 assume !(1 == ~t1_pc~0); 3195#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3386#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3477#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3430#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3431#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3444#L276-15 assume 1 == ~t2_pc~0; 3322#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3309#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3310#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3498#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3399#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3229#L295-15 assume !(1 == ~t3_pc~0); 3230#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 3428#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3471#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3492#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3461#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3462#L314-15 assume 1 == ~t4_pc~0; 3381#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3382#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3320#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3321#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3448#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3398#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3130#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3131#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3299#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3433#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3400#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3124#L580-3 assume !(1 == ~E_2~0); 3125#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3281#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3282#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3358#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3208#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3385#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3423#L795 assume !(0 == start_simulation_~tmp~3#1); 3425#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3445#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3172#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3311#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3312#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3290#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3291#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3356#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3235#L776-2 [2022-11-16 12:16:15,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:15,000 INFO L85 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2022-11-16 12:16:15,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:15,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783684638] [2022-11-16 12:16:15,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:15,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:15,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:15,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:15,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:15,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783684638] [2022-11-16 12:16:15,060 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783684638] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:15,060 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:15,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:15,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998051132] [2022-11-16 12:16:15,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:15,062 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:15,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:15,062 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 3 times [2022-11-16 12:16:15,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:15,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051068100] [2022-11-16 12:16:15,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:15,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:15,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:15,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:15,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:15,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051068100] [2022-11-16 12:16:15,120 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051068100] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:15,121 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:15,121 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:15,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680377327] [2022-11-16 12:16:15,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:15,122 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:15,122 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:15,123 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:15,123 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:15,124 INFO L87 Difference]: Start difference. First operand 384 states and 572 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:15,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:15,149 INFO L93 Difference]: Finished difference Result 384 states and 567 transitions. [2022-11-16 12:16:15,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 567 transitions. [2022-11-16 12:16:15,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:15,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 567 transitions. [2022-11-16 12:16:15,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-11-16 12:16:15,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-11-16 12:16:15,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 567 transitions. [2022-11-16 12:16:15,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:15,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 567 transitions. [2022-11-16 12:16:15,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 567 transitions. [2022-11-16 12:16:15,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2022-11-16 12:16:15,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4765625) internal successors, (567), 383 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:15,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 567 transitions. [2022-11-16 12:16:15,168 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 567 transitions. [2022-11-16 12:16:15,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:15,170 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 567 transitions. [2022-11-16 12:16:15,170 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 12:16:15,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 567 transitions. [2022-11-16 12:16:15,174 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2022-11-16 12:16:15,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:15,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:15,175 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:15,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:15,176 INFO L748 eck$LassoCheckResult]: Stem: 4271#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 4240#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3890#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3891#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4015#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 4121#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3974#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3975#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3987#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3988#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4033#L502 assume !(0 == ~M_E~0); 4034#L502-2 assume !(0 == ~T1_E~0); 3965#L507-1 assume !(0 == ~T2_E~0); 3966#L512-1 assume !(0 == ~T3_E~0); 4123#L517-1 assume !(0 == ~T4_E~0); 3944#L522-1 assume !(0 == ~E_1~0); 3945#L527-1 assume !(0 == ~E_2~0); 4140#L532-1 assume !(0 == ~E_3~0); 4234#L537-1 assume !(0 == ~E_4~0); 4248#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4224#L238 assume 1 == ~m_pc~0; 4225#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3903#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3904#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4204#L615 assume !(0 != activate_threads_~tmp~1#1); 3926#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3927#L257 assume 1 == ~t1_pc~0; 4182#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4042#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4077#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3897#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3898#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3892#L276 assume !(1 == ~t2_pc~0); 3893#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4153#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3989#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3990#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4259#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4203#L295 assume 1 == ~t3_pc~0; 4053#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4008#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4188#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4235#L639 assume !(0 != activate_threads_~tmp___2~0#1); 4228#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4229#L314 assume !(1 == ~t4_pc~0); 4045#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4044#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4230#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4180#L647 assume !(0 != activate_threads_~tmp___3~0#1); 4134#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4135#L555 assume !(1 == ~M_E~0); 4058#L555-2 assume !(1 == ~T1_E~0); 4059#L560-1 assume !(1 == ~T2_E~0); 3946#L565-1 assume !(1 == ~T3_E~0); 3947#L570-1 assume !(1 == ~T4_E~0); 4018#L575-1 assume !(1 == ~E_1~0); 4019#L580-1 assume !(1 == ~E_2~0); 4181#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4020#L590-1 assume !(1 == ~E_4~0); 4009#L595-1 assume { :end_inline_reset_delta_events } true; 4010#L776-2 [2022-11-16 12:16:15,177 INFO L750 eck$LassoCheckResult]: Loop: 4010#L776-2 assume !false; 3978#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3979#L477 assume !false; 4069#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4070#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3911#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3912#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3950#L416 assume !(0 != eval_~tmp~0#1); 3952#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4238#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4165#L502-3 assume !(0 == ~M_E~0); 4166#L502-5 assume !(0 == ~T1_E~0); 4191#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4114#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4115#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4100#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4101#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4183#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4117#L537-3 assume !(0 == ~E_4~0); 4118#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4127#L238-15 assume 1 == ~m_pc~0; 3928#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3929#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4213#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4039#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4040#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3969#L257-15 assume !(1 == ~t1_pc~0); 3970#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 4161#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4252#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4205#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4206#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4219#L276-15 assume 1 == ~t2_pc~0; 4097#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4084#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4085#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4273#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4174#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4004#L295-15 assume !(1 == ~t3_pc~0); 4005#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 4202#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4246#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4267#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4236#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4237#L314-15 assume 1 == ~t4_pc~0; 4156#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4157#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4095#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4096#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4223#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4173#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3905#L555-5 assume !(1 == ~T1_E~0); 3906#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4074#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4208#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4175#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3899#L580-3 assume !(1 == ~E_2~0); 3900#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4056#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4057#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4132#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3983#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4159#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4198#L795 assume !(0 == start_simulation_~tmp~3#1); 4200#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4220#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3941#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4086#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4087#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4065#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4066#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4133#L808 assume !(0 != start_simulation_~tmp___0~1#1); 4010#L776-2 [2022-11-16 12:16:15,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:15,178 INFO L85 PathProgramCache]: Analyzing trace with hash -1804375922, now seen corresponding path program 1 times [2022-11-16 12:16:15,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:15,178 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196804737] [2022-11-16 12:16:15,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:15,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:15,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:15,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:15,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:15,275 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1196804737] [2022-11-16 12:16:15,275 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1196804737] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:15,276 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:15,276 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:15,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81708499] [2022-11-16 12:16:15,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:15,277 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:15,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:15,278 INFO L85 PathProgramCache]: Analyzing trace with hash 680167841, now seen corresponding path program 1 times [2022-11-16 12:16:15,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:15,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37859966] [2022-11-16 12:16:15,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:15,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:15,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:15,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:15,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:15,383 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37859966] [2022-11-16 12:16:15,383 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37859966] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:15,383 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:15,383 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:15,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121877550] [2022-11-16 12:16:15,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:15,384 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:15,384 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:15,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:15,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:15,392 INFO L87 Difference]: Start difference. First operand 384 states and 567 transitions. cyclomatic complexity: 184 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:15,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:15,488 INFO L93 Difference]: Finished difference Result 694 states and 1012 transitions. [2022-11-16 12:16:15,488 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 694 states and 1012 transitions. [2022-11-16 12:16:15,495 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 629 [2022-11-16 12:16:15,501 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 694 states to 694 states and 1012 transitions. [2022-11-16 12:16:15,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 694 [2022-11-16 12:16:15,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 694 [2022-11-16 12:16:15,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 694 states and 1012 transitions. [2022-11-16 12:16:15,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:15,504 INFO L218 hiAutomatonCegarLoop]: Abstraction has 694 states and 1012 transitions. [2022-11-16 12:16:15,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states and 1012 transitions. [2022-11-16 12:16:15,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 658. [2022-11-16 12:16:15,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 658 states, 658 states have (on average 1.4635258358662615) internal successors, (963), 657 states have internal predecessors, (963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:15,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 963 transitions. [2022-11-16 12:16:15,524 INFO L240 hiAutomatonCegarLoop]: Abstraction has 658 states and 963 transitions. [2022-11-16 12:16:15,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:15,529 INFO L428 stractBuchiCegarLoop]: Abstraction has 658 states and 963 transitions. [2022-11-16 12:16:15,529 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 12:16:15,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 658 states and 963 transitions. [2022-11-16 12:16:15,534 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 593 [2022-11-16 12:16:15,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:15,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:15,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:15,537 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:15,537 INFO L748 eck$LassoCheckResult]: Stem: 5365#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 5328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4975#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4976#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5096#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 5204#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5059#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5060#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5072#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5073#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5118#L502 assume !(0 == ~M_E~0); 5119#L502-2 assume !(0 == ~T1_E~0); 5047#L507-1 assume !(0 == ~T2_E~0); 5048#L512-1 assume !(0 == ~T3_E~0); 5207#L517-1 assume !(0 == ~T4_E~0); 5020#L522-1 assume !(0 == ~E_1~0); 5021#L527-1 assume !(0 == ~E_2~0); 5226#L532-1 assume !(0 == ~E_3~0); 5320#L537-1 assume !(0 == ~E_4~0); 5340#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5311#L238 assume !(1 == ~m_pc~0); 5312#L238-2 is_master_triggered_~__retres1~0#1 := 0; 4986#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4987#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5292#L615 assume !(0 != activate_threads_~tmp~1#1); 5007#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5008#L257 assume 1 == ~t1_pc~0; 5268#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5127#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5162#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4980#L623 assume !(0 != activate_threads_~tmp___0~0#1); 4981#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4977#L276 assume !(1 == ~t2_pc~0); 4978#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5235#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5074#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5075#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5352#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5289#L295 assume 1 == ~t3_pc~0; 5138#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5093#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5274#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5321#L639 assume !(0 != activate_threads_~tmp___2~0#1); 5313#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5314#L314 assume !(1 == ~t4_pc~0); 5130#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5129#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5316#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5266#L647 assume !(0 != activate_threads_~tmp___3~0#1); 5219#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5220#L555 assume !(1 == ~M_E~0); 5143#L555-2 assume !(1 == ~T1_E~0); 5144#L560-1 assume !(1 == ~T2_E~0); 5022#L565-1 assume !(1 == ~T3_E~0); 5023#L570-1 assume !(1 == ~T4_E~0); 5103#L575-1 assume !(1 == ~E_1~0); 5104#L580-1 assume !(1 == ~E_2~0); 5267#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5105#L590-1 assume !(1 == ~E_4~0); 5094#L595-1 assume { :end_inline_reset_delta_events } true; 5095#L776-2 [2022-11-16 12:16:15,538 INFO L750 eck$LassoCheckResult]: Loop: 5095#L776-2 assume !false; 5063#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5064#L477 assume !false; 5154#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5155#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4994#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4995#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5035#L416 assume !(0 != eval_~tmp~0#1); 5037#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5324#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5250#L502-3 assume !(0 == ~M_E~0); 5251#L502-5 assume !(0 == ~T1_E~0); 5280#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5199#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5200#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5185#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5186#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5269#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5202#L537-3 assume !(0 == ~E_4~0); 5203#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5212#L238-15 assume !(1 == ~m_pc~0); 5262#L238-17 is_master_triggered_~__retres1~0#1 := 0; 5538#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5536#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5534#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5532#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5530#L257-15 assume 1 == ~t1_pc~0; 5527#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5525#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5523#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5521#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5519#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5518#L276-15 assume 1 == ~t2_pc~0; 5516#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5515#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5514#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5513#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5512#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5511#L295-15 assume !(1 == ~t3_pc~0); 5507#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 5503#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5502#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5501#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5500#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5499#L314-15 assume 1 == ~t4_pc~0; 5497#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5496#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5495#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5494#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5492#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5490#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5488#L555-5 assume !(1 == ~T1_E~0); 5486#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5483#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5481#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5479#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5477#L580-3 assume !(1 == ~E_2~0); 5475#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5473#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5470#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5463#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5459#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5458#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5454#L795 assume !(0 == start_simulation_~tmp~3#1); 5451#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5432#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5428#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5426#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5424#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5423#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5421#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5419#L808 assume !(0 != start_simulation_~tmp___0~1#1); 5095#L776-2 [2022-11-16 12:16:15,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:15,542 INFO L85 PathProgramCache]: Analyzing trace with hash -1404384723, now seen corresponding path program 1 times [2022-11-16 12:16:15,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:15,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1894326725] [2022-11-16 12:16:15,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:15,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:15,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:15,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:15,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:15,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1894326725] [2022-11-16 12:16:15,648 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1894326725] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:15,649 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:15,649 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:15,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408613222] [2022-11-16 12:16:15,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:15,650 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:15,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:15,650 INFO L85 PathProgramCache]: Analyzing trace with hash 1286604385, now seen corresponding path program 1 times [2022-11-16 12:16:15,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:15,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265551374] [2022-11-16 12:16:15,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:15,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:15,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:15,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:15,710 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:15,710 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265551374] [2022-11-16 12:16:15,711 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265551374] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:15,712 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:15,714 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:15,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [524832194] [2022-11-16 12:16:15,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:15,715 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:15,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:15,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:16:15,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:16:15,716 INFO L87 Difference]: Start difference. First operand 658 states and 963 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:15,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:15,888 INFO L93 Difference]: Finished difference Result 1490 states and 2153 transitions. [2022-11-16 12:16:15,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1490 states and 2153 transitions. [2022-11-16 12:16:15,901 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1382 [2022-11-16 12:16:15,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1490 states to 1490 states and 2153 transitions. [2022-11-16 12:16:15,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1490 [2022-11-16 12:16:15,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1490 [2022-11-16 12:16:15,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1490 states and 2153 transitions. [2022-11-16 12:16:15,915 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:15,915 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1490 states and 2153 transitions. [2022-11-16 12:16:15,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1490 states and 2153 transitions. [2022-11-16 12:16:15,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1490 to 1163. [2022-11-16 12:16:15,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1163 states, 1163 states have (on average 1.4557179707652623) internal successors, (1693), 1162 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:15,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1163 states to 1163 states and 1693 transitions. [2022-11-16 12:16:15,944 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1163 states and 1693 transitions. [2022-11-16 12:16:15,945 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:16:15,948 INFO L428 stractBuchiCegarLoop]: Abstraction has 1163 states and 1693 transitions. [2022-11-16 12:16:15,948 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 12:16:15,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1163 states and 1693 transitions. [2022-11-16 12:16:15,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1098 [2022-11-16 12:16:15,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:15,955 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:15,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:15,959 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:15,960 INFO L748 eck$LassoCheckResult]: Stem: 7536#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 7491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7133#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7134#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7258#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 7367#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7217#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7218#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7230#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7231#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7276#L502 assume !(0 == ~M_E~0); 7277#L502-2 assume !(0 == ~T1_E~0); 7209#L507-1 assume !(0 == ~T2_E~0); 7210#L512-1 assume !(0 == ~T3_E~0); 7369#L517-1 assume !(0 == ~T4_E~0); 7188#L522-1 assume !(0 == ~E_1~0); 7189#L527-1 assume !(0 == ~E_2~0); 7386#L532-1 assume !(0 == ~E_3~0); 7482#L537-1 assume !(0 == ~E_4~0); 7500#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7473#L238 assume !(1 == ~m_pc~0); 7474#L238-2 is_master_triggered_~__retres1~0#1 := 0; 7146#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7147#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7452#L615 assume !(0 != activate_threads_~tmp~1#1); 7169#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7170#L257 assume !(1 == ~t1_pc~0); 7284#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7285#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7320#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7140#L623 assume !(0 != activate_threads_~tmp___0~0#1); 7141#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7135#L276 assume !(1 == ~t2_pc~0); 7136#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7398#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7232#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7233#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7515#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7450#L295 assume 1 == ~t3_pc~0; 7296#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7251#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7437#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7483#L639 assume !(0 != activate_threads_~tmp___2~0#1); 7476#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7477#L314 assume !(1 == ~t4_pc~0); 7288#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7287#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7478#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7427#L647 assume !(0 != activate_threads_~tmp___3~0#1); 7380#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7381#L555 assume !(1 == ~M_E~0); 7301#L555-2 assume !(1 == ~T1_E~0); 7302#L560-1 assume !(1 == ~T2_E~0); 7190#L565-1 assume !(1 == ~T3_E~0); 7191#L570-1 assume !(1 == ~T4_E~0); 7261#L575-1 assume !(1 == ~E_1~0); 7262#L580-1 assume !(1 == ~E_2~0); 7428#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 7263#L590-1 assume !(1 == ~E_4~0); 7252#L595-1 assume { :end_inline_reset_delta_events } true; 7253#L776-2 [2022-11-16 12:16:15,961 INFO L750 eck$LassoCheckResult]: Loop: 7253#L776-2 assume !false; 7221#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7222#L477 assume !false; 7312#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7313#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7152#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7153#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7194#L416 assume !(0 != eval_~tmp~0#1); 7196#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7486#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7411#L502-3 assume !(0 == ~M_E~0); 7412#L502-5 assume !(0 == ~T1_E~0); 7441#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7360#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7361#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7347#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7348#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7429#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7363#L537-3 assume !(0 == ~E_4~0); 7364#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7375#L238-15 assume !(1 == ~m_pc~0); 7423#L238-17 is_master_triggered_~__retres1~0#1 := 0; 7461#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7462#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7282#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7283#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7213#L257-15 assume !(1 == ~t1_pc~0); 7214#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 7406#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7505#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7453#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7454#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7467#L276-15 assume 1 == ~t2_pc~0; 7344#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7325#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7326#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7538#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7420#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7247#L295-15 assume !(1 == ~t3_pc~0); 7248#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 7449#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7497#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7528#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7484#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7485#L314-15 assume 1 == ~t4_pc~0; 7401#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7402#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7342#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7343#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7472#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7418#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7148#L555-5 assume !(1 == ~T1_E~0); 7149#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7317#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7456#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7421#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7142#L580-3 assume !(1 == ~E_2~0); 7143#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7299#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7300#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7377#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7226#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7404#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7446#L795 assume !(0 == start_simulation_~tmp~3#1); 7448#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7468#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7182#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7330#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 7331#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7308#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7309#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7378#L808 assume !(0 != start_simulation_~tmp___0~1#1); 7253#L776-2 [2022-11-16 12:16:15,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:15,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1261932300, now seen corresponding path program 1 times [2022-11-16 12:16:15,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:15,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826154253] [2022-11-16 12:16:15,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:15,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:15,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:16,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:16,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:16,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826154253] [2022-11-16 12:16:16,042 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826154253] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:16,046 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:16,047 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:16,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303069779] [2022-11-16 12:16:16,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:16,048 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:16,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:16,048 INFO L85 PathProgramCache]: Analyzing trace with hash -21400384, now seen corresponding path program 1 times [2022-11-16 12:16:16,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:16,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815926774] [2022-11-16 12:16:16,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:16,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:16,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:16,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:16,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:16,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815926774] [2022-11-16 12:16:16,104 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815926774] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:16,104 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:16,104 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:16,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984030018] [2022-11-16 12:16:16,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:16,111 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:16,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:16,112 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:16:16,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:16:16,113 INFO L87 Difference]: Start difference. First operand 1163 states and 1693 transitions. cyclomatic complexity: 532 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:16,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:16,343 INFO L93 Difference]: Finished difference Result 2972 states and 4330 transitions. [2022-11-16 12:16:16,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2972 states and 4330 transitions. [2022-11-16 12:16:16,366 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2850 [2022-11-16 12:16:16,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2972 states to 2972 states and 4330 transitions. [2022-11-16 12:16:16,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2972 [2022-11-16 12:16:16,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2972 [2022-11-16 12:16:16,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2972 states and 4330 transitions. [2022-11-16 12:16:16,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:16,391 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2972 states and 4330 transitions. [2022-11-16 12:16:16,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states and 4330 transitions. [2022-11-16 12:16:16,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 1226. [2022-11-16 12:16:16,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1226 states, 1226 states have (on average 1.432300163132137) internal successors, (1756), 1225 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:16,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1226 states to 1226 states and 1756 transitions. [2022-11-16 12:16:16,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1226 states and 1756 transitions. [2022-11-16 12:16:16,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 12:16:16,427 INFO L428 stractBuchiCegarLoop]: Abstraction has 1226 states and 1756 transitions. [2022-11-16 12:16:16,427 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 12:16:16,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1226 states and 1756 transitions. [2022-11-16 12:16:16,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1158 [2022-11-16 12:16:16,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:16,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:16,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:16,437 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:16,437 INFO L748 eck$LassoCheckResult]: Stem: 11722#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 11659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11281#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11282#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11402#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 11517#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11365#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11366#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11378#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11379#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11424#L502 assume !(0 == ~M_E~0); 11425#L502-2 assume !(0 == ~T1_E~0); 11354#L507-1 assume !(0 == ~T2_E~0); 11355#L512-1 assume !(0 == ~T3_E~0); 11520#L517-1 assume !(0 == ~T4_E~0); 11326#L522-1 assume !(0 == ~E_1~0); 11327#L527-1 assume !(0 == ~E_2~0); 11542#L532-1 assume !(0 == ~E_3~0); 11654#L537-1 assume !(0 == ~E_4~0); 11673#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11643#L238 assume !(1 == ~m_pc~0); 11644#L238-2 is_master_triggered_~__retres1~0#1 := 0; 11292#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11293#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11620#L615 assume !(0 != activate_threads_~tmp~1#1); 11313#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11314#L257 assume !(1 == ~t1_pc~0); 11432#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11433#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11470#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11286#L623 assume !(0 != activate_threads_~tmp___0~0#1); 11287#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11283#L276 assume !(1 == ~t2_pc~0); 11284#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11552#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11680#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11689#L631 assume !(0 != activate_threads_~tmp___1~0#1); 11690#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11617#L295 assume 1 == ~t3_pc~0; 11444#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11399#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11598#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11655#L639 assume !(0 != activate_threads_~tmp___2~0#1); 11645#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11646#L314 assume !(1 == ~t4_pc~0); 11436#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11435#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11649#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11588#L647 assume !(0 != activate_threads_~tmp___3~0#1); 11534#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11535#L555 assume !(1 == ~M_E~0); 11449#L555-2 assume !(1 == ~T1_E~0); 11450#L560-1 assume !(1 == ~T2_E~0); 11328#L565-1 assume !(1 == ~T3_E~0); 11329#L570-1 assume !(1 == ~T4_E~0); 11409#L575-1 assume !(1 == ~E_1~0); 11410#L580-1 assume !(1 == ~E_2~0); 11589#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 11411#L590-1 assume !(1 == ~E_4~0); 11400#L595-1 assume { :end_inline_reset_delta_events } true; 11401#L776-2 [2022-11-16 12:16:16,437 INFO L750 eck$LassoCheckResult]: Loop: 11401#L776-2 assume !false; 11369#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11370#L477 assume !false; 11460#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11461#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11300#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11301#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11342#L416 assume !(0 != eval_~tmp~0#1); 11344#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12497#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12495#L502-3 assume !(0 == ~M_E~0); 12493#L502-5 assume !(0 == ~T1_E~0); 12491#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12489#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12487#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12485#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12483#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12481#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12480#L537-3 assume !(0 == ~E_4~0); 11525#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11526#L238-15 assume !(1 == ~m_pc~0); 12467#L238-17 is_master_triggered_~__retres1~0#1 := 0; 12466#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12465#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12464#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12463#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11361#L257-15 assume !(1 == ~t1_pc~0); 11362#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 12461#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11708#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11621#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11622#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11637#L276-15 assume !(1 == ~t2_pc~0); 12453#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 12451#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12449#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12448#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 12412#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12410#L295-15 assume !(1 == ~t3_pc~0); 12406#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 12404#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12401#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12399#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12397#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12395#L314-15 assume 1 == ~t4_pc~0; 12389#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12388#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11492#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11493#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12332#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12331#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12330#L555-5 assume !(1 == ~T1_E~0); 11465#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11466#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12314#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11580#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11290#L580-3 assume !(1 == ~E_2~0); 11291#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11447#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11448#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11532#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11374#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11561#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 11614#L795 assume !(0 == start_simulation_~tmp~3#1); 11616#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11638#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11336#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11479#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 11480#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11456#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11457#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 11533#L808 assume !(0 != start_simulation_~tmp___0~1#1); 11401#L776-2 [2022-11-16 12:16:16,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:16,438 INFO L85 PathProgramCache]: Analyzing trace with hash 1127918794, now seen corresponding path program 1 times [2022-11-16 12:16:16,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:16,439 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697717828] [2022-11-16 12:16:16,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:16,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:16,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:16,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:16,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:16,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697717828] [2022-11-16 12:16:16,499 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697717828] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:16,499 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:16,499 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:16,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [45609157] [2022-11-16 12:16:16,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:16,500 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:16,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:16,501 INFO L85 PathProgramCache]: Analyzing trace with hash -15775971, now seen corresponding path program 1 times [2022-11-16 12:16:16,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:16,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285178112] [2022-11-16 12:16:16,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:16,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:16,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:16,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:16,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:16,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285178112] [2022-11-16 12:16:16,556 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285178112] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:16,556 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:16,556 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:16,556 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855707621] [2022-11-16 12:16:16,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:16,557 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:16,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:16,558 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:16:16,558 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:16:16,559 INFO L87 Difference]: Start difference. First operand 1226 states and 1756 transitions. cyclomatic complexity: 532 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:16,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:16,727 INFO L93 Difference]: Finished difference Result 2784 states and 3948 transitions. [2022-11-16 12:16:16,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2784 states and 3948 transitions. [2022-11-16 12:16:16,750 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2624 [2022-11-16 12:16:16,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2784 states to 2784 states and 3948 transitions. [2022-11-16 12:16:16,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2784 [2022-11-16 12:16:16,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2784 [2022-11-16 12:16:16,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2784 states and 3948 transitions. [2022-11-16 12:16:16,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:16,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2784 states and 3948 transitions. [2022-11-16 12:16:16,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2784 states and 3948 transitions. [2022-11-16 12:16:16,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2784 to 2201. [2022-11-16 12:16:16,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2201 states, 2201 states have (on average 1.4279872785097683) internal successors, (3143), 2200 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:16,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2201 states to 2201 states and 3143 transitions. [2022-11-16 12:16:16,855 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2201 states and 3143 transitions. [2022-11-16 12:16:16,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:16:16,857 INFO L428 stractBuchiCegarLoop]: Abstraction has 2201 states and 3143 transitions. [2022-11-16 12:16:16,858 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 12:16:16,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2201 states and 3143 transitions. [2022-11-16 12:16:16,873 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2132 [2022-11-16 12:16:16,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:16,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:16,876 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:16,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:16,883 INFO L748 eck$LassoCheckResult]: Stem: 15727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 15673#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 15301#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15302#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15421#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 15540#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15385#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15386#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15398#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15399#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15443#L502 assume !(0 == ~M_E~0); 15444#L502-2 assume !(0 == ~T1_E~0); 15374#L507-1 assume !(0 == ~T2_E~0); 15375#L512-1 assume !(0 == ~T3_E~0); 15543#L517-1 assume !(0 == ~T4_E~0); 15346#L522-1 assume !(0 == ~E_1~0); 15347#L527-1 assume !(0 == ~E_2~0); 15561#L532-1 assume !(0 == ~E_3~0); 15665#L537-1 assume !(0 == ~E_4~0); 15688#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15654#L238 assume !(1 == ~m_pc~0); 15655#L238-2 is_master_triggered_~__retres1~0#1 := 0; 15312#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15313#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15633#L615 assume !(0 != activate_threads_~tmp~1#1); 15333#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15334#L257 assume !(1 == ~t1_pc~0); 15451#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15452#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15490#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15306#L623 assume !(0 != activate_threads_~tmp___0~0#1); 15307#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15303#L276 assume !(1 == ~t2_pc~0); 15304#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15570#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15400#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15401#L631 assume !(0 != activate_threads_~tmp___1~0#1); 15704#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15629#L295 assume !(1 == ~t3_pc~0); 15417#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15418#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15612#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15666#L639 assume !(0 != activate_threads_~tmp___2~0#1); 15656#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15657#L314 assume !(1 == ~t4_pc~0); 15456#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15455#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15660#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15604#L647 assume !(0 != activate_threads_~tmp___3~0#1); 15555#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15556#L555 assume !(1 == ~M_E~0); 15470#L555-2 assume !(1 == ~T1_E~0); 15471#L560-1 assume !(1 == ~T2_E~0); 15348#L565-1 assume !(1 == ~T3_E~0); 15349#L570-1 assume !(1 == ~T4_E~0); 15428#L575-1 assume !(1 == ~E_1~0); 15429#L580-1 assume !(1 == ~E_2~0); 15605#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 15430#L590-1 assume !(1 == ~E_4~0); 15419#L595-1 assume { :end_inline_reset_delta_events } true; 15420#L776-2 [2022-11-16 12:16:16,883 INFO L750 eck$LassoCheckResult]: Loop: 15420#L776-2 assume !false; 15389#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15390#L477 assume !false; 15480#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15481#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15320#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15321#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15362#L416 assume !(0 != eval_~tmp~0#1); 15364#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15669#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15588#L502-3 assume !(0 == ~M_E~0); 15589#L502-5 assume !(0 == ~T1_E~0); 15619#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15535#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15536#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15519#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15520#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15606#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15538#L537-3 assume !(0 == ~E_4~0); 15539#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15548#L238-15 assume !(1 == ~m_pc~0); 15600#L238-17 is_master_triggered_~__retres1~0#1 := 0; 15642#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15643#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15449#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15450#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15381#L257-15 assume !(1 == ~t1_pc~0); 15382#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 17460#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17458#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17456#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17454#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17452#L276-15 assume !(1 == ~t2_pc~0); 17448#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 17446#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17444#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17442#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 17439#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17437#L295-15 assume !(1 == ~t3_pc~0); 16565#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 17434#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17433#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17432#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17431#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17430#L314-15 assume 1 == ~t4_pc~0; 17421#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17419#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17418#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17416#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17414#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17412#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17410#L555-5 assume !(1 == ~T1_E~0); 17408#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17405#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17403#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17401#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17399#L580-3 assume !(1 == ~E_2~0); 17397#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17395#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17394#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 17389#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 17386#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 17385#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 17382#L795 assume !(0 == start_simulation_~tmp~3#1); 15659#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15649#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15356#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15500#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 15501#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15476#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15477#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 15554#L808 assume !(0 != start_simulation_~tmp___0~1#1); 15420#L776-2 [2022-11-16 12:16:16,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:16,884 INFO L85 PathProgramCache]: Analyzing trace with hash 1014532137, now seen corresponding path program 1 times [2022-11-16 12:16:16,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:16,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787973159] [2022-11-16 12:16:16,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:16,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:16,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:16,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:16,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:16,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1787973159] [2022-11-16 12:16:16,970 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1787973159] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:16,971 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:16,971 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:16,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004000166] [2022-11-16 12:16:16,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:16,972 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:16,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:16,972 INFO L85 PathProgramCache]: Analyzing trace with hash -15775971, now seen corresponding path program 2 times [2022-11-16 12:16:16,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:16,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159998355] [2022-11-16 12:16:16,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:16,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:16,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:17,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:17,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:17,019 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159998355] [2022-11-16 12:16:17,019 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1159998355] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:17,020 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:17,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:17,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259248837] [2022-11-16 12:16:17,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:17,020 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:17,021 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:17,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:16:17,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:16:17,022 INFO L87 Difference]: Start difference. First operand 2201 states and 3143 transitions. cyclomatic complexity: 944 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:17,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:17,204 INFO L93 Difference]: Finished difference Result 4550 states and 6445 transitions. [2022-11-16 12:16:17,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4550 states and 6445 transitions. [2022-11-16 12:16:17,237 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4372 [2022-11-16 12:16:17,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4550 states to 4550 states and 6445 transitions. [2022-11-16 12:16:17,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4550 [2022-11-16 12:16:17,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4550 [2022-11-16 12:16:17,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4550 states and 6445 transitions. [2022-11-16 12:16:17,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:17,278 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4550 states and 6445 transitions. [2022-11-16 12:16:17,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4550 states and 6445 transitions. [2022-11-16 12:16:17,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4550 to 4494. [2022-11-16 12:16:17,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4494 states, 4494 states have (on average 1.4181130396083668) internal successors, (6373), 4493 states have internal predecessors, (6373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:17,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4494 states to 4494 states and 6373 transitions. [2022-11-16 12:16:17,379 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4494 states and 6373 transitions. [2022-11-16 12:16:17,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:16:17,381 INFO L428 stractBuchiCegarLoop]: Abstraction has 4494 states and 6373 transitions. [2022-11-16 12:16:17,381 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 12:16:17,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4494 states and 6373 transitions. [2022-11-16 12:16:17,404 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4324 [2022-11-16 12:16:17,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:17,405 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:17,406 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:17,406 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:17,407 INFO L748 eck$LassoCheckResult]: Stem: 22521#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 22451#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 22062#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22063#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22184#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 22298#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22147#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22148#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22160#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22161#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22205#L502 assume !(0 == ~M_E~0); 22206#L502-2 assume !(0 == ~T1_E~0); 22135#L507-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22136#L512-1 assume !(0 == ~T3_E~0); 22301#L517-1 assume !(0 == ~T4_E~0); 22107#L522-1 assume !(0 == ~E_1~0); 22108#L527-1 assume !(0 == ~E_2~0); 22442#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 22443#L537-1 assume !(0 == ~E_4~0); 22591#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22589#L238 assume !(1 == ~m_pc~0); 22587#L238-2 is_master_triggered_~__retres1~0#1 := 0; 22585#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22583#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22581#L615 assume !(0 != activate_threads_~tmp~1#1); 22579#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22577#L257 assume !(1 == ~t1_pc~0); 22576#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22573#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22571#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22569#L623 assume !(0 != activate_threads_~tmp___0~0#1); 22568#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22566#L276 assume !(1 == ~t2_pc~0); 22564#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22562#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22560#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22556#L631 assume !(0 != activate_threads_~tmp___1~0#1); 22555#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22554#L295 assume !(1 == ~t3_pc~0); 22553#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22552#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22551#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22550#L639 assume !(0 != activate_threads_~tmp___2~0#1); 22549#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22548#L314 assume !(1 == ~t4_pc~0); 22547#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22545#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22544#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22543#L647 assume !(0 != activate_threads_~tmp___3~0#1); 22542#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22541#L555 assume !(1 == ~M_E~0); 22540#L555-2 assume !(1 == ~T1_E~0); 22539#L560-1 assume !(1 == ~T2_E~0); 22538#L565-1 assume !(1 == ~T3_E~0); 22537#L570-1 assume !(1 == ~T4_E~0); 22536#L575-1 assume !(1 == ~E_1~0); 22535#L580-1 assume !(1 == ~E_2~0); 22534#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 22193#L590-1 assume !(1 == ~E_4~0); 22182#L595-1 assume { :end_inline_reset_delta_events } true; 22183#L776-2 [2022-11-16 12:16:17,407 INFO L750 eck$LassoCheckResult]: Loop: 22183#L776-2 assume !false; 26069#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26062#L477 assume !false; 26058#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 26051#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 22081#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 22082#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25582#L416 assume !(0 != eval_~tmp~0#1); 25583#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26452#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26450#L502-3 assume !(0 == ~M_E~0); 26449#L502-5 assume !(0 == ~T1_E~0); 26447#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25875#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26448#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26446#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26445#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26442#L532-3 assume !(0 == ~E_3~0); 26443#L537-3 assume !(0 == ~E_4~0); 26498#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26497#L238-15 assume !(1 == ~m_pc~0); 26496#L238-17 is_master_triggered_~__retres1~0#1 := 0; 26495#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26494#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26493#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26492#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26491#L257-15 assume !(1 == ~t1_pc~0); 26328#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 26490#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26489#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26488#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26487#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26486#L276-15 assume 1 == ~t2_pc~0; 26403#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26400#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26398#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26363#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26361#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26359#L295-15 assume !(1 == ~t3_pc~0); 22515#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 22516#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26358#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22508#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22446#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22447#L314-15 assume 1 == ~t4_pc~0; 22336#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22337#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26351#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26350#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26349#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26348#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22077#L555-5 assume !(1 == ~T1_E~0); 22078#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22245#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22407#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22363#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22071#L580-3 assume !(1 == ~E_2~0); 22072#L585-3 assume !(1 == ~E_3~0); 22228#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22229#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 22314#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 22156#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 26155#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 26149#L795 assume !(0 == start_simulation_~tmp~3#1); 26145#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 26138#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 26132#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 22258#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 22259#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22236#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22237#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 22315#L808 assume !(0 != start_simulation_~tmp___0~1#1); 22183#L776-2 [2022-11-16 12:16:17,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:17,408 INFO L85 PathProgramCache]: Analyzing trace with hash -27236631, now seen corresponding path program 1 times [2022-11-16 12:16:17,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:17,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094730054] [2022-11-16 12:16:17,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:17,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:17,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:17,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:17,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:17,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094730054] [2022-11-16 12:16:17,443 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094730054] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:17,443 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:17,444 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:17,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1344591368] [2022-11-16 12:16:17,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:17,444 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:17,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:17,445 INFO L85 PathProgramCache]: Analyzing trace with hash 85521348, now seen corresponding path program 1 times [2022-11-16 12:16:17,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:17,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425192869] [2022-11-16 12:16:17,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:17,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:17,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:17,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:17,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:17,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425192869] [2022-11-16 12:16:17,535 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425192869] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:17,535 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:17,536 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:17,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559484253] [2022-11-16 12:16:17,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:17,536 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:17,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:17,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:17,538 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:17,538 INFO L87 Difference]: Start difference. First operand 4494 states and 6373 transitions. cyclomatic complexity: 1883 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:17,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:17,574 INFO L93 Difference]: Finished difference Result 4444 states and 6260 transitions. [2022-11-16 12:16:17,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4444 states and 6260 transitions. [2022-11-16 12:16:17,614 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4324 [2022-11-16 12:16:17,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4444 states to 4444 states and 6260 transitions. [2022-11-16 12:16:17,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4444 [2022-11-16 12:16:17,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4444 [2022-11-16 12:16:17,645 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4444 states and 6260 transitions. [2022-11-16 12:16:17,651 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:17,651 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4444 states and 6260 transitions. [2022-11-16 12:16:17,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4444 states and 6260 transitions. [2022-11-16 12:16:17,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4444 to 2614. [2022-11-16 12:16:17,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2614 states, 2614 states have (on average 1.4020657995409334) internal successors, (3665), 2613 states have internal predecessors, (3665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:17,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2614 states to 2614 states and 3665 transitions. [2022-11-16 12:16:17,712 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2614 states and 3665 transitions. [2022-11-16 12:16:17,713 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:17,713 INFO L428 stractBuchiCegarLoop]: Abstraction has 2614 states and 3665 transitions. [2022-11-16 12:16:17,714 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 12:16:17,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2614 states and 3665 transitions. [2022-11-16 12:16:17,726 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2500 [2022-11-16 12:16:17,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:17,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:17,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:17,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:17,729 INFO L748 eck$LassoCheckResult]: Stem: 31467#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 31388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 31007#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31008#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31129#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 31242#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31091#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31092#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31104#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31105#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31150#L502 assume !(0 == ~M_E~0); 31151#L502-2 assume !(0 == ~T1_E~0); 31080#L507-1 assume !(0 == ~T2_E~0); 31081#L512-1 assume !(0 == ~T3_E~0); 31245#L517-1 assume !(0 == ~T4_E~0); 31052#L522-1 assume !(0 == ~E_1~0); 31053#L527-1 assume !(0 == ~E_2~0); 31263#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 31378#L537-1 assume !(0 == ~E_4~0); 31449#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31367#L238 assume !(1 == ~m_pc~0); 31368#L238-2 is_master_triggered_~__retres1~0#1 := 0; 31018#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31019#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31344#L615 assume !(0 != activate_threads_~tmp~1#1); 31345#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31313#L257 assume !(1 == ~t1_pc~0); 31314#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31363#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31364#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31486#L623 assume !(0 != activate_threads_~tmp___0~0#1); 31113#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31114#L276 assume !(1 == ~t2_pc~0); 31272#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31273#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31106#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31107#L631 assume !(0 != activate_threads_~tmp___1~0#1); 31447#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31448#L295 assume !(1 == ~t3_pc~0); 31125#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31126#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31432#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31433#L639 assume !(0 != activate_threads_~tmp___2~0#1); 31369#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31370#L314 assume !(1 == ~t4_pc~0); 31163#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31162#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31373#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31374#L647 assume !(0 != activate_threads_~tmp___3~0#1); 31257#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31258#L555 assume !(1 == ~M_E~0); 31176#L555-2 assume !(1 == ~T1_E~0); 31177#L560-1 assume !(1 == ~T2_E~0); 31054#L565-1 assume !(1 == ~T3_E~0); 31055#L570-1 assume !(1 == ~T4_E~0); 31485#L575-1 assume !(1 == ~E_1~0); 31311#L580-1 assume !(1 == ~E_2~0); 31312#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 31138#L590-1 assume !(1 == ~E_4~0); 31127#L595-1 assume { :end_inline_reset_delta_events } true; 31128#L776-2 [2022-11-16 12:16:17,729 INFO L750 eck$LassoCheckResult]: Loop: 31128#L776-2 assume !false; 31095#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31096#L477 assume !false; 31186#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31187#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31026#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31027#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31068#L416 assume !(0 != eval_~tmp~0#1); 31070#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33381#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33379#L502-3 assume !(0 == ~M_E~0); 33377#L502-5 assume !(0 == ~T1_E~0); 33374#L507-3 assume !(0 == ~T2_E~0); 33372#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33370#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33368#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33367#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31415#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31416#L537-3 assume !(0 == ~E_4~0); 33550#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33549#L238-15 assume !(1 == ~m_pc~0); 33548#L238-17 is_master_triggered_~__retres1~0#1 := 0; 33547#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33546#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33545#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33544#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33543#L257-15 assume !(1 == ~t1_pc~0); 33297#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 33542#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33541#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33540#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33539#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33538#L276-15 assume 1 == ~t2_pc~0; 33536#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33534#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33532#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33530#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33529#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33528#L295-15 assume !(1 == ~t3_pc~0); 33028#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 33527#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33526#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33525#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33524#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33523#L314-15 assume 1 == ~t4_pc~0; 33521#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33520#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33519#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33518#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33517#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33516#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33515#L555-5 assume !(1 == ~T1_E~0); 33514#L560-3 assume !(1 == ~T2_E~0); 33513#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33512#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33511#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33510#L580-3 assume !(1 == ~E_2~0); 33509#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31174#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31175#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31255#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31100#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31282#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 31337#L795 assume !(0 == start_simulation_~tmp~3#1); 31339#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31360#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31062#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31203#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 31204#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31182#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31183#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 31256#L808 assume !(0 != start_simulation_~tmp___0~1#1); 31128#L776-2 [2022-11-16 12:16:17,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:17,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1911925415, now seen corresponding path program 1 times [2022-11-16 12:16:17,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:17,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433951481] [2022-11-16 12:16:17,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:17,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:17,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:17,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:17,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:17,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433951481] [2022-11-16 12:16:17,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1433951481] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:17,781 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:17,781 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:17,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207195159] [2022-11-16 12:16:17,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:17,783 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:17,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:17,784 INFO L85 PathProgramCache]: Analyzing trace with hash -637224900, now seen corresponding path program 1 times [2022-11-16 12:16:17,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:17,784 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113279863] [2022-11-16 12:16:17,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:17,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:17,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:17,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:17,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:17,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113279863] [2022-11-16 12:16:17,830 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113279863] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:17,830 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:17,830 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:17,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319471945] [2022-11-16 12:16:17,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:17,831 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:17,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:17,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:16:17,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:16:17,832 INFO L87 Difference]: Start difference. First operand 2614 states and 3665 transitions. cyclomatic complexity: 1053 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:17,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:17,927 INFO L93 Difference]: Finished difference Result 4037 states and 5667 transitions. [2022-11-16 12:16:17,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4037 states and 5667 transitions. [2022-11-16 12:16:17,950 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3956 [2022-11-16 12:16:17,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4037 states to 4037 states and 5667 transitions. [2022-11-16 12:16:17,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4037 [2022-11-16 12:16:17,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4037 [2022-11-16 12:16:17,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4037 states and 5667 transitions. [2022-11-16 12:16:17,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:17,989 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4037 states and 5667 transitions. [2022-11-16 12:16:18,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4037 states and 5667 transitions. [2022-11-16 12:16:18,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4037 to 2201. [2022-11-16 12:16:18,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2201 states, 2201 states have (on average 1.39709223080418) internal successors, (3075), 2200 states have internal predecessors, (3075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:18,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2201 states to 2201 states and 3075 transitions. [2022-11-16 12:16:18,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2201 states and 3075 transitions. [2022-11-16 12:16:18,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:16:18,072 INFO L428 stractBuchiCegarLoop]: Abstraction has 2201 states and 3075 transitions. [2022-11-16 12:16:18,072 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 12:16:18,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2201 states and 3075 transitions. [2022-11-16 12:16:18,082 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2132 [2022-11-16 12:16:18,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:18,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:18,084 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:18,084 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:18,084 INFO L748 eck$LassoCheckResult]: Stem: 38095#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 38039#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 37668#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37669#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37788#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 37902#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37752#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37753#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37765#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37766#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37809#L502 assume !(0 == ~M_E~0); 37810#L502-2 assume !(0 == ~T1_E~0); 37741#L507-1 assume !(0 == ~T2_E~0); 37742#L512-1 assume !(0 == ~T3_E~0); 37905#L517-1 assume !(0 == ~T4_E~0); 37713#L522-1 assume !(0 == ~E_1~0); 37714#L527-1 assume !(0 == ~E_2~0); 37924#L532-1 assume !(0 == ~E_3~0); 38031#L537-1 assume !(0 == ~E_4~0); 38052#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38021#L238 assume !(1 == ~m_pc~0); 38022#L238-2 is_master_triggered_~__retres1~0#1 := 0; 37679#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37680#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37999#L615 assume !(0 != activate_threads_~tmp~1#1); 37700#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37701#L257 assume !(1 == ~t1_pc~0); 37817#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37818#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37853#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37673#L623 assume !(0 != activate_threads_~tmp___0~0#1); 37674#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37670#L276 assume !(1 == ~t2_pc~0); 37671#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 37934#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37767#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37768#L631 assume !(0 != activate_threads_~tmp___1~0#1); 38067#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37995#L295 assume !(1 == ~t3_pc~0); 37784#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37785#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37979#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38032#L639 assume !(0 != activate_threads_~tmp___2~0#1); 38023#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38024#L314 assume !(1 == ~t4_pc~0); 37822#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37821#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38027#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37969#L647 assume !(0 != activate_threads_~tmp___3~0#1); 37917#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37918#L555 assume !(1 == ~M_E~0); 37835#L555-2 assume !(1 == ~T1_E~0); 37836#L560-1 assume !(1 == ~T2_E~0); 37715#L565-1 assume !(1 == ~T3_E~0); 37716#L570-1 assume !(1 == ~T4_E~0); 37795#L575-1 assume !(1 == ~E_1~0); 37796#L580-1 assume !(1 == ~E_2~0); 37970#L585-1 assume !(1 == ~E_3~0); 37797#L590-1 assume !(1 == ~E_4~0); 37786#L595-1 assume { :end_inline_reset_delta_events } true; 37787#L776-2 [2022-11-16 12:16:18,085 INFO L750 eck$LassoCheckResult]: Loop: 37787#L776-2 assume !false; 39226#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39183#L477 assume !false; 39181#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 39165#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 39159#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 39155#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39148#L416 assume !(0 != eval_~tmp~0#1); 39149#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39856#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39855#L502-3 assume !(0 == ~M_E~0); 39854#L502-5 assume !(0 == ~T1_E~0); 39853#L507-3 assume !(0 == ~T2_E~0); 39852#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39851#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37883#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37884#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38059#L532-3 assume !(0 == ~E_3~0); 37900#L537-3 assume !(0 == ~E_4~0); 37901#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37910#L238-15 assume !(1 == ~m_pc~0); 37964#L238-17 is_master_triggered_~__retres1~0#1 := 0; 39804#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38086#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37815#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37816#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37748#L257-15 assume !(1 == ~t1_pc~0); 37749#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 37945#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38056#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38000#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38001#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38014#L276-15 assume 1 == ~t2_pc~0; 37879#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37880#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39785#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39783#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37960#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37782#L295-15 assume !(1 == ~t3_pc~0); 37783#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 39552#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39550#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39548#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39544#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39542#L314-15 assume 1 == ~t4_pc~0; 39539#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39537#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39534#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39504#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39503#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39502#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39501#L555-5 assume !(1 == ~T1_E~0); 39500#L560-3 assume !(1 == ~T2_E~0); 39499#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39497#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39495#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39493#L580-3 assume !(1 == ~E_2~0); 39491#L585-3 assume !(1 == ~E_3~0); 39472#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39463#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 39456#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 39450#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 39444#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 39438#L795 assume !(0 == start_simulation_~tmp~3#1); 39398#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 39252#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 39246#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 39244#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 39242#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39240#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39237#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 39235#L808 assume !(0 != start_simulation_~tmp___0~1#1); 37787#L776-2 [2022-11-16 12:16:18,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:18,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2022-11-16 12:16:18,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:18,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872594776] [2022-11-16 12:16:18,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:18,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:18,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:18,100 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:18,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:18,154 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:18,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:18,155 INFO L85 PathProgramCache]: Analyzing trace with hash -530303168, now seen corresponding path program 1 times [2022-11-16 12:16:18,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:18,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955439457] [2022-11-16 12:16:18,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:18,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:18,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:18,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:18,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:18,196 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955439457] [2022-11-16 12:16:18,196 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955439457] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:18,196 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:18,196 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:18,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772280748] [2022-11-16 12:16:18,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:18,197 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:18,197 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:18,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:18,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:18,198 INFO L87 Difference]: Start difference. First operand 2201 states and 3075 transitions. cyclomatic complexity: 876 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:18,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:18,275 INFO L93 Difference]: Finished difference Result 3747 states and 5191 transitions. [2022-11-16 12:16:18,275 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3747 states and 5191 transitions. [2022-11-16 12:16:18,296 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3632 [2022-11-16 12:16:18,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3747 states to 3747 states and 5191 transitions. [2022-11-16 12:16:18,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3747 [2022-11-16 12:16:18,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3747 [2022-11-16 12:16:18,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3747 states and 5191 transitions. [2022-11-16 12:16:18,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:18,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3747 states and 5191 transitions. [2022-11-16 12:16:18,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3747 states and 5191 transitions. [2022-11-16 12:16:18,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3747 to 3743. [2022-11-16 12:16:18,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3743 states, 3743 states have (on average 1.385786802030457) internal successors, (5187), 3742 states have internal predecessors, (5187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:18,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3743 states to 3743 states and 5187 transitions. [2022-11-16 12:16:18,410 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3743 states and 5187 transitions. [2022-11-16 12:16:18,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:18,412 INFO L428 stractBuchiCegarLoop]: Abstraction has 3743 states and 5187 transitions. [2022-11-16 12:16:18,412 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 12:16:18,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3743 states and 5187 transitions. [2022-11-16 12:16:18,431 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3628 [2022-11-16 12:16:18,431 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:18,431 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:18,433 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:18,433 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:18,434 INFO L748 eck$LassoCheckResult]: Stem: 44081#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 44005#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 43622#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43623#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43746#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 43862#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43706#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43707#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43719#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43720#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43763#L502 assume !(0 == ~M_E~0); 43764#L502-2 assume !(0 == ~T1_E~0); 43698#L507-1 assume !(0 == ~T2_E~0); 43699#L512-1 assume !(0 == ~T3_E~0); 43864#L517-1 assume !(0 == ~T4_E~0); 43677#L522-1 assume !(0 == ~E_1~0); 43678#L527-1 assume 0 == ~E_2~0;~E_2~0 := 1; 43886#L532-1 assume !(0 == ~E_3~0); 43997#L537-1 assume !(0 == ~E_4~0); 44112#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44111#L238 assume !(1 == ~m_pc~0); 44110#L238-2 is_master_triggered_~__retres1~0#1 := 0; 44109#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44108#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 44107#L615 assume !(0 != activate_threads_~tmp~1#1); 43658#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43659#L257 assume !(1 == ~t1_pc~0); 43934#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44105#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44104#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 44103#L623 assume !(0 != activate_threads_~tmp___0~0#1); 44102#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43624#L276 assume !(1 == ~t2_pc~0); 43625#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43900#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43721#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43722#L631 assume !(0 != activate_threads_~tmp___1~0#1); 44057#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43963#L295 assume !(1 == ~t3_pc~0); 43738#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43739#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43946#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44118#L639 assume !(0 != activate_threads_~tmp___2~0#1); 44117#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44072#L314 assume !(1 == ~t4_pc~0); 44073#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44030#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43992#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43993#L647 assume !(0 != activate_threads_~tmp___3~0#1); 43877#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43878#L555 assume !(1 == ~M_E~0); 44088#L555-2 assume !(1 == ~T1_E~0); 44099#L560-1 assume !(1 == ~T2_E~0); 44098#L565-1 assume !(1 == ~T3_E~0); 44097#L570-1 assume !(1 == ~T4_E~0); 44096#L575-1 assume !(1 == ~E_1~0); 43932#L580-1 assume 1 == ~E_2~0;~E_2~0 := 2; 43933#L585-1 assume !(1 == ~E_3~0); 43751#L590-1 assume !(1 == ~E_4~0); 43740#L595-1 assume { :end_inline_reset_delta_events } true; 43741#L776-2 [2022-11-16 12:16:18,434 INFO L750 eck$LassoCheckResult]: Loop: 43741#L776-2 assume !false; 43710#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43711#L477 assume !false; 46936#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 46932#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 46929#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 46928#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46926#L416 assume !(0 != eval_~tmp~0#1); 44080#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44001#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43914#L502-3 assume !(0 == ~M_E~0); 43915#L502-5 assume !(0 == ~T1_E~0); 43953#L507-3 assume !(0 == ~T2_E~0); 43855#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43856#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43839#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43840#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47019#L532-3 assume !(0 == ~E_3~0); 47199#L537-3 assume !(0 == ~E_4~0); 47198#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47197#L238-15 assume !(1 == ~m_pc~0); 47196#L238-17 is_master_triggered_~__retres1~0#1 := 0; 47195#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47194#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 47193#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47192#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47191#L257-15 assume !(1 == ~t1_pc~0); 46170#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 47190#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47189#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 47188#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47187#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47185#L276-15 assume !(1 == ~t2_pc~0); 47184#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 47183#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47182#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 47181#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 47179#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46907#L295-15 assume !(1 == ~t3_pc~0); 46904#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 46902#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46900#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46898#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46896#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46894#L314-15 assume 1 == ~t4_pc~0; 46891#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46889#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46887#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46885#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46883#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46882#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46881#L555-5 assume !(1 == ~T1_E~0); 46878#L560-3 assume !(1 == ~T2_E~0); 46876#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46874#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46872#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46870#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46867#L585-3 assume !(1 == ~E_3~0); 43790#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43791#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43873#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43715#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43906#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 43958#L795 assume !(0 == start_simulation_~tmp~3#1); 43960#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43980#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43671#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43821#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 43822#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43798#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43799#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 46628#L808 assume !(0 != start_simulation_~tmp___0~1#1); 43741#L776-2 [2022-11-16 12:16:18,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:18,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1231104977, now seen corresponding path program 1 times [2022-11-16 12:16:18,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:18,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81790532] [2022-11-16 12:16:18,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:18,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:18,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:18,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:18,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:18,481 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81790532] [2022-11-16 12:16:18,481 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [81790532] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:18,481 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:18,481 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:18,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1541452878] [2022-11-16 12:16:18,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:18,485 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:18,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:18,487 INFO L85 PathProgramCache]: Analyzing trace with hash 496389599, now seen corresponding path program 1 times [2022-11-16 12:16:18,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:18,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558292975] [2022-11-16 12:16:18,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:18,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:18,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:18,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:18,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:18,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1558292975] [2022-11-16 12:16:18,572 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1558292975] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:18,572 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:18,573 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:18,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093665062] [2022-11-16 12:16:18,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:18,574 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:18,574 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:18,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:18,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:18,575 INFO L87 Difference]: Start difference. First operand 3743 states and 5187 transitions. cyclomatic complexity: 1446 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:18,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:18,621 INFO L93 Difference]: Finished difference Result 2102 states and 2880 transitions. [2022-11-16 12:16:18,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2102 states and 2880 transitions. [2022-11-16 12:16:18,633 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2036 [2022-11-16 12:16:18,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2102 states to 2102 states and 2880 transitions. [2022-11-16 12:16:18,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2102 [2022-11-16 12:16:18,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2102 [2022-11-16 12:16:18,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2102 states and 2880 transitions. [2022-11-16 12:16:18,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:18,647 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2102 states and 2880 transitions. [2022-11-16 12:16:18,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2102 states and 2880 transitions. [2022-11-16 12:16:18,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2102 to 2102. [2022-11-16 12:16:18,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2102 states, 2102 states have (on average 1.3701236917221693) internal successors, (2880), 2101 states have internal predecessors, (2880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:18,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2102 states to 2102 states and 2880 transitions. [2022-11-16 12:16:18,685 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2102 states and 2880 transitions. [2022-11-16 12:16:18,685 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:18,686 INFO L428 stractBuchiCegarLoop]: Abstraction has 2102 states and 2880 transitions. [2022-11-16 12:16:18,686 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 12:16:18,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2102 states and 2880 transitions. [2022-11-16 12:16:18,695 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2036 [2022-11-16 12:16:18,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:18,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:18,697 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:18,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:18,697 INFO L748 eck$LassoCheckResult]: Stem: 49889#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 49840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 49476#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49477#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49597#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 49708#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49560#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49561#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49573#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49574#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49616#L502 assume !(0 == ~M_E~0); 49617#L502-2 assume !(0 == ~T1_E~0); 49549#L507-1 assume !(0 == ~T2_E~0); 49550#L512-1 assume !(0 == ~T3_E~0); 49709#L517-1 assume !(0 == ~T4_E~0); 49527#L522-1 assume !(0 == ~E_1~0); 49528#L527-1 assume !(0 == ~E_2~0); 49728#L532-1 assume !(0 == ~E_3~0); 49834#L537-1 assume !(0 == ~E_4~0); 49853#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49824#L238 assume !(1 == ~m_pc~0); 49825#L238-2 is_master_triggered_~__retres1~0#1 := 0; 49489#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49490#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 49804#L615 assume !(0 != activate_threads_~tmp~1#1); 49508#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49509#L257 assume !(1 == ~t1_pc~0); 49624#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49625#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49659#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 49483#L623 assume !(0 != activate_threads_~tmp___0~0#1); 49484#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49478#L276 assume !(1 == ~t2_pc~0); 49479#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49737#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49575#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 49576#L631 assume !(0 != activate_threads_~tmp___1~0#1); 49866#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49800#L295 assume !(1 == ~t3_pc~0); 49591#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49592#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49781#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49835#L639 assume !(0 != activate_threads_~tmp___2~0#1); 49828#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49829#L314 assume !(1 == ~t4_pc~0); 49629#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49628#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49830#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49773#L647 assume !(0 != activate_threads_~tmp___3~0#1); 49722#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49723#L555 assume !(1 == ~M_E~0); 49641#L555-2 assume !(1 == ~T1_E~0); 49642#L560-1 assume !(1 == ~T2_E~0); 49529#L565-1 assume !(1 == ~T3_E~0); 49530#L570-1 assume !(1 == ~T4_E~0); 49602#L575-1 assume !(1 == ~E_1~0); 49603#L580-1 assume !(1 == ~E_2~0); 49774#L585-1 assume !(1 == ~E_3~0); 49604#L590-1 assume !(1 == ~E_4~0); 49593#L595-1 assume { :end_inline_reset_delta_events } true; 49594#L776-2 [2022-11-16 12:16:18,698 INFO L750 eck$LassoCheckResult]: Loop: 49594#L776-2 assume !false; 49564#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49565#L477 assume !false; 49651#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 49652#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 49497#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 49498#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49537#L416 assume !(0 != eval_~tmp~0#1); 49539#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51564#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51563#L502-3 assume !(0 == ~M_E~0); 51562#L502-5 assume !(0 == ~T1_E~0); 51561#L507-3 assume !(0 == ~T2_E~0); 51560#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51559#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51558#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51557#L527-3 assume !(0 == ~E_2~0); 51556#L532-3 assume !(0 == ~E_3~0); 51554#L537-3 assume !(0 == ~E_4~0); 51552#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51550#L238-15 assume !(1 == ~m_pc~0); 51547#L238-17 is_master_triggered_~__retres1~0#1 := 0; 51529#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51528#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 51527#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51525#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49556#L257-15 assume !(1 == ~t1_pc~0); 49557#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 51494#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51492#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51490#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51489#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51487#L276-15 assume !(1 == ~t2_pc~0); 51484#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 51482#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51480#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51478#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 51475#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51473#L295-15 assume !(1 == ~t3_pc~0); 50776#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 51470#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51468#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51466#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51464#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51462#L314-15 assume 1 == ~t4_pc~0; 51459#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51457#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51455#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51453#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51451#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51449#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51448#L555-5 assume !(1 == ~T1_E~0); 51447#L560-3 assume !(1 == ~T2_E~0); 51446#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51445#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51443#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51441#L580-3 assume !(1 == ~E_2~0); 51439#L585-3 assume !(1 == ~E_3~0); 51437#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51435#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 51426#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 51422#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 51420#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 51418#L795 assume !(0 == start_simulation_~tmp~3#1); 51416#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 51406#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 51402#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 51401#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 51399#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51397#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49719#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 49720#L808 assume !(0 != start_simulation_~tmp___0~1#1); 49594#L776-2 [2022-11-16 12:16:18,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:18,698 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2022-11-16 12:16:18,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:18,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520561788] [2022-11-16 12:16:18,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:18,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:18,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:18,709 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:18,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:18,727 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:18,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:18,728 INFO L85 PathProgramCache]: Analyzing trace with hash -484004005, now seen corresponding path program 1 times [2022-11-16 12:16:18,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:18,728 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22871376] [2022-11-16 12:16:18,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:18,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:18,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:18,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:18,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:18,780 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [22871376] [2022-11-16 12:16:18,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [22871376] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:18,781 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:18,781 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:18,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [210154449] [2022-11-16 12:16:18,781 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:18,782 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:18,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:18,782 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:16:18,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:16:18,783 INFO L87 Difference]: Start difference. First operand 2102 states and 2880 transitions. cyclomatic complexity: 780 Second operand has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:18,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:18,901 INFO L93 Difference]: Finished difference Result 3666 states and 4960 transitions. [2022-11-16 12:16:18,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3666 states and 4960 transitions. [2022-11-16 12:16:18,922 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3596 [2022-11-16 12:16:18,935 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3666 states to 3666 states and 4960 transitions. [2022-11-16 12:16:18,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3666 [2022-11-16 12:16:18,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3666 [2022-11-16 12:16:18,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3666 states and 4960 transitions. [2022-11-16 12:16:18,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:18,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3666 states and 4960 transitions. [2022-11-16 12:16:18,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3666 states and 4960 transitions. [2022-11-16 12:16:18,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3666 to 2126. [2022-11-16 12:16:18,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2126 states, 2126 states have (on average 1.3659454374412041) internal successors, (2904), 2125 states have internal predecessors, (2904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:18,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2126 states to 2126 states and 2904 transitions. [2022-11-16 12:16:18,996 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2126 states and 2904 transitions. [2022-11-16 12:16:18,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 12:16:18,997 INFO L428 stractBuchiCegarLoop]: Abstraction has 2126 states and 2904 transitions. [2022-11-16 12:16:18,997 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 12:16:18,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2126 states and 2904 transitions. [2022-11-16 12:16:19,008 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2060 [2022-11-16 12:16:19,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:19,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:19,010 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:19,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:19,011 INFO L748 eck$LassoCheckResult]: Stem: 55692#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 55629#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 55260#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55261#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55378#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 55493#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55343#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55344#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55356#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55357#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55400#L502 assume !(0 == ~M_E~0); 55401#L502-2 assume !(0 == ~T1_E~0); 55332#L507-1 assume !(0 == ~T2_E~0); 55333#L512-1 assume !(0 == ~T3_E~0); 55496#L517-1 assume !(0 == ~T4_E~0); 55305#L522-1 assume !(0 == ~E_1~0); 55306#L527-1 assume !(0 == ~E_2~0); 55517#L532-1 assume !(0 == ~E_3~0); 55621#L537-1 assume !(0 == ~E_4~0); 55645#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55610#L238 assume !(1 == ~m_pc~0); 55611#L238-2 is_master_triggered_~__retres1~0#1 := 0; 55271#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55272#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 55592#L615 assume !(0 != activate_threads_~tmp~1#1); 55292#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55293#L257 assume !(1 == ~t1_pc~0); 55408#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55409#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55444#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55265#L623 assume !(0 != activate_threads_~tmp___0~0#1); 55266#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55262#L276 assume !(1 == ~t2_pc~0); 55263#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55527#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55358#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55359#L631 assume !(0 != activate_threads_~tmp___1~0#1); 55662#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55587#L295 assume !(1 == ~t3_pc~0); 55374#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55375#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55569#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55622#L639 assume !(0 != activate_threads_~tmp___2~0#1); 55612#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55613#L314 assume !(1 == ~t4_pc~0); 55413#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55412#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55616#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55562#L647 assume !(0 != activate_threads_~tmp___3~0#1); 55510#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55511#L555 assume !(1 == ~M_E~0); 55426#L555-2 assume !(1 == ~T1_E~0); 55427#L560-1 assume !(1 == ~T2_E~0); 55307#L565-1 assume !(1 == ~T3_E~0); 55308#L570-1 assume !(1 == ~T4_E~0); 55385#L575-1 assume !(1 == ~E_1~0); 55386#L580-1 assume !(1 == ~E_2~0); 55563#L585-1 assume !(1 == ~E_3~0); 55387#L590-1 assume !(1 == ~E_4~0); 55376#L595-1 assume { :end_inline_reset_delta_events } true; 55377#L776-2 [2022-11-16 12:16:19,011 INFO L750 eck$LassoCheckResult]: Loop: 55377#L776-2 assume !false; 56863#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56854#L477 assume !false; 56789#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 56787#L374 assume !(0 == ~m_st~0); 56785#L378 assume !(0 == ~t1_st~0); 56783#L382 assume !(0 == ~t2_st~0); 56781#L386 assume !(0 == ~t3_st~0); 56772#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 56768#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 56764#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 56335#L416 assume !(0 != eval_~tmp~0#1); 56327#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56328#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56321#L502-3 assume !(0 == ~M_E~0); 56322#L502-5 assume !(0 == ~T1_E~0); 56317#L507-3 assume !(0 == ~T2_E~0); 56318#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55705#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55472#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55473#L527-3 assume !(0 == ~E_2~0); 55564#L532-3 assume !(0 == ~E_3~0); 56989#L537-3 assume !(0 == ~E_4~0); 55502#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55503#L238-15 assume !(1 == ~m_pc~0); 56968#L238-17 is_master_triggered_~__retres1~0#1 := 0; 56969#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56962#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 56963#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56956#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56957#L257-15 assume !(1 == ~t1_pc~0); 56604#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 56954#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57128#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 57127#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57126#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55687#L276-15 assume !(1 == ~t2_pc~0); 55470#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 55690#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57123#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 57122#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 57121#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57120#L295-15 assume !(1 == ~t3_pc~0); 56345#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 57119#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57118#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57117#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57116#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57115#L314-15 assume 1 == ~t4_pc~0; 57113#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 57112#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57111#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57110#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57109#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57108#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 57107#L555-5 assume !(1 == ~T1_E~0); 57106#L560-3 assume !(1 == ~T2_E~0); 57105#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57104#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57103#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57102#L580-3 assume !(1 == ~E_2~0); 57101#L585-3 assume !(1 == ~E_3~0); 57100#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57099#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 57096#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 57092#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 57090#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 57049#L795 assume !(0 == start_simulation_~tmp~3#1); 57044#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 57041#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 56988#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 56986#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 56985#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56984#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56983#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 56976#L808 assume !(0 != start_simulation_~tmp___0~1#1); 55377#L776-2 [2022-11-16 12:16:19,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:19,012 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2022-11-16 12:16:19,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:19,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124666335] [2022-11-16 12:16:19,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:19,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:19,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:19,053 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:19,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:19,088 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:19,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:19,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1567438159, now seen corresponding path program 1 times [2022-11-16 12:16:19,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:19,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597772279] [2022-11-16 12:16:19,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:19,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:19,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:19,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:19,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:19,205 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597772279] [2022-11-16 12:16:19,205 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597772279] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:19,206 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:19,206 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:19,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507902817] [2022-11-16 12:16:19,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:19,207 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:19,207 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:19,207 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:16:19,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:16:19,208 INFO L87 Difference]: Start difference. First operand 2126 states and 2904 transitions. cyclomatic complexity: 780 Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:19,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:19,416 INFO L93 Difference]: Finished difference Result 4194 states and 5677 transitions. [2022-11-16 12:16:19,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4194 states and 5677 transitions. [2022-11-16 12:16:19,445 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4128 [2022-11-16 12:16:19,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4194 states to 4194 states and 5677 transitions. [2022-11-16 12:16:19,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4194 [2022-11-16 12:16:19,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4194 [2022-11-16 12:16:19,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4194 states and 5677 transitions. [2022-11-16 12:16:19,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:19,475 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4194 states and 5677 transitions. [2022-11-16 12:16:19,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4194 states and 5677 transitions. [2022-11-16 12:16:19,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4194 to 2186. [2022-11-16 12:16:19,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2186 states, 2186 states have (on average 1.348124428179323) internal successors, (2947), 2185 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:19,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2186 states to 2186 states and 2947 transitions. [2022-11-16 12:16:19,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2186 states and 2947 transitions. [2022-11-16 12:16:19,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 12:16:19,540 INFO L428 stractBuchiCegarLoop]: Abstraction has 2186 states and 2947 transitions. [2022-11-16 12:16:19,540 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 12:16:19,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2186 states and 2947 transitions. [2022-11-16 12:16:19,551 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2120 [2022-11-16 12:16:19,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:19,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:19,553 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:19,554 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:19,554 INFO L748 eck$LassoCheckResult]: Stem: 62053#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 61978#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 61593#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61594#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61710#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 61825#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61675#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61676#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61688#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61689#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61731#L502 assume !(0 == ~M_E~0); 61732#L502-2 assume !(0 == ~T1_E~0); 61664#L507-1 assume !(0 == ~T2_E~0); 61665#L512-1 assume !(0 == ~T3_E~0); 61828#L517-1 assume !(0 == ~T4_E~0); 61638#L522-1 assume !(0 == ~E_1~0); 61639#L527-1 assume !(0 == ~E_2~0); 61853#L532-1 assume !(0 == ~E_3~0); 61969#L537-1 assume !(0 == ~E_4~0); 61995#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61956#L238 assume !(1 == ~m_pc~0); 61957#L238-2 is_master_triggered_~__retres1~0#1 := 0; 61604#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61605#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 61932#L615 assume !(0 != activate_threads_~tmp~1#1); 61625#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61626#L257 assume !(1 == ~t1_pc~0); 61739#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61740#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61776#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 61598#L623 assume !(0 != activate_threads_~tmp___0~0#1); 61599#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61595#L276 assume !(1 == ~t2_pc~0); 61596#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61863#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61690#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 61691#L631 assume !(0 != activate_threads_~tmp___1~0#1); 62013#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61929#L295 assume !(1 == ~t3_pc~0); 61706#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 61707#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61910#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61970#L639 assume !(0 != activate_threads_~tmp___2~0#1); 61958#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61959#L314 assume !(1 == ~t4_pc~0); 61744#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61743#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61962#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61902#L647 assume !(0 != activate_threads_~tmp___3~0#1); 61844#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61845#L555 assume !(1 == ~M_E~0); 61758#L555-2 assume !(1 == ~T1_E~0); 61759#L560-1 assume !(1 == ~T2_E~0); 61640#L565-1 assume !(1 == ~T3_E~0); 61641#L570-1 assume !(1 == ~T4_E~0); 61717#L575-1 assume !(1 == ~E_1~0); 61718#L580-1 assume !(1 == ~E_2~0); 61903#L585-1 assume !(1 == ~E_3~0); 61719#L590-1 assume !(1 == ~E_4~0); 61708#L595-1 assume { :end_inline_reset_delta_events } true; 61709#L776-2 [2022-11-16 12:16:19,554 INFO L750 eck$LassoCheckResult]: Loop: 61709#L776-2 assume !false; 62389#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 62386#L477 assume !false; 62385#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 62381#L374 assume !(0 == ~m_st~0); 62382#L378 assume !(0 == ~t1_st~0); 62384#L382 assume !(0 == ~t2_st~0); 62379#L386 assume !(0 == ~t3_st~0); 62380#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 62383#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 62359#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 62360#L416 assume !(0 != eval_~tmp~0#1); 62916#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 62913#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62910#L502-3 assume !(0 == ~M_E~0); 62907#L502-5 assume !(0 == ~T1_E~0); 62904#L507-3 assume !(0 == ~T2_E~0); 62901#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62898#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62895#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62892#L527-3 assume !(0 == ~E_2~0); 62887#L532-3 assume !(0 == ~E_3~0); 62683#L537-3 assume !(0 == ~E_4~0); 62684#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62597#L238-15 assume !(1 == ~m_pc~0); 62598#L238-17 is_master_triggered_~__retres1~0#1 := 0; 62589#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62590#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 62507#L615-15 assume !(0 != activate_threads_~tmp~1#1); 62508#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62484#L257-15 assume !(1 == ~t1_pc~0); 62483#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 62482#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62481#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 62480#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62478#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62476#L276-15 assume !(1 == ~t2_pc~0); 62473#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 62471#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62469#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 62467#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 62464#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62462#L295-15 assume !(1 == ~t3_pc~0); 62331#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 62459#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62457#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 62455#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62453#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62452#L314-15 assume 1 == ~t4_pc~0; 62449#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62447#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62445#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 62443#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62441#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62438#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62436#L555-5 assume !(1 == ~T1_E~0); 62434#L560-3 assume !(1 == ~T2_E~0); 62432#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62430#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62428#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62426#L580-3 assume !(1 == ~E_2~0); 62424#L585-3 assume !(1 == ~E_3~0); 62422#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62420#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 62416#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 62412#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 62410#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 62407#L795 assume !(0 == start_simulation_~tmp~3#1); 62405#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 62402#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 62399#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 62398#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 62397#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 62396#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62394#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 62392#L808 assume !(0 != start_simulation_~tmp___0~1#1); 61709#L776-2 [2022-11-16 12:16:19,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:19,555 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 4 times [2022-11-16 12:16:19,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:19,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143588585] [2022-11-16 12:16:19,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:19,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:19,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:19,566 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:19,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:19,583 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:19,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:19,584 INFO L85 PathProgramCache]: Analyzing trace with hash -788367091, now seen corresponding path program 1 times [2022-11-16 12:16:19,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:19,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313558771] [2022-11-16 12:16:19,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:19,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:19,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:19,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:19,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:19,624 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313558771] [2022-11-16 12:16:19,624 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313558771] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:19,625 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:19,625 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:19,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911225606] [2022-11-16 12:16:19,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:19,626 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:19,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:19,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:19,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:19,627 INFO L87 Difference]: Start difference. First operand 2186 states and 2947 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:19,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:19,684 INFO L93 Difference]: Finished difference Result 3576 states and 4749 transitions. [2022-11-16 12:16:19,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3576 states and 4749 transitions. [2022-11-16 12:16:19,703 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3508 [2022-11-16 12:16:19,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3576 states to 3576 states and 4749 transitions. [2022-11-16 12:16:19,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3576 [2022-11-16 12:16:19,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3576 [2022-11-16 12:16:19,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3576 states and 4749 transitions. [2022-11-16 12:16:19,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:19,724 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3576 states and 4749 transitions. [2022-11-16 12:16:19,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3576 states and 4749 transitions. [2022-11-16 12:16:19,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3576 to 3452. [2022-11-16 12:16:19,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3452 states, 3452 states have (on average 1.3311123986095017) internal successors, (4595), 3451 states have internal predecessors, (4595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:19,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3452 states to 3452 states and 4595 transitions. [2022-11-16 12:16:19,783 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3452 states and 4595 transitions. [2022-11-16 12:16:19,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:19,784 INFO L428 stractBuchiCegarLoop]: Abstraction has 3452 states and 4595 transitions. [2022-11-16 12:16:19,784 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 12:16:19,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3452 states and 4595 transitions. [2022-11-16 12:16:19,820 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3384 [2022-11-16 12:16:19,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:19,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:19,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:19,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:19,822 INFO L748 eck$LassoCheckResult]: Stem: 67798#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 67729#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 67361#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67362#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67483#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 67595#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67444#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67445#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67457#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67458#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67500#L502 assume !(0 == ~M_E~0); 67501#L502-2 assume !(0 == ~T1_E~0); 67436#L507-1 assume !(0 == ~T2_E~0); 67437#L512-1 assume !(0 == ~T3_E~0); 67597#L517-1 assume !(0 == ~T4_E~0); 67416#L522-1 assume !(0 == ~E_1~0); 67417#L527-1 assume !(0 == ~E_2~0); 67616#L532-1 assume !(0 == ~E_3~0); 67720#L537-1 assume !(0 == ~E_4~0); 67744#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67709#L238 assume !(1 == ~m_pc~0); 67710#L238-2 is_master_triggered_~__retres1~0#1 := 0; 67374#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67375#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 67689#L615 assume !(0 != activate_threads_~tmp~1#1); 67397#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67398#L257 assume !(1 == ~t1_pc~0); 67508#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67509#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67543#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67368#L623 assume !(0 != activate_threads_~tmp___0~0#1); 67369#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67363#L276 assume !(1 == ~t2_pc~0); 67364#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67631#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67459#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67460#L631 assume !(0 != activate_threads_~tmp___1~0#1); 67761#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67688#L295 assume !(1 == ~t3_pc~0); 67475#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67476#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67673#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 67721#L639 assume !(0 != activate_threads_~tmp___2~0#1); 67714#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67715#L314 assume !(1 == ~t4_pc~0); 67513#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67512#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67716#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67663#L647 assume !(0 != activate_threads_~tmp___3~0#1); 67609#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67610#L555 assume !(1 == ~M_E~0); 67525#L555-2 assume !(1 == ~T1_E~0); 67526#L560-1 assume !(1 == ~T2_E~0); 67418#L565-1 assume !(1 == ~T3_E~0); 67419#L570-1 assume !(1 == ~T4_E~0); 67486#L575-1 assume !(1 == ~E_1~0); 67487#L580-1 assume !(1 == ~E_2~0); 67664#L585-1 assume !(1 == ~E_3~0); 67488#L590-1 assume !(1 == ~E_4~0); 67477#L595-1 assume { :end_inline_reset_delta_events } true; 67478#L776-2 assume !false; 69818#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69810#L477 [2022-11-16 12:16:19,822 INFO L750 eck$LassoCheckResult]: Loop: 69810#L477 assume !false; 69808#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69805#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69802#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69800#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69798#L416 assume 0 != eval_~tmp~0#1; 69796#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 69792#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 69793#L421 assume !(0 == ~t1_st~0); 69836#L435 assume !(0 == ~t2_st~0); 69826#L449 assume !(0 == ~t3_st~0); 69817#L463 assume !(0 == ~t4_st~0); 69810#L477 [2022-11-16 12:16:19,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:19,823 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 1 times [2022-11-16 12:16:19,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:19,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1502721827] [2022-11-16 12:16:19,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:19,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:19,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:19,833 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:19,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:19,849 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:19,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:19,850 INFO L85 PathProgramCache]: Analyzing trace with hash 839567500, now seen corresponding path program 1 times [2022-11-16 12:16:19,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:19,850 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1976548039] [2022-11-16 12:16:19,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:19,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:19,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:19,854 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:19,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:19,858 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:19,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:19,859 INFO L85 PathProgramCache]: Analyzing trace with hash -1729123880, now seen corresponding path program 1 times [2022-11-16 12:16:19,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:19,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038657349] [2022-11-16 12:16:19,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:19,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:19,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:19,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:19,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:19,899 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1038657349] [2022-11-16 12:16:19,899 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1038657349] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:19,899 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:19,899 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:19,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821953061] [2022-11-16 12:16:19,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:20,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:20,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:20,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:20,021 INFO L87 Difference]: Start difference. First operand 3452 states and 4595 transitions. cyclomatic complexity: 1146 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:20,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:20,106 INFO L93 Difference]: Finished difference Result 6396 states and 8409 transitions. [2022-11-16 12:16:20,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6396 states and 8409 transitions. [2022-11-16 12:16:20,139 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6266 [2022-11-16 12:16:20,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6396 states to 6396 states and 8409 transitions. [2022-11-16 12:16:20,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6396 [2022-11-16 12:16:20,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6396 [2022-11-16 12:16:20,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6396 states and 8409 transitions. [2022-11-16 12:16:20,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:20,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6396 states and 8409 transitions. [2022-11-16 12:16:20,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6396 states and 8409 transitions. [2022-11-16 12:16:20,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6396 to 6176. [2022-11-16 12:16:20,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6176 states, 6176 states have (on average 1.3175194300518134) internal successors, (8137), 6175 states have internal predecessors, (8137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:20,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6176 states to 6176 states and 8137 transitions. [2022-11-16 12:16:20,286 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6176 states and 8137 transitions. [2022-11-16 12:16:20,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:20,287 INFO L428 stractBuchiCegarLoop]: Abstraction has 6176 states and 8137 transitions. [2022-11-16 12:16:20,287 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 12:16:20,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6176 states and 8137 transitions. [2022-11-16 12:16:20,308 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2022-11-16 12:16:20,309 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:20,309 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:20,310 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:20,310 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:20,310 INFO L748 eck$LassoCheckResult]: Stem: 77649#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 77585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 77217#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77218#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77335#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 77449#L341-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 77301#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77302#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77314#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77315#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77357#L502 assume !(0 == ~M_E~0); 77358#L502-2 assume !(0 == ~T1_E~0); 77290#L507-1 assume !(0 == ~T2_E~0); 77291#L512-1 assume !(0 == ~T3_E~0); 77452#L517-1 assume !(0 == ~T4_E~0); 77263#L522-1 assume !(0 == ~E_1~0); 77264#L527-1 assume !(0 == ~E_2~0); 77472#L532-1 assume !(0 == ~E_3~0); 77576#L537-1 assume !(0 == ~E_4~0); 77602#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77565#L238 assume !(1 == ~m_pc~0); 77566#L238-2 is_master_triggered_~__retres1~0#1 := 0; 77229#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77230#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 77544#L615 assume !(0 != activate_threads_~tmp~1#1); 77250#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77251#L257 assume !(1 == ~t1_pc~0); 77365#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 77366#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77402#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 77222#L623 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77223#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81305#L276 assume !(1 == ~t2_pc~0); 81303#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81302#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81301#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81300#L631 assume !(0 != activate_threads_~tmp___1~0#1); 81299#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81298#L295 assume !(1 == ~t3_pc~0); 81297#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81296#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81295#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81294#L639 assume !(0 != activate_threads_~tmp___2~0#1); 81293#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81292#L314 assume !(1 == ~t4_pc~0); 81291#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81289#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81288#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81287#L647 assume !(0 != activate_threads_~tmp___3~0#1); 81286#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81285#L555 assume !(1 == ~M_E~0); 81284#L555-2 assume !(1 == ~T1_E~0); 81280#L560-1 assume !(1 == ~T2_E~0); 81278#L565-1 assume !(1 == ~T3_E~0); 77529#L570-1 assume !(1 == ~T4_E~0); 77342#L575-1 assume !(1 == ~E_1~0); 77343#L580-1 assume !(1 == ~E_2~0); 81262#L585-1 assume !(1 == ~E_3~0); 81260#L590-1 assume !(1 == ~E_4~0); 77333#L595-1 assume { :end_inline_reset_delta_events } true; 77334#L776-2 assume !false; 81660#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81555#L477 [2022-11-16 12:16:20,311 INFO L750 eck$LassoCheckResult]: Loop: 81555#L477 assume !false; 81551#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 81548#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 81545#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 81543#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 81541#L416 assume 0 != eval_~tmp~0#1; 81539#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 81537#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 78605#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 78426#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 78427#L435 assume !(0 == ~t2_st~0); 81675#L449 assume !(0 == ~t3_st~0); 81659#L463 assume !(0 == ~t4_st~0); 81555#L477 [2022-11-16 12:16:20,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:20,311 INFO L85 PathProgramCache]: Analyzing trace with hash 995820945, now seen corresponding path program 1 times [2022-11-16 12:16:20,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:20,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579931258] [2022-11-16 12:16:20,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:20,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:20,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:20,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:20,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:20,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579931258] [2022-11-16 12:16:20,338 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579931258] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:20,338 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:20,338 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:20,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854151628] [2022-11-16 12:16:20,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:20,339 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:20,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:20,339 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 1 times [2022-11-16 12:16:20,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:20,340 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096492988] [2022-11-16 12:16:20,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:20,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:20,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:20,344 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:20,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:20,347 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:20,496 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:20,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:20,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:20,497 INFO L87 Difference]: Start difference. First operand 6176 states and 8137 transitions. cyclomatic complexity: 1964 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:20,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:20,526 INFO L93 Difference]: Finished difference Result 6118 states and 8062 transitions. [2022-11-16 12:16:20,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6118 states and 8062 transitions. [2022-11-16 12:16:20,551 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2022-11-16 12:16:20,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6118 states to 6118 states and 8062 transitions. [2022-11-16 12:16:20,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6118 [2022-11-16 12:16:20,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6118 [2022-11-16 12:16:20,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6118 states and 8062 transitions. [2022-11-16 12:16:20,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:20,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6118 states and 8062 transitions. [2022-11-16 12:16:20,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6118 states and 8062 transitions. [2022-11-16 12:16:20,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6118 to 6118. [2022-11-16 12:16:20,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6118 states, 6118 states have (on average 1.317750898986597) internal successors, (8062), 6117 states have internal predecessors, (8062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:20,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6118 states to 6118 states and 8062 transitions. [2022-11-16 12:16:20,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6118 states and 8062 transitions. [2022-11-16 12:16:20,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:20,746 INFO L428 stractBuchiCegarLoop]: Abstraction has 6118 states and 8062 transitions. [2022-11-16 12:16:20,746 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 12:16:20,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6118 states and 8062 transitions. [2022-11-16 12:16:20,767 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2022-11-16 12:16:20,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:20,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:20,769 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:20,769 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:20,769 INFO L748 eck$LassoCheckResult]: Stem: 89975#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 89896#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 89517#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89518#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89633#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 89748#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89599#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89600#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89612#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89613#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89654#L502 assume !(0 == ~M_E~0); 89655#L502-2 assume !(0 == ~T1_E~0); 89588#L507-1 assume !(0 == ~T2_E~0); 89589#L512-1 assume !(0 == ~T3_E~0); 89751#L517-1 assume !(0 == ~T4_E~0); 89562#L522-1 assume !(0 == ~E_1~0); 89563#L527-1 assume !(0 == ~E_2~0); 89777#L532-1 assume !(0 == ~E_3~0); 89888#L537-1 assume !(0 == ~E_4~0); 89914#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89877#L238 assume !(1 == ~m_pc~0); 89878#L238-2 is_master_triggered_~__retres1~0#1 := 0; 89528#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89529#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 89852#L615 assume !(0 != activate_threads_~tmp~1#1); 89549#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89550#L257 assume !(1 == ~t1_pc~0); 89662#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 89663#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89699#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 89522#L623 assume !(0 != activate_threads_~tmp___0~0#1); 89523#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89519#L276 assume !(1 == ~t2_pc~0); 89520#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 89787#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89614#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 89615#L631 assume !(0 != activate_threads_~tmp___1~0#1); 89932#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89848#L295 assume !(1 == ~t3_pc~0); 89629#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89630#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89831#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 89889#L639 assume !(0 != activate_threads_~tmp___2~0#1); 89879#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89880#L314 assume !(1 == ~t4_pc~0); 89668#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89667#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89883#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 89824#L647 assume !(0 != activate_threads_~tmp___3~0#1); 89767#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89768#L555 assume !(1 == ~M_E~0); 89681#L555-2 assume !(1 == ~T1_E~0); 89682#L560-1 assume !(1 == ~T2_E~0); 89564#L565-1 assume !(1 == ~T3_E~0); 89565#L570-1 assume !(1 == ~T4_E~0); 89640#L575-1 assume !(1 == ~E_1~0); 89641#L580-1 assume !(1 == ~E_2~0); 89825#L585-1 assume !(1 == ~E_3~0); 89642#L590-1 assume !(1 == ~E_4~0); 89631#L595-1 assume { :end_inline_reset_delta_events } true; 89632#L776-2 assume !false; 91027#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 91028#L477 [2022-11-16 12:16:20,770 INFO L750 eck$LassoCheckResult]: Loop: 91028#L477 assume !false; 91500#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 91498#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 91497#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 91011#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 91010#L416 assume 0 != eval_~tmp~0#1; 91006#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 91007#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 90998#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 90996#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 90997#L435 assume !(0 == ~t2_st~0); 91033#L449 assume !(0 == ~t3_st~0); 91034#L463 assume !(0 == ~t4_st~0); 91028#L477 [2022-11-16 12:16:20,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:20,770 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 2 times [2022-11-16 12:16:20,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:20,771 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876630629] [2022-11-16 12:16:20,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:20,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:20,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:20,782 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:20,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:20,799 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:20,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:20,800 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 2 times [2022-11-16 12:16:20,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:20,800 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530560792] [2022-11-16 12:16:20,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:20,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:20,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:20,805 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:20,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:20,809 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:20,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:20,810 INFO L85 PathProgramCache]: Analyzing trace with hash 2084563792, now seen corresponding path program 1 times [2022-11-16 12:16:20,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:20,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896561544] [2022-11-16 12:16:20,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:20,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:20,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:20,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:20,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:20,850 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896561544] [2022-11-16 12:16:20,850 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896561544] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:20,851 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:20,851 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:20,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429091522] [2022-11-16 12:16:20,851 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:20,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:20,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:20,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:20,985 INFO L87 Difference]: Start difference. First operand 6118 states and 8062 transitions. cyclomatic complexity: 1947 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:21,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:21,051 INFO L93 Difference]: Finished difference Result 9420 states and 12360 transitions. [2022-11-16 12:16:21,051 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9420 states and 12360 transitions. [2022-11-16 12:16:21,092 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9340 [2022-11-16 12:16:21,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9420 states to 9420 states and 12360 transitions. [2022-11-16 12:16:21,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9420 [2022-11-16 12:16:21,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9420 [2022-11-16 12:16:21,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9420 states and 12360 transitions. [2022-11-16 12:16:21,145 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:21,145 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9420 states and 12360 transitions. [2022-11-16 12:16:21,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9420 states and 12360 transitions. [2022-11-16 12:16:21,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9420 to 9420. [2022-11-16 12:16:21,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9420 states, 9420 states have (on average 1.3121019108280254) internal successors, (12360), 9419 states have internal predecessors, (12360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:21,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9420 states to 9420 states and 12360 transitions. [2022-11-16 12:16:21,432 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9420 states and 12360 transitions. [2022-11-16 12:16:21,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:21,433 INFO L428 stractBuchiCegarLoop]: Abstraction has 9420 states and 12360 transitions. [2022-11-16 12:16:21,433 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-16 12:16:21,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9420 states and 12360 transitions. [2022-11-16 12:16:21,465 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9340 [2022-11-16 12:16:21,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:21,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:21,467 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:21,467 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:21,467 INFO L748 eck$LassoCheckResult]: Stem: 105531#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 105447#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 105063#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105064#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105183#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 105299#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 105145#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105146#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105158#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105159#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105200#L502 assume !(0 == ~M_E~0); 105201#L502-2 assume !(0 == ~T1_E~0); 105137#L507-1 assume !(0 == ~T2_E~0); 105138#L512-1 assume !(0 == ~T3_E~0); 105301#L517-1 assume !(0 == ~T4_E~0); 105117#L522-1 assume !(0 == ~E_1~0); 105118#L527-1 assume !(0 == ~E_2~0); 105324#L532-1 assume !(0 == ~E_3~0); 105436#L537-1 assume !(0 == ~E_4~0); 105462#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105425#L238 assume !(1 == ~m_pc~0); 105426#L238-2 is_master_triggered_~__retres1~0#1 := 0; 105076#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105077#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 105402#L615 assume !(0 != activate_threads_~tmp~1#1); 105099#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105100#L257 assume !(1 == ~t1_pc~0); 105208#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105209#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105245#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 105070#L623 assume !(0 != activate_threads_~tmp___0~0#1); 105071#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105065#L276 assume !(1 == ~t2_pc~0); 105066#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 105337#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105160#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 105161#L631 assume !(0 != activate_threads_~tmp___1~0#1); 105477#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105399#L295 assume !(1 == ~t3_pc~0); 105175#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105176#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105379#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105437#L639 assume !(0 != activate_threads_~tmp___2~0#1); 105430#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105431#L314 assume !(1 == ~t4_pc~0); 105213#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105212#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105432#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105371#L647 assume !(0 != activate_threads_~tmp___3~0#1); 105315#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105316#L555 assume !(1 == ~M_E~0); 105225#L555-2 assume !(1 == ~T1_E~0); 105226#L560-1 assume !(1 == ~T2_E~0); 105119#L565-1 assume !(1 == ~T3_E~0); 105120#L570-1 assume !(1 == ~T4_E~0); 105186#L575-1 assume !(1 == ~E_1~0); 105187#L580-1 assume !(1 == ~E_2~0); 105372#L585-1 assume !(1 == ~E_3~0); 105188#L590-1 assume !(1 == ~E_4~0); 105177#L595-1 assume { :end_inline_reset_delta_events } true; 105178#L776-2 assume !false; 107876#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 107877#L477 [2022-11-16 12:16:21,468 INFO L750 eck$LassoCheckResult]: Loop: 107877#L477 assume !false; 107759#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 107760#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 107739#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 107740#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 107717#L416 assume 0 != eval_~tmp~0#1; 107718#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 107694#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 107619#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 107614#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 107615#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 107900#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 107897#L449 assume !(0 == ~t3_st~0); 107896#L463 assume !(0 == ~t4_st~0); 107877#L477 [2022-11-16 12:16:21,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:21,468 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 3 times [2022-11-16 12:16:21,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:21,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882099270] [2022-11-16 12:16:21,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:21,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:21,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:21,479 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:21,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:21,494 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:21,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:21,495 INFO L85 PathProgramCache]: Analyzing trace with hash -901553796, now seen corresponding path program 1 times [2022-11-16 12:16:21,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:21,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008241435] [2022-11-16 12:16:21,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:21,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:21,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:21,500 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:21,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:21,504 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:21,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:21,505 INFO L85 PathProgramCache]: Analyzing trace with hash 192225224, now seen corresponding path program 1 times [2022-11-16 12:16:21,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:21,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058840374] [2022-11-16 12:16:21,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:21,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:21,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:21,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:21,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:21,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058840374] [2022-11-16 12:16:21,545 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058840374] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:21,545 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:21,545 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:21,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158757018] [2022-11-16 12:16:21,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:21,785 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:21,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:21,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:21,786 INFO L87 Difference]: Start difference. First operand 9420 states and 12360 transitions. cyclomatic complexity: 2943 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:21,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:21,925 INFO L93 Difference]: Finished difference Result 17038 states and 22278 transitions. [2022-11-16 12:16:21,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17038 states and 22278 transitions. [2022-11-16 12:16:22,023 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16942 [2022-11-16 12:16:22,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17038 states to 17038 states and 22278 transitions. [2022-11-16 12:16:22,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17038 [2022-11-16 12:16:22,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17038 [2022-11-16 12:16:22,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17038 states and 22278 transitions. [2022-11-16 12:16:22,127 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:22,127 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17038 states and 22278 transitions. [2022-11-16 12:16:22,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17038 states and 22278 transitions. [2022-11-16 12:16:22,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17038 to 16686. [2022-11-16 12:16:22,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16686 states, 16686 states have (on average 1.3082823924247873) internal successors, (21830), 16685 states have internal predecessors, (21830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:22,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16686 states to 16686 states and 21830 transitions. [2022-11-16 12:16:22,452 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16686 states and 21830 transitions. [2022-11-16 12:16:22,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:22,454 INFO L428 stractBuchiCegarLoop]: Abstraction has 16686 states and 21830 transitions. [2022-11-16 12:16:22,454 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-16 12:16:22,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16686 states and 21830 transitions. [2022-11-16 12:16:22,596 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16590 [2022-11-16 12:16:22,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:22,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:22,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:22,599 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:22,599 INFO L748 eck$LassoCheckResult]: Stem: 132015#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 131913#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 131529#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131530#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131645#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 131761#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131611#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131612#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131624#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131625#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131666#L502 assume !(0 == ~M_E~0); 131667#L502-2 assume !(0 == ~T1_E~0); 131600#L507-1 assume !(0 == ~T2_E~0); 131601#L512-1 assume !(0 == ~T3_E~0); 131764#L517-1 assume !(0 == ~T4_E~0); 131574#L522-1 assume !(0 == ~E_1~0); 131575#L527-1 assume !(0 == ~E_2~0); 131787#L532-1 assume !(0 == ~E_3~0); 131902#L537-1 assume !(0 == ~E_4~0); 131931#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131891#L238 assume !(1 == ~m_pc~0); 131892#L238-2 is_master_triggered_~__retres1~0#1 := 0; 131540#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131541#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 131865#L615 assume !(0 != activate_threads_~tmp~1#1); 131561#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131562#L257 assume !(1 == ~t1_pc~0); 131674#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131675#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131710#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 131534#L623 assume !(0 != activate_threads_~tmp___0~0#1); 131535#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131531#L276 assume !(1 == ~t2_pc~0); 131532#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131796#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131626#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131627#L631 assume !(0 != activate_threads_~tmp___1~0#1); 131951#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131861#L295 assume !(1 == ~t3_pc~0); 131641#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 131642#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131842#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 131903#L639 assume !(0 != activate_threads_~tmp___2~0#1); 131893#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131894#L314 assume !(1 == ~t4_pc~0); 131679#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131678#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131896#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 131835#L647 assume !(0 != activate_threads_~tmp___3~0#1); 131779#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131780#L555 assume !(1 == ~M_E~0); 131691#L555-2 assume !(1 == ~T1_E~0); 131692#L560-1 assume !(1 == ~T2_E~0); 131576#L565-1 assume !(1 == ~T3_E~0); 131577#L570-1 assume !(1 == ~T4_E~0); 131652#L575-1 assume !(1 == ~E_1~0); 131653#L580-1 assume !(1 == ~E_2~0); 131836#L585-1 assume !(1 == ~E_3~0); 131654#L590-1 assume !(1 == ~E_4~0); 131643#L595-1 assume { :end_inline_reset_delta_events } true; 131644#L776-2 assume !false; 140397#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140392#L477 [2022-11-16 12:16:22,600 INFO L750 eck$LassoCheckResult]: Loop: 140392#L477 assume !false; 140388#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 140384#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 140381#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 140378#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 140375#L416 assume 0 != eval_~tmp~0#1; 140371#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 140367#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 139120#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 139113#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 139114#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 140996#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 140917#L449 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 140915#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 140396#L463 assume !(0 == ~t4_st~0); 140392#L477 [2022-11-16 12:16:22,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:22,601 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 4 times [2022-11-16 12:16:22,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:22,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913669878] [2022-11-16 12:16:22,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:22,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:22,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:22,612 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:22,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:22,634 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:22,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:22,635 INFO L85 PathProgramCache]: Analyzing trace with hash 2116454956, now seen corresponding path program 1 times [2022-11-16 12:16:22,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:22,636 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192525397] [2022-11-16 12:16:22,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:22,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:22,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:22,641 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:22,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:22,646 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:22,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:22,647 INFO L85 PathProgramCache]: Analyzing trace with hash 1663866208, now seen corresponding path program 1 times [2022-11-16 12:16:22,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:22,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528911512] [2022-11-16 12:16:22,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:22,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:22,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:22,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:22,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:22,693 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [528911512] [2022-11-16 12:16:22,693 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [528911512] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:22,693 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:22,693 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:22,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841869135] [2022-11-16 12:16:22,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:22,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:22,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:22,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:22,888 INFO L87 Difference]: Start difference. First operand 16686 states and 21830 transitions. cyclomatic complexity: 5147 Second operand has 3 states, 2 states have (on average 38.5) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:23,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:23,133 INFO L93 Difference]: Finished difference Result 31602 states and 41178 transitions. [2022-11-16 12:16:23,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31602 states and 41178 transitions. [2022-11-16 12:16:23,273 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31474 [2022-11-16 12:16:23,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31602 states to 31602 states and 41178 transitions. [2022-11-16 12:16:23,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31602 [2022-11-16 12:16:23,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31602 [2022-11-16 12:16:23,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31602 states and 41178 transitions. [2022-11-16 12:16:23,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:23,417 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31602 states and 41178 transitions. [2022-11-16 12:16:23,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31602 states and 41178 transitions. [2022-11-16 12:16:23,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31602 to 31602. [2022-11-16 12:16:23,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31602 states, 31602 states have (on average 1.3030187962787165) internal successors, (41178), 31601 states have internal predecessors, (41178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:24,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31602 states to 31602 states and 41178 transitions. [2022-11-16 12:16:24,065 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31602 states and 41178 transitions. [2022-11-16 12:16:24,065 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:24,066 INFO L428 stractBuchiCegarLoop]: Abstraction has 31602 states and 41178 transitions. [2022-11-16 12:16:24,066 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-16 12:16:24,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31602 states and 41178 transitions. [2022-11-16 12:16:24,204 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31474 [2022-11-16 12:16:24,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:24,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:24,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:24,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:24,207 INFO L748 eck$LassoCheckResult]: Stem: 180323#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~t1_st~0 := 0;~E_2~0 := 2;~t3_st~0 := 0;~t4_st~0 := 0;~E_4~0 := 2;~t3_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0; 180219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 179825#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 179826#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 179940#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 180059#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 179906#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 179907#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 179919#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 179920#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 179961#L502 assume !(0 == ~M_E~0); 179962#L502-2 assume !(0 == ~T1_E~0); 179895#L507-1 assume !(0 == ~T2_E~0); 179896#L512-1 assume !(0 == ~T3_E~0); 180062#L517-1 assume !(0 == ~T4_E~0); 179870#L522-1 assume !(0 == ~E_1~0); 179871#L527-1 assume !(0 == ~E_2~0); 180088#L532-1 assume !(0 == ~E_3~0); 180208#L537-1 assume !(0 == ~E_4~0); 180238#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 180193#L238 assume !(1 == ~m_pc~0); 180194#L238-2 is_master_triggered_~__retres1~0#1 := 0; 179836#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 179837#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 180167#L615 assume !(0 != activate_threads_~tmp~1#1); 179857#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 179858#L257 assume !(1 == ~t1_pc~0); 179969#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 179970#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180007#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 179830#L623 assume !(0 != activate_threads_~tmp___0~0#1); 179831#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 179827#L276 assume !(1 == ~t2_pc~0); 179828#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 180099#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179921#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 179922#L631 assume !(0 != activate_threads_~tmp___1~0#1); 180256#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180161#L295 assume !(1 == ~t3_pc~0); 179936#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 179937#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180144#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 180209#L639 assume !(0 != activate_threads_~tmp___2~0#1); 180195#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180196#L314 assume !(1 == ~t4_pc~0); 179974#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 179973#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180200#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 180136#L647 assume !(0 != activate_threads_~tmp___3~0#1); 180081#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180082#L555 assume !(1 == ~M_E~0); 179988#L555-2 assume !(1 == ~T1_E~0); 179989#L560-1 assume !(1 == ~T2_E~0); 179872#L565-1 assume !(1 == ~T3_E~0); 179873#L570-1 assume !(1 == ~T4_E~0); 179948#L575-1 assume !(1 == ~E_1~0); 179949#L580-1 assume !(1 == ~E_2~0); 180137#L585-1 assume !(1 == ~E_3~0); 179947#L590-1 assume !(1 == ~E_4~0); 179938#L595-1 assume { :end_inline_reset_delta_events } true; 179939#L776-2 assume !false; 209050#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 206228#L477 [2022-11-16 12:16:24,207 INFO L750 eck$LassoCheckResult]: Loop: 206228#L477 assume !false; 209045#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 209043#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 209040#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 209038#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 209037#L416 assume 0 != eval_~tmp~0#1; 209036#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 180312#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 180314#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 206032#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 206030#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 205855#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 196594#L449 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 196592#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 196593#L463 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 206204#L480 assume !(0 != eval_~tmp_ndt_5~0#1); 206228#L477 [2022-11-16 12:16:24,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:24,208 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 5 times [2022-11-16 12:16:24,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:24,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631412257] [2022-11-16 12:16:24,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:24,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:24,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:24,219 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:24,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:24,237 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:24,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:24,237 INFO L85 PathProgramCache]: Analyzing trace with hash 1185593964, now seen corresponding path program 1 times [2022-11-16 12:16:24,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:24,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514440252] [2022-11-16 12:16:24,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:24,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:24,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:24,248 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:24,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:24,254 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:24,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:24,258 INFO L85 PathProgramCache]: Analyzing trace with hash 40244664, now seen corresponding path program 1 times [2022-11-16 12:16:24,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:24,259 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125272039] [2022-11-16 12:16:24,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:24,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:24,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:24,274 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:24,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:24,297 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:16:26,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:26,209 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:16:26,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:16:26,421 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.11 12:16:26 BoogieIcfgContainer [2022-11-16 12:16:26,423 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-16 12:16:26,424 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-16 12:16:26,424 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-16 12:16:26,425 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-16 12:16:26,425 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:16:13" (3/4) ... [2022-11-16 12:16:26,431 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-16 12:16:26,539 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/witness.graphml [2022-11-16 12:16:26,540 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-16 12:16:26,541 INFO L158 Benchmark]: Toolchain (without parser) took 15542.47ms. Allocated memory was 132.1MB in the beginning and 1.0GB in the end (delta: 908.1MB). Free memory was 96.8MB in the beginning and 718.6MB in the end (delta: -621.8MB). Peak memory consumption was 286.2MB. Max. memory is 16.1GB. [2022-11-16 12:16:26,541 INFO L158 Benchmark]: CDTParser took 0.33ms. Allocated memory is still 77.6MB. Free memory was 28.5MB in the beginning and 28.4MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-16 12:16:26,543 INFO L158 Benchmark]: CACSL2BoogieTranslator took 468.62ms. Allocated memory is still 132.1MB. Free memory was 96.8MB in the beginning and 101.7MB in the end (delta: -4.9MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-16 12:16:26,543 INFO L158 Benchmark]: Boogie Procedure Inliner took 71.98ms. Allocated memory is still 132.1MB. Free memory was 101.7MB in the beginning and 97.5MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-16 12:16:26,544 INFO L158 Benchmark]: Boogie Preprocessor took 70.91ms. Allocated memory is still 132.1MB. Free memory was 97.5MB in the beginning and 93.8MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-16 12:16:26,544 INFO L158 Benchmark]: RCFGBuilder took 1630.07ms. Allocated memory was 132.1MB in the beginning and 176.2MB in the end (delta: 44.0MB). Free memory was 93.8MB in the beginning and 142.6MB in the end (delta: -48.8MB). Peak memory consumption was 48.3MB. Max. memory is 16.1GB. [2022-11-16 12:16:26,544 INFO L158 Benchmark]: BuchiAutomizer took 13174.36ms. Allocated memory was 176.2MB in the beginning and 1.0GB in the end (delta: 864.0MB). Free memory was 142.6MB in the beginning and 728.0MB in the end (delta: -585.5MB). Peak memory consumption was 278.5MB. Max. memory is 16.1GB. [2022-11-16 12:16:26,545 INFO L158 Benchmark]: Witness Printer took 115.91ms. Allocated memory is still 1.0GB. Free memory was 728.0MB in the beginning and 718.6MB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-16 12:16:26,547 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.33ms. Allocated memory is still 77.6MB. Free memory was 28.5MB in the beginning and 28.4MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 468.62ms. Allocated memory is still 132.1MB. Free memory was 96.8MB in the beginning and 101.7MB in the end (delta: -4.9MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 71.98ms. Allocated memory is still 132.1MB. Free memory was 101.7MB in the beginning and 97.5MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 70.91ms. Allocated memory is still 132.1MB. Free memory was 97.5MB in the beginning and 93.8MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1630.07ms. Allocated memory was 132.1MB in the beginning and 176.2MB in the end (delta: 44.0MB). Free memory was 93.8MB in the beginning and 142.6MB in the end (delta: -48.8MB). Peak memory consumption was 48.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 13174.36ms. Allocated memory was 176.2MB in the beginning and 1.0GB in the end (delta: 864.0MB). Free memory was 142.6MB in the beginning and 728.0MB in the end (delta: -585.5MB). Peak memory consumption was 278.5MB. Max. memory is 16.1GB. * Witness Printer took 115.91ms. Allocated memory is still 1.0GB. Free memory was 728.0MB in the beginning and 718.6MB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 31602 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 12.9s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 6.0s. Construction of modules took 0.9s. Büchi inclusion checks took 5.2s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 2.3s AutomataMinimizationTime, 22 MinimizatonAttempts, 10662 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 1.1s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 16146 SdHoareTripleChecker+Valid, 1.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 16146 mSDsluCounter, 25479 SdHoareTripleChecker+Invalid, 0.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 12262 mSDsCounter, 261 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 619 IncrementalHoareTripleChecker+Invalid, 880 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 261 mSolverCounterUnsat, 13217 mSDtfsCounter, 619 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 411]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L44] int T4_E = 2; [L30] int m_st ; [L42] int T2_E = 2; [L43] int T3_E = 2; [L41] int T1_E = 2; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L27] int t2_pc = 0; [L26] int t1_pc = 0; [L36] int t1_i ; [L40] int M_E = 2; [L35] int m_i ; [L45] int E_1 = 2; [L25] int m_pc = 0; [L32] int t2_st ; [L47] int E_3 = 2; [L31] int t1_st ; [L46] int E_2 = 2; [L33] int t3_st ; [L34] int t4_st ; [L48] int E_4 = 2; [L38] int t3_i ; [L37] int t2_i ; [L39] int t4_i ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 411]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L44] int T4_E = 2; [L30] int m_st ; [L42] int T2_E = 2; [L43] int T3_E = 2; [L41] int T1_E = 2; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L27] int t2_pc = 0; [L26] int t1_pc = 0; [L36] int t1_i ; [L40] int M_E = 2; [L35] int m_i ; [L45] int E_1 = 2; [L25] int m_pc = 0; [L32] int t2_st ; [L47] int E_3 = 2; [L31] int t1_st ; [L46] int E_2 = 2; [L33] int t3_st ; [L34] int t4_st ; [L48] int E_4 = 2; [L38] int t3_i ; [L37] int t2_i ; [L39] int t4_i ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-16 12:16:26,684 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a1ff5815-dbd3-4fc7-99be-4fccdf74bd4a/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)