./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 12:16:46,461 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 12:16:46,464 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 12:16:46,516 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 12:16:46,518 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 12:16:46,523 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 12:16:46,526 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 12:16:46,532 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 12:16:46,537 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 12:16:46,539 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 12:16:46,542 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 12:16:46,545 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 12:16:46,546 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 12:16:46,550 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 12:16:46,552 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 12:16:46,554 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 12:16:46,557 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 12:16:46,564 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 12:16:46,566 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 12:16:46,568 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 12:16:46,572 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 12:16:46,574 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 12:16:46,578 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 12:16:46,579 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 12:16:46,591 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 12:16:46,593 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 12:16:46,594 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 12:16:46,595 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 12:16:46,597 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 12:16:46,598 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 12:16:46,599 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 12:16:46,600 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 12:16:46,602 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 12:16:46,604 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 12:16:46,607 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 12:16:46,607 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 12:16:46,608 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 12:16:46,608 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 12:16:46,609 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 12:16:46,610 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 12:16:46,611 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 12:16:46,612 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 12:16:46,660 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 12:16:46,661 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 12:16:46,661 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 12:16:46,662 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 12:16:46,663 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 12:16:46,664 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 12:16:46,664 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 12:16:46,664 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 12:16:46,665 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 12:16:46,665 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 12:16:46,666 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 12:16:46,666 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 12:16:46,667 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 12:16:46,667 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 12:16:46,667 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 12:16:46,668 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 12:16:46,668 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 12:16:46,668 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 12:16:46,668 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 12:16:46,669 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 12:16:46,669 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 12:16:46,669 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 12:16:46,669 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 12:16:46,670 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 12:16:46,670 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 12:16:46,670 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 12:16:46,670 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 12:16:46,671 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 12:16:46,671 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 12:16:46,671 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 12:16:46,672 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 12:16:46,673 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 12:16:46,673 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f [2022-11-16 12:16:47,055 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 12:16:47,098 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 12:16:47,102 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 12:16:47,104 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 12:16:47,105 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 12:16:47,107 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/transmitter.05.cil.c [2022-11-16 12:16:47,197 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/data/b1bca60da/b2dbd276478649cfa988422a821a841b/FLAGf82bb2577 [2022-11-16 12:16:47,778 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 12:16:47,778 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/sv-benchmarks/c/systemc/transmitter.05.cil.c [2022-11-16 12:16:47,795 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/data/b1bca60da/b2dbd276478649cfa988422a821a841b/FLAGf82bb2577 [2022-11-16 12:16:48,109 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/data/b1bca60da/b2dbd276478649cfa988422a821a841b [2022-11-16 12:16:48,112 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 12:16:48,114 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 12:16:48,116 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 12:16:48,116 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 12:16:48,120 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 12:16:48,121 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,123 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6a51d7b4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48, skipping insertion in model container [2022-11-16 12:16:48,123 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,133 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 12:16:48,202 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 12:16:48,434 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2022-11-16 12:16:48,537 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:16:48,548 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 12:16:48,563 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2022-11-16 12:16:48,608 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:16:48,628 INFO L208 MainTranslator]: Completed translation [2022-11-16 12:16:48,629 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48 WrapperNode [2022-11-16 12:16:48,629 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 12:16:48,630 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 12:16:48,631 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 12:16:48,631 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 12:16:48,642 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,653 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,722 INFO L138 Inliner]: procedures = 38, calls = 45, calls flagged for inlining = 40, calls inlined = 86, statements flattened = 1229 [2022-11-16 12:16:48,722 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 12:16:48,723 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 12:16:48,723 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 12:16:48,724 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 12:16:48,740 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,740 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,746 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,746 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,782 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,832 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,844 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,848 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,872 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 12:16:48,873 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 12:16:48,873 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 12:16:48,874 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 12:16:48,875 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (1/1) ... [2022-11-16 12:16:48,890 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 12:16:48,904 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:16:48,925 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 12:16:48,941 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 12:16:48,988 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 12:16:48,989 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 12:16:48,989 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 12:16:48,989 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 12:16:49,096 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 12:16:49,098 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 12:16:50,391 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 12:16:50,423 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 12:16:50,423 INFO L300 CfgBuilder]: Removed 9 assume(true) statements. [2022-11-16 12:16:50,427 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:16:50 BoogieIcfgContainer [2022-11-16 12:16:50,443 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 12:16:50,444 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 12:16:50,444 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 12:16:50,449 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 12:16:50,450 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:16:50,451 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 12:16:48" (1/3) ... [2022-11-16 12:16:50,452 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@35d874c0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:16:50, skipping insertion in model container [2022-11-16 12:16:50,452 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:16:50,452 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:16:48" (2/3) ... [2022-11-16 12:16:50,453 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@35d874c0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:16:50, skipping insertion in model container [2022-11-16 12:16:50,453 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:16:50,453 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:16:50" (3/3) ... [2022-11-16 12:16:50,455 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2022-11-16 12:16:50,607 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 12:16:50,607 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 12:16:50,607 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 12:16:50,607 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 12:16:50,607 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 12:16:50,607 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 12:16:50,607 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 12:16:50,608 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 12:16:50,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:50,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2022-11-16 12:16:50,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:50,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:50,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:50,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:50,693 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 12:16:50,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:50,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2022-11-16 12:16:50,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:50,720 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:50,723 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:50,724 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:50,741 INFO L748 eck$LassoCheckResult]: Stem: 489#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 409#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 388#L863true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 384#L394true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 254#L401true assume !(1 == ~m_i~0);~m_st~0 := 2; 342#L401-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 105#L406-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 400#L411-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 383#L416-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 459#L421-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 325#L426-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86#L586true assume 0 == ~M_E~0;~M_E~0 := 1; 118#L586-2true assume !(0 == ~T1_E~0); 230#L591-1true assume !(0 == ~T2_E~0); 206#L596-1true assume !(0 == ~T3_E~0); 268#L601-1true assume !(0 == ~T4_E~0); 246#L606-1true assume !(0 == ~T5_E~0); 461#L611-1true assume !(0 == ~E_1~0); 340#L616-1true assume !(0 == ~E_2~0); 348#L621-1true assume 0 == ~E_3~0;~E_3~0 := 1; 49#L626-1true assume !(0 == ~E_4~0); 300#L631-1true assume !(0 == ~E_5~0); 139#L636-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47#L279true assume 1 == ~m_pc~0; 214#L280true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 365#L290true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 188#L291true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 267#L720true assume !(0 != activate_threads_~tmp~1#1); 483#L720-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143#L298true assume !(1 == ~t1_pc~0); 25#L298-2true is_transmit1_triggered_~__retres1~1#1 := 0; 450#L309true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180#L310true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54#L728true assume !(0 != activate_threads_~tmp___0~0#1); 259#L728-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121#L317true assume 1 == ~t2_pc~0; 237#L318true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 465#L328true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 401#L329true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 149#L736true assume !(0 != activate_threads_~tmp___1~0#1); 420#L736-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 322#L336true assume 1 == ~t3_pc~0; 184#L337true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 484#L347true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 229#L348true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 276#L744true assume !(0 != activate_threads_~tmp___2~0#1); 332#L744-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 404#L355true assume !(1 == ~t4_pc~0); 330#L355-2true is_transmit4_triggered_~__retres1~4#1 := 0; 97#L366true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 257#L367true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315#L752true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61#L752-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 368#L374true assume 1 == ~t5_pc~0; 381#L375true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 385#L385true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 187#L386true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 424#L760true assume !(0 != activate_threads_~tmp___4~0#1); 232#L760-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 433#L649true assume 1 == ~M_E~0;~M_E~0 := 2; 492#L649-2true assume !(1 == ~T1_E~0); 40#L654-1true assume !(1 == ~T2_E~0); 264#L659-1true assume !(1 == ~T3_E~0); 148#L664-1true assume !(1 == ~T4_E~0); 36#L669-1true assume !(1 == ~T5_E~0); 317#L674-1true assume !(1 == ~E_1~0); 328#L679-1true assume !(1 == ~E_2~0); 89#L684-1true assume 1 == ~E_3~0;~E_3~0 := 2; 200#L689-1true assume !(1 == ~E_4~0); 479#L694-1true assume !(1 == ~E_5~0); 199#L699-1true assume { :end_inline_reset_delta_events } true; 468#L900-2true [2022-11-16 12:16:50,743 INFO L750 eck$LassoCheckResult]: Loop: 468#L900-2true assume !false; 501#L901true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59#L561true assume !true; 453#L576true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 418#L394-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 421#L586-3true assume 0 == ~M_E~0;~M_E~0 := 1; 316#L586-5true assume !(0 == ~T1_E~0); 216#L591-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 100#L596-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 227#L601-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 371#L606-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 256#L611-3true assume 0 == ~E_1~0;~E_1~0 := 1; 260#L616-3true assume 0 == ~E_2~0;~E_2~0 := 1; 43#L621-3true assume 0 == ~E_3~0;~E_3~0 := 1; 23#L626-3true assume !(0 == ~E_4~0); 502#L631-3true assume 0 == ~E_5~0;~E_5~0 := 1; 27#L636-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 430#L279-18true assume 1 == ~m_pc~0; 77#L280-6true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 221#L290-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150#L291-6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 390#L720-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 343#L720-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 231#L298-18true assume 1 == ~t1_pc~0; 13#L299-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 104#L309-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132#L310-6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116#L728-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 442#L728-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 208#L317-18true assume !(1 == ~t2_pc~0); 225#L317-20true is_transmit2_triggered_~__retres1~2#1 := 0; 239#L328-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101#L329-6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 106#L736-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 352#L736-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 347#L336-18true assume 1 == ~t3_pc~0; 319#L337-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 393#L347-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152#L348-6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 173#L744-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 73#L744-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 286#L355-18true assume 1 == ~t4_pc~0; 411#L356-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 417#L366-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122#L367-6true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 212#L752-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 125#L752-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 331#L374-18true assume !(1 == ~t5_pc~0); 291#L374-20true is_transmit5_triggered_~__retres1~5#1 := 0; 170#L385-6true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 287#L386-6true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 444#L760-18true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 270#L760-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 455#L649-3true assume 1 == ~M_E~0;~M_E~0 := 2; 183#L649-5true assume !(1 == ~T1_E~0); 167#L654-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 78#L659-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 449#L664-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 28#L669-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 473#L674-3true assume 1 == ~E_1~0;~E_1~0 := 2; 22#L679-3true assume 1 == ~E_2~0;~E_2~0 := 2; 178#L684-3true assume 1 == ~E_3~0;~E_3~0 := 2; 2#L689-3true assume !(1 == ~E_4~0); 130#L694-3true assume 1 == ~E_5~0;~E_5~0 := 2; 20#L699-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 415#L439-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 472#L471-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 346#L472-1true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 198#L919true assume !(0 == start_simulation_~tmp~3#1); 482#L919-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 298#L439-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 374#L471-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 156#L472-2true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 191#L874true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 351#L881true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 154#L882true start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 327#L932true assume !(0 != start_simulation_~tmp___0~1#1); 468#L900-2true [2022-11-16 12:16:50,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:50,763 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2022-11-16 12:16:50,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:50,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506843817] [2022-11-16 12:16:50,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:50,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:50,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:51,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:51,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:51,102 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1506843817] [2022-11-16 12:16:51,103 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1506843817] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:51,103 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:51,103 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:51,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855061163] [2022-11-16 12:16:51,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:51,116 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:51,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:51,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1013670564, now seen corresponding path program 1 times [2022-11-16 12:16:51,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:51,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394248387] [2022-11-16 12:16:51,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:51,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:51,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:51,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:51,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:51,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [394248387] [2022-11-16 12:16:51,232 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [394248387] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:51,232 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:51,232 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:51,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790487453] [2022-11-16 12:16:51,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:51,234 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:51,235 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:51,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:51,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:51,279 INFO L87 Difference]: Start difference. First operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:51,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:51,361 INFO L93 Difference]: Finished difference Result 504 states and 752 transitions. [2022-11-16 12:16:51,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 752 transitions. [2022-11-16 12:16:51,380 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:51,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 498 states and 746 transitions. [2022-11-16 12:16:51,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-11-16 12:16:51,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-11-16 12:16:51,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 746 transitions. [2022-11-16 12:16:51,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:51,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 746 transitions. [2022-11-16 12:16:51,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 746 transitions. [2022-11-16 12:16:51,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-11-16 12:16:51,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:51,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 746 transitions. [2022-11-16 12:16:51,477 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 746 transitions. [2022-11-16 12:16:51,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:51,484 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2022-11-16 12:16:51,484 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 12:16:51,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 746 transitions. [2022-11-16 12:16:51,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:51,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:51,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:51,492 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:51,492 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:51,493 INFO L748 eck$LassoCheckResult]: Stem: 1515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 1501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1493#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1491#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1405#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1406#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1211#L406-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1212#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1489#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1490#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1183#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 1184#L586-2 assume !(0 == ~T1_E~0); 1237#L591-1 assume !(0 == ~T2_E~0); 1357#L596-1 assume !(0 == ~T3_E~0); 1358#L601-1 assume !(0 == ~T4_E~0); 1396#L606-1 assume !(0 == ~T5_E~0); 1397#L611-1 assume !(0 == ~E_1~0); 1468#L616-1 assume !(0 == ~E_2~0); 1469#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1116#L626-1 assume !(0 == ~E_4~0); 1117#L631-1 assume !(0 == ~E_5~0); 1272#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1111#L279 assume 1 == ~m_pc~0; 1112#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1363#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1339#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1340#L720 assume !(0 != activate_threads_~tmp~1#1); 1413#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1276#L298 assume !(1 == ~t1_pc~0); 1068#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1069#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1328#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1125#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1126#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1243#L317 assume 1 == ~t2_pc~0; 1244#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1390#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1497#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1285#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1286#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1460#L336 assume 1 == ~t3_pc~0; 1332#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1333#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1380#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1381#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1421#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1465#L355 assume !(1 == ~t4_pc~0); 1354#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1197#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1198#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1409#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1135#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1136#L374 assume 1 == ~t5_pc~0; 1483#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1264#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1337#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1338#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1383#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1384#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 1506#L649-2 assume !(1 == ~T1_E~0); 1100#L654-1 assume !(1 == ~T2_E~0); 1101#L659-1 assume !(1 == ~T3_E~0); 1284#L664-1 assume !(1 == ~T4_E~0); 1093#L669-1 assume !(1 == ~T5_E~0); 1094#L674-1 assume !(1 == ~E_1~0); 1456#L679-1 assume !(1 == ~E_2~0); 1188#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1189#L689-1 assume !(1 == ~E_4~0); 1351#L694-1 assume !(1 == ~E_5~0); 1349#L699-1 assume { :end_inline_reset_delta_events } true; 1350#L900-2 [2022-11-16 12:16:51,494 INFO L750 eck$LassoCheckResult]: Loop: 1350#L900-2 assume !false; 1513#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1047#L561 assume !false; 1132#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1313#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1070#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1071#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1176#L486 assume !(0 != eval_~tmp~0#1); 1178#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1503#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1504#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1455#L586-5 assume !(0 == ~T1_E~0); 1364#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1202#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1203#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1377#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1407#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1408#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1104#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1065#L626-3 assume !(0 == ~E_4~0); 1066#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1072#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1073#L279-18 assume 1 == ~m_pc~0; 1165#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1166#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1287#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1288#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1471#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1382#L298-18 assume 1 == ~t1_pc~0; 1044#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1038#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1210#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1233#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1234#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1359#L317-18 assume 1 == ~t2_pc~0; 1265#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1267#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1204#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1205#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1213#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1474#L336-18 assume 1 == ~t3_pc~0; 1457#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1458#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1290#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1291#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1157#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1158#L355-18 assume 1 == ~t4_pc~0; 1431#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1420#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1246#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1247#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1253#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1254#L374-18 assume 1 == ~t5_pc~0; 1464#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1318#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1319#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1432#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1414#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1415#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1331#L649-5 assume !(1 == ~T1_E~0); 1312#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1168#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1169#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1074#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1075#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1063#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1064#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1018#L689-3 assume !(1 == ~E_4~0); 1019#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1058#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1059#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1061#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1473#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1348#L919 assume !(0 == start_simulation_~tmp~3#1); 1077#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1444#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1052#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1297#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1298#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1343#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1293#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1294#L932 assume !(0 != start_simulation_~tmp___0~1#1); 1350#L900-2 [2022-11-16 12:16:51,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:51,517 INFO L85 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2022-11-16 12:16:51,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:51,517 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270312397] [2022-11-16 12:16:51,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:51,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:51,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:51,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:51,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:51,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [270312397] [2022-11-16 12:16:51,712 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [270312397] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:51,712 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:51,712 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:51,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633322138] [2022-11-16 12:16:51,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:51,714 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:51,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:51,715 INFO L85 PathProgramCache]: Analyzing trace with hash -1476238801, now seen corresponding path program 1 times [2022-11-16 12:16:51,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:51,717 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106607193] [2022-11-16 12:16:51,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:51,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:51,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:51,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:51,824 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:51,824 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106607193] [2022-11-16 12:16:51,825 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106607193] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:51,825 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:51,825 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:51,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607654289] [2022-11-16 12:16:51,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:51,826 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:51,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:51,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:51,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:51,828 INFO L87 Difference]: Start difference. First operand 498 states and 746 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:51,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:51,867 INFO L93 Difference]: Finished difference Result 498 states and 745 transitions. [2022-11-16 12:16:51,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 745 transitions. [2022-11-16 12:16:51,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:51,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 745 transitions. [2022-11-16 12:16:51,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-11-16 12:16:51,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-11-16 12:16:51,880 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 745 transitions. [2022-11-16 12:16:51,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:51,882 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 745 transitions. [2022-11-16 12:16:51,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 745 transitions. [2022-11-16 12:16:51,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-11-16 12:16:51,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:51,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 745 transitions. [2022-11-16 12:16:51,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 745 transitions. [2022-11-16 12:16:51,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:51,907 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2022-11-16 12:16:51,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 12:16:51,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 745 transitions. [2022-11-16 12:16:51,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:51,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:51,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:51,915 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:51,915 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:51,916 INFO L748 eck$LassoCheckResult]: Stem: 2518#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 2504#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2496#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2494#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2408#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 2409#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2214#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2215#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2492#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2493#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2465#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2186#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 2187#L586-2 assume !(0 == ~T1_E~0); 2240#L591-1 assume !(0 == ~T2_E~0); 2360#L596-1 assume !(0 == ~T3_E~0); 2361#L601-1 assume !(0 == ~T4_E~0); 2399#L606-1 assume !(0 == ~T5_E~0); 2400#L611-1 assume !(0 == ~E_1~0); 2471#L616-1 assume !(0 == ~E_2~0); 2472#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2119#L626-1 assume !(0 == ~E_4~0); 2120#L631-1 assume !(0 == ~E_5~0); 2275#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2114#L279 assume 1 == ~m_pc~0; 2115#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2366#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2342#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2343#L720 assume !(0 != activate_threads_~tmp~1#1); 2416#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2279#L298 assume !(1 == ~t1_pc~0); 2071#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2072#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2331#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2128#L728 assume !(0 != activate_threads_~tmp___0~0#1); 2129#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2246#L317 assume 1 == ~t2_pc~0; 2247#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2393#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2500#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2288#L736 assume !(0 != activate_threads_~tmp___1~0#1); 2289#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2463#L336 assume 1 == ~t3_pc~0; 2335#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2336#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2383#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2384#L744 assume !(0 != activate_threads_~tmp___2~0#1); 2424#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2468#L355 assume !(1 == ~t4_pc~0); 2357#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2200#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2201#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2412#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2138#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2139#L374 assume 1 == ~t5_pc~0; 2486#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2267#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2340#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2341#L760 assume !(0 != activate_threads_~tmp___4~0#1); 2386#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2387#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 2509#L649-2 assume !(1 == ~T1_E~0); 2103#L654-1 assume !(1 == ~T2_E~0); 2104#L659-1 assume !(1 == ~T3_E~0); 2287#L664-1 assume !(1 == ~T4_E~0); 2096#L669-1 assume !(1 == ~T5_E~0); 2097#L674-1 assume !(1 == ~E_1~0); 2459#L679-1 assume !(1 == ~E_2~0); 2191#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2192#L689-1 assume !(1 == ~E_4~0); 2354#L694-1 assume !(1 == ~E_5~0); 2352#L699-1 assume { :end_inline_reset_delta_events } true; 2353#L900-2 [2022-11-16 12:16:51,916 INFO L750 eck$LassoCheckResult]: Loop: 2353#L900-2 assume !false; 2516#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2050#L561 assume !false; 2135#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2316#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2073#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2074#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2179#L486 assume !(0 != eval_~tmp~0#1); 2181#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2506#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2507#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2458#L586-5 assume !(0 == ~T1_E~0); 2367#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2205#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2206#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2380#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2410#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2411#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2107#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2068#L626-3 assume !(0 == ~E_4~0); 2069#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2075#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2076#L279-18 assume 1 == ~m_pc~0; 2168#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2169#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2290#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2291#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2474#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2385#L298-18 assume !(1 == ~t1_pc~0); 2040#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2041#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2213#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2236#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2237#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2362#L317-18 assume 1 == ~t2_pc~0; 2268#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2270#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2207#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2208#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2216#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2477#L336-18 assume 1 == ~t3_pc~0; 2460#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2461#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2293#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2294#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2160#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2161#L355-18 assume 1 == ~t4_pc~0; 2434#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2423#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2249#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2250#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2256#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2257#L374-18 assume 1 == ~t5_pc~0; 2467#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2321#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2322#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2435#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2417#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2418#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2334#L649-5 assume !(1 == ~T1_E~0); 2315#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2171#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2172#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2077#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2078#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2066#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2067#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2021#L689-3 assume !(1 == ~E_4~0); 2022#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2061#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2062#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2064#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2476#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2351#L919 assume !(0 == start_simulation_~tmp~3#1); 2080#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2447#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2055#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2300#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2301#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2346#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2296#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2297#L932 assume !(0 != start_simulation_~tmp___0~1#1); 2353#L900-2 [2022-11-16 12:16:51,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:51,917 INFO L85 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2022-11-16 12:16:51,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:51,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372431972] [2022-11-16 12:16:51,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:51,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:51,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:51,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:51,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:51,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372431972] [2022-11-16 12:16:51,986 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372431972] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:51,986 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:51,986 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:51,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7446396] [2022-11-16 12:16:51,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:51,987 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:51,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:51,988 INFO L85 PathProgramCache]: Analyzing trace with hash -1373437554, now seen corresponding path program 1 times [2022-11-16 12:16:51,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:51,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591026787] [2022-11-16 12:16:51,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:51,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:52,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:52,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:52,066 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:52,067 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591026787] [2022-11-16 12:16:52,067 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1591026787] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:52,067 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:52,068 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:52,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108340258] [2022-11-16 12:16:52,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:52,069 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:52,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:52,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:52,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:52,070 INFO L87 Difference]: Start difference. First operand 498 states and 745 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:52,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:52,092 INFO L93 Difference]: Finished difference Result 498 states and 744 transitions. [2022-11-16 12:16:52,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 744 transitions. [2022-11-16 12:16:52,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:52,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 744 transitions. [2022-11-16 12:16:52,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-11-16 12:16:52,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-11-16 12:16:52,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 744 transitions. [2022-11-16 12:16:52,104 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:52,104 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 744 transitions. [2022-11-16 12:16:52,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 744 transitions. [2022-11-16 12:16:52,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-11-16 12:16:52,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:52,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 744 transitions. [2022-11-16 12:16:52,123 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 744 transitions. [2022-11-16 12:16:52,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:52,124 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2022-11-16 12:16:52,124 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 12:16:52,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 744 transitions. [2022-11-16 12:16:52,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:52,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:52,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:52,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:52,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:52,131 INFO L748 eck$LassoCheckResult]: Stem: 3521#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 3507#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3499#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3497#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3411#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 3412#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3217#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3218#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3495#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3496#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3468#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3189#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 3190#L586-2 assume !(0 == ~T1_E~0); 3243#L591-1 assume !(0 == ~T2_E~0); 3363#L596-1 assume !(0 == ~T3_E~0); 3364#L601-1 assume !(0 == ~T4_E~0); 3402#L606-1 assume !(0 == ~T5_E~0); 3403#L611-1 assume !(0 == ~E_1~0); 3474#L616-1 assume !(0 == ~E_2~0); 3475#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3122#L626-1 assume !(0 == ~E_4~0); 3123#L631-1 assume !(0 == ~E_5~0); 3278#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3117#L279 assume 1 == ~m_pc~0; 3118#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3369#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3345#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3346#L720 assume !(0 != activate_threads_~tmp~1#1); 3419#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3282#L298 assume !(1 == ~t1_pc~0); 3074#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3075#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3334#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3131#L728 assume !(0 != activate_threads_~tmp___0~0#1); 3132#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3249#L317 assume 1 == ~t2_pc~0; 3250#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3396#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3503#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3291#L736 assume !(0 != activate_threads_~tmp___1~0#1); 3292#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3466#L336 assume 1 == ~t3_pc~0; 3338#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3339#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3386#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3387#L744 assume !(0 != activate_threads_~tmp___2~0#1); 3427#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3471#L355 assume !(1 == ~t4_pc~0); 3360#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3203#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3204#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3415#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3141#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3142#L374 assume 1 == ~t5_pc~0; 3489#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3270#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3343#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3344#L760 assume !(0 != activate_threads_~tmp___4~0#1); 3389#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3390#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 3512#L649-2 assume !(1 == ~T1_E~0); 3106#L654-1 assume !(1 == ~T2_E~0); 3107#L659-1 assume !(1 == ~T3_E~0); 3290#L664-1 assume !(1 == ~T4_E~0); 3099#L669-1 assume !(1 == ~T5_E~0); 3100#L674-1 assume !(1 == ~E_1~0); 3462#L679-1 assume !(1 == ~E_2~0); 3194#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3195#L689-1 assume !(1 == ~E_4~0); 3357#L694-1 assume !(1 == ~E_5~0); 3355#L699-1 assume { :end_inline_reset_delta_events } true; 3356#L900-2 [2022-11-16 12:16:52,131 INFO L750 eck$LassoCheckResult]: Loop: 3356#L900-2 assume !false; 3519#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3053#L561 assume !false; 3138#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3319#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3076#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3077#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3182#L486 assume !(0 != eval_~tmp~0#1); 3184#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3509#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3510#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3461#L586-5 assume !(0 == ~T1_E~0); 3370#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3208#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3209#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3383#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3413#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3414#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3110#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3071#L626-3 assume !(0 == ~E_4~0); 3072#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3078#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3079#L279-18 assume 1 == ~m_pc~0; 3171#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3172#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3293#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3294#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3477#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3388#L298-18 assume !(1 == ~t1_pc~0); 3043#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3044#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3239#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3240#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3365#L317-18 assume 1 == ~t2_pc~0; 3271#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3273#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3210#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3211#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3219#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3480#L336-18 assume 1 == ~t3_pc~0; 3463#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3464#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3296#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3297#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3163#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3164#L355-18 assume !(1 == ~t4_pc~0); 3425#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3426#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3252#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3253#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3259#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3260#L374-18 assume !(1 == ~t5_pc~0); 3444#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 3324#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3325#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3438#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3420#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3421#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3337#L649-5 assume !(1 == ~T1_E~0); 3318#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3174#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3175#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3080#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3081#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3069#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3070#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3024#L689-3 assume !(1 == ~E_4~0); 3025#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3064#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3065#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3067#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3479#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3354#L919 assume !(0 == start_simulation_~tmp~3#1); 3083#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3450#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3058#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3303#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3304#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3349#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3299#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3300#L932 assume !(0 != start_simulation_~tmp___0~1#1); 3356#L900-2 [2022-11-16 12:16:52,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:52,132 INFO L85 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2022-11-16 12:16:52,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:52,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522463402] [2022-11-16 12:16:52,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:52,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:52,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:52,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:52,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:52,184 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522463402] [2022-11-16 12:16:52,184 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522463402] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:52,184 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:52,184 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:52,185 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944052257] [2022-11-16 12:16:52,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:52,185 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:52,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:52,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1099568908, now seen corresponding path program 1 times [2022-11-16 12:16:52,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:52,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926492661] [2022-11-16 12:16:52,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:52,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:52,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:52,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:52,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:52,301 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926492661] [2022-11-16 12:16:52,301 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926492661] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:52,301 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:52,302 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:52,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251651163] [2022-11-16 12:16:52,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:52,303 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:52,304 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:52,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:52,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:52,307 INFO L87 Difference]: Start difference. First operand 498 states and 744 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:52,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:52,330 INFO L93 Difference]: Finished difference Result 498 states and 743 transitions. [2022-11-16 12:16:52,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 743 transitions. [2022-11-16 12:16:52,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:52,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 743 transitions. [2022-11-16 12:16:52,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-11-16 12:16:52,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-11-16 12:16:52,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 743 transitions. [2022-11-16 12:16:52,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:52,340 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 743 transitions. [2022-11-16 12:16:52,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 743 transitions. [2022-11-16 12:16:52,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-11-16 12:16:52,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:52,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 743 transitions. [2022-11-16 12:16:52,361 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 743 transitions. [2022-11-16 12:16:52,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:52,362 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2022-11-16 12:16:52,362 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 12:16:52,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 743 transitions. [2022-11-16 12:16:52,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:52,366 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:52,366 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:52,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:52,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:52,373 INFO L748 eck$LassoCheckResult]: Stem: 4526#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 4512#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4504#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4502#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4416#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 4417#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4222#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4223#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4500#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4501#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4473#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4194#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 4195#L586-2 assume !(0 == ~T1_E~0); 4248#L591-1 assume !(0 == ~T2_E~0); 4368#L596-1 assume !(0 == ~T3_E~0); 4369#L601-1 assume !(0 == ~T4_E~0); 4407#L606-1 assume !(0 == ~T5_E~0); 4408#L611-1 assume !(0 == ~E_1~0); 4479#L616-1 assume !(0 == ~E_2~0); 4480#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4127#L626-1 assume !(0 == ~E_4~0); 4128#L631-1 assume !(0 == ~E_5~0); 4283#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4122#L279 assume 1 == ~m_pc~0; 4123#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4374#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4350#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4351#L720 assume !(0 != activate_threads_~tmp~1#1); 4424#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4287#L298 assume !(1 == ~t1_pc~0); 4079#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4080#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4339#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4136#L728 assume !(0 != activate_threads_~tmp___0~0#1); 4137#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4254#L317 assume 1 == ~t2_pc~0; 4255#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4401#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4508#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4296#L736 assume !(0 != activate_threads_~tmp___1~0#1); 4297#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4471#L336 assume 1 == ~t3_pc~0; 4343#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4344#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4391#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4392#L744 assume !(0 != activate_threads_~tmp___2~0#1); 4432#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4476#L355 assume !(1 == ~t4_pc~0); 4365#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4208#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4209#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4420#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4146#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4147#L374 assume 1 == ~t5_pc~0; 4494#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4275#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4348#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4349#L760 assume !(0 != activate_threads_~tmp___4~0#1); 4394#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4395#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 4517#L649-2 assume !(1 == ~T1_E~0); 4111#L654-1 assume !(1 == ~T2_E~0); 4112#L659-1 assume !(1 == ~T3_E~0); 4295#L664-1 assume !(1 == ~T4_E~0); 4104#L669-1 assume !(1 == ~T5_E~0); 4105#L674-1 assume !(1 == ~E_1~0); 4467#L679-1 assume !(1 == ~E_2~0); 4199#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4200#L689-1 assume !(1 == ~E_4~0); 4362#L694-1 assume !(1 == ~E_5~0); 4360#L699-1 assume { :end_inline_reset_delta_events } true; 4361#L900-2 [2022-11-16 12:16:52,379 INFO L750 eck$LassoCheckResult]: Loop: 4361#L900-2 assume !false; 4524#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4058#L561 assume !false; 4143#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4324#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4081#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4082#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4187#L486 assume !(0 != eval_~tmp~0#1); 4189#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4514#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4515#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4466#L586-5 assume !(0 == ~T1_E~0); 4375#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4213#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4214#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4388#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4418#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4419#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4115#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4076#L626-3 assume !(0 == ~E_4~0); 4077#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4083#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4084#L279-18 assume 1 == ~m_pc~0; 4176#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4177#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4298#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4299#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4482#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4393#L298-18 assume !(1 == ~t1_pc~0); 4048#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4049#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4221#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4244#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4245#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4370#L317-18 assume 1 == ~t2_pc~0; 4276#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4278#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4215#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4216#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4224#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4485#L336-18 assume 1 == ~t3_pc~0; 4468#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4469#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4301#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4302#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4168#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4169#L355-18 assume 1 == ~t4_pc~0; 4442#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4431#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4257#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4258#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4264#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4265#L374-18 assume !(1 == ~t5_pc~0); 4449#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 4329#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4330#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4443#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4425#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4426#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4342#L649-5 assume !(1 == ~T1_E~0); 4323#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4179#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4180#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4085#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4086#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4074#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4075#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4029#L689-3 assume !(1 == ~E_4~0); 4030#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4069#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4070#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4072#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4484#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4359#L919 assume !(0 == start_simulation_~tmp~3#1); 4088#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4455#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4063#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4308#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4309#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4354#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4304#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4305#L932 assume !(0 != start_simulation_~tmp___0~1#1); 4361#L900-2 [2022-11-16 12:16:52,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:52,380 INFO L85 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2022-11-16 12:16:52,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:52,382 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534762443] [2022-11-16 12:16:52,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:52,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:52,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:52,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:52,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:52,456 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534762443] [2022-11-16 12:16:52,456 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534762443] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:52,456 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:52,457 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:52,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498932764] [2022-11-16 12:16:52,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:52,457 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:52,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:52,458 INFO L85 PathProgramCache]: Analyzing trace with hash -1430581779, now seen corresponding path program 1 times [2022-11-16 12:16:52,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:52,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000635751] [2022-11-16 12:16:52,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:52,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:52,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:52,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:52,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:52,512 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000635751] [2022-11-16 12:16:52,512 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2000635751] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:52,512 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:52,512 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:52,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870116343] [2022-11-16 12:16:52,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:52,513 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:52,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:52,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:52,514 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:52,514 INFO L87 Difference]: Start difference. First operand 498 states and 743 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:52,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:52,532 INFO L93 Difference]: Finished difference Result 498 states and 742 transitions. [2022-11-16 12:16:52,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 742 transitions. [2022-11-16 12:16:52,537 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:52,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 742 transitions. [2022-11-16 12:16:52,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-11-16 12:16:52,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-11-16 12:16:52,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 742 transitions. [2022-11-16 12:16:52,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:52,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 498 states and 742 transitions. [2022-11-16 12:16:52,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 742 transitions. [2022-11-16 12:16:52,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-11-16 12:16:52,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:52,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 742 transitions. [2022-11-16 12:16:52,555 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 742 transitions. [2022-11-16 12:16:52,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:52,556 INFO L428 stractBuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2022-11-16 12:16:52,556 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 12:16:52,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 742 transitions. [2022-11-16 12:16:52,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-11-16 12:16:52,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:52,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:52,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:52,562 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:52,562 INFO L748 eck$LassoCheckResult]: Stem: 5529#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 5515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5507#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5505#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5419#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 5420#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5225#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5226#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5503#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5504#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5476#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5197#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 5198#L586-2 assume !(0 == ~T1_E~0); 5251#L591-1 assume !(0 == ~T2_E~0); 5371#L596-1 assume !(0 == ~T3_E~0); 5372#L601-1 assume !(0 == ~T4_E~0); 5410#L606-1 assume !(0 == ~T5_E~0); 5411#L611-1 assume !(0 == ~E_1~0); 5482#L616-1 assume !(0 == ~E_2~0); 5483#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5130#L626-1 assume !(0 == ~E_4~0); 5131#L631-1 assume !(0 == ~E_5~0); 5286#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5125#L279 assume 1 == ~m_pc~0; 5126#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5377#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5353#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5354#L720 assume !(0 != activate_threads_~tmp~1#1); 5427#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5290#L298 assume !(1 == ~t1_pc~0); 5082#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5083#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5342#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5139#L728 assume !(0 != activate_threads_~tmp___0~0#1); 5140#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5257#L317 assume 1 == ~t2_pc~0; 5258#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5404#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5511#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5299#L736 assume !(0 != activate_threads_~tmp___1~0#1); 5300#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5474#L336 assume 1 == ~t3_pc~0; 5346#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5347#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5394#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5395#L744 assume !(0 != activate_threads_~tmp___2~0#1); 5435#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5479#L355 assume !(1 == ~t4_pc~0); 5368#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5211#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5212#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5423#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5149#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5150#L374 assume 1 == ~t5_pc~0; 5497#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5278#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5351#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5352#L760 assume !(0 != activate_threads_~tmp___4~0#1); 5397#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5398#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 5520#L649-2 assume !(1 == ~T1_E~0); 5114#L654-1 assume !(1 == ~T2_E~0); 5115#L659-1 assume !(1 == ~T3_E~0); 5298#L664-1 assume !(1 == ~T4_E~0); 5107#L669-1 assume !(1 == ~T5_E~0); 5108#L674-1 assume !(1 == ~E_1~0); 5470#L679-1 assume !(1 == ~E_2~0); 5202#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5203#L689-1 assume !(1 == ~E_4~0); 5365#L694-1 assume !(1 == ~E_5~0); 5363#L699-1 assume { :end_inline_reset_delta_events } true; 5364#L900-2 [2022-11-16 12:16:52,563 INFO L750 eck$LassoCheckResult]: Loop: 5364#L900-2 assume !false; 5527#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5061#L561 assume !false; 5146#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5327#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5084#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5085#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5190#L486 assume !(0 != eval_~tmp~0#1); 5192#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5517#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5518#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5469#L586-5 assume !(0 == ~T1_E~0); 5378#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5216#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5217#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5391#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5421#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5422#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5118#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5079#L626-3 assume !(0 == ~E_4~0); 5080#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5086#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5087#L279-18 assume 1 == ~m_pc~0; 5179#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5180#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5301#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5302#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5485#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5396#L298-18 assume 1 == ~t1_pc~0; 5058#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5052#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5224#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5247#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5248#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5373#L317-18 assume !(1 == ~t2_pc~0); 5280#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 5281#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5218#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5219#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5227#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5488#L336-18 assume !(1 == ~t3_pc~0); 5473#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5472#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5304#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5305#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5171#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5172#L355-18 assume 1 == ~t4_pc~0; 5445#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5434#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5260#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5261#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5267#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5268#L374-18 assume 1 == ~t5_pc~0; 5478#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5332#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5333#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5446#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5428#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5429#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5345#L649-5 assume !(1 == ~T1_E~0); 5326#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5182#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5183#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5088#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5089#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5077#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5078#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5032#L689-3 assume !(1 == ~E_4~0); 5033#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5072#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5073#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5075#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5487#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5362#L919 assume !(0 == start_simulation_~tmp~3#1); 5091#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5458#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5066#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5311#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5312#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5357#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5307#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5308#L932 assume !(0 != start_simulation_~tmp___0~1#1); 5364#L900-2 [2022-11-16 12:16:52,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:52,564 INFO L85 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2022-11-16 12:16:52,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:52,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389360038] [2022-11-16 12:16:52,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:52,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:52,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:52,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:52,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:52,619 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389360038] [2022-11-16 12:16:52,620 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1389360038] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:52,620 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:52,620 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:52,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821667770] [2022-11-16 12:16:52,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:52,621 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:52,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:52,622 INFO L85 PathProgramCache]: Analyzing trace with hash 2096048813, now seen corresponding path program 1 times [2022-11-16 12:16:52,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:52,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902243107] [2022-11-16 12:16:52,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:52,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:52,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:52,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:52,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:52,675 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902243107] [2022-11-16 12:16:52,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902243107] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:52,675 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:52,675 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:52,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900034025] [2022-11-16 12:16:52,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:52,676 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:52,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:52,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:52,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:52,678 INFO L87 Difference]: Start difference. First operand 498 states and 742 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:52,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:52,780 INFO L93 Difference]: Finished difference Result 875 states and 1292 transitions. [2022-11-16 12:16:52,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 875 states and 1292 transitions. [2022-11-16 12:16:52,788 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2022-11-16 12:16:52,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 875 states to 875 states and 1292 transitions. [2022-11-16 12:16:52,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 875 [2022-11-16 12:16:52,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 875 [2022-11-16 12:16:52,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 875 states and 1292 transitions. [2022-11-16 12:16:52,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:52,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 875 states and 1292 transitions. [2022-11-16 12:16:52,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 875 states and 1292 transitions. [2022-11-16 12:16:52,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 875 to 875. [2022-11-16 12:16:52,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:52,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 875 states to 875 states and 1292 transitions. [2022-11-16 12:16:52,825 INFO L240 hiAutomatonCegarLoop]: Abstraction has 875 states and 1292 transitions. [2022-11-16 12:16:52,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:52,827 INFO L428 stractBuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2022-11-16 12:16:52,827 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 12:16:52,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 875 states and 1292 transitions. [2022-11-16 12:16:52,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2022-11-16 12:16:52,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:52,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:52,843 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:52,843 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:52,844 INFO L748 eck$LassoCheckResult]: Stem: 6939#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 6919#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6910#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6908#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6808#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 6809#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6608#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6609#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6906#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6907#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6871#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6581#L586 assume !(0 == ~M_E~0); 6582#L586-2 assume !(0 == ~T1_E~0); 6635#L591-1 assume !(0 == ~T2_E~0); 6760#L596-1 assume !(0 == ~T3_E~0); 6761#L601-1 assume !(0 == ~T4_E~0); 6799#L606-1 assume !(0 == ~T5_E~0); 6800#L611-1 assume !(0 == ~E_1~0); 6878#L616-1 assume !(0 == ~E_2~0); 6879#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6509#L626-1 assume !(0 == ~E_4~0); 6510#L631-1 assume !(0 == ~E_5~0); 6670#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6504#L279 assume !(1 == ~m_pc~0); 6506#L279-2 is_master_triggered_~__retres1~0#1 := 0; 6817#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6741#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6742#L720 assume !(0 != activate_threads_~tmp~1#1); 6816#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6676#L298 assume !(1 == ~t1_pc~0); 6462#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6463#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6729#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6518#L728 assume !(0 != activate_threads_~tmp___0~0#1); 6519#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6641#L317 assume 1 == ~t2_pc~0; 6642#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6793#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6914#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6690#L736 assume !(0 != activate_threads_~tmp___1~0#1); 6691#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6869#L336 assume 1 == ~t3_pc~0; 6733#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6734#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6782#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6783#L744 assume !(0 != activate_threads_~tmp___2~0#1); 6825#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6875#L355 assume !(1 == ~t4_pc~0); 6759#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6596#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6597#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6812#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6531#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6532#L374 assume 1 == ~t5_pc~0; 6897#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6665#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6739#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6740#L760 assume !(0 != activate_threads_~tmp___4~0#1); 6785#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6786#L649 assume !(1 == ~M_E~0); 6927#L649-2 assume !(1 == ~T1_E~0); 6493#L654-1 assume !(1 == ~T2_E~0); 6494#L659-1 assume !(1 == ~T3_E~0); 6684#L664-1 assume !(1 == ~T4_E~0); 6486#L669-1 assume !(1 == ~T5_E~0); 6487#L674-1 assume !(1 == ~E_1~0); 6863#L679-1 assume !(1 == ~E_2~0); 6583#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6584#L689-1 assume !(1 == ~E_4~0); 6754#L694-1 assume !(1 == ~E_5~0); 6752#L699-1 assume { :end_inline_reset_delta_events } true; 6753#L900-2 [2022-11-16 12:16:52,844 INFO L750 eck$LassoCheckResult]: Loop: 6753#L900-2 assume !false; 6936#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6441#L561 assume !false; 6525#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6714#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6464#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6465#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6570#L486 assume !(0 != eval_~tmp~0#1); 6572#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6922#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6923#L586-3 assume !(0 == ~M_E~0); 6925#L586-5 assume !(0 == ~T1_E~0); 7098#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7097#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7096#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7095#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7094#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7093#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7092#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7091#L626-3 assume !(0 == ~E_4~0); 7090#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6466#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6467#L279-18 assume !(1 == ~m_pc~0); 6559#L279-20 is_master_triggered_~__retres1~0#1 := 0; 6701#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6685#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6686#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6881#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6784#L298-18 assume 1 == ~t1_pc~0; 6438#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6432#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6607#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6631#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6632#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6762#L317-18 assume 1 == ~t2_pc~0; 6661#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6663#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6599#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6600#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6610#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6884#L336-18 assume 1 == ~t3_pc~0; 6864#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6865#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6688#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6689#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6550#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6551#L355-18 assume 1 == ~t4_pc~0; 6837#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6824#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6644#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6645#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6651#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6652#L374-18 assume 1 == ~t5_pc~0; 6873#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6719#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6720#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6838#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6818#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6819#L649-3 assume !(1 == ~M_E~0); 6732#L649-5 assume !(1 == ~T1_E~0); 6713#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6560#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6561#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6468#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6469#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6457#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6458#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6412#L689-3 assume !(1 == ~E_4~0); 6413#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6452#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6453#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6455#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6883#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6750#L919 assume !(0 == start_simulation_~tmp~3#1); 6471#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6938#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7074#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7073#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7072#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6885#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6693#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6694#L932 assume !(0 != start_simulation_~tmp___0~1#1); 6753#L900-2 [2022-11-16 12:16:52,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:52,849 INFO L85 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2022-11-16 12:16:52,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:52,850 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934714012] [2022-11-16 12:16:52,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:52,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:52,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:52,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:52,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:52,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934714012] [2022-11-16 12:16:52,973 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934714012] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:52,973 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:52,973 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:52,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090502511] [2022-11-16 12:16:52,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:52,974 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:52,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:52,975 INFO L85 PathProgramCache]: Analyzing trace with hash 855131594, now seen corresponding path program 1 times [2022-11-16 12:16:52,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:52,976 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225552828] [2022-11-16 12:16:52,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:52,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:52,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:53,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:53,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:53,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225552828] [2022-11-16 12:16:53,041 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225552828] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:53,042 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:53,044 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:53,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627577748] [2022-11-16 12:16:53,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:53,045 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:53,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:53,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:16:53,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:16:53,047 INFO L87 Difference]: Start difference. First operand 875 states and 1292 transitions. cyclomatic complexity: 418 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:53,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:53,218 INFO L93 Difference]: Finished difference Result 1596 states and 2357 transitions. [2022-11-16 12:16:53,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1596 states and 2357 transitions. [2022-11-16 12:16:53,231 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1508 [2022-11-16 12:16:53,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1596 states to 1596 states and 2357 transitions. [2022-11-16 12:16:53,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1596 [2022-11-16 12:16:53,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1596 [2022-11-16 12:16:53,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1596 states and 2357 transitions. [2022-11-16 12:16:53,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:53,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1596 states and 2357 transitions. [2022-11-16 12:16:53,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1596 states and 2357 transitions. [2022-11-16 12:16:53,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1596 to 1594. [2022-11-16 12:16:53,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1594 states, 1594 states have (on average 1.4774153074027603) internal successors, (2355), 1593 states have internal predecessors, (2355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:53,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1594 states to 1594 states and 2355 transitions. [2022-11-16 12:16:53,305 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1594 states and 2355 transitions. [2022-11-16 12:16:53,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:16:53,307 INFO L428 stractBuchiCegarLoop]: Abstraction has 1594 states and 2355 transitions. [2022-11-16 12:16:53,307 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 12:16:53,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1594 states and 2355 transitions. [2022-11-16 12:16:53,317 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1508 [2022-11-16 12:16:53,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:53,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:53,319 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:53,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:53,320 INFO L748 eck$LassoCheckResult]: Stem: 9476#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 9438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9422#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9420#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9305#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 9306#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9091#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9092#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9418#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9419#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9383#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9065#L586 assume !(0 == ~M_E~0); 9066#L586-2 assume !(0 == ~T1_E~0); 9118#L591-1 assume !(0 == ~T2_E~0); 9252#L596-1 assume !(0 == ~T3_E~0); 9253#L601-1 assume !(0 == ~T4_E~0); 9293#L606-1 assume !(0 == ~T5_E~0); 9294#L611-1 assume !(0 == ~E_1~0); 9390#L616-1 assume !(0 == ~E_2~0); 9391#L621-1 assume !(0 == ~E_3~0); 8993#L626-1 assume !(0 == ~E_4~0); 8994#L631-1 assume !(0 == ~E_5~0); 9155#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8988#L279 assume !(1 == ~m_pc~0); 8990#L279-2 is_master_triggered_~__retres1~0#1 := 0; 9318#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9228#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9229#L720 assume !(0 != activate_threads_~tmp~1#1); 9317#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9159#L298 assume !(1 == ~t1_pc~0); 8945#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8946#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9217#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9002#L728 assume !(0 != activate_threads_~tmp___0~0#1); 9003#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9125#L317 assume 1 == ~t2_pc~0; 9126#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9287#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9432#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9174#L736 assume !(0 != activate_threads_~tmp___1~0#1); 9175#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9381#L336 assume 1 == ~t3_pc~0; 9222#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9223#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9276#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9277#L744 assume !(0 != activate_threads_~tmp___2~0#1); 9327#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9388#L355 assume !(1 == ~t4_pc~0); 9251#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9079#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9080#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9311#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9016#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9017#L374 assume 1 == ~t5_pc~0; 9410#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9150#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9226#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9227#L760 assume !(0 != activate_threads_~tmp___4~0#1); 9279#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9280#L649 assume !(1 == ~M_E~0); 9448#L649-2 assume !(1 == ~T1_E~0); 8976#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8977#L659-1 assume !(1 == ~T3_E~0); 9167#L664-1 assume !(1 == ~T4_E~0); 9168#L669-1 assume !(1 == ~T5_E~0); 9373#L674-1 assume !(1 == ~E_1~0); 9374#L679-1 assume !(1 == ~E_2~0); 9067#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9068#L689-1 assume !(1 == ~E_4~0); 10368#L694-1 assume !(1 == ~E_5~0); 9243#L699-1 assume { :end_inline_reset_delta_events } true; 9244#L900-2 [2022-11-16 12:16:53,320 INFO L750 eck$LassoCheckResult]: Loop: 9244#L900-2 assume !false; 9472#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8922#L561 assume !false; 9010#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9209#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9515#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9501#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9502#L486 assume !(0 != eval_~tmp~0#1); 9789#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9787#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9784#L586-3 assume !(0 == ~M_E~0); 9785#L586-5 assume !(0 == ~T1_E~0); 9779#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9780#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10215#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10213#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10211#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10209#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10208#L621-3 assume !(0 == ~E_3~0); 10206#L626-3 assume !(0 == ~E_4~0); 10205#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10204#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10202#L279-18 assume !(1 == ~m_pc~0); 10198#L279-20 is_master_triggered_~__retres1~0#1 := 0; 10196#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10194#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10192#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10190#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10188#L298-18 assume 1 == ~t1_pc~0; 10185#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10181#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10178#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10175#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10172#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10169#L317-18 assume !(1 == ~t2_pc~0); 10165#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 10161#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10158#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10155#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10152#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10149#L336-18 assume 1 == ~t3_pc~0; 10146#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10143#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9172#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9173#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9036#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9037#L355-18 assume !(1 == ~t4_pc~0); 9977#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 9975#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9973#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9971#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9969#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9967#L374-18 assume 1 == ~t5_pc~0; 9963#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9961#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9959#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9957#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9955#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9953#L649-3 assume !(1 == ~M_E~0); 9950#L649-5 assume !(1 == ~T1_E~0); 9949#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9947#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9946#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9945#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9944#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9943#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9942#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9216#L689-3 assume !(1 == ~E_4~0); 9941#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9940#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9939#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9933#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9932#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 9930#L919 assume !(0 == start_simulation_~tmp~3#1); 9931#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10375#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10370#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9179#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9180#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9398#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9177#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9178#L932 assume !(0 != start_simulation_~tmp___0~1#1); 9244#L900-2 [2022-11-16 12:16:53,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:53,322 INFO L85 PathProgramCache]: Analyzing trace with hash 1446688901, now seen corresponding path program 1 times [2022-11-16 12:16:53,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:53,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748220301] [2022-11-16 12:16:53,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:53,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:53,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:53,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:53,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:53,388 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748220301] [2022-11-16 12:16:53,388 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1748220301] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:53,389 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:53,389 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:53,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996911510] [2022-11-16 12:16:53,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:53,390 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:53,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:53,391 INFO L85 PathProgramCache]: Analyzing trace with hash 468756806, now seen corresponding path program 1 times [2022-11-16 12:16:53,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:53,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499825684] [2022-11-16 12:16:53,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:53,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:53,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:53,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:53,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:53,480 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499825684] [2022-11-16 12:16:53,483 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [499825684] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:53,484 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:53,484 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:53,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2016166362] [2022-11-16 12:16:53,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:53,487 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:53,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:53,488 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:16:53,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:16:53,489 INFO L87 Difference]: Start difference. First operand 1594 states and 2355 transitions. cyclomatic complexity: 763 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:53,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:53,719 INFO L93 Difference]: Finished difference Result 4404 states and 6412 transitions. [2022-11-16 12:16:53,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4404 states and 6412 transitions. [2022-11-16 12:16:53,760 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4116 [2022-11-16 12:16:53,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4404 states to 4404 states and 6412 transitions. [2022-11-16 12:16:53,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4404 [2022-11-16 12:16:53,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4404 [2022-11-16 12:16:53,794 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4404 states and 6412 transitions. [2022-11-16 12:16:53,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:53,803 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4404 states and 6412 transitions. [2022-11-16 12:16:53,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4404 states and 6412 transitions. [2022-11-16 12:16:53,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4404 to 4162. [2022-11-16 12:16:53,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4162 states, 4162 states have (on average 1.4632388274867851) internal successors, (6090), 4161 states have internal predecessors, (6090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:53,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4162 states to 4162 states and 6090 transitions. [2022-11-16 12:16:53,980 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4162 states and 6090 transitions. [2022-11-16 12:16:53,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:16:53,985 INFO L428 stractBuchiCegarLoop]: Abstraction has 4162 states and 6090 transitions. [2022-11-16 12:16:53,985 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 12:16:53,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4162 states and 6090 transitions. [2022-11-16 12:16:54,011 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4058 [2022-11-16 12:16:54,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:54,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:54,012 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:54,013 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:54,013 INFO L748 eck$LassoCheckResult]: Stem: 15497#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 15454#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15443#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15441#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15319#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 15320#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15098#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15099#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15439#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15440#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15398#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15068#L586 assume !(0 == ~M_E~0); 15069#L586-2 assume !(0 == ~T1_E~0); 15125#L591-1 assume !(0 == ~T2_E~0); 15265#L596-1 assume !(0 == ~T3_E~0); 15266#L601-1 assume !(0 == ~T4_E~0); 15309#L606-1 assume !(0 == ~T5_E~0); 15310#L611-1 assume !(0 == ~E_1~0); 15408#L616-1 assume !(0 == ~E_2~0); 15409#L621-1 assume !(0 == ~E_3~0); 15000#L626-1 assume !(0 == ~E_4~0); 15001#L631-1 assume !(0 == ~E_5~0); 15160#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14996#L279 assume !(1 == ~m_pc~0); 14997#L279-2 is_master_triggered_~__retres1~0#1 := 0; 15331#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15236#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15237#L720 assume !(0 != activate_threads_~tmp~1#1); 15330#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15164#L298 assume !(1 == ~t1_pc~0); 14952#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14953#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15221#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15009#L728 assume !(0 != activate_threads_~tmp___0~0#1); 15010#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15131#L317 assume !(1 == ~t2_pc~0); 15132#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15350#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15449#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15174#L736 assume !(0 != activate_threads_~tmp___1~0#1); 15175#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15396#L336 assume 1 == ~t3_pc~0; 15228#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15229#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15289#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15290#L744 assume !(0 != activate_threads_~tmp___2~0#1); 15339#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15404#L355 assume !(1 == ~t4_pc~0); 15262#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15083#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15084#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15324#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15019#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15020#L374 assume 1 == ~t5_pc~0; 15431#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15152#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15234#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15235#L760 assume !(0 != activate_threads_~tmp___4~0#1); 15292#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15293#L649 assume !(1 == ~M_E~0); 15467#L649-2 assume !(1 == ~T1_E~0); 14984#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14985#L659-1 assume !(1 == ~T3_E~0); 15172#L664-1 assume !(1 == ~T4_E~0); 15173#L669-1 assume !(1 == ~T5_E~0); 15388#L674-1 assume !(1 == ~E_1~0); 15389#L679-1 assume !(1 == ~E_2~0); 15073#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 15074#L689-1 assume !(1 == ~E_4~0); 15256#L694-1 assume !(1 == ~E_5~0); 15254#L699-1 assume { :end_inline_reset_delta_events } true; 15255#L900-2 [2022-11-16 12:16:54,013 INFO L750 eck$LassoCheckResult]: Loop: 15255#L900-2 assume !false; 15484#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14931#L561 assume !false; 15016#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 15205#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14954#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14955#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15061#L486 assume !(0 != eval_~tmp~0#1); 15063#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15459#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15460#L586-3 assume !(0 == ~M_E~0); 15387#L586-5 assume !(0 == ~T1_E~0); 15272#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15089#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15090#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15286#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15322#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15323#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14989#L621-3 assume !(0 == ~E_3~0); 14949#L626-3 assume !(0 == ~E_4~0); 14950#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14956#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14957#L279-18 assume !(1 == ~m_pc~0); 15464#L279-20 is_master_triggered_~__retres1~0#1 := 0; 19005#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19002#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19000#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18998#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18996#L298-18 assume 1 == ~t1_pc~0; 18993#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18991#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18988#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18986#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18984#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18982#L317-18 assume !(1 == ~t2_pc~0); 18981#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 18980#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18979#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18978#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18977#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18976#L336-18 assume 1 == ~t3_pc~0; 18974#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18973#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18972#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18971#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18970#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18969#L355-18 assume !(1 == ~t4_pc~0); 18967#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 18966#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18965#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18964#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18963#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15402#L374-18 assume !(1 == ~t5_pc~0); 15362#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 15210#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15211#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15356#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15332#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15333#L649-3 assume !(1 == ~M_E~0); 15226#L649-5 assume !(1 == ~T1_E~0); 15227#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15052#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15053#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15473#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18900#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18872#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18868#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17106#L689-3 assume !(1 == ~E_4~0); 18865#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18864#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18860#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18853#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16370#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 16131#L919 assume !(0 == start_simulation_~tmp~3#1); 14961#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 15369#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14936#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 15186#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 15187#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15241#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15182#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 15183#L932 assume !(0 != start_simulation_~tmp___0~1#1); 15255#L900-2 [2022-11-16 12:16:54,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:54,014 INFO L85 PathProgramCache]: Analyzing trace with hash -318127708, now seen corresponding path program 1 times [2022-11-16 12:16:54,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:54,015 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796843810] [2022-11-16 12:16:54,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:54,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:54,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:54,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:54,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:54,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796843810] [2022-11-16 12:16:54,087 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796843810] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:54,088 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:54,088 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:54,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527362211] [2022-11-16 12:16:54,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:54,089 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:54,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:54,089 INFO L85 PathProgramCache]: Analyzing trace with hash 411612581, now seen corresponding path program 1 times [2022-11-16 12:16:54,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:54,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754308264] [2022-11-16 12:16:54,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:54,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:54,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:54,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:54,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:54,158 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754308264] [2022-11-16 12:16:54,158 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754308264] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:54,158 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:54,158 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:54,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [578683187] [2022-11-16 12:16:54,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:54,159 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:54,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:54,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:16:54,160 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:16:54,160 INFO L87 Difference]: Start difference. First operand 4162 states and 6090 transitions. cyclomatic complexity: 1932 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:54,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:54,400 INFO L93 Difference]: Finished difference Result 11351 states and 16460 transitions. [2022-11-16 12:16:54,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11351 states and 16460 transitions. [2022-11-16 12:16:54,606 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10788 [2022-11-16 12:16:54,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11351 states to 11351 states and 16460 transitions. [2022-11-16 12:16:54,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11351 [2022-11-16 12:16:54,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11351 [2022-11-16 12:16:54,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11351 states and 16460 transitions. [2022-11-16 12:16:54,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:54,711 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11351 states and 16460 transitions. [2022-11-16 12:16:54,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11351 states and 16460 transitions. [2022-11-16 12:16:54,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11351 to 10667. [2022-11-16 12:16:55,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10667 states, 10667 states have (on average 1.4594543920502485) internal successors, (15568), 10666 states have internal predecessors, (15568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:55,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10667 states to 10667 states and 15568 transitions. [2022-11-16 12:16:55,112 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10667 states and 15568 transitions. [2022-11-16 12:16:55,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:16:55,116 INFO L428 stractBuchiCegarLoop]: Abstraction has 10667 states and 15568 transitions. [2022-11-16 12:16:55,116 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 12:16:55,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10667 states and 15568 transitions. [2022-11-16 12:16:55,170 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10524 [2022-11-16 12:16:55,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:55,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:55,172 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:55,172 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:55,173 INFO L748 eck$LassoCheckResult]: Stem: 30998#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 30963#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 30949#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30946#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30831#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 30832#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30622#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30623#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30944#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30945#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30902#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30594#L586 assume !(0 == ~M_E~0); 30595#L586-2 assume !(0 == ~T1_E~0); 30649#L591-1 assume !(0 == ~T2_E~0); 30779#L596-1 assume !(0 == ~T3_E~0); 30780#L601-1 assume !(0 == ~T4_E~0); 30822#L606-1 assume !(0 == ~T5_E~0); 30823#L611-1 assume !(0 == ~E_1~0); 30915#L616-1 assume !(0 == ~E_2~0); 30916#L621-1 assume !(0 == ~E_3~0); 30525#L626-1 assume !(0 == ~E_4~0); 30526#L631-1 assume !(0 == ~E_5~0); 30682#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30521#L279 assume !(1 == ~m_pc~0); 30522#L279-2 is_master_triggered_~__retres1~0#1 := 0; 30843#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30755#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30756#L720 assume !(0 != activate_threads_~tmp~1#1); 30842#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30688#L298 assume !(1 == ~t1_pc~0); 30477#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30478#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30746#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30534#L728 assume !(0 != activate_threads_~tmp___0~0#1); 30535#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30655#L317 assume !(1 == ~t2_pc~0); 30656#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30862#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30956#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30698#L736 assume !(0 != activate_threads_~tmp___1~0#1); 30699#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30899#L336 assume !(1 == ~t3_pc~0); 30900#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30979#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30806#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30807#L744 assume !(0 != activate_threads_~tmp___2~0#1); 30851#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30909#L355 assume !(1 == ~t4_pc~0); 30776#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30608#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30609#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30836#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30546#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30547#L374 assume 1 == ~t5_pc~0; 30935#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30674#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30753#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30754#L760 assume !(0 != activate_threads_~tmp___4~0#1); 30809#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30810#L649 assume !(1 == ~M_E~0); 30970#L649-2 assume !(1 == ~T1_E~0); 30509#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30510#L659-1 assume !(1 == ~T3_E~0); 30696#L664-1 assume !(1 == ~T4_E~0); 30697#L669-1 assume !(1 == ~T5_E~0); 30893#L674-1 assume !(1 == ~E_1~0); 30894#L679-1 assume !(1 == ~E_2~0); 30599#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 30600#L689-1 assume !(1 == ~E_4~0); 30995#L694-1 assume !(1 == ~E_5~0); 30996#L699-1 assume { :end_inline_reset_delta_events } true; 36827#L900-2 [2022-11-16 12:16:55,173 INFO L750 eck$LassoCheckResult]: Loop: 36827#L900-2 assume !false; 36820#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36815#L561 assume !false; 36813#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 36765#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 36759#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 36757#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36754#L486 assume !(0 != eval_~tmp~0#1); 36755#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37798#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37796#L586-3 assume !(0 == ~M_E~0); 37794#L586-5 assume !(0 == ~T1_E~0); 37791#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37789#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37786#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37783#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37779#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37775#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37770#L621-3 assume !(0 == ~E_3~0); 37766#L626-3 assume !(0 == ~E_4~0); 37762#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37757#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37756#L279-18 assume !(1 == ~m_pc~0); 37755#L279-20 is_master_triggered_~__retres1~0#1 := 0; 37753#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37751#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37749#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37747#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37745#L298-18 assume 1 == ~t1_pc~0; 37712#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37710#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37708#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37706#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37704#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37702#L317-18 assume !(1 == ~t2_pc~0); 37700#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 37698#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37696#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37693#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37682#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37677#L336-18 assume !(1 == ~t3_pc~0); 37671#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 37659#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37644#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37639#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37634#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37623#L355-18 assume !(1 == ~t4_pc~0); 37619#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 37609#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37603#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37596#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37588#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37580#L374-18 assume 1 == ~t5_pc~0; 37576#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37571#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37569#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37566#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37563#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37131#L649-3 assume !(1 == ~M_E~0); 37127#L649-5 assume !(1 == ~T1_E~0); 37125#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37122#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37119#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37117#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37115#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37113#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37111#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37107#L689-3 assume !(1 == ~E_4~0); 37104#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37102#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 37100#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 37093#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 37060#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 37053#L919 assume !(0 == start_simulation_~tmp~3#1); 37048#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 36856#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 36850#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 36848#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 36846#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36844#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36842#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 36839#L932 assume !(0 != start_simulation_~tmp___0~1#1); 36827#L900-2 [2022-11-16 12:16:55,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:55,174 INFO L85 PathProgramCache]: Analyzing trace with hash -375271933, now seen corresponding path program 1 times [2022-11-16 12:16:55,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:55,175 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107079813] [2022-11-16 12:16:55,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:55,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:55,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:55,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:55,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:55,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107079813] [2022-11-16 12:16:55,325 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107079813] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:55,325 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:55,325 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:55,326 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952290075] [2022-11-16 12:16:55,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:55,327 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:55,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:55,328 INFO L85 PathProgramCache]: Analyzing trace with hash -1686757595, now seen corresponding path program 1 times [2022-11-16 12:16:55,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:55,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111215375] [2022-11-16 12:16:55,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:55,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:55,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:55,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:55,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:55,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111215375] [2022-11-16 12:16:55,419 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111215375] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:55,419 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:55,419 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:55,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654047085] [2022-11-16 12:16:55,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:55,420 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:55,420 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:55,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:16:55,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:16:55,423 INFO L87 Difference]: Start difference. First operand 10667 states and 15568 transitions. cyclomatic complexity: 4909 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:55,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:55,795 INFO L93 Difference]: Finished difference Result 26236 states and 38605 transitions. [2022-11-16 12:16:55,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26236 states and 38605 transitions. [2022-11-16 12:16:56,064 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25924 [2022-11-16 12:16:56,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26236 states to 26236 states and 38605 transitions. [2022-11-16 12:16:56,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26236 [2022-11-16 12:16:56,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26236 [2022-11-16 12:16:56,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26236 states and 38605 transitions. [2022-11-16 12:16:56,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:56,302 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26236 states and 38605 transitions. [2022-11-16 12:16:56,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26236 states and 38605 transitions. [2022-11-16 12:16:56,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26236 to 11150. [2022-11-16 12:16:56,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11150 states, 11150 states have (on average 1.4395515695067265) internal successors, (16051), 11149 states have internal predecessors, (16051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:56,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11150 states to 11150 states and 16051 transitions. [2022-11-16 12:16:56,720 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11150 states and 16051 transitions. [2022-11-16 12:16:56,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 12:16:56,721 INFO L428 stractBuchiCegarLoop]: Abstraction has 11150 states and 16051 transitions. [2022-11-16 12:16:56,722 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 12:16:56,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11150 states and 16051 transitions. [2022-11-16 12:16:56,774 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11004 [2022-11-16 12:16:56,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:56,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:56,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:56,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:56,778 INFO L748 eck$LassoCheckResult]: Stem: 67952#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 67904#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 67891#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67887#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67764#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 67765#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67549#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67550#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67885#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67886#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67844#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67516#L586 assume !(0 == ~M_E~0); 67517#L586-2 assume !(0 == ~T1_E~0); 67576#L591-1 assume !(0 == ~T2_E~0); 67711#L596-1 assume !(0 == ~T3_E~0); 67712#L601-1 assume !(0 == ~T4_E~0); 67755#L606-1 assume !(0 == ~T5_E~0); 67756#L611-1 assume !(0 == ~E_1~0); 67857#L616-1 assume !(0 == ~E_2~0); 67858#L621-1 assume !(0 == ~E_3~0); 67442#L626-1 assume !(0 == ~E_4~0); 67443#L631-1 assume !(0 == ~E_5~0); 67609#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67438#L279 assume !(1 == ~m_pc~0); 67439#L279-2 is_master_triggered_~__retres1~0#1 := 0; 67776#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67683#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67684#L720 assume !(0 != activate_threads_~tmp~1#1); 67775#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67613#L298 assume !(1 == ~t1_pc~0); 67395#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67396#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67672#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67451#L728 assume !(0 != activate_threads_~tmp___0~0#1); 67452#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67582#L317 assume !(1 == ~t2_pc~0); 67583#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67795#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67898#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 67622#L736 assume !(0 != activate_threads_~tmp___1~0#1); 67623#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67839#L336 assume !(1 == ~t3_pc~0); 67840#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67933#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67739#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67740#L744 assume !(0 != activate_threads_~tmp___2~0#1); 67785#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67850#L355 assume !(1 == ~t4_pc~0); 67708#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67535#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67536#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 67831#L752 assume !(0 != activate_threads_~tmp___3~0#1); 67467#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67468#L374 assume 1 == ~t5_pc~0; 67877#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67601#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67681#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 67682#L760 assume !(0 != activate_threads_~tmp___4~0#1); 67742#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67743#L649 assume !(1 == ~M_E~0); 67918#L649-2 assume !(1 == ~T1_E~0); 67426#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67427#L659-1 assume !(1 == ~T3_E~0); 67621#L664-1 assume !(1 == ~T4_E~0); 67419#L669-1 assume !(1 == ~T5_E~0); 67420#L674-1 assume !(1 == ~E_1~0); 67847#L679-1 assume !(1 == ~E_2~0); 67848#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 67523#L689-1 assume !(1 == ~E_4~0); 67702#L694-1 assume !(1 == ~E_5~0); 67700#L699-1 assume { :end_inline_reset_delta_events } true; 67701#L900-2 [2022-11-16 12:16:56,778 INFO L750 eck$LassoCheckResult]: Loop: 67701#L900-2 assume !false; 78222#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78219#L561 assume !false; 78218#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 78200#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 78164#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 78149#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 78146#L486 assume !(0 != eval_~tmp~0#1); 67936#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67910#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67911#L586-3 assume !(0 == ~M_E~0); 67913#L586-5 assume !(0 == ~T1_E~0); 78294#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78292#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78290#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78288#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78286#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78280#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 78278#L621-3 assume !(0 == ~E_3~0); 78271#L626-3 assume !(0 == ~E_4~0); 78268#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78260#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78259#L279-18 assume !(1 == ~m_pc~0); 78258#L279-20 is_master_triggered_~__retres1~0#1 := 0; 78257#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78256#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 78255#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78254#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78253#L298-18 assume 1 == ~t1_pc~0; 78251#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 78250#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78249#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 78248#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78247#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78246#L317-18 assume !(1 == ~t2_pc~0); 78245#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 78244#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78243#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 78242#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78241#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78240#L336-18 assume !(1 == ~t3_pc~0); 78239#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 78238#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78237#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 78236#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78235#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78234#L355-18 assume !(1 == ~t4_pc~0); 78233#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 78231#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78229#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 78227#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 78220#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78202#L374-18 assume 1 == ~t5_pc~0; 78177#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78175#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78173#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 78171#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78169#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78167#L649-3 assume !(1 == ~M_E~0); 78035#L649-5 assume !(1 == ~T1_E~0); 78162#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75519#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78157#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78156#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78152#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78150#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78147#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75512#L689-3 assume !(1 == ~E_4~0); 78143#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78138#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 78137#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 78129#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 78127#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 67696#L919 assume !(0 == start_simulation_~tmp~3#1); 67404#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 67951#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 78293#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 78291#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 78289#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78287#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78272#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 78269#L932 assume !(0 != start_simulation_~tmp___0~1#1); 67701#L900-2 [2022-11-16 12:16:56,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:56,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1192920383, now seen corresponding path program 1 times [2022-11-16 12:16:56,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:56,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770243875] [2022-11-16 12:16:56,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:56,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:56,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:56,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:56,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:56,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770243875] [2022-11-16 12:16:56,890 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770243875] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:56,890 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:56,890 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:56,890 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086959080] [2022-11-16 12:16:56,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:56,891 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:56,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:56,892 INFO L85 PathProgramCache]: Analyzing trace with hash -1411997981, now seen corresponding path program 1 times [2022-11-16 12:16:56,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:56,892 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380523759] [2022-11-16 12:16:56,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:56,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:56,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:57,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:57,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:57,088 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380523759] [2022-11-16 12:16:57,088 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380523759] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:57,088 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:57,088 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:57,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110383925] [2022-11-16 12:16:57,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:57,089 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:57,089 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:57,090 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:57,090 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:57,091 INFO L87 Difference]: Start difference. First operand 11150 states and 16051 transitions. cyclomatic complexity: 4909 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:57,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:57,243 INFO L93 Difference]: Finished difference Result 22017 states and 31458 transitions. [2022-11-16 12:16:57,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22017 states and 31458 transitions. [2022-11-16 12:16:57,359 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21740 [2022-11-16 12:16:57,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22017 states to 22017 states and 31458 transitions. [2022-11-16 12:16:57,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22017 [2022-11-16 12:16:57,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22017 [2022-11-16 12:16:57,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22017 states and 31458 transitions. [2022-11-16 12:16:57,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:57,486 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22017 states and 31458 transitions. [2022-11-16 12:16:57,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22017 states and 31458 transitions. [2022-11-16 12:16:58,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22017 to 21873. [2022-11-16 12:16:58,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21873 states, 21873 states have (on average 1.4299821697983817) internal successors, (31278), 21872 states have internal predecessors, (31278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:58,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21873 states to 21873 states and 31278 transitions. [2022-11-16 12:16:58,323 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21873 states and 31278 transitions. [2022-11-16 12:16:58,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:58,324 INFO L428 stractBuchiCegarLoop]: Abstraction has 21873 states and 31278 transitions. [2022-11-16 12:16:58,324 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 12:16:58,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21873 states and 31278 transitions. [2022-11-16 12:16:58,488 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21668 [2022-11-16 12:16:58,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:58,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:58,489 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:58,490 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:58,490 INFO L748 eck$LassoCheckResult]: Stem: 101117#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 101079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 101064#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101062#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100942#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 100943#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100722#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100723#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101060#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 101061#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 101025#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100694#L586 assume !(0 == ~M_E~0); 100695#L586-2 assume !(0 == ~T1_E~0); 100750#L591-1 assume !(0 == ~T2_E~0); 100884#L596-1 assume !(0 == ~T3_E~0); 100885#L601-1 assume !(0 == ~T4_E~0); 100933#L606-1 assume !(0 == ~T5_E~0); 100934#L611-1 assume !(0 == ~E_1~0); 101032#L616-1 assume !(0 == ~E_2~0); 101033#L621-1 assume !(0 == ~E_3~0); 100620#L626-1 assume !(0 == ~E_4~0); 100621#L631-1 assume !(0 == ~E_5~0); 100785#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100616#L279 assume !(1 == ~m_pc~0); 100617#L279-2 is_master_triggered_~__retres1~0#1 := 0; 100955#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100859#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 100860#L720 assume !(0 != activate_threads_~tmp~1#1); 100954#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100789#L298 assume !(1 == ~t1_pc~0); 100572#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100573#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100849#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 100630#L728 assume !(0 != activate_threads_~tmp___0~0#1); 100631#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100757#L317 assume !(1 == ~t2_pc~0); 100758#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100976#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101073#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 100800#L736 assume !(0 != activate_threads_~tmp___1~0#1); 100801#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101023#L336 assume !(1 == ~t3_pc~0); 101024#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101096#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100914#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100915#L744 assume !(0 != activate_threads_~tmp___2~0#1); 100963#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101029#L355 assume !(1 == ~t4_pc~0); 100881#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100708#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100709#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100947#L752 assume !(0 != activate_threads_~tmp___3~0#1); 100645#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100646#L374 assume !(1 == ~t5_pc~0); 100776#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100777#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100857#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100858#L760 assume !(0 != activate_threads_~tmp___4~0#1); 100917#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100918#L649 assume !(1 == ~M_E~0); 101090#L649-2 assume !(1 == ~T1_E~0); 100604#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100605#L659-1 assume !(1 == ~T3_E~0); 100797#L664-1 assume !(1 == ~T4_E~0); 100597#L669-1 assume !(1 == ~T5_E~0); 100598#L674-1 assume !(1 == ~E_1~0); 101017#L679-1 assume !(1 == ~E_2~0); 100699#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 100700#L689-1 assume !(1 == ~E_4~0); 100876#L694-1 assume !(1 == ~E_5~0); 100874#L699-1 assume { :end_inline_reset_delta_events } true; 100875#L900-2 [2022-11-16 12:16:58,490 INFO L750 eck$LassoCheckResult]: Loop: 100875#L900-2 assume !false; 121870#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 121248#L561 assume !false; 121869#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 100831#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 100755#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 109530#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 109482#L486 assume !(0 != eval_~tmp~0#1); 109483#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 122120#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 122118#L586-3 assume !(0 == ~M_E~0); 122114#L586-5 assume !(0 == ~T1_E~0); 122112#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 122110#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 122108#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 122105#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 122103#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 122101#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 122098#L621-3 assume !(0 == ~E_3~0); 122096#L626-3 assume !(0 == ~E_4~0); 122094#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 122092#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122090#L279-18 assume !(1 == ~m_pc~0); 122089#L279-20 is_master_triggered_~__retres1~0#1 := 0; 122085#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122083#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 122082#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 122081#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122080#L298-18 assume 1 == ~t1_pc~0; 122077#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 122075#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122073#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 122071#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 122069#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100887#L317-18 assume !(1 == ~t2_pc~0); 100888#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 100909#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100715#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 100716#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100724#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101038#L336-18 assume !(1 == ~t3_pc~0); 101039#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 101069#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100798#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100799#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100666#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100667#L355-18 assume !(1 == ~t4_pc~0); 100961#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 100962#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121703#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100893#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 100766#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100767#L374-18 assume !(1 == ~t5_pc~0); 100987#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 100836#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100837#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100981#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100956#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100957#L649-3 assume !(1 == ~M_E~0); 101101#L649-5 assume !(1 == ~T1_E~0); 121491#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 114530#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 121488#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 121271#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 121269#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 121268#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 121264#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 114515#L689-3 assume !(1 == ~E_4~0); 121261#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 121260#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 121256#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 121249#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 121246#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 121192#L919 assume !(0 == start_simulation_~tmp~3#1); 121193#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 121888#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 121882#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 121879#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 121877#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 121875#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 121873#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 121871#L932 assume !(0 != start_simulation_~tmp___0~1#1); 100875#L900-2 [2022-11-16 12:16:58,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:58,491 INFO L85 PathProgramCache]: Analyzing trace with hash -52568672, now seen corresponding path program 1 times [2022-11-16 12:16:58,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:58,492 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533451588] [2022-11-16 12:16:58,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:58,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:58,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:58,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:58,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:58,549 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533451588] [2022-11-16 12:16:58,549 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533451588] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:58,549 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:58,550 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:16:58,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524683977] [2022-11-16 12:16:58,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:58,550 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:58,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:58,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1469142206, now seen corresponding path program 1 times [2022-11-16 12:16:58,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:58,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [719419757] [2022-11-16 12:16:58,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:58,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:58,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:58,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:58,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:58,619 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [719419757] [2022-11-16 12:16:58,619 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [719419757] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:58,619 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:58,619 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:16:58,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054738915] [2022-11-16 12:16:58,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:58,620 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:58,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:58,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:16:58,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:16:58,621 INFO L87 Difference]: Start difference. First operand 21873 states and 31278 transitions. cyclomatic complexity: 9421 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:58,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:58,737 INFO L93 Difference]: Finished difference Result 21867 states and 31085 transitions. [2022-11-16 12:16:58,738 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21867 states and 31085 transitions. [2022-11-16 12:16:58,968 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21668 [2022-11-16 12:16:59,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21867 states to 21867 states and 31085 transitions. [2022-11-16 12:16:59,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21867 [2022-11-16 12:16:59,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21867 [2022-11-16 12:16:59,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21867 states and 31085 transitions. [2022-11-16 12:16:59,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:16:59,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21867 states and 31085 transitions. [2022-11-16 12:16:59,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21867 states and 31085 transitions. [2022-11-16 12:16:59,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21867 to 11243. [2022-11-16 12:16:59,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11243 states, 11243 states have (on average 1.4189273325624834) internal successors, (15953), 11242 states have internal predecessors, (15953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:59,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11243 states to 11243 states and 15953 transitions. [2022-11-16 12:16:59,419 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11243 states and 15953 transitions. [2022-11-16 12:16:59,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:16:59,420 INFO L428 stractBuchiCegarLoop]: Abstraction has 11243 states and 15953 transitions. [2022-11-16 12:16:59,420 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 12:16:59,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11243 states and 15953 transitions. [2022-11-16 12:16:59,457 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11107 [2022-11-16 12:16:59,458 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:16:59,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:16:59,459 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:59,459 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:16:59,460 INFO L748 eck$LassoCheckResult]: Stem: 144870#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 144822#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 144807#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 144805#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 144680#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 144681#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 144466#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144467#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144803#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144804#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144766#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 144441#L586 assume !(0 == ~M_E~0); 144442#L586-2 assume !(0 == ~T1_E~0); 144494#L591-1 assume !(0 == ~T2_E~0); 144629#L596-1 assume !(0 == ~T3_E~0); 144630#L601-1 assume !(0 == ~T4_E~0); 144670#L606-1 assume !(0 == ~T5_E~0); 144671#L611-1 assume !(0 == ~E_1~0); 144773#L616-1 assume !(0 == ~E_2~0); 144774#L621-1 assume !(0 == ~E_3~0); 144366#L626-1 assume !(0 == ~E_4~0); 144367#L631-1 assume !(0 == ~E_5~0); 144529#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144364#L279 assume !(1 == ~m_pc~0); 144365#L279-2 is_master_triggered_~__retres1~0#1 := 0; 144696#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144599#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 144600#L720 assume !(0 != activate_threads_~tmp~1#1); 144695#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144535#L298 assume !(1 == ~t1_pc~0); 144322#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 144323#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144590#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 144375#L728 assume !(0 != activate_threads_~tmp___0~0#1); 144376#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144501#L317 assume !(1 == ~t2_pc~0); 144502#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 144717#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144818#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 144549#L736 assume !(0 != activate_threads_~tmp___1~0#1); 144550#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144762#L336 assume !(1 == ~t3_pc~0); 144763#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 144845#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144653#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144654#L744 assume !(0 != activate_threads_~tmp___2~0#1); 144706#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144770#L355 assume !(1 == ~t4_pc~0); 144628#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 144767#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144876#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144751#L752 assume !(0 != activate_threads_~tmp___3~0#1); 144389#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144390#L374 assume !(1 == ~t5_pc~0); 144523#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 144524#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144597#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144598#L760 assume !(0 != activate_threads_~tmp___4~0#1); 144656#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144657#L649 assume !(1 == ~M_E~0); 144836#L649-2 assume !(1 == ~T1_E~0); 144351#L654-1 assume !(1 == ~T2_E~0); 144352#L659-1 assume !(1 == ~T3_E~0); 144543#L664-1 assume !(1 == ~T4_E~0); 144344#L669-1 assume !(1 == ~T5_E~0); 144345#L674-1 assume !(1 == ~E_1~0); 144752#L679-1 assume !(1 == ~E_2~0); 144443#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 144444#L689-1 assume !(1 == ~E_4~0); 144622#L694-1 assume !(1 == ~E_5~0); 144620#L699-1 assume { :end_inline_reset_delta_events } true; 144621#L900-2 [2022-11-16 12:16:59,460 INFO L750 eck$LassoCheckResult]: Loop: 144621#L900-2 assume !false; 153317#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 153273#L561 assume !false; 153314#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 153309#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 153303#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 153302#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 153297#L486 assume !(0 != eval_~tmp~0#1); 153298#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 153486#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 153484#L586-3 assume !(0 == ~M_E~0); 153482#L586-5 assume !(0 == ~T1_E~0); 153480#L591-3 assume !(0 == ~T2_E~0); 153478#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 153475#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 153473#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 153471#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 153469#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 153467#L621-3 assume !(0 == ~E_3~0); 153465#L626-3 assume !(0 == ~E_4~0); 153463#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 153461#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153459#L279-18 assume !(1 == ~m_pc~0); 153457#L279-20 is_master_triggered_~__retres1~0#1 := 0; 153455#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153453#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 153451#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 153449#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153447#L298-18 assume 1 == ~t1_pc~0; 153444#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 153442#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153441#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 153437#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 153435#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153433#L317-18 assume !(1 == ~t2_pc~0); 153431#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 153428#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153426#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 153424#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 153422#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153420#L336-18 assume !(1 == ~t3_pc~0); 153418#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 153416#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153414#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 153413#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 153412#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153411#L355-18 assume 1 == ~t4_pc~0; 153410#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 153408#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153406#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 153403#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 153402#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153401#L374-18 assume !(1 == ~t5_pc~0); 153400#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 153399#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153398#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 153396#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 153395#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153394#L649-3 assume !(1 == ~M_E~0); 152398#L649-5 assume !(1 == ~T1_E~0); 153393#L654-3 assume !(1 == ~T2_E~0); 153392#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 153391#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 153390#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 153389#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 153388#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 153387#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 153386#L689-3 assume !(1 == ~E_4~0); 153384#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 153382#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 153380#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 153373#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 153371#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 153346#L919 assume !(0 == start_simulation_~tmp~3#1); 153344#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 153339#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 153333#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 153331#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 153327#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 153325#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 153323#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 153321#L932 assume !(0 != start_simulation_~tmp___0~1#1); 144621#L900-2 [2022-11-16 12:16:59,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:59,460 INFO L85 PathProgramCache]: Analyzing trace with hash -445595682, now seen corresponding path program 1 times [2022-11-16 12:16:59,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:59,461 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468853397] [2022-11-16 12:16:59,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:59,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:59,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:59,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:59,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:59,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [468853397] [2022-11-16 12:16:59,531 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [468853397] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:59,531 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:59,532 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:59,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373147818] [2022-11-16 12:16:59,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:59,532 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:16:59,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:16:59,533 INFO L85 PathProgramCache]: Analyzing trace with hash -2146739999, now seen corresponding path program 1 times [2022-11-16 12:16:59,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:16:59,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587106214] [2022-11-16 12:16:59,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:16:59,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:16:59,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:16:59,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:16:59,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:16:59,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587106214] [2022-11-16 12:16:59,574 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587106214] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:16:59,575 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:16:59,575 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:16:59,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675788333] [2022-11-16 12:16:59,575 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:16:59,576 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:16:59,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:16:59,576 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:16:59,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:16:59,577 INFO L87 Difference]: Start difference. First operand 11243 states and 15953 transitions. cyclomatic complexity: 4718 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:16:59,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:16:59,873 INFO L93 Difference]: Finished difference Result 18761 states and 26436 transitions. [2022-11-16 12:16:59,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18761 states and 26436 transitions. [2022-11-16 12:16:59,977 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 18573 [2022-11-16 12:17:00,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18761 states to 18761 states and 26436 transitions. [2022-11-16 12:17:00,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18761 [2022-11-16 12:17:00,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18761 [2022-11-16 12:17:00,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18761 states and 26436 transitions. [2022-11-16 12:17:00,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:00,089 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18761 states and 26436 transitions. [2022-11-16 12:17:00,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18761 states and 26436 transitions. [2022-11-16 12:17:00,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18761 to 11243. [2022-11-16 12:17:00,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11243 states, 11243 states have (on average 1.4069198612469982) internal successors, (15818), 11242 states have internal predecessors, (15818), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:00,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11243 states to 11243 states and 15818 transitions. [2022-11-16 12:17:00,351 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11243 states and 15818 transitions. [2022-11-16 12:17:00,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:17:00,353 INFO L428 stractBuchiCegarLoop]: Abstraction has 11243 states and 15818 transitions. [2022-11-16 12:17:00,353 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 12:17:00,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11243 states and 15818 transitions. [2022-11-16 12:17:00,486 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11107 [2022-11-16 12:17:00,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:00,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:00,488 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:00,488 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:00,488 INFO L748 eck$LassoCheckResult]: Stem: 174869#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 174826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 174814#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174811#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 174691#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 174692#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 174477#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 174478#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 174809#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174810#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 174770#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 174452#L586 assume !(0 == ~M_E~0); 174453#L586-2 assume !(0 == ~T1_E~0); 174505#L591-1 assume !(0 == ~T2_E~0); 174635#L596-1 assume !(0 == ~T3_E~0); 174636#L601-1 assume !(0 == ~T4_E~0); 174680#L606-1 assume !(0 == ~T5_E~0); 174681#L611-1 assume !(0 == ~E_1~0); 174779#L616-1 assume !(0 == ~E_2~0); 174780#L621-1 assume !(0 == ~E_3~0); 174380#L626-1 assume !(0 == ~E_4~0); 174381#L631-1 assume !(0 == ~E_5~0); 174537#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174378#L279 assume !(1 == ~m_pc~0); 174379#L279-2 is_master_triggered_~__retres1~0#1 := 0; 174705#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174608#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 174609#L720 assume !(0 != activate_threads_~tmp~1#1); 174704#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174543#L298 assume !(1 == ~t1_pc~0); 174336#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 174337#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174599#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 174389#L728 assume !(0 != activate_threads_~tmp___0~0#1); 174390#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174510#L317 assume !(1 == ~t2_pc~0); 174511#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 174722#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174822#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 174559#L736 assume !(0 != activate_threads_~tmp___1~0#1); 174560#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174766#L336 assume !(1 == ~t3_pc~0); 174767#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 174849#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174663#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174664#L744 assume !(0 != activate_threads_~tmp___2~0#1); 174714#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174776#L355 assume !(1 == ~t4_pc~0); 174634#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 174773#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 174878#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174758#L752 assume !(0 != activate_threads_~tmp___3~0#1); 174402#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174403#L374 assume !(1 == ~t5_pc~0); 174531#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 174532#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174606#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 174607#L760 assume !(0 != activate_threads_~tmp___4~0#1); 174666#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174667#L649 assume !(1 == ~M_E~0); 174838#L649-2 assume !(1 == ~T1_E~0); 174365#L654-1 assume !(1 == ~T2_E~0); 174366#L659-1 assume !(1 == ~T3_E~0); 174552#L664-1 assume !(1 == ~T4_E~0); 174358#L669-1 assume !(1 == ~T5_E~0); 174359#L674-1 assume !(1 == ~E_1~0); 174759#L679-1 assume !(1 == ~E_2~0); 174454#L684-1 assume !(1 == ~E_3~0); 174455#L689-1 assume !(1 == ~E_4~0); 174627#L694-1 assume !(1 == ~E_5~0); 174625#L699-1 assume { :end_inline_reset_delta_events } true; 174626#L900-2 [2022-11-16 12:17:00,489 INFO L750 eck$LassoCheckResult]: Loop: 174626#L900-2 assume !false; 177837#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 177649#L561 assume !false; 177818#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 177819#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 177787#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 177788#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 177728#L486 assume !(0 != eval_~tmp~0#1); 177730#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 179633#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 179634#L586-3 assume !(0 == ~M_E~0); 179124#L586-5 assume !(0 == ~T1_E~0); 179125#L591-3 assume !(0 == ~T2_E~0); 178187#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 178188#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 178175#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 178176#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 178167#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 178168#L621-3 assume !(0 == ~E_3~0); 178161#L626-3 assume !(0 == ~E_4~0); 178162#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 178155#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 178156#L279-18 assume !(1 == ~m_pc~0); 178149#L279-20 is_master_triggered_~__retres1~0#1 := 0; 178150#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178143#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 178144#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 178137#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 178138#L298-18 assume !(1 == ~t1_pc~0); 178130#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 178129#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 178122#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 178123#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 178116#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 178117#L317-18 assume !(1 == ~t2_pc~0); 178110#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 178111#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178104#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 178105#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 178097#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 178098#L336-18 assume !(1 == ~t3_pc~0); 178092#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 178093#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 178086#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 178087#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 178080#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 178081#L355-18 assume !(1 == ~t4_pc~0); 178070#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 178071#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 178064#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 178065#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 178057#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 178058#L374-18 assume !(1 == ~t5_pc~0); 178051#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 178052#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 178008#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 178009#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 177992#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 177993#L649-3 assume !(1 == ~M_E~0); 177971#L649-5 assume !(1 == ~T1_E~0); 177972#L654-3 assume !(1 == ~T2_E~0); 177951#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 177952#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 177933#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 177934#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 177916#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 177917#L684-3 assume !(1 == ~E_3~0); 177902#L689-3 assume !(1 == ~E_4~0); 177903#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 177888#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 177889#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 181287#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 181286#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 181285#L919 assume !(0 == start_simulation_~tmp~3#1); 177867#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 177863#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 177856#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 177853#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 177854#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 177847#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 177845#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 177843#L932 assume !(0 != start_simulation_~tmp___0~1#1); 174626#L900-2 [2022-11-16 12:17:00,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:00,490 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times [2022-11-16 12:17:00,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:00,490 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487779632] [2022-11-16 12:17:00,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:00,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:00,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:00,505 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:00,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:00,566 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:00,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:00,569 INFO L85 PathProgramCache]: Analyzing trace with hash -260096805, now seen corresponding path program 1 times [2022-11-16 12:17:00,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:00,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477917433] [2022-11-16 12:17:00,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:00,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:00,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:17:00,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:17:00,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:17:00,645 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [477917433] [2022-11-16 12:17:00,645 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [477917433] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:17:00,645 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:17:00,646 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:17:00,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352253105] [2022-11-16 12:17:00,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:17:00,647 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:17:00,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:17:00,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:17:00,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:17:00,648 INFO L87 Difference]: Start difference. First operand 11243 states and 15818 transitions. cyclomatic complexity: 4583 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:00,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:17:00,846 INFO L93 Difference]: Finished difference Result 19724 states and 27311 transitions. [2022-11-16 12:17:00,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19724 states and 27311 transitions. [2022-11-16 12:17:00,934 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19528 [2022-11-16 12:17:00,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19724 states to 19724 states and 27311 transitions. [2022-11-16 12:17:00,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19724 [2022-11-16 12:17:01,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19724 [2022-11-16 12:17:01,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19724 states and 27311 transitions. [2022-11-16 12:17:01,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:01,028 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19724 states and 27311 transitions. [2022-11-16 12:17:01,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19724 states and 27311 transitions. [2022-11-16 12:17:01,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19724 to 11351. [2022-11-16 12:17:01,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11351 states, 11351 states have (on average 1.4030481895868205) internal successors, (15926), 11350 states have internal predecessors, (15926), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:01,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11351 states to 11351 states and 15926 transitions. [2022-11-16 12:17:01,398 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11351 states and 15926 transitions. [2022-11-16 12:17:01,398 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 12:17:01,399 INFO L428 stractBuchiCegarLoop]: Abstraction has 11351 states and 15926 transitions. [2022-11-16 12:17:01,400 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 12:17:01,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11351 states and 15926 transitions. [2022-11-16 12:17:01,437 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11215 [2022-11-16 12:17:01,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:01,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:01,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:01,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:01,441 INFO L748 eck$LassoCheckResult]: Stem: 205892#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 205839#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 205823#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 205820#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 205697#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 205698#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 205462#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 205463#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 205818#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 205819#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 205779#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 205435#L586 assume !(0 == ~M_E~0); 205436#L586-2 assume !(0 == ~T1_E~0); 205491#L591-1 assume !(0 == ~T2_E~0); 205630#L596-1 assume !(0 == ~T3_E~0); 205631#L601-1 assume !(0 == ~T4_E~0); 205686#L606-1 assume !(0 == ~T5_E~0); 205687#L611-1 assume !(0 == ~E_1~0); 205787#L616-1 assume !(0 == ~E_2~0); 205788#L621-1 assume !(0 == ~E_3~0); 205363#L626-1 assume !(0 == ~E_4~0); 205364#L631-1 assume !(0 == ~E_5~0); 205526#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 205361#L279 assume !(1 == ~m_pc~0); 205362#L279-2 is_master_triggered_~__retres1~0#1 := 0; 205710#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 205605#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 205606#L720 assume !(0 != activate_threads_~tmp~1#1); 205709#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205530#L298 assume !(1 == ~t1_pc~0); 205318#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 205319#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 205594#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 205372#L728 assume !(0 != activate_threads_~tmp___0~0#1); 205373#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 205497#L317 assume !(1 == ~t2_pc~0); 205498#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 205727#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 205834#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 205545#L736 assume !(0 != activate_threads_~tmp___1~0#1); 205546#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 205775#L336 assume !(1 == ~t3_pc~0); 205776#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 205869#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 205665#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 205666#L744 assume !(0 != activate_threads_~tmp___2~0#1); 205718#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 205785#L355 assume !(1 == ~t4_pc~0); 205629#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 205782#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 205897#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 205769#L752 assume !(0 != activate_threads_~tmp___3~0#1); 205388#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 205389#L374 assume !(1 == ~t5_pc~0); 205520#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 205521#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 205603#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 205604#L760 assume !(0 != activate_threads_~tmp___4~0#1); 205670#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 205671#L649 assume !(1 == ~M_E~0); 205858#L649-2 assume !(1 == ~T1_E~0); 205347#L654-1 assume !(1 == ~T2_E~0); 205348#L659-1 assume !(1 == ~T3_E~0); 205538#L664-1 assume !(1 == ~T4_E~0); 205340#L669-1 assume !(1 == ~T5_E~0); 205341#L674-1 assume !(1 == ~E_1~0); 205770#L679-1 assume !(1 == ~E_2~0); 205437#L684-1 assume !(1 == ~E_3~0); 205438#L689-1 assume !(1 == ~E_4~0); 205623#L694-1 assume !(1 == ~E_5~0); 205621#L699-1 assume { :end_inline_reset_delta_events } true; 205622#L900-2 [2022-11-16 12:17:01,441 INFO L750 eck$LassoCheckResult]: Loop: 205622#L900-2 assume !false; 215067#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 215064#L561 assume !false; 215063#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 215061#L439 assume !(0 == ~m_st~0); 215062#L443 assume !(0 == ~t1_st~0); 215058#L447 assume !(0 == ~t2_st~0); 215059#L451 assume !(0 == ~t3_st~0); 215060#L455 assume !(0 == ~t4_st~0); 215056#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 215057#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 214083#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 214084#L486 assume !(0 != eval_~tmp~0#1); 215250#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 215248#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 215246#L586-3 assume !(0 == ~M_E~0); 215244#L586-5 assume !(0 == ~T1_E~0); 215242#L591-3 assume !(0 == ~T2_E~0); 215240#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 215238#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 215236#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 215234#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 215232#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 215230#L621-3 assume !(0 == ~E_3~0); 215228#L626-3 assume !(0 == ~E_4~0); 215226#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 215224#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 215222#L279-18 assume !(1 == ~m_pc~0); 215220#L279-20 is_master_triggered_~__retres1~0#1 := 0; 215218#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 215216#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 215214#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 215212#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215210#L298-18 assume 1 == ~t1_pc~0; 215207#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 215204#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215202#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 215200#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 215198#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 215196#L317-18 assume !(1 == ~t2_pc~0); 215194#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 215192#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215190#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 215188#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 215186#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 215184#L336-18 assume !(1 == ~t3_pc~0); 215182#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 215180#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 215178#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 215176#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 215174#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 215172#L355-18 assume !(1 == ~t4_pc~0); 215170#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 215166#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215162#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 215158#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 215154#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215152#L374-18 assume !(1 == ~t5_pc~0); 215150#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 215148#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 215146#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 215144#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 215142#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215140#L649-3 assume !(1 == ~M_E~0); 215137#L649-5 assume !(1 == ~T1_E~0); 215136#L654-3 assume !(1 == ~T2_E~0); 215135#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 215134#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 215133#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 215132#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 215131#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 215130#L684-3 assume !(1 == ~E_3~0); 215129#L689-3 assume !(1 == ~E_4~0); 215128#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 215127#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 215126#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 215117#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 215113#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 215109#L919 assume !(0 == start_simulation_~tmp~3#1); 215107#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 215105#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 215099#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 215097#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 215095#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 215093#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 215091#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 215087#L932 assume !(0 != start_simulation_~tmp___0~1#1); 205622#L900-2 [2022-11-16 12:17:01,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:01,442 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times [2022-11-16 12:17:01,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:01,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963366516] [2022-11-16 12:17:01,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:01,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:01,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:01,461 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:01,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:01,506 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:01,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:01,508 INFO L85 PathProgramCache]: Analyzing trace with hash 1042126395, now seen corresponding path program 1 times [2022-11-16 12:17:01,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:01,508 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120930704] [2022-11-16 12:17:01,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:01,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:01,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:17:01,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:17:01,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:17:01,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120930704] [2022-11-16 12:17:01,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1120930704] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:17:01,652 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:17:01,652 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:17:01,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686773789] [2022-11-16 12:17:01,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:17:01,653 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:17:01,653 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:17:01,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:17:01,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:17:01,654 INFO L87 Difference]: Start difference. First operand 11351 states and 15926 transitions. cyclomatic complexity: 4583 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:02,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:17:02,099 INFO L93 Difference]: Finished difference Result 18911 states and 26663 transitions. [2022-11-16 12:17:02,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18911 states and 26663 transitions. [2022-11-16 12:17:02,179 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 18775 [2022-11-16 12:17:02,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18911 states to 18911 states and 26663 transitions. [2022-11-16 12:17:02,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18911 [2022-11-16 12:17:02,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18911 [2022-11-16 12:17:02,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18911 states and 26663 transitions. [2022-11-16 12:17:02,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:02,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18911 states and 26663 transitions. [2022-11-16 12:17:02,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18911 states and 26663 transitions. [2022-11-16 12:17:02,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18911 to 11495. [2022-11-16 12:17:02,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11495 states, 11495 states have (on average 1.3876468029578077) internal successors, (15951), 11494 states have internal predecessors, (15951), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:02,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11495 states to 11495 states and 15951 transitions. [2022-11-16 12:17:02,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11495 states and 15951 transitions. [2022-11-16 12:17:02,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 12:17:02,456 INFO L428 stractBuchiCegarLoop]: Abstraction has 11495 states and 15951 transitions. [2022-11-16 12:17:02,456 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 12:17:02,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11495 states and 15951 transitions. [2022-11-16 12:17:02,618 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11359 [2022-11-16 12:17:02,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:02,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:02,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:02,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:02,621 INFO L748 eck$LassoCheckResult]: Stem: 236133#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 236082#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 236069#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 236066#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 235953#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 235954#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 235734#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 235735#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 236064#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 236065#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 236028#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 235708#L586 assume !(0 == ~M_E~0); 235709#L586-2 assume !(0 == ~T1_E~0); 235760#L591-1 assume !(0 == ~T2_E~0); 235892#L596-1 assume !(0 == ~T3_E~0); 235893#L601-1 assume !(0 == ~T4_E~0); 235941#L606-1 assume !(0 == ~T5_E~0); 235942#L611-1 assume !(0 == ~E_1~0); 236037#L616-1 assume !(0 == ~E_2~0); 236038#L621-1 assume !(0 == ~E_3~0); 235638#L626-1 assume !(0 == ~E_4~0); 235639#L631-1 assume !(0 == ~E_5~0); 235796#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 235634#L279 assume !(1 == ~m_pc~0); 235635#L279-2 is_master_triggered_~__retres1~0#1 := 0; 235964#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 235868#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 235869#L720 assume !(0 != activate_threads_~tmp~1#1); 235963#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 235802#L298 assume !(1 == ~t1_pc~0); 235591#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 235592#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 235859#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 235647#L728 assume !(0 != activate_threads_~tmp___0~0#1); 235648#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 235766#L317 assume !(1 == ~t2_pc~0); 235767#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 235984#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 236076#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 235818#L736 assume !(0 != activate_threads_~tmp___1~0#1); 235819#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 236025#L336 assume !(1 == ~t3_pc~0); 236026#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 236105#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 235921#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 235922#L744 assume !(0 != activate_threads_~tmp___2~0#1); 235973#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 236033#L355 assume !(1 == ~t4_pc~0); 235891#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 236030#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 236141#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 236019#L752 assume !(0 != activate_threads_~tmp___3~0#1); 235660#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 235661#L374 assume !(1 == ~t5_pc~0); 235788#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 235789#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 235866#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 235867#L760 assume !(0 != activate_threads_~tmp___4~0#1); 235924#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 235925#L649 assume !(1 == ~M_E~0); 236097#L649-2 assume !(1 == ~T1_E~0); 235623#L654-1 assume !(1 == ~T2_E~0); 235624#L659-1 assume !(1 == ~T3_E~0); 235811#L664-1 assume !(1 == ~T4_E~0); 235616#L669-1 assume !(1 == ~T5_E~0); 235617#L674-1 assume !(1 == ~E_1~0); 236021#L679-1 assume !(1 == ~E_2~0); 235710#L684-1 assume !(1 == ~E_3~0); 235711#L689-1 assume !(1 == ~E_4~0); 235886#L694-1 assume !(1 == ~E_5~0); 235884#L699-1 assume { :end_inline_reset_delta_events } true; 235885#L900-2 [2022-11-16 12:17:02,622 INFO L750 eck$LassoCheckResult]: Loop: 235885#L900-2 assume !false; 238954#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 238953#L561 assume !false; 238952#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 238951#L439 assume !(0 == ~m_st~0); 238950#L443 assume !(0 == ~t1_st~0); 238949#L447 assume !(0 == ~t2_st~0); 238948#L451 assume !(0 == ~t3_st~0); 238947#L455 assume !(0 == ~t4_st~0); 238946#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 238945#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 238944#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 238647#L486 assume !(0 != eval_~tmp~0#1); 238644#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 238645#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 238636#L586-3 assume !(0 == ~M_E~0); 238637#L586-5 assume !(0 == ~T1_E~0); 238628#L591-3 assume !(0 == ~T2_E~0); 238629#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 238622#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 238623#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 238618#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 238619#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 238610#L621-3 assume !(0 == ~E_3~0); 238611#L626-3 assume !(0 == ~E_4~0); 238602#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 238603#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 238594#L279-18 assume !(1 == ~m_pc~0); 238595#L279-20 is_master_triggered_~__retres1~0#1 := 0; 238586#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 238587#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 238578#L720-18 assume !(0 != activate_threads_~tmp~1#1); 238579#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 238569#L298-18 assume !(1 == ~t1_pc~0); 238571#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 238560#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 238561#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 238552#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 238553#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238544#L317-18 assume !(1 == ~t2_pc~0); 238545#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 238536#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238537#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 238528#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 238529#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238520#L336-18 assume !(1 == ~t3_pc~0); 238521#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 238511#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 238512#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 238499#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 238500#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 238486#L355-18 assume !(1 == ~t4_pc~0); 238487#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 238472#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 238473#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 238456#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 238455#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 238441#L374-18 assume !(1 == ~t5_pc~0); 238442#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 238429#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 238430#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 238417#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 238418#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 238405#L649-3 assume !(1 == ~M_E~0); 238406#L649-5 assume !(1 == ~T1_E~0); 238387#L654-3 assume !(1 == ~T2_E~0); 238388#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 238371#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 238372#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 238355#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 238356#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 238337#L684-3 assume !(1 == ~E_3~0); 238338#L689-3 assume !(1 == ~E_4~0); 238314#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 238315#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 238258#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 238248#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 238095#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 238090#L919 assume !(0 == start_simulation_~tmp~3#1); 238091#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 238692#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 238687#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 238686#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 238684#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 238681#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 238679#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 238676#L932 assume !(0 != start_simulation_~tmp___0~1#1); 235885#L900-2 [2022-11-16 12:17:02,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:02,624 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times [2022-11-16 12:17:02,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:02,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426949059] [2022-11-16 12:17:02,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:02,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:02,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:02,643 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:02,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:02,674 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:02,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:02,676 INFO L85 PathProgramCache]: Analyzing trace with hash 1185602392, now seen corresponding path program 1 times [2022-11-16 12:17:02,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:02,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243460243] [2022-11-16 12:17:02,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:02,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:02,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:17:02,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:17:02,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:17:02,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243460243] [2022-11-16 12:17:02,738 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243460243] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:17:02,738 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:17:02,738 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:17:02,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343772297] [2022-11-16 12:17:02,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:17:02,739 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:17:02,740 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:17:02,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:17:02,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:17:02,741 INFO L87 Difference]: Start difference. First operand 11495 states and 15951 transitions. cyclomatic complexity: 4464 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:02,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:17:02,870 INFO L93 Difference]: Finished difference Result 17280 states and 23623 transitions. [2022-11-16 12:17:02,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17280 states and 23623 transitions. [2022-11-16 12:17:02,965 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 17172 [2022-11-16 12:17:03,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17280 states to 17280 states and 23623 transitions. [2022-11-16 12:17:03,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17280 [2022-11-16 12:17:03,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17280 [2022-11-16 12:17:03,045 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17280 states and 23623 transitions. [2022-11-16 12:17:03,063 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:03,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17280 states and 23623 transitions. [2022-11-16 12:17:03,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17280 states and 23623 transitions. [2022-11-16 12:17:03,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17280 to 16956. [2022-11-16 12:17:03,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16956 states, 16956 states have (on average 1.3686600613352207) internal successors, (23207), 16955 states have internal predecessors, (23207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:03,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16956 states to 16956 states and 23207 transitions. [2022-11-16 12:17:03,368 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16956 states and 23207 transitions. [2022-11-16 12:17:03,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:17:03,369 INFO L428 stractBuchiCegarLoop]: Abstraction has 16956 states and 23207 transitions. [2022-11-16 12:17:03,369 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 12:17:03,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16956 states and 23207 transitions. [2022-11-16 12:17:03,440 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 16848 [2022-11-16 12:17:03,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:03,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:03,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:03,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:03,443 INFO L748 eck$LassoCheckResult]: Stem: 264898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 264860#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 264848#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 264845#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264731#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 264732#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 264518#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 264519#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 264843#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 264844#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 264803#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 264490#L586 assume !(0 == ~M_E~0); 264491#L586-2 assume !(0 == ~T1_E~0); 264545#L591-1 assume !(0 == ~T2_E~0); 264675#L596-1 assume !(0 == ~T3_E~0); 264676#L601-1 assume !(0 == ~T4_E~0); 264721#L606-1 assume !(0 == ~T5_E~0); 264722#L611-1 assume !(0 == ~E_1~0); 264812#L616-1 assume !(0 == ~E_2~0); 264813#L621-1 assume !(0 == ~E_3~0); 264421#L626-1 assume !(0 == ~E_4~0); 264422#L631-1 assume !(0 == ~E_5~0); 264577#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264417#L279 assume !(1 == ~m_pc~0); 264418#L279-2 is_master_triggered_~__retres1~0#1 := 0; 264743#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264650#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 264651#L720 assume !(0 != activate_threads_~tmp~1#1); 264742#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264581#L298 assume !(1 == ~t1_pc~0); 264373#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 264374#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264639#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 264430#L728 assume !(0 != activate_threads_~tmp___0~0#1); 264431#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264550#L317 assume !(1 == ~t2_pc~0); 264551#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 264760#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264855#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 264592#L736 assume !(0 != activate_threads_~tmp___1~0#1); 264593#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264801#L336 assume !(1 == ~t3_pc~0); 264802#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264880#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264703#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264704#L744 assume !(0 != activate_threads_~tmp___2~0#1); 264751#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 264808#L355 assume !(1 == ~t4_pc~0); 264672#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 264807#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 264904#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264792#L752 assume !(0 != activate_threads_~tmp___3~0#1); 264444#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 264445#L374 assume !(1 == ~t5_pc~0); 264571#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 264572#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264648#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 264649#L760 assume !(0 != activate_threads_~tmp___4~0#1); 264706#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264707#L649 assume !(1 == ~M_E~0); 264872#L649-2 assume !(1 == ~T1_E~0); 264406#L654-1 assume !(1 == ~T2_E~0); 264407#L659-1 assume !(1 == ~T3_E~0); 264589#L664-1 assume !(1 == ~T4_E~0); 264398#L669-1 assume !(1 == ~T5_E~0); 264399#L674-1 assume !(1 == ~E_1~0); 264794#L679-1 assume !(1 == ~E_2~0); 264494#L684-1 assume !(1 == ~E_3~0); 264495#L689-1 assume !(1 == ~E_4~0); 264668#L694-1 assume !(1 == ~E_5~0); 264666#L699-1 assume { :end_inline_reset_delta_events } true; 264667#L900-2 assume !false; 274032#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 274033#L561 [2022-11-16 12:17:03,443 INFO L750 eck$LassoCheckResult]: Loop: 274033#L561 assume !false; 274202#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 274200#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 274199#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 274198#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 274197#L486 assume 0 != eval_~tmp~0#1; 274195#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 274194#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 274146#L491 assume !(0 == ~t1_st~0); 274143#L505 assume !(0 == ~t2_st~0); 274141#L519 assume !(0 == ~t3_st~0); 274140#L533 assume !(0 == ~t4_st~0); 274205#L547 assume !(0 == ~t5_st~0); 274033#L561 [2022-11-16 12:17:03,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:03,444 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 1 times [2022-11-16 12:17:03,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:03,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588334208] [2022-11-16 12:17:03,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:03,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:03,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:03,461 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:03,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:03,502 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:03,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:03,503 INFO L85 PathProgramCache]: Analyzing trace with hash -519083082, now seen corresponding path program 1 times [2022-11-16 12:17:03,503 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:03,504 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862985225] [2022-11-16 12:17:03,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:03,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:03,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:03,509 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:03,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:03,516 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:03,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:03,517 INFO L85 PathProgramCache]: Analyzing trace with hash -517720007, now seen corresponding path program 1 times [2022-11-16 12:17:03,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:03,517 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152136526] [2022-11-16 12:17:03,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:03,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:03,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:17:03,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:17:03,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:17:03,578 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152136526] [2022-11-16 12:17:03,578 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1152136526] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:17:03,578 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:17:03,578 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:17:03,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957271653] [2022-11-16 12:17:03,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:17:03,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:17:03,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:17:03,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:17:03,740 INFO L87 Difference]: Start difference. First operand 16956 states and 23207 transitions. cyclomatic complexity: 6265 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:03,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:17:03,923 INFO L93 Difference]: Finished difference Result 31200 states and 42157 transitions. [2022-11-16 12:17:03,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31200 states and 42157 transitions. [2022-11-16 12:17:04,100 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 30990 [2022-11-16 12:17:04,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31200 states to 31200 states and 42157 transitions. [2022-11-16 12:17:04,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31200 [2022-11-16 12:17:04,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31200 [2022-11-16 12:17:04,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31200 states and 42157 transitions. [2022-11-16 12:17:04,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:04,459 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31200 states and 42157 transitions. [2022-11-16 12:17:04,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31200 states and 42157 transitions. [2022-11-16 12:17:04,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31200 to 29141. [2022-11-16 12:17:04,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29141 states, 29141 states have (on average 1.3588414948011394) internal successors, (39598), 29140 states have internal predecessors, (39598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:04,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29141 states to 29141 states and 39598 transitions. [2022-11-16 12:17:04,848 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29141 states and 39598 transitions. [2022-11-16 12:17:04,848 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:17:04,850 INFO L428 stractBuchiCegarLoop]: Abstraction has 29141 states and 39598 transitions. [2022-11-16 12:17:04,850 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 12:17:04,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29141 states and 39598 transitions. [2022-11-16 12:17:04,949 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 28931 [2022-11-16 12:17:04,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:04,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:04,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:04,951 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:04,951 INFO L748 eck$LassoCheckResult]: Stem: 313100#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 313053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 313036#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 313033#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 312907#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 312908#L401-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 312687#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 312688#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 313031#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 313032#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 312983#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 312657#L586 assume !(0 == ~M_E~0); 312658#L586-2 assume !(0 == ~T1_E~0); 312715#L591-1 assume !(0 == ~T2_E~0); 312851#L596-1 assume !(0 == ~T3_E~0); 312852#L601-1 assume !(0 == ~T4_E~0); 312896#L606-1 assume !(0 == ~T5_E~0); 312897#L611-1 assume !(0 == ~E_1~0); 312995#L616-1 assume !(0 == ~E_2~0); 312996#L621-1 assume !(0 == ~E_3~0); 312584#L626-1 assume !(0 == ~E_4~0); 312585#L631-1 assume !(0 == ~E_5~0); 312748#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 312580#L279 assume !(1 == ~m_pc~0); 312581#L279-2 is_master_triggered_~__retres1~0#1 := 0; 312919#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 312823#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 312824#L720 assume !(0 != activate_threads_~tmp~1#1); 312918#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 312753#L298 assume !(1 == ~t1_pc~0); 312537#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 312538#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 312812#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 312594#L728 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 312595#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 331144#L317 assume !(1 == ~t2_pc~0); 331143#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 331142#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 331141#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 331140#L736 assume !(0 != activate_threads_~tmp___1~0#1); 331139#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 331138#L336 assume !(1 == ~t3_pc~0); 331137#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 331136#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 331135#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 331134#L744 assume !(0 != activate_threads_~tmp___2~0#1); 331133#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 331132#L355 assume !(1 == ~t4_pc~0); 331131#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 331174#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 331173#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 331126#L752 assume !(0 != activate_threads_~tmp___3~0#1); 331125#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 331124#L374 assume !(1 == ~t5_pc~0); 331123#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 331122#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 331121#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 331120#L760 assume !(0 != activate_threads_~tmp___4~0#1); 331119#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 331118#L649 assume !(1 == ~M_E~0); 331117#L649-2 assume !(1 == ~T1_E~0); 331116#L654-1 assume !(1 == ~T2_E~0); 331115#L659-1 assume !(1 == ~T3_E~0); 331114#L664-1 assume !(1 == ~T4_E~0); 312561#L669-1 assume !(1 == ~T5_E~0); 312562#L674-1 assume !(1 == ~E_1~0); 312976#L679-1 assume !(1 == ~E_2~0); 312987#L684-1 assume !(1 == ~E_3~0); 331107#L689-1 assume !(1 == ~E_4~0); 331104#L694-1 assume !(1 == ~E_5~0); 312843#L699-1 assume { :end_inline_reset_delta_events } true; 312844#L900-2 assume !false; 330879#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 330878#L561 [2022-11-16 12:17:04,951 INFO L750 eck$LassoCheckResult]: Loop: 330878#L561 assume !false; 330876#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 330719#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 330716#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 330717#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 330903#L486 assume 0 != eval_~tmp~0#1; 330901#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 330898#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 330896#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 324835#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 330892#L505 assume !(0 == ~t2_st~0); 330889#L519 assume !(0 == ~t3_st~0); 330883#L533 assume !(0 == ~t4_st~0); 330882#L547 assume !(0 == ~t5_st~0); 330878#L561 [2022-11-16 12:17:04,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:04,952 INFO L85 PathProgramCache]: Analyzing trace with hash -632671842, now seen corresponding path program 1 times [2022-11-16 12:17:04,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:04,952 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008178654] [2022-11-16 12:17:04,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:04,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:04,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:17:04,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:17:04,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:17:04,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1008178654] [2022-11-16 12:17:04,987 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1008178654] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:17:04,987 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:17:04,987 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:17:04,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [252100235] [2022-11-16 12:17:04,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:17:04,988 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:17:04,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:04,989 INFO L85 PathProgramCache]: Analyzing trace with hash 140407213, now seen corresponding path program 1 times [2022-11-16 12:17:04,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:04,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715826075] [2022-11-16 12:17:04,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:04,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:04,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:04,994 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:04,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:04,998 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:05,165 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:17:05,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:17:05,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:17:05,166 INFO L87 Difference]: Start difference. First operand 29141 states and 39598 transitions. cyclomatic complexity: 10471 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:05,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:17:05,264 INFO L93 Difference]: Finished difference Result 29069 states and 39500 transitions. [2022-11-16 12:17:05,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29069 states and 39500 transitions. [2022-11-16 12:17:05,406 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 28931 [2022-11-16 12:17:05,859 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29069 states to 29069 states and 39500 transitions. [2022-11-16 12:17:05,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29069 [2022-11-16 12:17:05,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29069 [2022-11-16 12:17:05,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29069 states and 39500 transitions. [2022-11-16 12:17:05,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:05,903 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29069 states and 39500 transitions. [2022-11-16 12:17:05,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29069 states and 39500 transitions. [2022-11-16 12:17:06,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29069 to 29069. [2022-11-16 12:17:06,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29069 states, 29069 states have (on average 1.3588358732670542) internal successors, (39500), 29068 states have internal predecessors, (39500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:06,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29069 states to 29069 states and 39500 transitions. [2022-11-16 12:17:06,286 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29069 states and 39500 transitions. [2022-11-16 12:17:06,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:17:06,287 INFO L428 stractBuchiCegarLoop]: Abstraction has 29069 states and 39500 transitions. [2022-11-16 12:17:06,287 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 12:17:06,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29069 states and 39500 transitions. [2022-11-16 12:17:06,385 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 28931 [2022-11-16 12:17:06,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:06,385 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:06,386 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:06,386 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:06,387 INFO L748 eck$LassoCheckResult]: Stem: 371288#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 371248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 371232#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 371229#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 371112#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 371113#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 370899#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 370900#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 371227#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 371228#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 371188#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 370870#L586 assume !(0 == ~M_E~0); 370871#L586-2 assume !(0 == ~T1_E~0); 370928#L591-1 assume !(0 == ~T2_E~0); 371055#L596-1 assume !(0 == ~T3_E~0); 371056#L601-1 assume !(0 == ~T4_E~0); 371101#L606-1 assume !(0 == ~T5_E~0); 371102#L611-1 assume !(0 == ~E_1~0); 371199#L616-1 assume !(0 == ~E_2~0); 371200#L621-1 assume !(0 == ~E_3~0); 370799#L626-1 assume !(0 == ~E_4~0); 370800#L631-1 assume !(0 == ~E_5~0); 370962#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 370795#L279 assume !(1 == ~m_pc~0); 370796#L279-2 is_master_triggered_~__retres1~0#1 := 0; 371124#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 371032#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 371033#L720 assume !(0 != activate_threads_~tmp~1#1); 371123#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 370966#L298 assume !(1 == ~t1_pc~0); 370753#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 370754#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 371021#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 370809#L728 assume !(0 != activate_threads_~tmp___0~0#1); 370810#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 370934#L317 assume !(1 == ~t2_pc~0); 370935#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 371143#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 371241#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 370976#L736 assume !(0 != activate_threads_~tmp___1~0#1); 370977#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 371185#L336 assume !(1 == ~t3_pc~0); 371186#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 371267#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 371085#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 371086#L744 assume !(0 != activate_threads_~tmp___2~0#1); 371132#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 371194#L355 assume !(1 == ~t4_pc~0); 371052#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 371192#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 371297#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 371178#L752 assume !(0 != activate_threads_~tmp___3~0#1); 370821#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 370822#L374 assume !(1 == ~t5_pc~0); 370952#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 370953#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 371030#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371031#L760 assume !(0 != activate_threads_~tmp___4~0#1); 371088#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 371089#L649 assume !(1 == ~M_E~0); 371259#L649-2 assume !(1 == ~T1_E~0); 370784#L654-1 assume !(1 == ~T2_E~0); 370785#L659-1 assume !(1 == ~T3_E~0); 370975#L664-1 assume !(1 == ~T4_E~0); 370777#L669-1 assume !(1 == ~T5_E~0); 370778#L674-1 assume !(1 == ~E_1~0); 371180#L679-1 assume !(1 == ~E_2~0); 370874#L684-1 assume !(1 == ~E_3~0); 370875#L689-1 assume !(1 == ~E_4~0); 371049#L694-1 assume !(1 == ~E_5~0); 371047#L699-1 assume { :end_inline_reset_delta_events } true; 371048#L900-2 assume !false; 383699#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 383697#L561 [2022-11-16 12:17:06,387 INFO L750 eck$LassoCheckResult]: Loop: 383697#L561 assume !false; 383695#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 383195#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 383196#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 383823#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 383822#L486 assume 0 != eval_~tmp~0#1; 383821#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 383819#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 383818#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 383175#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 383816#L505 assume !(0 == ~t2_st~0); 383813#L519 assume !(0 == ~t3_st~0); 383704#L533 assume !(0 == ~t4_st~0); 383702#L547 assume !(0 == ~t5_st~0); 383697#L561 [2022-11-16 12:17:06,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:06,388 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 2 times [2022-11-16 12:17:06,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:06,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868259829] [2022-11-16 12:17:06,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:06,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:06,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:06,399 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:06,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:06,431 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:06,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:06,433 INFO L85 PathProgramCache]: Analyzing trace with hash 140407213, now seen corresponding path program 2 times [2022-11-16 12:17:06,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:06,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317076061] [2022-11-16 12:17:06,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:06,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:06,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:06,437 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:06,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:06,442 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:06,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:06,443 INFO L85 PathProgramCache]: Analyzing trace with hash 182662538, now seen corresponding path program 1 times [2022-11-16 12:17:06,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:06,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752244729] [2022-11-16 12:17:06,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:06,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:06,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:17:06,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:17:06,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:17:06,491 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752244729] [2022-11-16 12:17:06,491 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752244729] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:17:06,491 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:17:06,491 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:17:06,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8218631] [2022-11-16 12:17:06,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:17:06,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:17:06,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:17:06,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:17:06,670 INFO L87 Difference]: Start difference. First operand 29069 states and 39500 transitions. cyclomatic complexity: 10445 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:06,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:17:06,851 INFO L93 Difference]: Finished difference Result 44714 states and 60345 transitions. [2022-11-16 12:17:06,851 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44714 states and 60345 transitions. [2022-11-16 12:17:07,485 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 44536 [2022-11-16 12:17:07,594 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44714 states to 44714 states and 60345 transitions. [2022-11-16 12:17:07,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44714 [2022-11-16 12:17:07,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44714 [2022-11-16 12:17:07,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44714 states and 60345 transitions. [2022-11-16 12:17:07,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:07,656 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44714 states and 60345 transitions. [2022-11-16 12:17:07,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44714 states and 60345 transitions. [2022-11-16 12:17:08,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44714 to 43532. [2022-11-16 12:17:08,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43532 states, 43532 states have (on average 1.352269594780851) internal successors, (58867), 43531 states have internal predecessors, (58867), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:08,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43532 states to 43532 states and 58867 transitions. [2022-11-16 12:17:08,671 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43532 states and 58867 transitions. [2022-11-16 12:17:08,672 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:17:08,672 INFO L428 stractBuchiCegarLoop]: Abstraction has 43532 states and 58867 transitions. [2022-11-16 12:17:08,673 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 12:17:08,673 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43532 states and 58867 transitions. [2022-11-16 12:17:08,830 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 43354 [2022-11-16 12:17:08,830 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:08,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:08,832 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:08,832 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:08,833 INFO L748 eck$LassoCheckResult]: Stem: 445091#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 445052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 445038#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 445035#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 444904#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 444905#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 444687#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 444688#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 445033#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 445034#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 444982#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 444658#L586 assume !(0 == ~M_E~0); 444659#L586-2 assume !(0 == ~T1_E~0); 444713#L591-1 assume !(0 == ~T2_E~0); 444847#L596-1 assume !(0 == ~T3_E~0); 444848#L601-1 assume !(0 == ~T4_E~0); 444894#L606-1 assume !(0 == ~T5_E~0); 444895#L611-1 assume !(0 == ~E_1~0); 444996#L616-1 assume !(0 == ~E_2~0); 444997#L621-1 assume !(0 == ~E_3~0); 444590#L626-1 assume !(0 == ~E_4~0); 444591#L631-1 assume !(0 == ~E_5~0); 444747#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 444586#L279 assume !(1 == ~m_pc~0); 444587#L279-2 is_master_triggered_~__retres1~0#1 := 0; 444918#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 444824#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 444825#L720 assume !(0 != activate_threads_~tmp~1#1); 444917#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 444754#L298 assume !(1 == ~t1_pc~0); 444544#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 444545#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 444813#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 444600#L728 assume !(0 != activate_threads_~tmp___0~0#1); 444601#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 444719#L317 assume !(1 == ~t2_pc~0); 444720#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 444937#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 445047#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 444764#L736 assume !(0 != activate_threads_~tmp___1~0#1); 444765#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 444979#L336 assume !(1 == ~t3_pc~0); 444980#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 445076#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 444877#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 444878#L744 assume !(0 != activate_threads_~tmp___2~0#1); 444926#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 444988#L355 assume !(1 == ~t4_pc~0); 444844#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 444986#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 445101#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 444970#L752 assume !(0 != activate_threads_~tmp___3~0#1); 444610#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 444611#L374 assume !(1 == ~t5_pc~0); 444736#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 444737#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 444822#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 444823#L760 assume !(0 != activate_threads_~tmp___4~0#1); 444880#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 444881#L649 assume !(1 == ~M_E~0); 445069#L649-2 assume !(1 == ~T1_E~0); 444575#L654-1 assume !(1 == ~T2_E~0); 444576#L659-1 assume !(1 == ~T3_E~0); 444763#L664-1 assume !(1 == ~T4_E~0); 444568#L669-1 assume !(1 == ~T5_E~0); 444569#L674-1 assume !(1 == ~E_1~0); 444972#L679-1 assume !(1 == ~E_2~0); 444662#L684-1 assume !(1 == ~E_3~0); 444663#L689-1 assume !(1 == ~E_4~0); 444841#L694-1 assume !(1 == ~E_5~0); 444839#L699-1 assume { :end_inline_reset_delta_events } true; 444840#L900-2 assume !false; 450651#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 450649#L561 [2022-11-16 12:17:08,833 INFO L750 eck$LassoCheckResult]: Loop: 450649#L561 assume !false; 450646#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 450643#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 450641#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 450639#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 450637#L486 assume 0 != eval_~tmp~0#1; 450634#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 450631#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 450597#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 450594#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 450592#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 450588#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 450589#L519 assume !(0 == ~t3_st~0); 451416#L533 assume !(0 == ~t4_st~0); 450654#L547 assume !(0 == ~t5_st~0); 450649#L561 [2022-11-16 12:17:08,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:08,834 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 3 times [2022-11-16 12:17:08,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:08,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570422397] [2022-11-16 12:17:08,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:08,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:08,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:08,851 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:08,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:08,883 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:08,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:08,884 INFO L85 PathProgramCache]: Analyzing trace with hash -111462417, now seen corresponding path program 1 times [2022-11-16 12:17:08,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:08,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918607005] [2022-11-16 12:17:08,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:08,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:08,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:08,895 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:08,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:08,900 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:08,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:08,901 INFO L85 PathProgramCache]: Analyzing trace with hash 1198452658, now seen corresponding path program 1 times [2022-11-16 12:17:08,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:08,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616157276] [2022-11-16 12:17:08,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:08,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:08,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:17:08,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:17:08,956 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:17:08,956 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616157276] [2022-11-16 12:17:08,956 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616157276] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:17:08,956 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:17:08,957 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:17:08,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437899224] [2022-11-16 12:17:08,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:17:09,154 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:17:09,155 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:17:09,155 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:17:09,155 INFO L87 Difference]: Start difference. First operand 43532 states and 58867 transitions. cyclomatic complexity: 15349 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:09,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:17:09,499 INFO L93 Difference]: Finished difference Result 68938 states and 92965 transitions. [2022-11-16 12:17:09,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68938 states and 92965 transitions. [2022-11-16 12:17:09,888 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 68720 [2022-11-16 12:17:10,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68938 states to 68938 states and 92965 transitions. [2022-11-16 12:17:10,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68938 [2022-11-16 12:17:10,179 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68938 [2022-11-16 12:17:10,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68938 states and 92965 transitions. [2022-11-16 12:17:10,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:10,245 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68938 states and 92965 transitions. [2022-11-16 12:17:10,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68938 states and 92965 transitions. [2022-11-16 12:17:11,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68938 to 67462. [2022-11-16 12:17:11,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67462 states, 67462 states have (on average 1.3508197207316712) internal successors, (91129), 67461 states have internal predecessors, (91129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:11,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67462 states to 67462 states and 91129 transitions. [2022-11-16 12:17:11,694 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67462 states and 91129 transitions. [2022-11-16 12:17:11,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:17:11,695 INFO L428 stractBuchiCegarLoop]: Abstraction has 67462 states and 91129 transitions. [2022-11-16 12:17:11,695 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-16 12:17:11,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67462 states and 91129 transitions. [2022-11-16 12:17:11,926 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 67244 [2022-11-16 12:17:11,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:11,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:11,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:11,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:11,928 INFO L748 eck$LassoCheckResult]: Stem: 557620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 557566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 557543#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 557539#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 557405#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 557406#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 557172#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 557173#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 557537#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 557538#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 557489#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 557141#L586 assume !(0 == ~M_E~0); 557142#L586-2 assume !(0 == ~T1_E~0); 557201#L591-1 assume !(0 == ~T2_E~0); 557345#L596-1 assume !(0 == ~T3_E~0); 557346#L601-1 assume !(0 == ~T4_E~0); 557394#L606-1 assume !(0 == ~T5_E~0); 557395#L611-1 assume !(0 == ~E_1~0); 557502#L616-1 assume !(0 == ~E_2~0); 557503#L621-1 assume !(0 == ~E_3~0); 557068#L626-1 assume !(0 == ~E_4~0); 557069#L631-1 assume !(0 == ~E_5~0); 557236#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 557066#L279 assume !(1 == ~m_pc~0); 557067#L279-2 is_master_triggered_~__retres1~0#1 := 0; 557418#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 557317#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 557318#L720 assume !(0 != activate_threads_~tmp~1#1); 557417#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 557242#L298 assume !(1 == ~t1_pc~0); 557024#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 557025#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 557306#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 557078#L728 assume !(0 != activate_threads_~tmp___0~0#1); 557079#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 557206#L317 assume !(1 == ~t2_pc~0); 557207#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 557436#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 557559#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 557257#L736 assume !(0 != activate_threads_~tmp___1~0#1); 557258#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 557483#L336 assume !(1 == ~t3_pc~0); 557484#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 557592#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 557375#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 557376#L744 assume !(0 != activate_threads_~tmp___2~0#1); 557426#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 557496#L355 assume !(1 == ~t4_pc~0); 557344#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 557493#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 557633#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 557477#L752 assume !(0 != activate_threads_~tmp___3~0#1); 557094#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 557095#L374 assume !(1 == ~t5_pc~0); 557228#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 557229#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 557315#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 557316#L760 assume !(0 != activate_threads_~tmp___4~0#1); 557378#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 557379#L649 assume !(1 == ~M_E~0); 557584#L649-2 assume !(1 == ~T1_E~0); 557053#L654-1 assume !(1 == ~T2_E~0); 557054#L659-1 assume !(1 == ~T3_E~0); 557250#L664-1 assume !(1 == ~T4_E~0); 557046#L669-1 assume !(1 == ~T5_E~0); 557047#L674-1 assume !(1 == ~E_1~0); 557478#L679-1 assume !(1 == ~E_2~0); 557143#L684-1 assume !(1 == ~E_3~0); 557144#L689-1 assume !(1 == ~E_4~0); 557338#L694-1 assume !(1 == ~E_5~0); 557334#L699-1 assume { :end_inline_reset_delta_events } true; 557335#L900-2 assume !false; 616548#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 616546#L561 [2022-11-16 12:17:11,928 INFO L750 eck$LassoCheckResult]: Loop: 616546#L561 assume !false; 616544#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 614031#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 614032#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 619840#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 619839#L486 assume 0 != eval_~tmp~0#1; 619838#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 611205#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 600425#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 600422#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 600415#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 597607#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 597608#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 577449#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 577450#L533 assume !(0 == ~t4_st~0); 616551#L547 assume !(0 == ~t5_st~0); 616546#L561 [2022-11-16 12:17:11,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:11,929 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 4 times [2022-11-16 12:17:11,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:11,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621242567] [2022-11-16 12:17:11,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:11,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:11,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:11,943 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:11,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:11,965 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:11,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:11,966 INFO L85 PathProgramCache]: Analyzing trace with hash 834182516, now seen corresponding path program 1 times [2022-11-16 12:17:11,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:11,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969349467] [2022-11-16 12:17:11,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:11,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:11,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:11,972 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:11,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:11,977 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:11,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:11,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1508123119, now seen corresponding path program 1 times [2022-11-16 12:17:11,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:11,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035229842] [2022-11-16 12:17:11,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:11,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:11,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:17:12,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:17:12,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:17:12,028 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035229842] [2022-11-16 12:17:12,028 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2035229842] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:17:12,028 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:17:12,028 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:17:12,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111275260] [2022-11-16 12:17:12,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:17:12,238 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:17:12,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:17:12,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:17:12,239 INFO L87 Difference]: Start difference. First operand 67462 states and 91129 transitions. cyclomatic complexity: 23681 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:13,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:17:13,173 INFO L93 Difference]: Finished difference Result 117662 states and 158923 transitions. [2022-11-16 12:17:13,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117662 states and 158923 transitions. [2022-11-16 12:17:13,638 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 117304 [2022-11-16 12:17:13,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117662 states to 117662 states and 158923 transitions. [2022-11-16 12:17:13,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117662 [2022-11-16 12:17:13,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117662 [2022-11-16 12:17:13,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117662 states and 158923 transitions. [2022-11-16 12:17:14,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:14,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117662 states and 158923 transitions. [2022-11-16 12:17:14,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117662 states and 158923 transitions. [2022-11-16 12:17:15,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117662 to 114218. [2022-11-16 12:17:15,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 114218 states, 114218 states have (on average 1.3555043863489118) internal successors, (154823), 114217 states have internal predecessors, (154823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:15,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114218 states to 114218 states and 154823 transitions. [2022-11-16 12:17:15,777 INFO L240 hiAutomatonCegarLoop]: Abstraction has 114218 states and 154823 transitions. [2022-11-16 12:17:15,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:17:15,778 INFO L428 stractBuchiCegarLoop]: Abstraction has 114218 states and 154823 transitions. [2022-11-16 12:17:15,778 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-16 12:17:15,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114218 states and 154823 transitions. [2022-11-16 12:17:16,826 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 113860 [2022-11-16 12:17:16,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:16,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:16,828 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:16,828 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:16,829 INFO L748 eck$LassoCheckResult]: Stem: 742730#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 742683#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 742667#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 742664#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 742531#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 742532#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 742303#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 742304#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 742662#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 742663#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 742612#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 742273#L586 assume !(0 == ~M_E~0); 742274#L586-2 assume !(0 == ~T1_E~0); 742330#L591-1 assume !(0 == ~T2_E~0); 742469#L596-1 assume !(0 == ~T3_E~0); 742470#L601-1 assume !(0 == ~T4_E~0); 742518#L606-1 assume !(0 == ~T5_E~0); 742519#L611-1 assume !(0 == ~E_1~0); 742623#L616-1 assume !(0 == ~E_2~0); 742624#L621-1 assume !(0 == ~E_3~0); 742201#L626-1 assume !(0 == ~E_4~0); 742202#L631-1 assume !(0 == ~E_5~0); 742364#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 742197#L279 assume !(1 == ~m_pc~0); 742198#L279-2 is_master_triggered_~__retres1~0#1 := 0; 742544#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 742444#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 742445#L720 assume !(0 != activate_threads_~tmp~1#1); 742543#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 742368#L298 assume !(1 == ~t1_pc~0); 742153#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 742154#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 742433#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 742211#L728 assume !(0 != activate_threads_~tmp___0~0#1); 742212#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 742335#L317 assume !(1 == ~t2_pc~0); 742336#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 742562#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 742677#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 742378#L736 assume !(0 != activate_threads_~tmp___1~0#1); 742379#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 742607#L336 assume !(1 == ~t3_pc~0); 742608#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 742711#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 742501#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 742502#L744 assume !(0 != activate_threads_~tmp___2~0#1); 742552#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 742617#L355 assume !(1 == ~t4_pc~0); 742466#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 742615#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 742738#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 742600#L752 assume !(0 != activate_threads_~tmp___3~0#1); 742224#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 742225#L374 assume !(1 == ~t5_pc~0); 742353#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 742354#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 742442#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 742443#L760 assume !(0 != activate_threads_~tmp___4~0#1); 742504#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 742505#L649 assume !(1 == ~M_E~0); 742703#L649-2 assume !(1 == ~T1_E~0); 742186#L654-1 assume !(1 == ~T2_E~0); 742187#L659-1 assume !(1 == ~T3_E~0); 742377#L664-1 assume !(1 == ~T4_E~0); 742178#L669-1 assume !(1 == ~T5_E~0); 742179#L674-1 assume !(1 == ~E_1~0); 742602#L679-1 assume !(1 == ~E_2~0); 742277#L684-1 assume !(1 == ~E_3~0); 742278#L689-1 assume !(1 == ~E_4~0); 742463#L694-1 assume !(1 == ~E_5~0); 742461#L699-1 assume { :end_inline_reset_delta_events } true; 742462#L900-2 assume !false; 838223#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 838221#L561 [2022-11-16 12:17:16,829 INFO L750 eck$LassoCheckResult]: Loop: 838221#L561 assume !false; 838218#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 838215#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 838213#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 838211#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 838209#L486 assume 0 != eval_~tmp~0#1; 838206#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 838204#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 813468#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 813466#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 813464#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 813461#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 813460#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 813457#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 813458#L533 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 808090#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 831695#L547 assume !(0 == ~t5_st~0); 838221#L561 [2022-11-16 12:17:16,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:16,830 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 5 times [2022-11-16 12:17:16,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:16,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239391649] [2022-11-16 12:17:16,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:16,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:16,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:16,844 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:16,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:16,870 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:16,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:16,871 INFO L85 PathProgramCache]: Analyzing trace with hash 89684008, now seen corresponding path program 1 times [2022-11-16 12:17:16,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:16,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160873809] [2022-11-16 12:17:16,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:16,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:16,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:16,877 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:16,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:16,882 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:16,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:16,883 INFO L85 PathProgramCache]: Analyzing trace with hash 492653355, now seen corresponding path program 1 times [2022-11-16 12:17:16,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:16,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170413698] [2022-11-16 12:17:16,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:16,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:16,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:17:16,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:17:16,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:17:16,943 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170413698] [2022-11-16 12:17:16,943 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170413698] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:17:16,943 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:17:16,943 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:17:16,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237815489] [2022-11-16 12:17:16,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:17:17,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:17:17,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:17:17,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:17:17,203 INFO L87 Difference]: Start difference. First operand 114218 states and 154823 transitions. cyclomatic complexity: 40619 Second operand has 3 states, 2 states have (on average 45.0) internal successors, (90), 3 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:17,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:17:17,741 INFO L93 Difference]: Finished difference Result 132524 states and 179227 transitions. [2022-11-16 12:17:17,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132524 states and 179227 transitions. [2022-11-16 12:17:18,360 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 128762 [2022-11-16 12:17:19,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132524 states to 132524 states and 179227 transitions. [2022-11-16 12:17:19,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 132524 [2022-11-16 12:17:19,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 132524 [2022-11-16 12:17:19,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132524 states and 179227 transitions. [2022-11-16 12:17:19,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:17:19,735 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132524 states and 179227 transitions. [2022-11-16 12:17:19,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132524 states and 179227 transitions. [2022-11-16 12:17:21,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132524 to 132524. [2022-11-16 12:17:21,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132524 states, 132524 states have (on average 1.3524116386465848) internal successors, (179227), 132523 states have internal predecessors, (179227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:17:21,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132524 states to 132524 states and 179227 transitions. [2022-11-16 12:17:21,758 INFO L240 hiAutomatonCegarLoop]: Abstraction has 132524 states and 179227 transitions. [2022-11-16 12:17:21,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:17:21,759 INFO L428 stractBuchiCegarLoop]: Abstraction has 132524 states and 179227 transitions. [2022-11-16 12:17:21,759 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-16 12:17:21,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 132524 states and 179227 transitions. [2022-11-16 12:17:22,125 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 128762 [2022-11-16 12:17:22,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:17:22,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:17:22,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:22,126 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:17:22,127 INFO L748 eck$LassoCheckResult]: Stem: 989470#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~t1_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t1_st~0 := 0;~t3_st~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t2_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2; 989422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 989403#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 989398#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 989273#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 989274#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 989047#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 989048#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 989396#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 989397#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 989352#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 989018#L586 assume !(0 == ~M_E~0); 989019#L586-2 assume !(0 == ~T1_E~0); 989073#L591-1 assume !(0 == ~T2_E~0); 989213#L596-1 assume !(0 == ~T3_E~0); 989214#L601-1 assume !(0 == ~T4_E~0); 989262#L606-1 assume !(0 == ~T5_E~0); 989263#L611-1 assume !(0 == ~E_1~0); 989364#L616-1 assume !(0 == ~E_2~0); 989365#L621-1 assume !(0 == ~E_3~0); 988948#L626-1 assume !(0 == ~E_4~0); 988949#L631-1 assume !(0 == ~E_5~0); 989106#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 988944#L279 assume !(1 == ~m_pc~0); 988945#L279-2 is_master_triggered_~__retres1~0#1 := 0; 989285#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 989185#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 989186#L720 assume !(0 != activate_threads_~tmp~1#1); 989284#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 989113#L298 assume !(1 == ~t1_pc~0); 988902#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 988903#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 989174#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 988958#L728 assume !(0 != activate_threads_~tmp___0~0#1); 988959#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 989078#L317 assume !(1 == ~t2_pc~0); 989079#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 989304#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 989414#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 989124#L736 assume !(0 != activate_threads_~tmp___1~0#1); 989125#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 989349#L336 assume !(1 == ~t3_pc~0); 989350#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 989449#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 989243#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 989244#L744 assume !(0 != activate_threads_~tmp___2~0#1); 989294#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 989358#L355 assume !(1 == ~t4_pc~0); 989210#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 989355#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 989475#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 989342#L752 assume !(0 != activate_threads_~tmp___3~0#1); 988970#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 988971#L374 assume !(1 == ~t5_pc~0); 989096#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 989097#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 989183#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 989184#L760 assume !(0 != activate_threads_~tmp___4~0#1); 989246#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 989247#L649 assume !(1 == ~M_E~0); 989440#L649-2 assume !(1 == ~T1_E~0); 988933#L654-1 assume !(1 == ~T2_E~0); 988934#L659-1 assume !(1 == ~T3_E~0); 989123#L664-1 assume !(1 == ~T4_E~0); 988926#L669-1 assume !(1 == ~T5_E~0); 988927#L674-1 assume !(1 == ~E_1~0); 989344#L679-1 assume !(1 == ~E_2~0); 989022#L684-1 assume !(1 == ~E_3~0); 989023#L689-1 assume !(1 == ~E_4~0); 989205#L694-1 assume !(1 == ~E_5~0); 989203#L699-1 assume { :end_inline_reset_delta_events } true; 989204#L900-2 assume !false; 1109968#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1109967#L561 [2022-11-16 12:17:22,127 INFO L750 eck$LassoCheckResult]: Loop: 1109967#L561 assume !false; 1109966#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1109964#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1109963#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1109962#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1109961#L486 assume 0 != eval_~tmp~0#1; 1109959#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1109958#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1109956#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1109742#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1109955#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1100930#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1080500#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1080488#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1080489#L533 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1109971#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 1109970#L547 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1109969#L564 assume !(0 != eval_~tmp_ndt_6~0#1); 1109967#L561 [2022-11-16 12:17:22,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:22,128 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 6 times [2022-11-16 12:17:22,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:22,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092072103] [2022-11-16 12:17:22,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:22,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:22,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:22,139 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:22,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:22,161 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:22,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:22,162 INFO L85 PathProgramCache]: Analyzing trace with hash -1514762949, now seen corresponding path program 1 times [2022-11-16 12:17:22,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:22,163 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253395703] [2022-11-16 12:17:22,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:22,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:22,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:22,168 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:22,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:22,172 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:22,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:17:22,173 INFO L85 PathProgramCache]: Analyzing trace with hash -1907615080, now seen corresponding path program 1 times [2022-11-16 12:17:22,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:17:22,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424668460] [2022-11-16 12:17:22,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:17:22,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:17:22,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:22,186 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:22,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:22,216 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:17:24,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:24,697 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:17:24,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:17:24,987 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.11 12:17:24 BoogieIcfgContainer [2022-11-16 12:17:24,987 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-16 12:17:24,988 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-16 12:17:24,988 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-16 12:17:24,988 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-16 12:17:24,989 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:16:50" (3/4) ... [2022-11-16 12:17:24,996 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-16 12:17:25,104 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/witness.graphml [2022-11-16 12:17:25,105 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-16 12:17:25,106 INFO L158 Benchmark]: Toolchain (without parser) took 36991.96ms. Allocated memory was 134.2MB in the beginning and 12.9GB in the end (delta: 12.8GB). Free memory was 93.9MB in the beginning and 10.4GB in the end (delta: -10.3GB). Peak memory consumption was 2.5GB. Max. memory is 16.1GB. [2022-11-16 12:17:25,106 INFO L158 Benchmark]: CDTParser took 0.35ms. Allocated memory is still 134.2MB. Free memory is still 110.6MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-16 12:17:25,107 INFO L158 Benchmark]: CACSL2BoogieTranslator took 513.83ms. Allocated memory is still 134.2MB. Free memory was 93.8MB in the beginning and 104.3MB in the end (delta: -10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-16 12:17:25,107 INFO L158 Benchmark]: Boogie Procedure Inliner took 92.24ms. Allocated memory is still 134.2MB. Free memory was 103.6MB in the beginning and 99.5MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-16 12:17:25,108 INFO L158 Benchmark]: Boogie Preprocessor took 149.36ms. Allocated memory is still 134.2MB. Free memory was 99.5MB in the beginning and 94.5MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-16 12:17:25,108 INFO L158 Benchmark]: RCFGBuilder took 1569.94ms. Allocated memory is still 134.2MB. Free memory was 94.5MB in the beginning and 100.7MB in the end (delta: -6.2MB). Peak memory consumption was 56.7MB. Max. memory is 16.1GB. [2022-11-16 12:17:25,109 INFO L158 Benchmark]: BuchiAutomizer took 34542.96ms. Allocated memory was 134.2MB in the beginning and 12.9GB in the end (delta: 12.8GB). Free memory was 100.6MB in the beginning and 10.4GB in the end (delta: -10.3GB). Peak memory consumption was 2.5GB. Max. memory is 16.1GB. [2022-11-16 12:17:25,109 INFO L158 Benchmark]: Witness Printer took 117.01ms. Allocated memory is still 12.9GB. Free memory was 10.4GB in the beginning and 10.4GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-16 12:17:25,112 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.35ms. Allocated memory is still 134.2MB. Free memory is still 110.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 513.83ms. Allocated memory is still 134.2MB. Free memory was 93.8MB in the beginning and 104.3MB in the end (delta: -10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 92.24ms. Allocated memory is still 134.2MB. Free memory was 103.6MB in the beginning and 99.5MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 149.36ms. Allocated memory is still 134.2MB. Free memory was 99.5MB in the beginning and 94.5MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1569.94ms. Allocated memory is still 134.2MB. Free memory was 94.5MB in the beginning and 100.7MB in the end (delta: -6.2MB). Peak memory consumption was 56.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 34542.96ms. Allocated memory was 134.2MB in the beginning and 12.9GB in the end (delta: 12.8GB). Free memory was 100.6MB in the beginning and 10.4GB in the end (delta: -10.3GB). Peak memory consumption was 2.5GB. Max. memory is 16.1GB. * Witness Printer took 117.01ms. Allocated memory is still 12.9GB. Free memory was 10.4GB in the beginning and 10.4GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 132524 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 34.2s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 7.6s. Construction of modules took 0.9s. Büchi inclusion checks took 22.5s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 10.4s AutomataMinimizationTime, 22 MinimizatonAttempts, 58574 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 7.0s Buchi closure took 0.4s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 21710 SdHoareTripleChecker+Valid, 1.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 21710 mSDsluCounter, 33415 SdHoareTripleChecker+Invalid, 1.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 16487 mSDsCounter, 315 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 700 IncrementalHoareTripleChecker+Invalid, 1015 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 315 mSolverCounterUnsat, 16928 mSDtfsCounter, 700 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 481]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L47] int T4_E = 2; [L48] int T5_E = 2; [L31] int m_st ; [L45] int T2_E = 2; [L46] int T3_E = 2; [L44] int T1_E = 2; [L28] int t3_pc = 0; [L30] int t5_pc = 0; [L26] int t1_pc = 0; [L38] int t1_i ; [L43] int M_E = 2; [L37] int m_i ; [L32] int t1_st ; [L34] int t3_st ; [L40] int t3_i ; [L39] int t2_i ; [L42] int t5_i ; [L41] int t4_i ; [L36] int t5_st ; [L29] int t4_pc = 0; [L27] int t2_pc = 0; [L49] int E_1 = 2; [L25] int m_pc = 0; [L33] int t2_st ; [L51] int E_3 = 2; [L50] int E_2 = 2; [L53] int E_5 = 2; [L35] int t4_st ; [L52] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_1)) [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE !(\read(tmp_ndt_2)) [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE !(\read(tmp_ndt_3)) [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE !(\read(tmp_ndt_4)) [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE !(\read(tmp_ndt_5)) [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 481]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L47] int T4_E = 2; [L48] int T5_E = 2; [L31] int m_st ; [L45] int T2_E = 2; [L46] int T3_E = 2; [L44] int T1_E = 2; [L28] int t3_pc = 0; [L30] int t5_pc = 0; [L26] int t1_pc = 0; [L38] int t1_i ; [L43] int M_E = 2; [L37] int m_i ; [L32] int t1_st ; [L34] int t3_st ; [L40] int t3_i ; [L39] int t2_i ; [L42] int t5_i ; [L41] int t4_i ; [L36] int t5_st ; [L29] int t4_pc = 0; [L27] int t2_pc = 0; [L49] int E_1 = 2; [L25] int m_pc = 0; [L33] int t2_st ; [L51] int E_3 = 2; [L50] int E_2 = 2; [L53] int E_5 = 2; [L35] int t4_st ; [L52] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_1)) [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE !(\read(tmp_ndt_2)) [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE !(\read(tmp_ndt_3)) [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE !(\read(tmp_ndt_4)) [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE !(\read(tmp_ndt_5)) [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-16 12:17:25,293 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e8458bf-1926-447d-9081-8b4cfadb3042/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)