./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.08.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.08.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 12:33:58,406 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 12:33:58,408 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 12:33:58,444 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 12:33:58,445 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 12:33:58,449 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 12:33:58,452 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 12:33:58,458 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 12:33:58,463 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 12:33:58,465 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 12:33:58,466 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 12:33:58,467 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 12:33:58,468 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 12:33:58,469 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 12:33:58,470 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 12:33:58,472 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 12:33:58,473 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 12:33:58,474 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 12:33:58,479 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 12:33:58,492 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 12:33:58,494 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 12:33:58,498 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 12:33:58,500 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 12:33:58,501 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 12:33:58,505 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 12:33:58,505 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 12:33:58,506 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 12:33:58,516 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 12:33:58,517 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 12:33:58,518 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 12:33:58,519 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 12:33:58,521 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 12:33:58,523 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 12:33:58,526 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 12:33:58,527 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 12:33:58,527 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 12:33:58,528 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 12:33:58,528 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 12:33:58,529 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 12:33:58,530 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 12:33:58,531 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 12:33:58,532 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 12:33:58,579 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 12:33:58,580 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 12:33:58,580 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 12:33:58,581 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 12:33:58,582 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 12:33:58,582 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 12:33:58,583 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 12:33:58,583 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 12:33:58,583 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 12:33:58,584 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 12:33:58,584 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 12:33:58,584 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 12:33:58,585 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 12:33:58,585 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 12:33:58,585 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 12:33:58,586 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 12:33:58,586 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 12:33:58,586 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 12:33:58,587 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 12:33:58,587 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 12:33:58,587 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 12:33:58,588 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 12:33:58,588 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 12:33:58,588 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 12:33:58,589 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 12:33:58,589 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 12:33:58,589 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 12:33:58,590 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 12:33:58,590 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 12:33:58,591 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 12:33:58,591 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 12:33:58,592 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 12:33:58,593 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 [2022-11-16 12:33:58,999 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 12:33:59,051 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 12:33:59,054 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 12:33:59,056 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 12:33:59,057 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 12:33:59,059 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/transmitter.08.cil.c [2022-11-16 12:33:59,148 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/data/b23e92f40/27c1360f994c4b62bd44fcaac1d16c9b/FLAG76832e588 [2022-11-16 12:33:59,796 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 12:33:59,797 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/sv-benchmarks/c/systemc/transmitter.08.cil.c [2022-11-16 12:33:59,810 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/data/b23e92f40/27c1360f994c4b62bd44fcaac1d16c9b/FLAG76832e588 [2022-11-16 12:34:00,112 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/data/b23e92f40/27c1360f994c4b62bd44fcaac1d16c9b [2022-11-16 12:34:00,115 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 12:34:00,118 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 12:34:00,124 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 12:34:00,125 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 12:34:00,130 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 12:34:00,131 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:00,133 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@686b3c08 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00, skipping insertion in model container [2022-11-16 12:34:00,133 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:00,142 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 12:34:00,214 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 12:34:00,530 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/sv-benchmarks/c/systemc/transmitter.08.cil.c[706,719] [2022-11-16 12:34:00,674 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:34:00,686 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 12:34:00,701 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/sv-benchmarks/c/systemc/transmitter.08.cil.c[706,719] [2022-11-16 12:34:00,768 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:34:00,803 INFO L208 MainTranslator]: Completed translation [2022-11-16 12:34:00,805 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00 WrapperNode [2022-11-16 12:34:00,805 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 12:34:00,806 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 12:34:00,807 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 12:34:00,807 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 12:34:00,816 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:00,830 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:00,968 INFO L138 Inliner]: procedures = 44, calls = 54, calls flagged for inlining = 49, calls inlined = 146, statements flattened = 2198 [2022-11-16 12:34:00,969 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 12:34:00,970 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 12:34:00,970 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 12:34:00,970 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 12:34:00,981 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:00,982 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:00,991 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:00,991 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:01,020 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:01,047 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:01,052 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:01,059 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:01,071 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 12:34:01,072 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 12:34:01,072 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 12:34:01,072 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 12:34:01,074 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (1/1) ... [2022-11-16 12:34:01,091 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 12:34:01,122 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:34:01,160 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 12:34:01,204 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5a587ff8-6e34-43b0-a909-7874831eb764/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 12:34:01,228 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 12:34:01,228 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 12:34:01,228 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 12:34:01,228 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 12:34:01,436 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 12:34:01,439 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 12:34:03,282 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 12:34:03,309 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 12:34:03,311 INFO L300 CfgBuilder]: Removed 12 assume(true) statements. [2022-11-16 12:34:03,344 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:34:03 BoogieIcfgContainer [2022-11-16 12:34:03,344 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 12:34:03,345 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 12:34:03,346 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 12:34:03,353 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 12:34:03,354 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:34:03,354 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 12:34:00" (1/3) ... [2022-11-16 12:34:03,356 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41100658 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:34:03, skipping insertion in model container [2022-11-16 12:34:03,357 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:34:03,357 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:34:00" (2/3) ... [2022-11-16 12:34:03,357 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41100658 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:34:03, skipping insertion in model container [2022-11-16 12:34:03,358 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:34:03,358 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:34:03" (3/3) ... [2022-11-16 12:34:03,359 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.08.cil.c [2022-11-16 12:34:03,471 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 12:34:03,471 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 12:34:03,472 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 12:34:03,472 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 12:34:03,472 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 12:34:03,472 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 12:34:03,472 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 12:34:03,473 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 12:34:03,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:03,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 814 [2022-11-16 12:34:03,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:03,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:03,582 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:03,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:03,583 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 12:34:03,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:03,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 814 [2022-11-16 12:34:03,605 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:03,605 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:03,611 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:03,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:03,622 INFO L748 eck$LassoCheckResult]: Stem: 421#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 840#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 847#L1235true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46#L574true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 670#L581true assume !(1 == ~m_i~0);~m_st~0 := 2; 192#L581-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 807#L586-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 663#L591-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 636#L596-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 231#L601-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 671#L606-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 404#L611-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 751#L616-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 286#L621-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 696#L838true assume !(0 == ~M_E~0); 412#L838-2true assume !(0 == ~T1_E~0); 27#L843-1true assume !(0 == ~T2_E~0); 85#L848-1true assume !(0 == ~T3_E~0); 425#L853-1true assume !(0 == ~T4_E~0); 277#L858-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 2#L863-1true assume !(0 == ~T6_E~0); 744#L868-1true assume !(0 == ~T7_E~0); 863#L873-1true assume !(0 == ~T8_E~0); 739#L878-1true assume !(0 == ~E_1~0); 705#L883-1true assume !(0 == ~E_2~0); 777#L888-1true assume !(0 == ~E_3~0); 382#L893-1true assume !(0 == ~E_4~0); 778#L898-1true assume 0 == ~E_5~0;~E_5~0 := 1; 912#L903-1true assume !(0 == ~E_6~0); 703#L908-1true assume !(0 == ~E_7~0); 495#L913-1true assume !(0 == ~E_8~0); 33#L918-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 512#L402true assume !(1 == ~m_pc~0); 261#L402-2true is_master_triggered_~__retres1~0#1 := 0; 97#L413true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 919#L414true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 235#L1035true assume !(0 != activate_threads_~tmp~1#1); 270#L1035-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692#L421true assume 1 == ~t1_pc~0; 806#L422true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 882#L432true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 263#L433true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 307#L1043true assume !(0 != activate_threads_~tmp___0~0#1); 766#L1043-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 895#L440true assume 1 == ~t2_pc~0; 20#L441true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 102#L451true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 864#L452true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 815#L1051true assume !(0 != activate_threads_~tmp___1~0#1); 514#L1051-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210#L459true assume !(1 == ~t3_pc~0); 685#L459-2true is_transmit3_triggered_~__retres1~3#1 := 0; 762#L470true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 445#L471true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 93#L1059true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 920#L1059-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99#L478true assume 1 == ~t4_pc~0; 386#L479true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 661#L489true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 808#L490true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 195#L1067true assume !(0 != activate_threads_~tmp___3~0#1); 55#L1067-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 422#L497true assume !(1 == ~t5_pc~0); 353#L497-2true is_transmit5_triggered_~__retres1~5#1 := 0; 449#L508true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 244#L509true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 767#L1075true assume !(0 != activate_threads_~tmp___4~0#1); 677#L1075-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 874#L516true assume 1 == ~t6_pc~0; 875#L517true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 403#L527true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 843#L528true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 121#L1083true assume !(0 != activate_threads_~tmp___5~0#1); 461#L1083-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 399#L535true assume !(1 == ~t7_pc~0); 782#L535-2true is_transmit7_triggered_~__retres1~7#1 := 0; 460#L546true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 588#L547true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 488#L1091true assume !(0 != activate_threads_~tmp___6~0#1); 481#L1091-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 672#L554true assume 1 == ~t8_pc~0; 429#L555true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 809#L565true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 534#L566true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 170#L1099true assume !(0 != activate_threads_~tmp___7~0#1); 489#L1099-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8#L931true assume !(1 == ~M_E~0); 725#L931-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 804#L936-1true assume !(1 == ~T2_E~0); 890#L941-1true assume !(1 == ~T3_E~0); 271#L946-1true assume !(1 == ~T4_E~0); 688#L951-1true assume !(1 == ~T5_E~0); 130#L956-1true assume !(1 == ~T6_E~0); 876#L961-1true assume !(1 == ~T7_E~0); 383#L966-1true assume !(1 == ~T8_E~0); 483#L971-1true assume 1 == ~E_1~0;~E_1~0 := 2; 828#L976-1true assume !(1 == ~E_2~0); 454#L981-1true assume !(1 == ~E_3~0); 274#L986-1true assume !(1 == ~E_4~0); 147#L991-1true assume !(1 == ~E_5~0); 853#L996-1true assume !(1 == ~E_6~0); 756#L1001-1true assume !(1 == ~E_7~0); 420#L1006-1true assume !(1 == ~E_8~0); 689#L1011-1true assume { :end_inline_reset_delta_events } true; 38#L1272-2true [2022-11-16 12:34:03,625 INFO L750 eck$LassoCheckResult]: Loop: 38#L1272-2true assume !false; 416#L1273true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39#L813true assume false; 423#L828true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 551#L574-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 641#L838-3true assume !(0 == ~M_E~0); 466#L838-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 788#L843-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 344#L848-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 384#L853-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 570#L858-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 443#L863-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 433#L868-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 452#L873-3true assume !(0 == ~T8_E~0); 159#L878-3true assume 0 == ~E_1~0;~E_1~0 := 1; 21#L883-3true assume 0 == ~E_2~0;~E_2~0 := 1; 656#L888-3true assume 0 == ~E_3~0;~E_3~0 := 1; 22#L893-3true assume 0 == ~E_4~0;~E_4~0 := 1; 288#L898-3true assume 0 == ~E_5~0;~E_5~0 := 1; 591#L903-3true assume 0 == ~E_6~0;~E_6~0 := 1; 776#L908-3true assume 0 == ~E_7~0;~E_7~0 := 1; 296#L913-3true assume !(0 == ~E_8~0); 42#L918-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 884#L402-27true assume 1 == ~m_pc~0; 16#L403-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 834#L413-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 291#L414-9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 731#L1035-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 622#L1035-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 658#L421-27true assume 1 == ~t1_pc~0; 493#L422-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 814#L432-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 317#L433-9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 757#L1043-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 880#L1043-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 400#L440-27true assume !(1 == ~t2_pc~0); 585#L440-29true is_transmit2_triggered_~__retres1~2#1 := 0; 928#L451-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206#L452-9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 324#L1051-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 410#L1051-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149#L459-27true assume 1 == ~t3_pc~0; 457#L460-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 830#L470-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 188#L471-9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 398#L1059-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 742#L1059-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 877#L478-27true assume 1 == ~t4_pc~0; 823#L479-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 405#L489-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 885#L490-9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 540#L1067-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 743#L1067-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 592#L497-27true assume 1 == ~t5_pc~0; 822#L498-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 164#L508-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 340#L509-9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 133#L1075-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 664#L1075-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 292#L516-27true assume !(1 == ~t6_pc~0); 408#L516-29true is_transmit6_triggered_~__retres1~6#1 := 0; 199#L527-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 293#L528-9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 414#L1083-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 754#L1083-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 245#L535-27true assume 1 == ~t7_pc~0; 642#L536-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 925#L546-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 553#L547-9true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 824#L1091-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 219#L1091-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 765#L554-27true assume !(1 == ~t8_pc~0); 29#L554-29true is_transmit8_triggered_~__retres1~8#1 := 0; 101#L565-9true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 308#L566-9true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 328#L1099-27true assume !(0 != activate_threads_~tmp___7~0#1); 157#L1099-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516#L931-3true assume 1 == ~M_E~0;~M_E~0 := 2; 91#L931-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 217#L936-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 303#L941-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 518#L946-3true assume !(1 == ~T4_E~0); 168#L951-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 501#L956-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 363#L961-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 224#L966-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 709#L971-3true assume 1 == ~E_1~0;~E_1~0 := 2; 402#L976-3true assume 1 == ~E_2~0;~E_2~0 := 2; 37#L981-3true assume 1 == ~E_3~0;~E_3~0 := 2; 158#L986-3true assume !(1 == ~E_4~0); 32#L991-3true assume 1 == ~E_5~0;~E_5~0 := 2; 469#L996-3true assume 1 == ~E_6~0;~E_6~0 := 2; 595#L1001-3true assume 1 == ~E_7~0;~E_7~0 := 2; 212#L1006-3true assume 1 == ~E_8~0;~E_8~0 := 2; 503#L1011-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 53#L634-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 306#L681-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 227#L682-1true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 772#L1291true assume !(0 == start_simulation_~tmp~3#1); 740#L1291-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 284#L634-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4#L681-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 563#L682-2true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 713#L1246true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 257#L1253true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 437#L1254true start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 541#L1304true assume !(0 != start_simulation_~tmp___0~1#1); 38#L1272-2true [2022-11-16 12:34:03,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:03,632 INFO L85 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2022-11-16 12:34:03,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:03,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468728432] [2022-11-16 12:34:03,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:03,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:03,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:04,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:04,096 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:04,097 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1468728432] [2022-11-16 12:34:04,098 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1468728432] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:04,098 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:04,098 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:04,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929898182] [2022-11-16 12:34:04,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:04,107 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:04,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:04,108 INFO L85 PathProgramCache]: Analyzing trace with hash 1238630933, now seen corresponding path program 1 times [2022-11-16 12:34:04,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:04,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170917997] [2022-11-16 12:34:04,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:04,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:04,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:04,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:04,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:04,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170917997] [2022-11-16 12:34:04,165 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170917997] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:04,166 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:04,166 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:34:04,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427238372] [2022-11-16 12:34:04,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:04,168 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:04,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:04,207 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:04,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:04,213 INFO L87 Difference]: Start difference. First operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:04,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:04,302 INFO L93 Difference]: Finished difference Result 930 states and 1385 transitions. [2022-11-16 12:34:04,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 930 states and 1385 transitions. [2022-11-16 12:34:04,315 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:04,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 930 states to 924 states and 1379 transitions. [2022-11-16 12:34:04,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-11-16 12:34:04,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-11-16 12:34:04,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1379 transitions. [2022-11-16 12:34:04,339 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:04,339 INFO L218 hiAutomatonCegarLoop]: Abstraction has 924 states and 1379 transitions. [2022-11-16 12:34:04,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1379 transitions. [2022-11-16 12:34:04,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-11-16 12:34:04,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4924242424242424) internal successors, (1379), 923 states have internal predecessors, (1379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:04,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1379 transitions. [2022-11-16 12:34:04,424 INFO L240 hiAutomatonCegarLoop]: Abstraction has 924 states and 1379 transitions. [2022-11-16 12:34:04,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:04,429 INFO L428 stractBuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2022-11-16 12:34:04,430 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 12:34:04,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1379 transitions. [2022-11-16 12:34:04,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:04,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:04,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:04,440 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:04,440 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:04,441 INFO L748 eck$LassoCheckResult]: Stem: 2546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 2547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2789#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1961#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1962#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2233#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2234#L586-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2731#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2721#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2301#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2302#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2526#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2527#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2383#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2384#L838 assume !(0 == ~M_E~0); 2533#L838-2 assume !(0 == ~T1_E~0); 1923#L843-1 assume !(0 == ~T2_E~0); 1924#L848-1 assume !(0 == ~T3_E~0); 2043#L853-1 assume !(0 == ~T4_E~0); 2369#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1870#L863-1 assume !(0 == ~T6_E~0); 1871#L868-1 assume !(0 == ~T7_E~0); 2763#L873-1 assume !(0 == ~T8_E~0); 2761#L878-1 assume !(0 == ~E_1~0); 2750#L883-1 assume !(0 == ~E_2~0); 2751#L888-1 assume !(0 == ~E_3~0); 2498#L893-1 assume !(0 == ~E_4~0); 2499#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2775#L903-1 assume !(0 == ~E_6~0); 2749#L908-1 assume !(0 == ~E_7~0); 2623#L913-1 assume !(0 == ~E_8~0); 1937#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1938#L402 assume !(1 == ~m_pc~0); 2146#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2064#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2065#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2307#L1035 assume !(0 != activate_threads_~tmp~1#1); 2308#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2360#L421 assume 1 == ~t1_pc~0; 2745#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2764#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2352#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2353#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2411#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2772#L440 assume 1 == ~t2_pc~0; 1907#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1908#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2074#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2783#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2637#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2261#L459 assume !(1 == ~t3_pc~0); 2262#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2744#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2568#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2058#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2059#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2068#L478 assume 1 == ~t4_pc~0; 2069#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2503#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2730#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2239#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1982#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1983#L497 assume !(1 == ~t5_pc~0); 2029#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2030#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2321#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2322#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2737#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2738#L516 assume 1 == ~t6_pc~0; 2792#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2524#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2525#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2113#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2114#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2515#L535 assume !(1 == ~t7_pc~0); 2516#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2585#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2586#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2614#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2604#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2605#L554 assume 1 == ~t8_pc~0; 2554#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1899#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2655#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2201#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2202#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1883#L931 assume !(1 == ~M_E~0); 1884#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2758#L936-1 assume !(1 == ~T2_E~0); 2781#L941-1 assume !(1 == ~T3_E~0); 2361#L946-1 assume !(1 == ~T4_E~0); 2362#L951-1 assume !(1 == ~T5_E~0); 2128#L956-1 assume !(1 == ~T6_E~0); 2129#L961-1 assume !(1 == ~T7_E~0); 2500#L966-1 assume !(1 == ~T8_E~0); 2501#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2607#L976-1 assume !(1 == ~E_2~0); 2577#L981-1 assume !(1 == ~E_3~0); 2366#L986-1 assume !(1 == ~E_4~0); 2158#L991-1 assume !(1 == ~E_5~0); 2159#L996-1 assume !(1 == ~E_6~0); 2768#L1001-1 assume !(1 == ~E_7~0); 2544#L1006-1 assume !(1 == ~E_8~0); 2545#L1011-1 assume { :end_inline_reset_delta_events } true; 1946#L1272-2 [2022-11-16 12:34:04,442 INFO L750 eck$LassoCheckResult]: Loop: 1946#L1272-2 assume !false; 1947#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1948#L813 assume !false; 1949#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2695#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1951#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2495#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2505#L696 assume !(0 != eval_~tmp~0#1); 2548#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2549#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2670#L838-3 assume !(0 == ~M_E~0); 2590#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2591#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2453#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2454#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2502#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2565#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2557#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2558#L873-3 assume !(0 == ~T8_E~0); 2181#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1910#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1911#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1912#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1913#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2387#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2696#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2400#L913-3 assume !(0 == ~E_8~0); 1953#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1954#L402-27 assume 1 == ~m_pc~0; 1900#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1901#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2390#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2391#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2709#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2710#L421-27 assume !(1 == ~t1_pc~0); 2173#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2174#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2423#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2424#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2769#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2518#L440-27 assume 1 == ~t2_pc~0; 2519#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2692#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2257#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2258#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2432#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2161#L459-27 assume !(1 == ~t3_pc~0); 2162#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2580#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2225#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2226#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2514#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2762#L478-27 assume 1 == ~t4_pc~0; 2784#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2528#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2660#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2661#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2697#L497-27 assume 1 == ~t5_pc~0; 2698#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2190#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2191#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2134#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2135#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2392#L516-27 assume 1 == ~t6_pc~0; 2393#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2247#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2248#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2395#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2535#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2324#L535-27 assume 1 == ~t7_pc~0; 2325#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2641#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2671#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2672#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2278#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2279#L554-27 assume !(1 == ~t8_pc~0); 1927#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1928#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2073#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2412#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 2178#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2179#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2054#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2055#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2275#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2407#L946-3 assume !(1 == ~T4_E~0); 2196#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2197#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2476#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2285#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2286#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2523#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1944#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1945#L986-3 assume !(1 == ~E_4~0); 1935#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1936#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2595#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2266#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2267#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1977#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1979#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2293#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2294#L1291 assume !(0 == start_simulation_~tmp~3#1); 2473#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2379#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1874#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1875#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2679#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2343#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2344#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2560#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1946#L1272-2 [2022-11-16 12:34:04,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:04,443 INFO L85 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2022-11-16 12:34:04,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:04,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130129619] [2022-11-16 12:34:04,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:04,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:04,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:04,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:04,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:04,600 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130129619] [2022-11-16 12:34:04,600 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130129619] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:04,601 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:04,601 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:04,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436164299] [2022-11-16 12:34:04,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:04,602 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:04,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:04,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1268138686, now seen corresponding path program 1 times [2022-11-16 12:34:04,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:04,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751816026] [2022-11-16 12:34:04,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:04,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:04,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:04,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:04,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:04,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751816026] [2022-11-16 12:34:04,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751816026] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:04,823 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:04,823 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:04,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420965582] [2022-11-16 12:34:04,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:04,824 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:04,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:04,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:04,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:04,826 INFO L87 Difference]: Start difference. First operand 924 states and 1379 transitions. cyclomatic complexity: 456 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:04,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:04,871 INFO L93 Difference]: Finished difference Result 924 states and 1378 transitions. [2022-11-16 12:34:04,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1378 transitions. [2022-11-16 12:34:04,882 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:04,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1378 transitions. [2022-11-16 12:34:04,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-11-16 12:34:04,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-11-16 12:34:04,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1378 transitions. [2022-11-16 12:34:04,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:04,896 INFO L218 hiAutomatonCegarLoop]: Abstraction has 924 states and 1378 transitions. [2022-11-16 12:34:04,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1378 transitions. [2022-11-16 12:34:04,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-11-16 12:34:04,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4913419913419914) internal successors, (1378), 923 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:04,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1378 transitions. [2022-11-16 12:34:04,933 INFO L240 hiAutomatonCegarLoop]: Abstraction has 924 states and 1378 transitions. [2022-11-16 12:34:04,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:04,936 INFO L428 stractBuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2022-11-16 12:34:04,936 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 12:34:04,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1378 transitions. [2022-11-16 12:34:04,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:04,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:04,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:04,957 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:04,957 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:04,959 INFO L748 eck$LassoCheckResult]: Stem: 4401#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 4402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4644#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3816#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3817#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4088#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4089#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4586#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4576#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4156#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4157#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4381#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4382#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4238#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4239#L838 assume !(0 == ~M_E~0); 4388#L838-2 assume !(0 == ~T1_E~0); 3778#L843-1 assume !(0 == ~T2_E~0); 3779#L848-1 assume !(0 == ~T3_E~0); 3898#L853-1 assume !(0 == ~T4_E~0); 4224#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3725#L863-1 assume !(0 == ~T6_E~0); 3726#L868-1 assume !(0 == ~T7_E~0); 4618#L873-1 assume !(0 == ~T8_E~0); 4616#L878-1 assume !(0 == ~E_1~0); 4605#L883-1 assume !(0 == ~E_2~0); 4606#L888-1 assume !(0 == ~E_3~0); 4353#L893-1 assume !(0 == ~E_4~0); 4354#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4630#L903-1 assume !(0 == ~E_6~0); 4604#L908-1 assume !(0 == ~E_7~0); 4478#L913-1 assume !(0 == ~E_8~0); 3792#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3793#L402 assume !(1 == ~m_pc~0); 4001#L402-2 is_master_triggered_~__retres1~0#1 := 0; 3919#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3920#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4162#L1035 assume !(0 != activate_threads_~tmp~1#1); 4163#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4215#L421 assume 1 == ~t1_pc~0; 4600#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4619#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4207#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4208#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4266#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4627#L440 assume 1 == ~t2_pc~0; 3762#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3763#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3929#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4638#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4492#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4116#L459 assume !(1 == ~t3_pc~0); 4117#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4599#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3913#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3914#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3923#L478 assume 1 == ~t4_pc~0; 3924#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4358#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4585#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4094#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 3837#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3838#L497 assume !(1 == ~t5_pc~0); 3884#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3885#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4176#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4177#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4592#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4593#L516 assume 1 == ~t6_pc~0; 4647#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4379#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4380#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3968#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 3969#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4370#L535 assume !(1 == ~t7_pc~0); 4371#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4440#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4441#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4469#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4459#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4460#L554 assume 1 == ~t8_pc~0; 4409#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3754#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4510#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4056#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4057#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3738#L931 assume !(1 == ~M_E~0); 3739#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4613#L936-1 assume !(1 == ~T2_E~0); 4636#L941-1 assume !(1 == ~T3_E~0); 4216#L946-1 assume !(1 == ~T4_E~0); 4217#L951-1 assume !(1 == ~T5_E~0); 3983#L956-1 assume !(1 == ~T6_E~0); 3984#L961-1 assume !(1 == ~T7_E~0); 4355#L966-1 assume !(1 == ~T8_E~0); 4356#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4462#L976-1 assume !(1 == ~E_2~0); 4432#L981-1 assume !(1 == ~E_3~0); 4221#L986-1 assume !(1 == ~E_4~0); 4013#L991-1 assume !(1 == ~E_5~0); 4014#L996-1 assume !(1 == ~E_6~0); 4623#L1001-1 assume !(1 == ~E_7~0); 4399#L1006-1 assume !(1 == ~E_8~0); 4400#L1011-1 assume { :end_inline_reset_delta_events } true; 3801#L1272-2 [2022-11-16 12:34:04,960 INFO L750 eck$LassoCheckResult]: Loop: 3801#L1272-2 assume !false; 3802#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3803#L813 assume !false; 3804#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4550#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3806#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4350#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4360#L696 assume !(0 != eval_~tmp~0#1); 4403#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4404#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4525#L838-3 assume !(0 == ~M_E~0); 4445#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4446#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4308#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4309#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4357#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4420#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4412#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4413#L873-3 assume !(0 == ~T8_E~0); 4036#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3765#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3766#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3767#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3768#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4242#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4551#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4255#L913-3 assume !(0 == ~E_8~0); 3808#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3809#L402-27 assume 1 == ~m_pc~0; 3755#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3756#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4245#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4246#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4564#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4565#L421-27 assume !(1 == ~t1_pc~0); 4028#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4029#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4278#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4279#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4624#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4373#L440-27 assume 1 == ~t2_pc~0; 4374#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4547#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4112#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4113#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4287#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4016#L459-27 assume !(1 == ~t3_pc~0); 4017#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 4435#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4080#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4081#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4369#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4617#L478-27 assume !(1 == ~t4_pc~0); 4006#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4007#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4383#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4515#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4516#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4552#L497-27 assume 1 == ~t5_pc~0; 4553#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4045#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4046#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3989#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3990#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4247#L516-27 assume 1 == ~t6_pc~0; 4248#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4102#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4103#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4250#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4390#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4179#L535-27 assume 1 == ~t7_pc~0; 4180#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4496#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4526#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4527#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4133#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4134#L554-27 assume !(1 == ~t8_pc~0); 3782#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 3783#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3928#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4267#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 4033#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4034#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3909#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3910#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4130#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4262#L946-3 assume !(1 == ~T4_E~0); 4051#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4052#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4331#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4140#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4141#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4378#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3799#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3800#L986-3 assume !(1 == ~E_4~0); 3790#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3791#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4450#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4121#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4122#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3832#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3834#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4148#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4149#L1291 assume !(0 == start_simulation_~tmp~3#1); 4328#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4234#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3729#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3730#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 4534#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4198#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4199#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4415#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 3801#L1272-2 [2022-11-16 12:34:04,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:04,961 INFO L85 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2022-11-16 12:34:04,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:04,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962904683] [2022-11-16 12:34:04,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:04,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:04,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:05,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:05,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:05,092 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962904683] [2022-11-16 12:34:05,092 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962904683] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:05,092 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:05,092 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:05,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812525140] [2022-11-16 12:34:05,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:05,093 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:05,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:05,094 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 1 times [2022-11-16 12:34:05,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:05,095 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952422244] [2022-11-16 12:34:05,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:05,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:05,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:05,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:05,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:05,175 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952422244] [2022-11-16 12:34:05,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952422244] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:05,176 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:05,176 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:05,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394735618] [2022-11-16 12:34:05,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:05,177 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:05,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:05,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:05,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:05,179 INFO L87 Difference]: Start difference. First operand 924 states and 1378 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:05,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:05,205 INFO L93 Difference]: Finished difference Result 924 states and 1377 transitions. [2022-11-16 12:34:05,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1377 transitions. [2022-11-16 12:34:05,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:05,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1377 transitions. [2022-11-16 12:34:05,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-11-16 12:34:05,220 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-11-16 12:34:05,220 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1377 transitions. [2022-11-16 12:34:05,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:05,222 INFO L218 hiAutomatonCegarLoop]: Abstraction has 924 states and 1377 transitions. [2022-11-16 12:34:05,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1377 transitions. [2022-11-16 12:34:05,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-11-16 12:34:05,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4902597402597402) internal successors, (1377), 923 states have internal predecessors, (1377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:05,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1377 transitions. [2022-11-16 12:34:05,245 INFO L240 hiAutomatonCegarLoop]: Abstraction has 924 states and 1377 transitions. [2022-11-16 12:34:05,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:05,247 INFO L428 stractBuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2022-11-16 12:34:05,247 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 12:34:05,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1377 transitions. [2022-11-16 12:34:05,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:05,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:05,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:05,265 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:05,267 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:05,268 INFO L748 eck$LassoCheckResult]: Stem: 6256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 6257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6499#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5671#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5672#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 5943#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5944#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6441#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6431#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6011#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6012#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6236#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6237#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6093#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6094#L838 assume !(0 == ~M_E~0); 6243#L838-2 assume !(0 == ~T1_E~0); 5633#L843-1 assume !(0 == ~T2_E~0); 5634#L848-1 assume !(0 == ~T3_E~0); 5753#L853-1 assume !(0 == ~T4_E~0); 6079#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5580#L863-1 assume !(0 == ~T6_E~0); 5581#L868-1 assume !(0 == ~T7_E~0); 6473#L873-1 assume !(0 == ~T8_E~0); 6471#L878-1 assume !(0 == ~E_1~0); 6460#L883-1 assume !(0 == ~E_2~0); 6461#L888-1 assume !(0 == ~E_3~0); 6208#L893-1 assume !(0 == ~E_4~0); 6209#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6485#L903-1 assume !(0 == ~E_6~0); 6459#L908-1 assume !(0 == ~E_7~0); 6333#L913-1 assume !(0 == ~E_8~0); 5647#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5648#L402 assume !(1 == ~m_pc~0); 5856#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5774#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5775#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6017#L1035 assume !(0 != activate_threads_~tmp~1#1); 6018#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6070#L421 assume 1 == ~t1_pc~0; 6455#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6474#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6062#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6063#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6121#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6482#L440 assume 1 == ~t2_pc~0; 5617#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5618#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5784#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6493#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6347#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5971#L459 assume !(1 == ~t3_pc~0); 5972#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6454#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6278#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5768#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5769#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5778#L478 assume 1 == ~t4_pc~0; 5779#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6213#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6440#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5949#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5692#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5693#L497 assume !(1 == ~t5_pc~0); 5739#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5740#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6031#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6032#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6447#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6448#L516 assume 1 == ~t6_pc~0; 6502#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6234#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6235#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5823#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5824#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6225#L535 assume !(1 == ~t7_pc~0); 6226#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6295#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6296#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6324#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6314#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6315#L554 assume 1 == ~t8_pc~0; 6264#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5609#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6365#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5911#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5912#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5593#L931 assume !(1 == ~M_E~0); 5594#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6468#L936-1 assume !(1 == ~T2_E~0); 6491#L941-1 assume !(1 == ~T3_E~0); 6071#L946-1 assume !(1 == ~T4_E~0); 6072#L951-1 assume !(1 == ~T5_E~0); 5838#L956-1 assume !(1 == ~T6_E~0); 5839#L961-1 assume !(1 == ~T7_E~0); 6210#L966-1 assume !(1 == ~T8_E~0); 6211#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6317#L976-1 assume !(1 == ~E_2~0); 6287#L981-1 assume !(1 == ~E_3~0); 6076#L986-1 assume !(1 == ~E_4~0); 5868#L991-1 assume !(1 == ~E_5~0); 5869#L996-1 assume !(1 == ~E_6~0); 6478#L1001-1 assume !(1 == ~E_7~0); 6254#L1006-1 assume !(1 == ~E_8~0); 6255#L1011-1 assume { :end_inline_reset_delta_events } true; 5656#L1272-2 [2022-11-16 12:34:05,268 INFO L750 eck$LassoCheckResult]: Loop: 5656#L1272-2 assume !false; 5657#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5658#L813 assume !false; 5659#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6405#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5661#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6205#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6215#L696 assume !(0 != eval_~tmp~0#1); 6258#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6259#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6380#L838-3 assume !(0 == ~M_E~0); 6300#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6301#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6163#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6164#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6212#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6275#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6267#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6268#L873-3 assume !(0 == ~T8_E~0); 5891#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5620#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5621#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5622#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5623#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6097#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6406#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6110#L913-3 assume !(0 == ~E_8~0); 5663#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5664#L402-27 assume 1 == ~m_pc~0; 5610#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5611#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6100#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6101#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6419#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6420#L421-27 assume !(1 == ~t1_pc~0); 5883#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5884#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6133#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6134#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6479#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6228#L440-27 assume 1 == ~t2_pc~0; 6229#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6402#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5967#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5968#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6142#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5871#L459-27 assume !(1 == ~t3_pc~0); 5872#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 6290#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5935#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5936#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6224#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6472#L478-27 assume !(1 == ~t4_pc~0); 5861#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5862#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6238#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6370#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6371#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6407#L497-27 assume 1 == ~t5_pc~0; 6408#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5900#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5901#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5844#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5845#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6102#L516-27 assume 1 == ~t6_pc~0; 6103#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5957#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5958#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6105#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6245#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6034#L535-27 assume 1 == ~t7_pc~0; 6035#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6351#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6381#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6382#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5988#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5989#L554-27 assume !(1 == ~t8_pc~0); 5637#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 5638#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5783#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6122#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 5888#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5889#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5764#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5765#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5985#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6117#L946-3 assume !(1 == ~T4_E~0); 5906#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5907#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6186#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5995#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5996#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6233#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5654#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5655#L986-3 assume !(1 == ~E_4~0); 5645#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5646#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6305#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5976#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5977#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5687#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5689#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6003#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 6004#L1291 assume !(0 == start_simulation_~tmp~3#1); 6183#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6089#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5584#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5585#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6389#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6053#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6054#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6270#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 5656#L1272-2 [2022-11-16 12:34:05,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:05,269 INFO L85 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2022-11-16 12:34:05,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:05,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136953822] [2022-11-16 12:34:05,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:05,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:05,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:05,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:05,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:05,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136953822] [2022-11-16 12:34:05,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136953822] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:05,348 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:05,348 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:05,349 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050229182] [2022-11-16 12:34:05,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:05,349 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:05,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:05,350 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 2 times [2022-11-16 12:34:05,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:05,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8702935] [2022-11-16 12:34:05,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:05,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:05,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:05,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:05,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:05,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8702935] [2022-11-16 12:34:05,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [8702935] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:05,420 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:05,420 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:05,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257826903] [2022-11-16 12:34:05,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:05,421 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:05,421 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:05,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:05,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:05,422 INFO L87 Difference]: Start difference. First operand 924 states and 1377 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:05,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:05,448 INFO L93 Difference]: Finished difference Result 924 states and 1376 transitions. [2022-11-16 12:34:05,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1376 transitions. [2022-11-16 12:34:05,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:05,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1376 transitions. [2022-11-16 12:34:05,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-11-16 12:34:05,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-11-16 12:34:05,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1376 transitions. [2022-11-16 12:34:05,464 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:05,464 INFO L218 hiAutomatonCegarLoop]: Abstraction has 924 states and 1376 transitions. [2022-11-16 12:34:05,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1376 transitions. [2022-11-16 12:34:05,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-11-16 12:34:05,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4891774891774892) internal successors, (1376), 923 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:05,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1376 transitions. [2022-11-16 12:34:05,486 INFO L240 hiAutomatonCegarLoop]: Abstraction has 924 states and 1376 transitions. [2022-11-16 12:34:05,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:05,487 INFO L428 stractBuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2022-11-16 12:34:05,487 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 12:34:05,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1376 transitions. [2022-11-16 12:34:05,493 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:05,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:05,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:05,495 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:05,495 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:05,496 INFO L748 eck$LassoCheckResult]: Stem: 8111#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 8112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8354#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7526#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7527#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 7798#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7799#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8296#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8286#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7866#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7867#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8091#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8092#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7948#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7949#L838 assume !(0 == ~M_E~0); 8098#L838-2 assume !(0 == ~T1_E~0); 7488#L843-1 assume !(0 == ~T2_E~0); 7489#L848-1 assume !(0 == ~T3_E~0); 7608#L853-1 assume !(0 == ~T4_E~0); 7934#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7435#L863-1 assume !(0 == ~T6_E~0); 7436#L868-1 assume !(0 == ~T7_E~0); 8328#L873-1 assume !(0 == ~T8_E~0); 8326#L878-1 assume !(0 == ~E_1~0); 8315#L883-1 assume !(0 == ~E_2~0); 8316#L888-1 assume !(0 == ~E_3~0); 8063#L893-1 assume !(0 == ~E_4~0); 8064#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8340#L903-1 assume !(0 == ~E_6~0); 8314#L908-1 assume !(0 == ~E_7~0); 8188#L913-1 assume !(0 == ~E_8~0); 7502#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7503#L402 assume !(1 == ~m_pc~0); 7711#L402-2 is_master_triggered_~__retres1~0#1 := 0; 7629#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7630#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7872#L1035 assume !(0 != activate_threads_~tmp~1#1); 7873#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7925#L421 assume 1 == ~t1_pc~0; 8310#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8329#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7917#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7918#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 7976#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8337#L440 assume 1 == ~t2_pc~0; 7472#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7473#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7639#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8348#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 8202#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7826#L459 assume !(1 == ~t3_pc~0); 7827#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8309#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8133#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7623#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7624#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7633#L478 assume 1 == ~t4_pc~0; 7634#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8068#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8295#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7804#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 7547#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7548#L497 assume !(1 == ~t5_pc~0); 7594#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7595#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7886#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7887#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 8302#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8303#L516 assume 1 == ~t6_pc~0; 8357#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8089#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8090#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7678#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 7679#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8080#L535 assume !(1 == ~t7_pc~0); 8081#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8150#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8151#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8179#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 8169#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8170#L554 assume 1 == ~t8_pc~0; 8119#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7464#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8220#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7766#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 7767#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7448#L931 assume !(1 == ~M_E~0); 7449#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8323#L936-1 assume !(1 == ~T2_E~0); 8346#L941-1 assume !(1 == ~T3_E~0); 7926#L946-1 assume !(1 == ~T4_E~0); 7927#L951-1 assume !(1 == ~T5_E~0); 7693#L956-1 assume !(1 == ~T6_E~0); 7694#L961-1 assume !(1 == ~T7_E~0); 8065#L966-1 assume !(1 == ~T8_E~0); 8066#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8172#L976-1 assume !(1 == ~E_2~0); 8142#L981-1 assume !(1 == ~E_3~0); 7931#L986-1 assume !(1 == ~E_4~0); 7723#L991-1 assume !(1 == ~E_5~0); 7724#L996-1 assume !(1 == ~E_6~0); 8333#L1001-1 assume !(1 == ~E_7~0); 8109#L1006-1 assume !(1 == ~E_8~0); 8110#L1011-1 assume { :end_inline_reset_delta_events } true; 7511#L1272-2 [2022-11-16 12:34:05,496 INFO L750 eck$LassoCheckResult]: Loop: 7511#L1272-2 assume !false; 7512#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7513#L813 assume !false; 7514#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8260#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7516#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8060#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8070#L696 assume !(0 != eval_~tmp~0#1); 8113#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8114#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8235#L838-3 assume !(0 == ~M_E~0); 8155#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8156#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8018#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8019#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8067#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8130#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8122#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8123#L873-3 assume !(0 == ~T8_E~0); 7746#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7475#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7476#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7477#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7478#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7952#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8261#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7965#L913-3 assume !(0 == ~E_8~0); 7518#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7519#L402-27 assume 1 == ~m_pc~0; 7465#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7466#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7955#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7956#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8274#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8275#L421-27 assume !(1 == ~t1_pc~0); 7738#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7739#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7988#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7989#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8334#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8083#L440-27 assume 1 == ~t2_pc~0; 8084#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8257#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7822#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7823#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7997#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7726#L459-27 assume 1 == ~t3_pc~0; 7728#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8145#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7790#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7791#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8079#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8327#L478-27 assume !(1 == ~t4_pc~0); 7716#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 7717#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8093#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8225#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8226#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8262#L497-27 assume 1 == ~t5_pc~0; 8263#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7755#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7756#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7699#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7700#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7957#L516-27 assume 1 == ~t6_pc~0; 7958#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7812#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7813#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7960#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8100#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7889#L535-27 assume 1 == ~t7_pc~0; 7890#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8206#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8236#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8237#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7843#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7844#L554-27 assume !(1 == ~t8_pc~0); 7492#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 7493#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7638#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7977#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 7743#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7744#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7619#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7620#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7840#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7972#L946-3 assume !(1 == ~T4_E~0); 7761#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7762#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8041#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7850#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7851#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8088#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7509#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7510#L986-3 assume !(1 == ~E_4~0); 7500#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7501#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8160#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7831#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7832#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7542#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7544#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7858#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7859#L1291 assume !(0 == start_simulation_~tmp~3#1); 8038#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7944#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7439#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7440#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8244#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7908#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7909#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8125#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 7511#L1272-2 [2022-11-16 12:34:05,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:05,497 INFO L85 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2022-11-16 12:34:05,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:05,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044121557] [2022-11-16 12:34:05,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:05,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:05,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:05,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:05,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:05,558 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044121557] [2022-11-16 12:34:05,558 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2044121557] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:05,558 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:05,558 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:05,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133756355] [2022-11-16 12:34:05,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:05,559 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:05,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:05,560 INFO L85 PathProgramCache]: Analyzing trace with hash 539629054, now seen corresponding path program 1 times [2022-11-16 12:34:05,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:05,561 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67128654] [2022-11-16 12:34:05,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:05,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:05,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:05,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:05,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:05,649 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [67128654] [2022-11-16 12:34:05,649 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [67128654] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:05,649 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:05,649 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:05,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62033041] [2022-11-16 12:34:05,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:05,652 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:05,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:05,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:05,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:05,654 INFO L87 Difference]: Start difference. First operand 924 states and 1376 transitions. cyclomatic complexity: 453 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:05,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:05,679 INFO L93 Difference]: Finished difference Result 924 states and 1375 transitions. [2022-11-16 12:34:05,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1375 transitions. [2022-11-16 12:34:05,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:05,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1375 transitions. [2022-11-16 12:34:05,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-11-16 12:34:05,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-11-16 12:34:05,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1375 transitions. [2022-11-16 12:34:05,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:05,696 INFO L218 hiAutomatonCegarLoop]: Abstraction has 924 states and 1375 transitions. [2022-11-16 12:34:05,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1375 transitions. [2022-11-16 12:34:05,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-11-16 12:34:05,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4880952380952381) internal successors, (1375), 923 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:05,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1375 transitions. [2022-11-16 12:34:05,783 INFO L240 hiAutomatonCegarLoop]: Abstraction has 924 states and 1375 transitions. [2022-11-16 12:34:05,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:05,787 INFO L428 stractBuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2022-11-16 12:34:05,788 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 12:34:05,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1375 transitions. [2022-11-16 12:34:05,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:05,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:05,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:05,797 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:05,797 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:05,797 INFO L748 eck$LassoCheckResult]: Stem: 9966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 9967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10209#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9381#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9382#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9653#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9654#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10151#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10141#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9721#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9722#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9946#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9947#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9803#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9804#L838 assume !(0 == ~M_E~0); 9953#L838-2 assume !(0 == ~T1_E~0); 9343#L843-1 assume !(0 == ~T2_E~0); 9344#L848-1 assume !(0 == ~T3_E~0); 9463#L853-1 assume !(0 == ~T4_E~0); 9789#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9290#L863-1 assume !(0 == ~T6_E~0); 9291#L868-1 assume !(0 == ~T7_E~0); 10183#L873-1 assume !(0 == ~T8_E~0); 10181#L878-1 assume !(0 == ~E_1~0); 10170#L883-1 assume !(0 == ~E_2~0); 10171#L888-1 assume !(0 == ~E_3~0); 9918#L893-1 assume !(0 == ~E_4~0); 9919#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10195#L903-1 assume !(0 == ~E_6~0); 10169#L908-1 assume !(0 == ~E_7~0); 10043#L913-1 assume !(0 == ~E_8~0); 9357#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9358#L402 assume !(1 == ~m_pc~0); 9566#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9484#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9485#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9727#L1035 assume !(0 != activate_threads_~tmp~1#1); 9728#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9780#L421 assume 1 == ~t1_pc~0; 10165#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10184#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9772#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9773#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9831#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10192#L440 assume 1 == ~t2_pc~0; 9327#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9328#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9494#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10203#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 10057#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9681#L459 assume !(1 == ~t3_pc~0); 9682#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10164#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9988#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9478#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9479#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9488#L478 assume 1 == ~t4_pc~0; 9489#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9923#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10150#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9659#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9402#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9403#L497 assume !(1 == ~t5_pc~0); 9449#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9450#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9741#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9742#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 10157#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10158#L516 assume 1 == ~t6_pc~0; 10212#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9944#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9945#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9533#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9534#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9935#L535 assume !(1 == ~t7_pc~0); 9936#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10005#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10006#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10034#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 10024#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10025#L554 assume 1 == ~t8_pc~0; 9974#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9319#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10075#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9621#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9622#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9303#L931 assume !(1 == ~M_E~0); 9304#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10178#L936-1 assume !(1 == ~T2_E~0); 10201#L941-1 assume !(1 == ~T3_E~0); 9781#L946-1 assume !(1 == ~T4_E~0); 9782#L951-1 assume !(1 == ~T5_E~0); 9548#L956-1 assume !(1 == ~T6_E~0); 9549#L961-1 assume !(1 == ~T7_E~0); 9920#L966-1 assume !(1 == ~T8_E~0); 9921#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10027#L976-1 assume !(1 == ~E_2~0); 9997#L981-1 assume !(1 == ~E_3~0); 9786#L986-1 assume !(1 == ~E_4~0); 9578#L991-1 assume !(1 == ~E_5~0); 9579#L996-1 assume !(1 == ~E_6~0); 10188#L1001-1 assume !(1 == ~E_7~0); 9964#L1006-1 assume !(1 == ~E_8~0); 9965#L1011-1 assume { :end_inline_reset_delta_events } true; 9366#L1272-2 [2022-11-16 12:34:05,798 INFO L750 eck$LassoCheckResult]: Loop: 9366#L1272-2 assume !false; 9367#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9368#L813 assume !false; 9369#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10115#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9371#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9915#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9925#L696 assume !(0 != eval_~tmp~0#1); 9968#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9969#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10090#L838-3 assume !(0 == ~M_E~0); 10010#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10011#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9873#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9874#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9922#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9985#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9977#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9978#L873-3 assume !(0 == ~T8_E~0); 9601#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9330#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9331#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9332#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9333#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9807#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10116#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9820#L913-3 assume !(0 == ~E_8~0); 9373#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9374#L402-27 assume 1 == ~m_pc~0; 9320#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9321#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9810#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9811#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10129#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10130#L421-27 assume !(1 == ~t1_pc~0); 9593#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 9594#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9843#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9844#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10189#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9938#L440-27 assume 1 == ~t2_pc~0; 9939#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10112#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9677#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9678#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9852#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9581#L459-27 assume !(1 == ~t3_pc~0); 9582#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10000#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9645#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9646#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9934#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10182#L478-27 assume !(1 == ~t4_pc~0); 9571#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 9572#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9948#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10080#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10081#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10117#L497-27 assume 1 == ~t5_pc~0; 10118#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9610#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9611#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9554#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9555#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9812#L516-27 assume 1 == ~t6_pc~0; 9813#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9667#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9668#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9815#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9955#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9744#L535-27 assume 1 == ~t7_pc~0; 9745#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10061#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10091#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10092#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9698#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9699#L554-27 assume !(1 == ~t8_pc~0); 9347#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 9348#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9493#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9832#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 9598#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9599#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9474#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9475#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9695#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9827#L946-3 assume !(1 == ~T4_E~0); 9616#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9617#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9896#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9705#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9706#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9943#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9364#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9365#L986-3 assume !(1 == ~E_4~0); 9355#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9356#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10015#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9686#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9687#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9397#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9399#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9713#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9714#L1291 assume !(0 == start_simulation_~tmp~3#1); 9893#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9799#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9294#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9295#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10099#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9763#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9764#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9980#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 9366#L1272-2 [2022-11-16 12:34:05,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:05,801 INFO L85 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2022-11-16 12:34:05,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:05,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369055814] [2022-11-16 12:34:05,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:05,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:05,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:05,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:05,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:05,883 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369055814] [2022-11-16 12:34:05,883 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369055814] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:05,884 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:05,884 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:05,890 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [859872884] [2022-11-16 12:34:05,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:05,891 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:05,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:05,894 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 3 times [2022-11-16 12:34:05,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:05,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506866495] [2022-11-16 12:34:05,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:05,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:05,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:05,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:05,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:05,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506866495] [2022-11-16 12:34:05,978 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [506866495] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:05,978 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:05,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:05,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165834073] [2022-11-16 12:34:05,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:05,980 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:05,980 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:05,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:05,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:05,982 INFO L87 Difference]: Start difference. First operand 924 states and 1375 transitions. cyclomatic complexity: 452 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:06,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:06,017 INFO L93 Difference]: Finished difference Result 924 states and 1374 transitions. [2022-11-16 12:34:06,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1374 transitions. [2022-11-16 12:34:06,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:06,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1374 transitions. [2022-11-16 12:34:06,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-11-16 12:34:06,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-11-16 12:34:06,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1374 transitions. [2022-11-16 12:34:06,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:06,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 924 states and 1374 transitions. [2022-11-16 12:34:06,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1374 transitions. [2022-11-16 12:34:06,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-11-16 12:34:06,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4870129870129871) internal successors, (1374), 923 states have internal predecessors, (1374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:06,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1374 transitions. [2022-11-16 12:34:06,060 INFO L240 hiAutomatonCegarLoop]: Abstraction has 924 states and 1374 transitions. [2022-11-16 12:34:06,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:06,064 INFO L428 stractBuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2022-11-16 12:34:06,064 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 12:34:06,064 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1374 transitions. [2022-11-16 12:34:06,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:06,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:06,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:06,074 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:06,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:06,075 INFO L748 eck$LassoCheckResult]: Stem: 11821#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 11822#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12064#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11236#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11237#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 11508#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11509#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12006#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11997#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11576#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11577#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11802#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11803#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11658#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11659#L838 assume !(0 == ~M_E~0); 11809#L838-2 assume !(0 == ~T1_E~0); 11198#L843-1 assume !(0 == ~T2_E~0); 11199#L848-1 assume !(0 == ~T3_E~0); 11318#L853-1 assume !(0 == ~T4_E~0); 11644#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11145#L863-1 assume !(0 == ~T6_E~0); 11146#L868-1 assume !(0 == ~T7_E~0); 12038#L873-1 assume !(0 == ~T8_E~0); 12036#L878-1 assume !(0 == ~E_1~0); 12025#L883-1 assume !(0 == ~E_2~0); 12026#L888-1 assume !(0 == ~E_3~0); 11773#L893-1 assume !(0 == ~E_4~0); 11774#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12050#L903-1 assume !(0 == ~E_6~0); 12024#L908-1 assume !(0 == ~E_7~0); 11898#L913-1 assume !(0 == ~E_8~0); 11212#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11213#L402 assume !(1 == ~m_pc~0); 11421#L402-2 is_master_triggered_~__retres1~0#1 := 0; 11339#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11340#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11582#L1035 assume !(0 != activate_threads_~tmp~1#1); 11583#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11635#L421 assume 1 == ~t1_pc~0; 12020#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12039#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11627#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11628#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 11686#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12047#L440 assume 1 == ~t2_pc~0; 11182#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11183#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11349#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12058#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 11912#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11536#L459 assume !(1 == ~t3_pc~0); 11537#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12019#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11843#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11333#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11334#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11343#L478 assume 1 == ~t4_pc~0; 11344#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11778#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12005#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11514#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 11257#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11258#L497 assume !(1 == ~t5_pc~0); 11304#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11305#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11596#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11597#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 12012#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12013#L516 assume 1 == ~t6_pc~0; 12067#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11799#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11800#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11388#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 11389#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11790#L535 assume !(1 == ~t7_pc~0); 11791#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11860#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11861#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11889#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 11879#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11880#L554 assume 1 == ~t8_pc~0; 11829#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11174#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11930#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11476#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 11477#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11158#L931 assume !(1 == ~M_E~0); 11159#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12033#L936-1 assume !(1 == ~T2_E~0); 12056#L941-1 assume !(1 == ~T3_E~0); 11636#L946-1 assume !(1 == ~T4_E~0); 11637#L951-1 assume !(1 == ~T5_E~0); 11403#L956-1 assume !(1 == ~T6_E~0); 11404#L961-1 assume !(1 == ~T7_E~0); 11775#L966-1 assume !(1 == ~T8_E~0); 11776#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11882#L976-1 assume !(1 == ~E_2~0); 11852#L981-1 assume !(1 == ~E_3~0); 11641#L986-1 assume !(1 == ~E_4~0); 11433#L991-1 assume !(1 == ~E_5~0); 11434#L996-1 assume !(1 == ~E_6~0); 12043#L1001-1 assume !(1 == ~E_7~0); 11819#L1006-1 assume !(1 == ~E_8~0); 11820#L1011-1 assume { :end_inline_reset_delta_events } true; 11221#L1272-2 [2022-11-16 12:34:06,075 INFO L750 eck$LassoCheckResult]: Loop: 11221#L1272-2 assume !false; 11222#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11223#L813 assume !false; 11224#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11970#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11226#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11770#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11780#L696 assume !(0 != eval_~tmp~0#1); 11823#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11824#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11945#L838-3 assume !(0 == ~M_E~0); 11865#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11866#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11728#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11729#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11777#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11840#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11832#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11833#L873-3 assume !(0 == ~T8_E~0); 11456#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11185#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11186#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11187#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11188#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11662#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11971#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11675#L913-3 assume !(0 == ~E_8~0); 11228#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11229#L402-27 assume 1 == ~m_pc~0; 11175#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11176#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11665#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11666#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11984#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11985#L421-27 assume !(1 == ~t1_pc~0); 11448#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 11449#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11698#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11699#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12044#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11793#L440-27 assume 1 == ~t2_pc~0; 11794#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11967#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11532#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11533#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11707#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11436#L459-27 assume !(1 == ~t3_pc~0); 11437#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 11855#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11500#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11501#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11789#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12037#L478-27 assume !(1 == ~t4_pc~0); 11426#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 11427#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11801#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11935#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11936#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11972#L497-27 assume 1 == ~t5_pc~0; 11973#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11465#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11466#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11409#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11410#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11667#L516-27 assume 1 == ~t6_pc~0; 11668#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11522#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11523#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11670#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11810#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11599#L535-27 assume 1 == ~t7_pc~0; 11600#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11916#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11946#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11947#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11553#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11554#L554-27 assume !(1 == ~t8_pc~0); 11202#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 11203#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11348#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11687#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 11453#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11454#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11329#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11330#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11550#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11682#L946-3 assume !(1 == ~T4_E~0); 11471#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11472#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11751#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11560#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11561#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11798#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11219#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11220#L986-3 assume !(1 == ~E_4~0); 11210#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11211#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11870#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11541#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11542#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11252#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11254#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11568#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11569#L1291 assume !(0 == start_simulation_~tmp~3#1); 11748#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11654#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11149#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11150#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11954#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11618#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11619#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 11835#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 11221#L1272-2 [2022-11-16 12:34:06,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:06,076 INFO L85 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2022-11-16 12:34:06,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:06,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127208289] [2022-11-16 12:34:06,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:06,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:06,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:06,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:06,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:06,131 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127208289] [2022-11-16 12:34:06,131 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127208289] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:06,131 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:06,131 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:06,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760360335] [2022-11-16 12:34:06,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:06,132 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:06,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:06,133 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 4 times [2022-11-16 12:34:06,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:06,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331361307] [2022-11-16 12:34:06,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:06,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:06,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:06,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:06,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:06,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331361307] [2022-11-16 12:34:06,223 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [331361307] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:06,223 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:06,224 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:06,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058544207] [2022-11-16 12:34:06,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:06,224 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:06,225 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:06,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:06,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:06,225 INFO L87 Difference]: Start difference. First operand 924 states and 1374 transitions. cyclomatic complexity: 451 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:06,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:06,254 INFO L93 Difference]: Finished difference Result 924 states and 1373 transitions. [2022-11-16 12:34:06,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1373 transitions. [2022-11-16 12:34:06,261 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:06,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1373 transitions. [2022-11-16 12:34:06,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-11-16 12:34:06,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-11-16 12:34:06,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1373 transitions. [2022-11-16 12:34:06,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:06,271 INFO L218 hiAutomatonCegarLoop]: Abstraction has 924 states and 1373 transitions. [2022-11-16 12:34:06,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1373 transitions. [2022-11-16 12:34:06,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-11-16 12:34:06,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4859307359307359) internal successors, (1373), 923 states have internal predecessors, (1373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:06,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1373 transitions. [2022-11-16 12:34:06,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 924 states and 1373 transitions. [2022-11-16 12:34:06,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:06,296 INFO L428 stractBuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2022-11-16 12:34:06,296 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 12:34:06,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1373 transitions. [2022-11-16 12:34:06,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:06,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:06,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:06,303 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:06,304 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:06,304 INFO L748 eck$LassoCheckResult]: Stem: 13676#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 13677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13919#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13091#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13092#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 13363#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13364#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13861#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13852#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13431#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13432#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13657#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13658#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13513#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13514#L838 assume !(0 == ~M_E~0); 13664#L838-2 assume !(0 == ~T1_E~0); 13053#L843-1 assume !(0 == ~T2_E~0); 13054#L848-1 assume !(0 == ~T3_E~0); 13173#L853-1 assume !(0 == ~T4_E~0); 13501#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13002#L863-1 assume !(0 == ~T6_E~0); 13003#L868-1 assume !(0 == ~T7_E~0); 13893#L873-1 assume !(0 == ~T8_E~0); 13891#L878-1 assume !(0 == ~E_1~0); 13880#L883-1 assume !(0 == ~E_2~0); 13881#L888-1 assume !(0 == ~E_3~0); 13628#L893-1 assume !(0 == ~E_4~0); 13629#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13905#L903-1 assume !(0 == ~E_6~0); 13879#L908-1 assume !(0 == ~E_7~0); 13755#L913-1 assume !(0 == ~E_8~0); 13067#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13068#L402 assume !(1 == ~m_pc~0); 13280#L402-2 is_master_triggered_~__retres1~0#1 := 0; 13194#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13195#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13437#L1035 assume !(0 != activate_threads_~tmp~1#1); 13438#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13490#L421 assume 1 == ~t1_pc~0; 13875#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13897#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13482#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13483#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 13542#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13902#L440 assume 1 == ~t2_pc~0; 13037#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13038#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13204#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13913#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 13767#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13395#L459 assume !(1 == ~t3_pc~0); 13396#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13874#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13699#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13188#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13189#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13198#L478 assume 1 == ~t4_pc~0; 13199#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13633#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13860#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13369#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 13114#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13115#L497 assume !(1 == ~t5_pc~0); 13159#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13160#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13451#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13452#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 13868#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13869#L516 assume 1 == ~t6_pc~0; 13922#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13654#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13655#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13243#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 13244#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13645#L535 assume !(1 == ~t7_pc~0); 13646#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13715#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13716#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13744#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 13735#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13736#L554 assume 1 == ~t8_pc~0; 13685#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13029#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13785#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13334#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 13335#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13013#L931 assume !(1 == ~M_E~0); 13014#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13888#L936-1 assume !(1 == ~T2_E~0); 13911#L941-1 assume !(1 == ~T3_E~0); 13491#L946-1 assume !(1 == ~T4_E~0); 13492#L951-1 assume !(1 == ~T5_E~0); 13258#L956-1 assume !(1 == ~T6_E~0); 13259#L961-1 assume !(1 == ~T7_E~0); 13630#L966-1 assume !(1 == ~T8_E~0); 13631#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13738#L976-1 assume !(1 == ~E_2~0); 13707#L981-1 assume !(1 == ~E_3~0); 13496#L986-1 assume !(1 == ~E_4~0); 13288#L991-1 assume !(1 == ~E_5~0); 13289#L996-1 assume !(1 == ~E_6~0); 13898#L1001-1 assume !(1 == ~E_7~0); 13674#L1006-1 assume !(1 == ~E_8~0); 13675#L1011-1 assume { :end_inline_reset_delta_events } true; 13076#L1272-2 [2022-11-16 12:34:06,305 INFO L750 eck$LassoCheckResult]: Loop: 13076#L1272-2 assume !false; 13077#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13078#L813 assume !false; 13079#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13825#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13081#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13627#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13635#L696 assume !(0 != eval_~tmp~0#1); 13678#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13679#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13802#L838-3 assume !(0 == ~M_E~0); 13720#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13721#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13584#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13585#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13632#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13695#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13687#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13688#L873-3 assume !(0 == ~T8_E~0); 13311#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13040#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13041#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13042#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13043#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13517#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13826#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13530#L913-3 assume !(0 == ~E_8~0); 13083#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13084#L402-27 assume 1 == ~m_pc~0; 13030#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13031#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13520#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13521#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13839#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13840#L421-27 assume 1 == ~t1_pc~0; 13750#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13304#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13553#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13554#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13899#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13648#L440-27 assume 1 == ~t2_pc~0; 13649#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13821#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13387#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13388#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13562#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13291#L459-27 assume !(1 == ~t3_pc~0); 13292#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 13710#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13355#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13356#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13644#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13892#L478-27 assume !(1 == ~t4_pc~0); 13281#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 13282#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13656#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13790#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13791#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13827#L497-27 assume 1 == ~t5_pc~0; 13828#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13320#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13321#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13264#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13265#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13522#L516-27 assume 1 == ~t6_pc~0; 13523#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13374#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13375#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13525#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13665#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13454#L535-27 assume !(1 == ~t7_pc~0); 13456#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 13771#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13800#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13801#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13408#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13409#L554-27 assume !(1 == ~t8_pc~0); 13057#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 13058#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13203#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13541#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 13308#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13309#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13184#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13185#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13405#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13537#L946-3 assume !(1 == ~T4_E~0); 13326#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13327#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13606#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13415#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13416#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13653#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13074#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13075#L986-3 assume !(1 == ~E_4~0); 13065#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13066#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13725#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13393#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13394#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13107#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13109#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13423#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 13424#L1291 assume !(0 == start_simulation_~tmp~3#1); 13603#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13509#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13004#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13005#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13809#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13473#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13474#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 13690#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 13076#L1272-2 [2022-11-16 12:34:06,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:06,305 INFO L85 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2022-11-16 12:34:06,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:06,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586640290] [2022-11-16 12:34:06,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:06,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:06,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:06,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:06,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:06,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [586640290] [2022-11-16 12:34:06,407 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [586640290] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:06,407 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:06,407 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:06,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906241767] [2022-11-16 12:34:06,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:06,410 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:06,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:06,411 INFO L85 PathProgramCache]: Analyzing trace with hash -1516707235, now seen corresponding path program 1 times [2022-11-16 12:34:06,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:06,411 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126014166] [2022-11-16 12:34:06,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:06,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:06,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:06,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:06,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:06,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [126014166] [2022-11-16 12:34:06,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [126014166] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:06,509 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:06,509 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:06,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1736853215] [2022-11-16 12:34:06,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:06,510 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:06,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:06,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:06,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:06,511 INFO L87 Difference]: Start difference. First operand 924 states and 1373 transitions. cyclomatic complexity: 450 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:06,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:06,541 INFO L93 Difference]: Finished difference Result 924 states and 1372 transitions. [2022-11-16 12:34:06,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1372 transitions. [2022-11-16 12:34:06,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:06,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1372 transitions. [2022-11-16 12:34:06,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-11-16 12:34:06,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-11-16 12:34:06,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1372 transitions. [2022-11-16 12:34:06,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:06,557 INFO L218 hiAutomatonCegarLoop]: Abstraction has 924 states and 1372 transitions. [2022-11-16 12:34:06,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1372 transitions. [2022-11-16 12:34:06,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-11-16 12:34:06,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4848484848484849) internal successors, (1372), 923 states have internal predecessors, (1372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:06,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1372 transitions. [2022-11-16 12:34:06,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 924 states and 1372 transitions. [2022-11-16 12:34:06,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:06,584 INFO L428 stractBuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2022-11-16 12:34:06,584 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 12:34:06,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1372 transitions. [2022-11-16 12:34:06,590 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:06,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:06,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:06,592 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:06,592 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:06,592 INFO L748 eck$LassoCheckResult]: Stem: 15531#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 15532#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15774#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14946#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14947#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 15218#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15219#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15716#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15706#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15286#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15287#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15512#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15513#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15368#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15369#L838 assume !(0 == ~M_E~0); 15519#L838-2 assume !(0 == ~T1_E~0); 14908#L843-1 assume !(0 == ~T2_E~0); 14909#L848-1 assume !(0 == ~T3_E~0); 15028#L853-1 assume !(0 == ~T4_E~0); 15356#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14855#L863-1 assume !(0 == ~T6_E~0); 14856#L868-1 assume !(0 == ~T7_E~0); 15748#L873-1 assume !(0 == ~T8_E~0); 15746#L878-1 assume !(0 == ~E_1~0); 15735#L883-1 assume !(0 == ~E_2~0); 15736#L888-1 assume !(0 == ~E_3~0); 15483#L893-1 assume !(0 == ~E_4~0); 15484#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 15760#L903-1 assume !(0 == ~E_6~0); 15734#L908-1 assume !(0 == ~E_7~0); 15608#L913-1 assume !(0 == ~E_8~0); 14922#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14923#L402 assume !(1 == ~m_pc~0); 15133#L402-2 is_master_triggered_~__retres1~0#1 := 0; 15049#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15050#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15292#L1035 assume !(0 != activate_threads_~tmp~1#1); 15293#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15345#L421 assume 1 == ~t1_pc~0; 15730#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15752#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15337#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15338#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 15397#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15757#L440 assume 1 == ~t2_pc~0; 14892#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14893#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15059#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15768#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 15622#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15250#L459 assume !(1 == ~t3_pc~0); 15251#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15729#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15554#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15043#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15044#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15053#L478 assume 1 == ~t4_pc~0; 15054#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15488#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15715#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15224#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 14969#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14970#L497 assume !(1 == ~t5_pc~0); 15014#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15015#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15306#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15307#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 15723#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15724#L516 assume 1 == ~t6_pc~0; 15777#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15509#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15510#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15098#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 15099#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15500#L535 assume !(1 == ~t7_pc~0); 15501#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15570#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15571#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15599#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 15589#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15590#L554 assume 1 == ~t8_pc~0; 15540#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14884#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15640#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15189#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 15190#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14868#L931 assume !(1 == ~M_E~0); 14869#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15743#L936-1 assume !(1 == ~T2_E~0); 15766#L941-1 assume !(1 == ~T3_E~0); 15346#L946-1 assume !(1 == ~T4_E~0); 15347#L951-1 assume !(1 == ~T5_E~0); 15113#L956-1 assume !(1 == ~T6_E~0); 15114#L961-1 assume !(1 == ~T7_E~0); 15485#L966-1 assume !(1 == ~T8_E~0); 15486#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15592#L976-1 assume !(1 == ~E_2~0); 15562#L981-1 assume !(1 == ~E_3~0); 15351#L986-1 assume !(1 == ~E_4~0); 15143#L991-1 assume !(1 == ~E_5~0); 15144#L996-1 assume !(1 == ~E_6~0); 15753#L1001-1 assume !(1 == ~E_7~0); 15529#L1006-1 assume !(1 == ~E_8~0); 15530#L1011-1 assume { :end_inline_reset_delta_events } true; 14931#L1272-2 [2022-11-16 12:34:06,593 INFO L750 eck$LassoCheckResult]: Loop: 14931#L1272-2 assume !false; 14932#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14933#L813 assume !false; 14934#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15680#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14936#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15480#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15490#L696 assume !(0 != eval_~tmp~0#1); 15533#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15534#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15657#L838-3 assume !(0 == ~M_E~0); 15575#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15576#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15438#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15439#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15487#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15550#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15542#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15543#L873-3 assume !(0 == ~T8_E~0); 15168#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14895#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14896#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14897#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14898#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15374#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15683#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15385#L913-3 assume !(0 == ~E_8~0); 14938#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14939#L402-27 assume 1 == ~m_pc~0; 14885#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14886#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15379#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15380#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15697#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15698#L421-27 assume 1 == ~t1_pc~0; 15605#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15159#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15408#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15409#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15754#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15503#L440-27 assume 1 == ~t2_pc~0; 15504#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15676#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15242#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15243#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15417#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15146#L459-27 assume !(1 == ~t3_pc~0); 15147#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 15565#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15210#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15211#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15499#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15747#L478-27 assume !(1 == ~t4_pc~0); 15136#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 15137#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15511#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15645#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15646#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15681#L497-27 assume !(1 == ~t5_pc~0); 15298#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15175#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15176#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15119#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15120#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15375#L516-27 assume 1 == ~t6_pc~0; 15376#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15225#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15226#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15378#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15520#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15309#L535-27 assume 1 == ~t7_pc~0; 15310#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15626#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15655#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15656#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15263#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15264#L554-27 assume !(1 == ~t8_pc~0); 14912#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 14913#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15058#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15396#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 15163#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15164#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15039#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15040#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15260#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15392#L946-3 assume !(1 == ~T4_E~0); 15181#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15182#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15461#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15270#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15271#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15508#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14929#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14930#L986-3 assume !(1 == ~E_4~0); 14920#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14921#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15580#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15248#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15249#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14962#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14964#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15278#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15279#L1291 assume !(0 == start_simulation_~tmp~3#1); 15458#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15364#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14859#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14860#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15664#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15328#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15329#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15545#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 14931#L1272-2 [2022-11-16 12:34:06,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:06,594 INFO L85 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2022-11-16 12:34:06,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:06,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557709759] [2022-11-16 12:34:06,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:06,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:06,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:06,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:06,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:06,659 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557709759] [2022-11-16 12:34:06,659 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1557709759] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:06,659 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:06,660 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:34:06,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445115395] [2022-11-16 12:34:06,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:06,661 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:06,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:06,661 INFO L85 PathProgramCache]: Analyzing trace with hash 741608413, now seen corresponding path program 1 times [2022-11-16 12:34:06,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:06,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465863723] [2022-11-16 12:34:06,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:06,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:06,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:06,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:06,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:06,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465863723] [2022-11-16 12:34:06,729 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465863723] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:06,729 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:06,729 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:06,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539632764] [2022-11-16 12:34:06,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:06,730 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:06,730 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:06,731 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:06,731 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:06,731 INFO L87 Difference]: Start difference. First operand 924 states and 1372 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:06,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:06,796 INFO L93 Difference]: Finished difference Result 924 states and 1367 transitions. [2022-11-16 12:34:06,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1367 transitions. [2022-11-16 12:34:06,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:06,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1367 transitions. [2022-11-16 12:34:06,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-11-16 12:34:06,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-11-16 12:34:06,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1367 transitions. [2022-11-16 12:34:06,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:06,811 INFO L218 hiAutomatonCegarLoop]: Abstraction has 924 states and 1367 transitions. [2022-11-16 12:34:06,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1367 transitions. [2022-11-16 12:34:06,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-11-16 12:34:06,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4794372294372293) internal successors, (1367), 923 states have internal predecessors, (1367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:06,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1367 transitions. [2022-11-16 12:34:06,834 INFO L240 hiAutomatonCegarLoop]: Abstraction has 924 states and 1367 transitions. [2022-11-16 12:34:06,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:06,835 INFO L428 stractBuchiCegarLoop]: Abstraction has 924 states and 1367 transitions. [2022-11-16 12:34:06,835 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 12:34:06,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1367 transitions. [2022-11-16 12:34:06,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-11-16 12:34:06,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:06,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:06,845 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:06,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:06,846 INFO L748 eck$LassoCheckResult]: Stem: 17386#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 17387#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17629#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16801#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16802#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 17073#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17074#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17571#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17561#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17141#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17142#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17367#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17368#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 17223#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17224#L838 assume !(0 == ~M_E~0); 17374#L838-2 assume !(0 == ~T1_E~0); 16763#L843-1 assume !(0 == ~T2_E~0); 16764#L848-1 assume !(0 == ~T3_E~0); 16883#L853-1 assume !(0 == ~T4_E~0); 17211#L858-1 assume !(0 == ~T5_E~0); 16710#L863-1 assume !(0 == ~T6_E~0); 16711#L868-1 assume !(0 == ~T7_E~0); 17603#L873-1 assume !(0 == ~T8_E~0); 17601#L878-1 assume !(0 == ~E_1~0); 17590#L883-1 assume !(0 == ~E_2~0); 17591#L888-1 assume !(0 == ~E_3~0); 17338#L893-1 assume !(0 == ~E_4~0); 17339#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17615#L903-1 assume !(0 == ~E_6~0); 17589#L908-1 assume !(0 == ~E_7~0); 17463#L913-1 assume !(0 == ~E_8~0); 16777#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16778#L402 assume !(1 == ~m_pc~0); 16988#L402-2 is_master_triggered_~__retres1~0#1 := 0; 16904#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16905#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17147#L1035 assume !(0 != activate_threads_~tmp~1#1); 17148#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17200#L421 assume 1 == ~t1_pc~0; 17585#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17604#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17192#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17193#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 17252#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17612#L440 assume 1 == ~t2_pc~0; 16747#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16748#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16914#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17623#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 17477#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17105#L459 assume !(1 == ~t3_pc~0); 17106#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17584#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17409#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16898#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16899#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16908#L478 assume 1 == ~t4_pc~0; 16909#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17343#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17570#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17079#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 16824#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16825#L497 assume !(1 == ~t5_pc~0); 16869#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16870#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17161#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17162#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 17577#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17578#L516 assume 1 == ~t6_pc~0; 17632#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17364#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17365#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16953#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 16954#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17355#L535 assume !(1 == ~t7_pc~0); 17356#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17425#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17426#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17454#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 17444#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17445#L554 assume 1 == ~t8_pc~0; 17394#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16739#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17495#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17044#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 17045#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16723#L931 assume !(1 == ~M_E~0); 16724#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17598#L936-1 assume !(1 == ~T2_E~0); 17621#L941-1 assume !(1 == ~T3_E~0); 17201#L946-1 assume !(1 == ~T4_E~0); 17202#L951-1 assume !(1 == ~T5_E~0); 16968#L956-1 assume !(1 == ~T6_E~0); 16969#L961-1 assume !(1 == ~T7_E~0); 17340#L966-1 assume !(1 == ~T8_E~0); 17341#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17447#L976-1 assume !(1 == ~E_2~0); 17417#L981-1 assume !(1 == ~E_3~0); 17206#L986-1 assume !(1 == ~E_4~0); 16998#L991-1 assume !(1 == ~E_5~0); 16999#L996-1 assume !(1 == ~E_6~0); 17608#L1001-1 assume !(1 == ~E_7~0); 17384#L1006-1 assume !(1 == ~E_8~0); 17385#L1011-1 assume { :end_inline_reset_delta_events } true; 16786#L1272-2 [2022-11-16 12:34:06,847 INFO L750 eck$LassoCheckResult]: Loop: 16786#L1272-2 assume !false; 16787#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16788#L813 assume !false; 16789#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17535#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16791#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17335#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17345#L696 assume !(0 != eval_~tmp~0#1); 17388#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17389#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17512#L838-3 assume !(0 == ~M_E~0); 17430#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17431#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17293#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17294#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17342#L858-3 assume !(0 == ~T5_E~0); 17405#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17397#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17398#L873-3 assume !(0 == ~T8_E~0); 17023#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16750#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16751#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16752#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16753#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17229#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17538#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17240#L913-3 assume !(0 == ~E_8~0); 16793#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16794#L402-27 assume 1 == ~m_pc~0; 16740#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16741#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17234#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17235#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17550#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17551#L421-27 assume !(1 == ~t1_pc~0); 17013#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 17014#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17263#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17264#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17609#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17358#L440-27 assume !(1 == ~t2_pc~0); 17360#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 17532#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17097#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17098#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17272#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17001#L459-27 assume !(1 == ~t3_pc~0); 17002#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 17420#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17065#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17066#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17354#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17602#L478-27 assume 1 == ~t4_pc~0; 17624#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16992#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17366#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17498#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17499#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17536#L497-27 assume !(1 == ~t5_pc~0); 17153#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 17030#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17031#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16974#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16975#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17230#L516-27 assume !(1 == ~t6_pc~0); 17232#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 17080#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17081#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17233#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17375#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17164#L535-27 assume 1 == ~t7_pc~0; 17165#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17480#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17510#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17511#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17116#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17117#L554-27 assume 1 == ~t8_pc~0; 17315#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16768#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16913#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17251#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 17018#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17019#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16894#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16895#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17115#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17247#L946-3 assume !(1 == ~T4_E~0); 17036#L951-3 assume !(1 == ~T5_E~0); 17037#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17316#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17125#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17126#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17363#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16784#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16785#L986-3 assume !(1 == ~E_4~0); 16775#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16776#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17435#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17103#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17104#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16817#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16819#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17133#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 17134#L1291 assume !(0 == start_simulation_~tmp~3#1); 17313#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17218#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16714#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16715#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 17519#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17183#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17184#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 17400#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 16786#L1272-2 [2022-11-16 12:34:06,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:06,847 INFO L85 PathProgramCache]: Analyzing trace with hash 623392352, now seen corresponding path program 1 times [2022-11-16 12:34:06,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:06,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882374965] [2022-11-16 12:34:06,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:06,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:06,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:06,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:06,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:06,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882374965] [2022-11-16 12:34:06,958 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1882374965] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:06,958 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:06,958 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:06,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272940161] [2022-11-16 12:34:06,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:06,960 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:06,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:06,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1529828160, now seen corresponding path program 1 times [2022-11-16 12:34:06,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:06,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323489278] [2022-11-16 12:34:06,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:06,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:06,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:07,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:07,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:07,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323489278] [2022-11-16 12:34:07,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323489278] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:07,017 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:07,017 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:07,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227429043] [2022-11-16 12:34:07,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:07,018 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:07,018 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:07,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:34:07,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:34:07,019 INFO L87 Difference]: Start difference. First operand 924 states and 1367 transitions. cyclomatic complexity: 444 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:07,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:07,250 INFO L93 Difference]: Finished difference Result 1686 states and 2493 transitions. [2022-11-16 12:34:07,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1686 states and 2493 transitions. [2022-11-16 12:34:07,261 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1557 [2022-11-16 12:34:07,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1686 states to 1686 states and 2493 transitions. [2022-11-16 12:34:07,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1686 [2022-11-16 12:34:07,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1686 [2022-11-16 12:34:07,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1686 states and 2493 transitions. [2022-11-16 12:34:07,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:07,276 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1686 states and 2493 transitions. [2022-11-16 12:34:07,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1686 states and 2493 transitions. [2022-11-16 12:34:07,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1686 to 1685. [2022-11-16 12:34:07,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1685 states, 1685 states have (on average 1.4789317507418398) internal successors, (2492), 1684 states have internal predecessors, (2492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:07,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1685 states to 1685 states and 2492 transitions. [2022-11-16 12:34:07,324 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1685 states and 2492 transitions. [2022-11-16 12:34:07,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:34:07,325 INFO L428 stractBuchiCegarLoop]: Abstraction has 1685 states and 2492 transitions. [2022-11-16 12:34:07,325 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 12:34:07,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1685 states and 2492 transitions. [2022-11-16 12:34:07,333 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1557 [2022-11-16 12:34:07,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:07,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:07,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:07,335 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:07,335 INFO L748 eck$LassoCheckResult]: Stem: 20014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 20015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20297#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19421#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19422#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 19694#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19695#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20226#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20213#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19762#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19763#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19993#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19994#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19844#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19845#L838 assume !(0 == ~M_E~0); 20000#L838-2 assume !(0 == ~T1_E~0); 19383#L843-1 assume !(0 == ~T2_E~0); 19384#L848-1 assume !(0 == ~T3_E~0); 19504#L853-1 assume !(0 == ~T4_E~0); 19830#L858-1 assume !(0 == ~T5_E~0); 19330#L863-1 assume !(0 == ~T6_E~0); 19331#L868-1 assume !(0 == ~T7_E~0); 20266#L873-1 assume !(0 == ~T8_E~0); 20264#L878-1 assume !(0 == ~E_1~0); 20249#L883-1 assume !(0 == ~E_2~0); 20250#L888-1 assume !(0 == ~E_3~0); 19964#L893-1 assume !(0 == ~E_4~0); 19965#L898-1 assume !(0 == ~E_5~0); 20281#L903-1 assume !(0 == ~E_6~0); 20248#L908-1 assume !(0 == ~E_7~0); 20098#L913-1 assume !(0 == ~E_8~0); 19397#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19398#L402 assume !(1 == ~m_pc~0); 19607#L402-2 is_master_triggered_~__retres1~0#1 := 0; 19525#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19526#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19768#L1035 assume !(0 != activate_threads_~tmp~1#1); 19769#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19821#L421 assume 1 == ~t1_pc~0; 20244#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20268#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19813#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19814#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 19872#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20276#L440 assume 1 == ~t2_pc~0; 19367#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19368#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19535#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20290#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 20115#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19722#L459 assume !(1 == ~t3_pc~0); 19723#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20240#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20038#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19519#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19520#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19529#L478 assume 1 == ~t4_pc~0; 19530#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19969#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20225#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19700#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 19442#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19443#L497 assume !(1 == ~t5_pc~0); 19489#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19490#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19782#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19783#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 20232#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20233#L516 assume 1 == ~t6_pc~0; 20303#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19991#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19992#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19574#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 19575#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19982#L535 assume !(1 == ~t7_pc~0); 19983#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20057#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20058#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20089#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 20079#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20080#L554 assume 1 == ~t8_pc~0; 20022#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19359#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20135#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19662#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 19663#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19343#L931 assume !(1 == ~M_E~0); 19344#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20259#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20287#L941-1 assume !(1 == ~T3_E~0); 20782#L946-1 assume !(1 == ~T4_E~0); 20241#L951-1 assume !(1 == ~T5_E~0); 19589#L956-1 assume !(1 == ~T6_E~0); 19590#L961-1 assume !(1 == ~T7_E~0); 19966#L966-1 assume !(1 == ~T8_E~0); 19967#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20082#L976-1 assume !(1 == ~E_2~0); 20049#L981-1 assume !(1 == ~E_3~0); 19827#L986-1 assume !(1 == ~E_4~0); 19619#L991-1 assume !(1 == ~E_5~0); 19620#L996-1 assume !(1 == ~E_6~0); 20272#L1001-1 assume !(1 == ~E_7~0); 20012#L1006-1 assume !(1 == ~E_8~0); 20013#L1011-1 assume { :end_inline_reset_delta_events } true; 20324#L1272-2 [2022-11-16 12:34:07,336 INFO L750 eck$LassoCheckResult]: Loop: 20324#L1272-2 assume !false; 20004#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19408#L813 assume !false; 19409#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20316#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19960#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19961#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20190#L696 assume !(0 != eval_~tmp~0#1); 20016#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20017#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20218#L838-3 assume !(0 == ~M_E~0); 20219#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20305#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20306#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21014#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21013#L858-3 assume !(0 == ~T5_E~0); 21012#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21011#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21010#L873-3 assume !(0 == ~T8_E~0); 21009#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21008#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21007#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21006#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21005#L898-3 assume !(0 == ~E_5~0); 21004#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21003#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21002#L913-3 assume !(0 == ~E_8~0); 21001#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21000#L402-27 assume 1 == ~m_pc~0; 20998#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20997#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20996#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20995#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20994#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20993#L421-27 assume !(1 == ~t1_pc~0); 20992#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 20990#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20989#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20988#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20987#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20986#L440-27 assume 1 == ~t2_pc~0; 20984#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20983#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20982#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20981#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20980#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20979#L459-27 assume !(1 == ~t3_pc~0); 20977#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 20976#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20975#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20974#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20973#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20972#L478-27 assume 1 == ~t4_pc~0; 20970#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20969#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20968#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20967#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20966#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20965#L497-27 assume !(1 == ~t5_pc~0); 20963#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 20962#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20961#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20960#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20959#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20958#L516-27 assume 1 == ~t6_pc~0; 19908#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19708#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19709#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19856#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20002#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19785#L535-27 assume 1 == ~t7_pc~0; 19786#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20119#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20153#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20154#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19739#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19740#L554-27 assume 1 == ~t8_pc~0; 19939#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19388#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19534#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19873#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 19639#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19640#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19515#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19516#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19736#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19868#L946-3 assume !(1 == ~T4_E~0); 19657#L951-3 assume !(1 == ~T5_E~0); 19658#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19940#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19746#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19747#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19990#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19404#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19405#L986-3 assume !(1 == ~E_4~0); 19395#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19396#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20068#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19727#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19728#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19437#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19439#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19754#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19755#L1291 assume !(0 == start_simulation_~tmp~3#1); 19937#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19840#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19334#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19335#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 20161#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20337#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20028#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20029#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 20324#L1272-2 [2022-11-16 12:34:07,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:07,336 INFO L85 PathProgramCache]: Analyzing trace with hash 1671526308, now seen corresponding path program 1 times [2022-11-16 12:34:07,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:07,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184968255] [2022-11-16 12:34:07,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:07,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:07,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:07,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:07,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:07,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184968255] [2022-11-16 12:34:07,419 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184968255] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:07,419 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:07,419 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:07,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521390700] [2022-11-16 12:34:07,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:07,420 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:07,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:07,420 INFO L85 PathProgramCache]: Analyzing trace with hash -188324604, now seen corresponding path program 1 times [2022-11-16 12:34:07,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:07,421 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771732244] [2022-11-16 12:34:07,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:07,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:07,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:07,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:07,483 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:07,483 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771732244] [2022-11-16 12:34:07,483 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771732244] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:07,483 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:07,483 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:07,483 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946856370] [2022-11-16 12:34:07,484 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:07,484 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:07,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:07,485 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:34:07,485 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:34:07,485 INFO L87 Difference]: Start difference. First operand 1685 states and 2492 transitions. cyclomatic complexity: 809 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:07,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:07,823 INFO L93 Difference]: Finished difference Result 4590 states and 6693 transitions. [2022-11-16 12:34:07,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4590 states and 6693 transitions. [2022-11-16 12:34:07,853 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4320 [2022-11-16 12:34:07,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4590 states to 4590 states and 6693 transitions. [2022-11-16 12:34:07,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4590 [2022-11-16 12:34:07,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4590 [2022-11-16 12:34:07,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4590 states and 6693 transitions. [2022-11-16 12:34:07,897 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:07,898 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4590 states and 6693 transitions. [2022-11-16 12:34:07,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4590 states and 6693 transitions. [2022-11-16 12:34:07,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4590 to 4342. [2022-11-16 12:34:07,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4342 states, 4342 states have (on average 1.4631506218332566) internal successors, (6353), 4341 states have internal predecessors, (6353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:08,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4342 states to 4342 states and 6353 transitions. [2022-11-16 12:34:08,014 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4342 states and 6353 transitions. [2022-11-16 12:34:08,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:34:08,015 INFO L428 stractBuchiCegarLoop]: Abstraction has 4342 states and 6353 transitions. [2022-11-16 12:34:08,015 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 12:34:08,016 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4342 states and 6353 transitions. [2022-11-16 12:34:08,061 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4206 [2022-11-16 12:34:08,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:08,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:08,063 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:08,064 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:08,064 INFO L748 eck$LassoCheckResult]: Stem: 26328#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 26329#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 26666#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25708#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25709#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 25980#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25981#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26567#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26551#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26052#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26053#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26305#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26306#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26144#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26145#L838 assume !(0 == ~M_E~0); 26313#L838-2 assume !(0 == ~T1_E~0); 25670#L843-1 assume !(0 == ~T2_E~0); 25671#L848-1 assume !(0 == ~T3_E~0); 25789#L853-1 assume !(0 == ~T4_E~0); 26130#L858-1 assume !(0 == ~T5_E~0); 25615#L863-1 assume !(0 == ~T6_E~0); 25616#L868-1 assume !(0 == ~T7_E~0); 26624#L873-1 assume !(0 == ~T8_E~0); 26621#L878-1 assume !(0 == ~E_1~0); 26596#L883-1 assume !(0 == ~E_2~0); 26597#L888-1 assume !(0 == ~E_3~0); 26275#L893-1 assume !(0 == ~E_4~0); 26276#L898-1 assume !(0 == ~E_5~0); 26640#L903-1 assume !(0 == ~E_6~0); 26595#L908-1 assume !(0 == ~E_7~0); 26416#L913-1 assume !(0 == ~E_8~0); 25684#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25685#L402 assume !(1 == ~m_pc~0); 26106#L402-2 is_master_triggered_~__retres1~0#1 := 0; 25811#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25812#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26059#L1035 assume !(0 != activate_threads_~tmp~1#1); 26060#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26120#L421 assume !(1 == ~t1_pc~0); 26591#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26625#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26109#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26110#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 26177#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26635#L440 assume 1 == ~t2_pc~0; 25654#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25655#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25821#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26652#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 26433#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26011#L459 assume !(1 == ~t3_pc~0); 26012#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26589#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26351#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25804#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25805#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25815#L478 assume 1 == ~t4_pc~0; 25816#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26279#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26566#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25986#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 25728#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25729#L497 assume !(1 == ~t5_pc~0); 25775#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25776#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26074#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26075#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 26579#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26580#L516 assume 1 == ~t6_pc~0; 26683#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26303#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26304#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25861#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 25862#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26294#L535 assume !(1 == ~t7_pc~0); 26295#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26369#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26370#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26405#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 26395#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26396#L554 assume 1 == ~t8_pc~0; 26336#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25644#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26454#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25947#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 25948#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25628#L931 assume !(1 == ~M_E~0); 25629#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26612#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26649#L941-1 assume !(1 == ~T3_E~0); 26121#L946-1 assume !(1 == ~T4_E~0); 26122#L951-1 assume !(1 == ~T5_E~0); 25877#L956-1 assume !(1 == ~T6_E~0); 25878#L961-1 assume !(1 == ~T7_E~0); 26277#L966-1 assume !(1 == ~T8_E~0); 26278#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26399#L976-1 assume !(1 == ~E_2~0); 26361#L981-1 assume !(1 == ~E_3~0); 26126#L986-1 assume !(1 == ~E_4~0); 26127#L991-1 assume !(1 == ~E_5~0); 25906#L996-1 assume !(1 == ~E_6~0); 26630#L1001-1 assume !(1 == ~E_7~0); 26326#L1006-1 assume !(1 == ~E_8~0); 26327#L1011-1 assume { :end_inline_reset_delta_events } true; 25693#L1272-2 [2022-11-16 12:34:08,065 INFO L750 eck$LassoCheckResult]: Loop: 25693#L1272-2 assume !false; 25694#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25695#L813 assume !false; 25696#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26511#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25698#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 27751#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27749#L696 assume !(0 != eval_~tmp~0#1); 27748#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27746#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27744#L838-3 assume !(0 == ~M_E~0); 27742#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27739#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27740#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27734#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27735#L858-3 assume !(0 == ~T5_E~0); 27728#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27729#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27721#L873-3 assume !(0 == ~T8_E~0); 27722#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27715#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27716#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27709#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27710#L898-3 assume !(0 == ~E_5~0); 27702#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27703#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27696#L913-3 assume !(0 == ~E_8~0); 27697#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27689#L402-27 assume !(1 == ~m_pc~0); 27690#L402-29 is_master_triggered_~__retres1~0#1 := 0; 27682#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27683#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27678#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27679#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26562#L421-27 assume !(1 == ~t1_pc~0); 25919#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 25920#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26188#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26189#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26631#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26297#L440-27 assume 1 == ~t2_pc~0; 26298#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29862#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29860#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29861#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26311#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25909#L459-27 assume !(1 == ~t3_pc~0); 25910#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 26364#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25971#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25972#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26293#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26622#L478-27 assume 1 == ~t4_pc~0; 26658#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25899#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26307#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26460#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26461#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26513#L497-27 assume !(1 == ~t5_pc~0); 26514#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 29880#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29879#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29878#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29877#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29876#L516-27 assume 1 == ~t6_pc~0; 29874#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29832#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26154#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26155#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26315#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26076#L535-27 assume 1 == ~t7_pc~0; 26077#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26437#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29816#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26659#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26025#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26026#L554-27 assume 1 == ~t8_pc~0; 26246#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25675#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25820#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26176#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 25924#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25925#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25800#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25801#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26024#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26171#L946-3 assume !(1 == ~T4_E~0); 25942#L951-3 assume !(1 == ~T5_E~0); 25943#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26247#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26036#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26037#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26302#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25691#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25692#L986-3 assume !(1 == ~E_4~0); 25682#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25683#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29636#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29635#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29633#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 29631#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 29621#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 29619#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 29616#L1291 assume !(0 == start_simulation_~tmp~3#1); 27943#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 27800#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 27797#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 27795#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 26602#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26098#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26099#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 26342#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 25693#L1272-2 [2022-11-16 12:34:08,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:08,066 INFO L85 PathProgramCache]: Analyzing trace with hash 493551747, now seen corresponding path program 1 times [2022-11-16 12:34:08,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:08,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493624357] [2022-11-16 12:34:08,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:08,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:08,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:08,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:08,152 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:08,152 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [493624357] [2022-11-16 12:34:08,152 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [493624357] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:08,152 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:08,152 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:08,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220800182] [2022-11-16 12:34:08,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:08,153 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:08,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:08,154 INFO L85 PathProgramCache]: Analyzing trace with hash -643230685, now seen corresponding path program 1 times [2022-11-16 12:34:08,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:08,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907456528] [2022-11-16 12:34:08,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:08,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:08,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:08,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:08,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:08,217 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907456528] [2022-11-16 12:34:08,217 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [907456528] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:08,217 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:08,217 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:08,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872044624] [2022-11-16 12:34:08,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:08,218 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:08,218 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:08,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:34:08,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:34:08,219 INFO L87 Difference]: Start difference. First operand 4342 states and 6353 transitions. cyclomatic complexity: 2015 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:08,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:08,566 INFO L93 Difference]: Finished difference Result 12155 states and 17606 transitions. [2022-11-16 12:34:08,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12155 states and 17606 transitions. [2022-11-16 12:34:08,645 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11706 [2022-11-16 12:34:08,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12155 states to 12155 states and 17606 transitions. [2022-11-16 12:34:08,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12155 [2022-11-16 12:34:08,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12155 [2022-11-16 12:34:08,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12155 states and 17606 transitions. [2022-11-16 12:34:08,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:08,763 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12155 states and 17606 transitions. [2022-11-16 12:34:08,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12155 states and 17606 transitions. [2022-11-16 12:34:09,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12155 to 11561. [2022-11-16 12:34:09,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11561 states, 11561 states have (on average 1.4531614912204827) internal successors, (16800), 11560 states have internal predecessors, (16800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:09,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11561 states to 11561 states and 16800 transitions. [2022-11-16 12:34:09,371 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11561 states and 16800 transitions. [2022-11-16 12:34:09,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:34:09,375 INFO L428 stractBuchiCegarLoop]: Abstraction has 11561 states and 16800 transitions. [2022-11-16 12:34:09,375 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 12:34:09,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11561 states and 16800 transitions. [2022-11-16 12:34:09,424 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11406 [2022-11-16 12:34:09,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:09,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:09,426 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:09,426 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:09,426 INFO L748 eck$LassoCheckResult]: Stem: 42821#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 42822#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 43151#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42212#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42213#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 42483#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42484#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43049#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43039#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42556#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42557#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42800#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42801#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42643#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42644#L838 assume !(0 == ~M_E~0); 42807#L838-2 assume !(0 == ~T1_E~0); 42174#L843-1 assume !(0 == ~T2_E~0); 42175#L848-1 assume !(0 == ~T3_E~0); 42292#L853-1 assume !(0 == ~T4_E~0); 42630#L858-1 assume !(0 == ~T5_E~0); 42124#L863-1 assume !(0 == ~T6_E~0); 42125#L868-1 assume !(0 == ~T7_E~0); 43108#L873-1 assume !(0 == ~T8_E~0); 43102#L878-1 assume !(0 == ~E_1~0); 43078#L883-1 assume !(0 == ~E_2~0); 43079#L888-1 assume !(0 == ~E_3~0); 42771#L893-1 assume !(0 == ~E_4~0); 42772#L898-1 assume !(0 == ~E_5~0); 43127#L903-1 assume !(0 == ~E_6~0); 43076#L908-1 assume !(0 == ~E_7~0); 42912#L913-1 assume !(0 == ~E_8~0); 42188#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42189#L402 assume !(1 == ~m_pc~0); 42608#L402-2 is_master_triggered_~__retres1~0#1 := 0; 42314#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42315#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42562#L1035 assume !(0 != activate_threads_~tmp~1#1); 42563#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42619#L421 assume !(1 == ~t1_pc~0); 43070#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43112#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42611#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42612#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 42677#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43120#L440 assume !(1 == ~t2_pc~0); 43168#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42324#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42325#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43142#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 42925#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42516#L459 assume !(1 == ~t3_pc~0); 42517#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43066#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42849#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42307#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42308#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42318#L478 assume 1 == ~t4_pc~0; 42319#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42775#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43048#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42489#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 42234#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42235#L497 assume !(1 == ~t5_pc~0); 42278#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 42279#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42578#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42579#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 43059#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43060#L516 assume 1 == ~t6_pc~0; 43164#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42796#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42797#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42363#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 42364#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42788#L535 assume !(1 == ~t7_pc~0); 42789#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 42867#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42868#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42900#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 42889#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42890#L554 assume 1 == ~t8_pc~0; 42831#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42151#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42946#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42454#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 42455#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42135#L931 assume !(1 == ~M_E~0); 42136#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43095#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43138#L941-1 assume !(1 == ~T3_E~0); 42620#L946-1 assume !(1 == ~T4_E~0); 42621#L951-1 assume !(1 == ~T5_E~0); 42380#L956-1 assume !(1 == ~T6_E~0); 42381#L961-1 assume !(1 == ~T7_E~0); 42773#L966-1 assume !(1 == ~T8_E~0); 42774#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 49321#L976-1 assume !(1 == ~E_2~0); 49319#L981-1 assume !(1 == ~E_3~0); 42625#L986-1 assume !(1 == ~E_4~0); 42410#L991-1 assume !(1 == ~E_5~0); 42411#L996-1 assume !(1 == ~E_6~0); 43116#L1001-1 assume !(1 == ~E_7~0); 42819#L1006-1 assume !(1 == ~E_8~0); 42820#L1011-1 assume { :end_inline_reset_delta_events } true; 42199#L1272-2 [2022-11-16 12:34:09,427 INFO L750 eck$LassoCheckResult]: Loop: 42199#L1272-2 assume !false; 42200#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42197#L813 assume !false; 42198#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 43001#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 42202#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 42767#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42777#L696 assume !(0 != eval_~tmp~0#1); 43011#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52890#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52887#L838-3 assume !(0 == ~M_E~0); 52885#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52883#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52881#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52879#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52877#L858-3 assume !(0 == ~T5_E~0); 52874#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52872#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52870#L873-3 assume !(0 == ~T8_E~0); 52868#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52866#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52865#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52864#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52860#L898-3 assume !(0 == ~E_5~0); 52859#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52858#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 52857#L913-3 assume !(0 == ~E_8~0); 52856#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52855#L402-27 assume !(1 == ~m_pc~0); 52853#L402-29 is_master_triggered_~__retres1~0#1 := 0; 52851#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52849#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 52847#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52845#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52843#L421-27 assume !(1 == ~t1_pc~0); 52841#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 52839#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52837#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 52835#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52834#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52833#L440-27 assume !(1 == ~t2_pc~0); 52821#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 52819#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52817#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52815#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52813#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52811#L459-27 assume !(1 == ~t3_pc~0); 52808#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 52806#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52804#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52802#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43103#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43104#L478-27 assume !(1 == ~t4_pc~0); 42401#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 42402#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43166#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42952#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42953#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43003#L497-27 assume !(1 == ~t5_pc~0); 42570#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 42439#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42440#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42386#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42387#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42652#L516-27 assume 1 == ~t6_pc~0; 42653#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42491#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42492#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42655#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42808#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42581#L535-27 assume 1 == ~t7_pc~0; 42582#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42929#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42968#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42969#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42529#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42530#L554-27 assume !(1 == ~t8_pc~0); 42178#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 42179#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42323#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42676#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 42428#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42429#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42303#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42304#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42526#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42672#L946-3 assume !(1 == ~T4_E~0); 42446#L951-3 assume !(1 == ~T5_E~0); 42447#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42743#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42540#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42541#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42795#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42195#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42196#L986-3 assume !(1 == ~E_4~0); 42186#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42187#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42878#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43005#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42917#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 42227#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 42229#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 42548#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 42549#L1291 assume !(0 == start_simulation_~tmp~3#1); 42740#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 42637#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 42126#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 42127#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 42979#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42601#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42602#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 42837#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 42199#L1272-2 [2022-11-16 12:34:09,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:09,428 INFO L85 PathProgramCache]: Analyzing trace with hash -1412932446, now seen corresponding path program 1 times [2022-11-16 12:34:09,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:09,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205750373] [2022-11-16 12:34:09,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:09,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:09,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:09,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:09,506 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:09,507 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205750373] [2022-11-16 12:34:09,507 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205750373] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:09,507 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:09,507 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:34:09,507 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779705800] [2022-11-16 12:34:09,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:09,508 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:09,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:09,508 INFO L85 PathProgramCache]: Analyzing trace with hash -504979712, now seen corresponding path program 1 times [2022-11-16 12:34:09,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:09,509 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27149327] [2022-11-16 12:34:09,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:09,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:09,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:09,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:09,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:09,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [27149327] [2022-11-16 12:34:09,560 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [27149327] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:09,560 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:09,561 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:09,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1354673319] [2022-11-16 12:34:09,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:09,561 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:09,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:09,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:34:09,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:34:09,563 INFO L87 Difference]: Start difference. First operand 11561 states and 16800 transitions. cyclomatic complexity: 5247 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:10,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:10,072 INFO L93 Difference]: Finished difference Result 30699 states and 44801 transitions. [2022-11-16 12:34:10,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30699 states and 44801 transitions. [2022-11-16 12:34:10,251 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 30349 [2022-11-16 12:34:10,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30699 states to 30699 states and 44801 transitions. [2022-11-16 12:34:10,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30699 [2022-11-16 12:34:10,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30699 [2022-11-16 12:34:10,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30699 states and 44801 transitions. [2022-11-16 12:34:10,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:10,611 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30699 states and 44801 transitions. [2022-11-16 12:34:10,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30699 states and 44801 transitions. [2022-11-16 12:34:11,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30699 to 11975. [2022-11-16 12:34:11,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11975 states, 11975 states have (on average 1.4374947807933194) internal successors, (17214), 11974 states have internal predecessors, (17214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:11,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11975 states to 11975 states and 17214 transitions. [2022-11-16 12:34:11,091 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11975 states and 17214 transitions. [2022-11-16 12:34:11,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 12:34:11,093 INFO L428 stractBuchiCegarLoop]: Abstraction has 11975 states and 17214 transitions. [2022-11-16 12:34:11,093 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 12:34:11,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11975 states and 17214 transitions. [2022-11-16 12:34:11,154 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11817 [2022-11-16 12:34:11,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:11,154 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:11,157 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:11,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:11,157 INFO L748 eck$LassoCheckResult]: Stem: 85128#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 85129#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 85539#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84486#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84487#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 84765#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84766#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85395#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85375#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84843#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84844#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85107#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85108#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84929#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84930#L838 assume !(0 == ~M_E~0); 85115#L838-2 assume !(0 == ~T1_E~0); 84447#L843-1 assume !(0 == ~T2_E~0); 84448#L848-1 assume !(0 == ~T3_E~0); 84567#L853-1 assume !(0 == ~T4_E~0); 84917#L858-1 assume !(0 == ~T5_E~0); 84395#L863-1 assume !(0 == ~T6_E~0); 84396#L868-1 assume !(0 == ~T7_E~0); 85469#L873-1 assume !(0 == ~T8_E~0); 85464#L878-1 assume !(0 == ~E_1~0); 85432#L883-1 assume !(0 == ~E_2~0); 85433#L888-1 assume !(0 == ~E_3~0); 85076#L893-1 assume !(0 == ~E_4~0); 85077#L898-1 assume !(0 == ~E_5~0); 85494#L903-1 assume !(0 == ~E_6~0); 85429#L908-1 assume !(0 == ~E_7~0); 85227#L913-1 assume !(0 == ~E_8~0); 84462#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84463#L402 assume !(1 == ~m_pc~0); 84893#L402-2 is_master_triggered_~__retres1~0#1 := 0; 84589#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84590#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84850#L1035 assume !(0 != activate_threads_~tmp~1#1); 84851#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84905#L421 assume !(1 == ~t1_pc~0); 85419#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 85474#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84897#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 84898#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 84961#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85488#L440 assume !(1 == ~t2_pc~0); 85574#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 84600#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84601#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 85517#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 85243#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84800#L459 assume !(1 == ~t3_pc~0); 84801#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85414#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85487#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84582#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 84583#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84593#L478 assume 1 == ~t4_pc~0; 84594#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85080#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85394#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 84771#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 84508#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84509#L497 assume !(1 == ~t5_pc~0); 84553#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 84554#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84864#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 84865#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 85407#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85408#L516 assume 1 == ~t6_pc~0; 85560#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85104#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85105#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84640#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 84641#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85096#L535 assume !(1 == ~t7_pc~0); 85097#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85182#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85183#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85216#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 85205#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85206#L554 assume 1 == ~t8_pc~0; 85138#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84424#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85267#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84735#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 84736#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84408#L931 assume !(1 == ~M_E~0); 84409#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85454#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85511#L941-1 assume !(1 == ~T3_E~0); 85572#L946-1 assume !(1 == ~T4_E~0); 85415#L951-1 assume !(1 == ~T5_E~0); 84659#L956-1 assume !(1 == ~T6_E~0); 84660#L961-1 assume !(1 == ~T7_E~0); 85078#L966-1 assume !(1 == ~T8_E~0); 85079#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 85210#L976-1 assume !(1 == ~E_2~0); 89949#L981-1 assume !(1 == ~E_3~0); 84911#L986-1 assume !(1 == ~E_4~0); 84912#L991-1 assume !(1 == ~E_5~0); 84690#L996-1 assume !(1 == ~E_6~0); 85542#L1001-1 assume !(1 == ~E_7~0); 85126#L1006-1 assume !(1 == ~E_8~0); 85127#L1011-1 assume { :end_inline_reset_delta_events } true; 89948#L1272-2 [2022-11-16 12:34:11,158 INFO L750 eck$LassoCheckResult]: Loop: 89948#L1272-2 assume !false; 92306#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92303#L813 assume !false; 92302#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 92300#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 92292#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 92291#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 92289#L696 assume !(0 != eval_~tmp~0#1); 92290#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90778#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90779#L838-3 assume !(0 == ~M_E~0); 90772#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 90773#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 90765#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 90766#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90759#L858-3 assume !(0 == ~T5_E~0); 90760#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 90753#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 90754#L873-3 assume !(0 == ~T8_E~0); 90746#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 90747#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 90740#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 90741#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 90734#L898-3 assume !(0 == ~E_5~0); 90735#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 90727#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 90728#L913-3 assume !(0 == ~E_8~0); 90721#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90722#L402-27 assume !(1 == ~m_pc~0); 90717#L402-29 is_master_triggered_~__retres1~0#1 := 0; 90718#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90713#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 90714#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 90709#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 90710#L421-27 assume !(1 == ~t1_pc~0); 90706#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 90707#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90702#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 90703#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 90698#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90699#L440-27 assume !(1 == ~t2_pc~0); 90694#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 90695#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90690#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 90691#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 90686#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 90687#L459-27 assume 1 == ~t3_pc~0; 90679#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 90681#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90671#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 90672#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 93040#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93039#L478-27 assume 1 == ~t4_pc~0; 93037#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 93036#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93035#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 93034#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 93033#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 93032#L497-27 assume 1 == ~t5_pc~0; 93031#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 93029#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93028#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 93027#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 93026#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 93025#L516-27 assume !(1 == ~t6_pc~0); 93024#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 93022#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 93021#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 93020#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 93019#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 93018#L535-27 assume 1 == ~t7_pc~0; 93017#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 93015#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 93014#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 93013#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 93012#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 93011#L554-27 assume 1 == ~t8_pc~0; 93009#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 93008#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 93007#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90597#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 90598#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90591#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 90592#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 90052#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90048#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90045#L946-3 assume !(1 == ~T4_E~0); 90043#L951-3 assume !(1 == ~T5_E~0); 90041#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 90039#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 90037#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 90035#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 90031#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 90032#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 90025#L986-3 assume !(1 == ~E_4~0); 90026#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 92343#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 92342#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 92341#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 92340#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 92339#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 92330#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 92329#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 92327#L1291 assume !(0 == start_simulation_~tmp~3#1); 92326#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 92317#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 92316#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 92315#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 92314#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 92313#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 92312#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 92311#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 89948#L1272-2 [2022-11-16 12:34:11,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:11,159 INFO L85 PathProgramCache]: Analyzing trace with hash -1894012704, now seen corresponding path program 1 times [2022-11-16 12:34:11,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:11,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949612245] [2022-11-16 12:34:11,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:11,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:11,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:11,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:11,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:11,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949612245] [2022-11-16 12:34:11,268 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [949612245] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:11,268 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:11,268 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:34:11,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193768823] [2022-11-16 12:34:11,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:11,271 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:11,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:11,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1379361827, now seen corresponding path program 1 times [2022-11-16 12:34:11,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:11,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173529456] [2022-11-16 12:34:11,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:11,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:11,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:11,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:11,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:11,366 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173529456] [2022-11-16 12:34:11,366 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1173529456] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:11,366 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:11,367 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:11,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285283612] [2022-11-16 12:34:11,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:11,368 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:11,368 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:11,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:11,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:11,369 INFO L87 Difference]: Start difference. First operand 11975 states and 17214 transitions. cyclomatic complexity: 5247 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:11,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:11,711 INFO L93 Difference]: Finished difference Result 23080 states and 33008 transitions. [2022-11-16 12:34:11,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23080 states and 33008 transitions. [2022-11-16 12:34:11,857 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22857 [2022-11-16 12:34:11,935 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23080 states to 23080 states and 33008 transitions. [2022-11-16 12:34:11,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23080 [2022-11-16 12:34:11,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23080 [2022-11-16 12:34:11,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23080 states and 33008 transitions. [2022-11-16 12:34:11,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:11,976 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23080 states and 33008 transitions. [2022-11-16 12:34:11,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23080 states and 33008 transitions. [2022-11-16 12:34:12,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23080 to 23044. [2022-11-16 12:34:12,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23044 states, 23044 states have (on average 1.4308279812532547) internal successors, (32972), 23043 states have internal predecessors, (32972), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:12,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23044 states to 23044 states and 32972 transitions. [2022-11-16 12:34:12,513 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23044 states and 32972 transitions. [2022-11-16 12:34:12,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:12,514 INFO L428 stractBuchiCegarLoop]: Abstraction has 23044 states and 32972 transitions. [2022-11-16 12:34:12,514 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 12:34:12,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23044 states and 32972 transitions. [2022-11-16 12:34:12,603 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22821 [2022-11-16 12:34:12,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:12,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:12,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:12,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:12,607 INFO L748 eck$LassoCheckResult]: Stem: 120162#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 120163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 120501#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 119548#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119549#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 119820#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119821#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 120392#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 120378#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 119896#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 119897#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 120140#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 120141#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 119983#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119984#L838 assume !(0 == ~M_E~0); 120148#L838-2 assume !(0 == ~T1_E~0); 119509#L843-1 assume !(0 == ~T2_E~0); 119510#L848-1 assume !(0 == ~T3_E~0); 119628#L853-1 assume !(0 == ~T4_E~0); 119971#L858-1 assume !(0 == ~T5_E~0); 119459#L863-1 assume !(0 == ~T6_E~0); 119460#L868-1 assume !(0 == ~T7_E~0); 120452#L873-1 assume !(0 == ~T8_E~0); 120449#L878-1 assume !(0 == ~E_1~0); 120429#L883-1 assume !(0 == ~E_2~0); 120430#L888-1 assume !(0 == ~E_3~0); 120112#L893-1 assume !(0 == ~E_4~0); 120113#L898-1 assume !(0 == ~E_5~0); 120478#L903-1 assume !(0 == ~E_6~0); 120427#L908-1 assume !(0 == ~E_7~0); 120249#L913-1 assume !(0 == ~E_8~0); 119524#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119525#L402 assume !(1 == ~m_pc~0); 119946#L402-2 is_master_triggered_~__retres1~0#1 := 0; 119652#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119653#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119903#L1035 assume !(0 != activate_threads_~tmp~1#1); 119904#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119959#L421 assume !(1 == ~t1_pc~0); 120418#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 120456#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119949#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119950#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 120016#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 120467#L440 assume !(1 == ~t2_pc~0); 120520#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 119662#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119663#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 120491#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 120265#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119854#L459 assume !(1 == ~t3_pc~0); 119855#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 120415#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120187#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119645#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 119646#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119656#L478 assume !(1 == ~t4_pc~0); 119657#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 120324#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120391#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119826#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 119570#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119571#L497 assume !(1 == ~t5_pc~0); 119614#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 119615#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119918#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 119919#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 120408#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 120409#L516 assume 1 == ~t6_pc~0; 120513#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 120137#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 120138#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119700#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 119701#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 120129#L535 assume !(1 == ~t7_pc~0); 120130#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 120205#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120206#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 120238#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 120229#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 120230#L554 assume 1 == ~t8_pc~0; 120172#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 119486#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 120290#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 119792#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 119793#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119470#L931 assume !(1 == ~M_E~0); 119471#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 120443#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 120485#L941-1 assume !(1 == ~T3_E~0); 120519#L946-1 assume !(1 == ~T4_E~0); 133782#L951-1 assume !(1 == ~T5_E~0); 133780#L956-1 assume !(1 == ~T6_E~0); 120514#L961-1 assume !(1 == ~T7_E~0); 120114#L966-1 assume !(1 == ~T8_E~0); 120115#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 120232#L976-1 assume !(1 == ~E_2~0); 120496#L981-1 assume !(1 == ~E_3~0); 119965#L986-1 assume !(1 == ~E_4~0); 119966#L991-1 assume !(1 == ~E_5~0); 119745#L996-1 assume !(1 == ~E_6~0); 133349#L1001-1 assume !(1 == ~E_7~0); 120160#L1006-1 assume !(1 == ~E_8~0); 120161#L1011-1 assume { :end_inline_reset_delta_events } true; 120416#L1272-2 [2022-11-16 12:34:12,607 INFO L750 eck$LassoCheckResult]: Loop: 120416#L1272-2 assume !false; 134477#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134466#L813 assume !false; 134328#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 134313#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 134304#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 134302#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 134299#L696 assume !(0 != eval_~tmp~0#1); 134300#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 138050#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 138048#L838-3 assume !(0 == ~M_E~0); 138046#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 138044#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 138042#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 138040#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 138039#L858-3 assume !(0 == ~T5_E~0); 138038#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 138036#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 138035#L873-3 assume !(0 == ~T8_E~0); 138034#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 138033#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 138032#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 138031#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 138030#L898-3 assume !(0 == ~E_5~0); 138029#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 138027#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 138026#L913-3 assume !(0 == ~E_8~0); 138025#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138024#L402-27 assume !(1 == ~m_pc~0); 138023#L402-29 is_master_triggered_~__retres1~0#1 := 0; 138022#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138021#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 138020#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 138019#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138017#L421-27 assume !(1 == ~t1_pc~0); 138016#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 138015#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138014#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 138012#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 138010#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138008#L440-27 assume !(1 == ~t2_pc~0); 138006#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 138004#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138002#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 138000#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 137998#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 137996#L459-27 assume 1 == ~t3_pc~0; 137994#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 137995#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138018#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 137985#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 137983#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137981#L478-27 assume !(1 == ~t4_pc~0); 137979#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 137977#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137975#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 137973#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 137971#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 137968#L497-27 assume 1 == ~t5_pc~0; 137966#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 137963#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 137961#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 137959#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 137957#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 137956#L516-27 assume !(1 == ~t6_pc~0); 137954#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 137951#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 137949#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 137947#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 137945#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 137944#L535-27 assume 1 == ~t7_pc~0; 137942#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 137939#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 137937#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 137935#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 137931#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 137929#L554-27 assume 1 == ~t8_pc~0; 137926#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 137924#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 137921#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 137919#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 137917#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137915#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 137913#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 137911#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 133578#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 137908#L946-3 assume !(1 == ~T4_E~0); 137906#L951-3 assume !(1 == ~T5_E~0); 137903#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 137901#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 137899#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 137897#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 137895#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 137893#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 137890#L986-3 assume !(1 == ~E_4~0); 137888#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 133565#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 137885#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 137883#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 137881#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 134712#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 134702#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 134700#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 134697#L1291 assume !(0 == start_simulation_~tmp~3#1); 134694#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 134682#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 134680#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 134678#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 134675#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 134673#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 134671#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 134669#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 120416#L1272-2 [2022-11-16 12:34:12,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:12,608 INFO L85 PathProgramCache]: Analyzing trace with hash -461177985, now seen corresponding path program 1 times [2022-11-16 12:34:12,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:12,608 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198480446] [2022-11-16 12:34:12,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:12,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:12,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:12,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:12,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:12,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198480446] [2022-11-16 12:34:12,826 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198480446] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:12,826 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:12,826 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:12,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2021382848] [2022-11-16 12:34:12,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:12,827 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:12,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:12,828 INFO L85 PathProgramCache]: Analyzing trace with hash -527122366, now seen corresponding path program 1 times [2022-11-16 12:34:12,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:12,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210658024] [2022-11-16 12:34:12,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:12,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:12,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:12,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:12,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:12,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210658024] [2022-11-16 12:34:12,885 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210658024] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:12,885 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:12,885 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:12,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1322349668] [2022-11-16 12:34:12,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:12,886 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:12,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:12,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:34:12,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:34:12,887 INFO L87 Difference]: Start difference. First operand 23044 states and 32972 transitions. cyclomatic complexity: 9944 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:13,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:13,636 INFO L93 Difference]: Finished difference Result 64211 states and 91283 transitions. [2022-11-16 12:34:13,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64211 states and 91283 transitions. [2022-11-16 12:34:14,206 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62541 [2022-11-16 12:34:14,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64211 states to 64211 states and 91283 transitions. [2022-11-16 12:34:14,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64211 [2022-11-16 12:34:14,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64211 [2022-11-16 12:34:14,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64211 states and 91283 transitions. [2022-11-16 12:34:14,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:14,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64211 states and 91283 transitions. [2022-11-16 12:34:14,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64211 states and 91283 transitions. [2022-11-16 12:34:15,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64211 to 62123. [2022-11-16 12:34:16,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62123 states, 62123 states have (on average 1.4256072630104792) internal successors, (88563), 62122 states have internal predecessors, (88563), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:16,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62123 states to 62123 states and 88563 transitions. [2022-11-16 12:34:16,342 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62123 states and 88563 transitions. [2022-11-16 12:34:16,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:34:16,343 INFO L428 stractBuchiCegarLoop]: Abstraction has 62123 states and 88563 transitions. [2022-11-16 12:34:16,343 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 12:34:16,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62123 states and 88563 transitions. [2022-11-16 12:34:16,569 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 61749 [2022-11-16 12:34:16,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:16,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:16,572 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:16,572 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:16,574 INFO L748 eck$LassoCheckResult]: Stem: 207421#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 207422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 207800#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 206810#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 206811#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 207077#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 207078#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 207682#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 207662#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 207149#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 207150#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 207396#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 207397#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 207237#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 207238#L838 assume !(0 == ~M_E~0); 207405#L838-2 assume !(0 == ~T1_E~0); 206772#L843-1 assume !(0 == ~T2_E~0); 206773#L848-1 assume !(0 == ~T3_E~0); 206890#L853-1 assume !(0 == ~T4_E~0); 207223#L858-1 assume !(0 == ~T5_E~0); 206722#L863-1 assume !(0 == ~T6_E~0); 206723#L868-1 assume !(0 == ~T7_E~0); 207743#L873-1 assume !(0 == ~T8_E~0); 207741#L878-1 assume !(0 == ~E_1~0); 207715#L883-1 assume !(0 == ~E_2~0); 207716#L888-1 assume !(0 == ~E_3~0); 207368#L893-1 assume !(0 == ~E_4~0); 207369#L898-1 assume !(0 == ~E_5~0); 207765#L903-1 assume !(0 == ~E_6~0); 207712#L908-1 assume !(0 == ~E_7~0); 207512#L913-1 assume !(0 == ~E_8~0); 206786#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 206787#L402 assume !(1 == ~m_pc~0); 207202#L402-2 is_master_triggered_~__retres1~0#1 := 0; 206912#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 206913#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 207155#L1035 assume !(0 != activate_threads_~tmp~1#1); 207156#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 207213#L421 assume !(1 == ~t1_pc~0); 207706#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 207744#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 207205#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 207206#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 207266#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 207755#L440 assume !(1 == ~t2_pc~0); 207829#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 206922#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206923#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 207782#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 207534#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 207105#L459 assume !(1 == ~t3_pc~0); 207106#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 207700#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 207449#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 206905#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 206906#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 206916#L478 assume !(1 == ~t4_pc~0); 206917#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 207593#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 207680#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 207083#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 206830#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 206831#L497 assume !(1 == ~t5_pc~0); 206876#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 206877#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 207169#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 207170#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 207691#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 207692#L516 assume !(1 == ~t6_pc~0); 207611#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 207394#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 207395#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 206963#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 206964#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 207386#L535 assume !(1 == ~t7_pc~0); 207387#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 207469#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 207470#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 207502#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 207490#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 207491#L554 assume 1 == ~t8_pc~0; 207430#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 206751#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 207556#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 207047#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 207048#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 206735#L931 assume !(1 == ~M_E~0); 206736#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 207728#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 207777#L941-1 assume !(1 == ~T3_E~0); 207214#L946-1 assume !(1 == ~T4_E~0); 207215#L951-1 assume !(1 == ~T5_E~0); 206978#L956-1 assume !(1 == ~T6_E~0); 206979#L961-1 assume !(1 == ~T7_E~0); 207370#L966-1 assume !(1 == ~T8_E~0); 207371#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 207791#L976-1 assume !(1 == ~E_2~0); 207792#L981-1 assume !(1 == ~E_3~0); 207219#L986-1 assume !(1 == ~E_4~0); 207220#L991-1 assume !(1 == ~E_5~0); 207008#L996-1 assume !(1 == ~E_6~0); 207809#L1001-1 assume !(1 == ~E_7~0); 207419#L1006-1 assume !(1 == ~E_8~0); 207420#L1011-1 assume { :end_inline_reset_delta_events } true; 225454#L1272-2 [2022-11-16 12:34:16,574 INFO L750 eck$LassoCheckResult]: Loop: 225454#L1272-2 assume !false; 225445#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 225438#L813 assume !false; 225439#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 225374#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 225363#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 225358#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 225351#L696 assume !(0 != eval_~tmp~0#1); 225352#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 226839#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 226840#L838-3 assume !(0 == ~M_E~0); 226833#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 226834#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 226826#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 226827#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 226820#L858-3 assume !(0 == ~T5_E~0); 226821#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 226814#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 226815#L873-3 assume !(0 == ~T8_E~0); 226810#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 226811#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 226806#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 226807#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 226802#L898-3 assume !(0 == ~E_5~0); 226803#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 226794#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 226795#L913-3 assume !(0 == ~E_8~0); 226790#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 226791#L402-27 assume !(1 == ~m_pc~0); 226785#L402-29 is_master_triggered_~__retres1~0#1 := 0; 226786#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 226779#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 226780#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 226773#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226774#L421-27 assume !(1 == ~t1_pc~0); 226768#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 226769#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 226763#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 226764#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 226757#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226758#L440-27 assume !(1 == ~t2_pc~0); 226751#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 226752#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 226745#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 226746#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 226739#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 226740#L459-27 assume !(1 == ~t3_pc~0); 226730#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 226731#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 226723#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 226724#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 226717#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 226718#L478-27 assume !(1 == ~t4_pc~0); 226710#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 226711#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 226704#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 226705#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 226698#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 226699#L497-27 assume !(1 == ~t5_pc~0); 226690#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 226691#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 226683#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 226684#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 226677#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226678#L516-27 assume !(1 == ~t6_pc~0); 226671#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 226672#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226665#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 226666#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 226659#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 226660#L535-27 assume !(1 == ~t7_pc~0); 226647#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 226648#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 226640#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 226641#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 226634#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 226635#L554-27 assume 1 == ~t8_pc~0; 226626#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 226627#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 226619#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 226620#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 226613#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 226614#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 226604#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 226605#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 225679#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 225680#L946-3 assume !(1 == ~T4_E~0); 225673#L951-3 assume !(1 == ~T5_E~0); 225674#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 225668#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 225669#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 225662#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 225663#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 225656#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 225657#L986-3 assume !(1 == ~E_4~0); 225651#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 225647#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 225645#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 225643#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 225641#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 225608#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 225598#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 225597#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 225593#L1291 assume !(0 == start_simulation_~tmp~3#1); 225590#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 225513#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 225505#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 225493#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 225489#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 225487#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 225473#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 225463#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 225454#L1272-2 [2022-11-16 12:34:16,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:16,575 INFO L85 PathProgramCache]: Analyzing trace with hash 2068972702, now seen corresponding path program 1 times [2022-11-16 12:34:16,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:16,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178100816] [2022-11-16 12:34:16,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:16,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:16,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:16,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:16,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:16,941 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178100816] [2022-11-16 12:34:16,941 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178100816] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:16,942 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:16,942 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:34:16,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121192991] [2022-11-16 12:34:16,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:16,943 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:16,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:16,943 INFO L85 PathProgramCache]: Analyzing trace with hash 1216429469, now seen corresponding path program 1 times [2022-11-16 12:34:16,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:16,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687968573] [2022-11-16 12:34:16,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:16,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:16,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:16,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:16,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:16,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687968573] [2022-11-16 12:34:16,999 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687968573] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:16,999 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:16,999 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:16,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410986994] [2022-11-16 12:34:16,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:17,000 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:17,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:17,000 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:17,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:17,001 INFO L87 Difference]: Start difference. First operand 62123 states and 88563 transitions. cyclomatic complexity: 26472 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:17,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:17,791 INFO L93 Difference]: Finished difference Result 123304 states and 174707 transitions. [2022-11-16 12:34:17,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123304 states and 174707 transitions. [2022-11-16 12:34:18,570 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 122467 [2022-11-16 12:34:19,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123304 states to 123304 states and 174707 transitions. [2022-11-16 12:34:19,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123304 [2022-11-16 12:34:19,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123304 [2022-11-16 12:34:19,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123304 states and 174707 transitions. [2022-11-16 12:34:19,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:19,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123304 states and 174707 transitions. [2022-11-16 12:34:19,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123304 states and 174707 transitions. [2022-11-16 12:34:21,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123304 to 122872. [2022-11-16 12:34:21,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122872 states, 122872 states have (on average 1.4174669574842111) internal successors, (174167), 122871 states have internal predecessors, (174167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:22,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122872 states to 122872 states and 174167 transitions. [2022-11-16 12:34:22,005 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122872 states and 174167 transitions. [2022-11-16 12:34:22,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:22,006 INFO L428 stractBuchiCegarLoop]: Abstraction has 122872 states and 174167 transitions. [2022-11-16 12:34:22,006 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 12:34:22,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122872 states and 174167 transitions. [2022-11-16 12:34:22,332 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 122251 [2022-11-16 12:34:22,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:22,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:22,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:22,335 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:22,335 INFO L748 eck$LassoCheckResult]: Stem: 392873#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 392874#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 393279#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 392244#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 392245#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 392521#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 392522#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 393146#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 393132#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 392595#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 392596#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 392853#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 392854#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 392687#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 392688#L838 assume !(0 == ~M_E~0); 392861#L838-2 assume !(0 == ~T1_E~0); 392206#L843-1 assume !(0 == ~T2_E~0); 392207#L848-1 assume !(0 == ~T3_E~0); 392324#L853-1 assume !(0 == ~T4_E~0); 392673#L858-1 assume !(0 == ~T5_E~0); 392156#L863-1 assume !(0 == ~T6_E~0); 392157#L868-1 assume !(0 == ~T7_E~0); 393217#L873-1 assume !(0 == ~T8_E~0); 393213#L878-1 assume !(0 == ~E_1~0); 393188#L883-1 assume !(0 == ~E_2~0); 393189#L888-1 assume !(0 == ~E_3~0); 392822#L893-1 assume !(0 == ~E_4~0); 392823#L898-1 assume !(0 == ~E_5~0); 393242#L903-1 assume !(0 == ~E_6~0); 393187#L908-1 assume !(0 == ~E_7~0); 392974#L913-1 assume !(0 == ~E_8~0); 392220#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 392221#L402 assume !(1 == ~m_pc~0); 392650#L402-2 is_master_triggered_~__retres1~0#1 := 0; 392348#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 392349#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 392602#L1035 assume !(0 != activate_threads_~tmp~1#1); 392603#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 392662#L421 assume !(1 == ~t1_pc~0); 393178#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 393220#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 392653#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 392654#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 392718#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 393233#L440 assume !(1 == ~t2_pc~0); 393316#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 392358#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 392359#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 393262#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 392993#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 392550#L459 assume !(1 == ~t3_pc~0); 392551#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 393171#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 392900#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 392341#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 392342#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 392352#L478 assume !(1 == ~t4_pc~0); 392353#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 393057#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 393145#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 392527#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 392264#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 392265#L497 assume !(1 == ~t5_pc~0); 392310#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 392311#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 392617#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 392618#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 393161#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 393162#L516 assume !(1 == ~t6_pc~0); 393080#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 392851#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 392852#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 392397#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 392398#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 392843#L535 assume !(1 == ~t7_pc~0); 392844#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 392920#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 392921#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 392962#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 392948#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 392949#L554 assume !(1 == ~t8_pc~0); 392184#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 392185#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 393015#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 392486#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 392487#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392169#L931 assume !(1 == ~M_E~0); 392170#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 393200#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 393257#L941-1 assume !(1 == ~T3_E~0); 392663#L946-1 assume !(1 == ~T4_E~0); 392664#L951-1 assume !(1 == ~T5_E~0); 392413#L956-1 assume !(1 == ~T6_E~0); 392414#L961-1 assume !(1 == ~T7_E~0); 392824#L966-1 assume !(1 == ~T8_E~0); 392825#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 393273#L976-1 assume !(1 == ~E_2~0); 393274#L981-1 assume !(1 == ~E_3~0); 392669#L986-1 assume !(1 == ~E_4~0); 392670#L991-1 assume !(1 == ~E_5~0); 392443#L996-1 assume !(1 == ~E_6~0); 393288#L1001-1 assume !(1 == ~E_7~0); 392871#L1006-1 assume !(1 == ~E_8~0); 392872#L1011-1 assume { :end_inline_reset_delta_events } true; 408289#L1272-2 [2022-11-16 12:34:22,336 INFO L750 eck$LassoCheckResult]: Loop: 408289#L1272-2 assume !false; 453686#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 453682#L813 assume !false; 453680#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 407568#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 407559#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 405849#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 405847#L696 assume !(0 != eval_~tmp~0#1); 405848#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 455214#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 455213#L838-3 assume !(0 == ~M_E~0); 455212#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 455211#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 455210#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 455209#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 455208#L858-3 assume !(0 == ~T5_E~0); 455207#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 455206#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 455205#L873-3 assume !(0 == ~T8_E~0); 455204#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 455203#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 455202#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 455201#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 455200#L898-3 assume !(0 == ~E_5~0); 455199#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 455198#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 455197#L913-3 assume !(0 == ~E_8~0); 455196#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 455195#L402-27 assume !(1 == ~m_pc~0); 455194#L402-29 is_master_triggered_~__retres1~0#1 := 0; 455193#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 455192#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 455191#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 455190#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 455189#L421-27 assume !(1 == ~t1_pc~0); 455188#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 455187#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 455186#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 455185#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 455184#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 455183#L440-27 assume !(1 == ~t2_pc~0); 455182#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 455181#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 455180#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 455179#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 455178#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 455177#L459-27 assume !(1 == ~t3_pc~0); 455174#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 455173#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 455172#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 455171#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 455169#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 455168#L478-27 assume !(1 == ~t4_pc~0); 455167#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 455166#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 455165#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 455164#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 455163#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 455162#L497-27 assume !(1 == ~t5_pc~0); 455160#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 455159#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 455158#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 410754#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 410755#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 455088#L516-27 assume !(1 == ~t6_pc~0); 455087#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 410475#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 410476#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 410469#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 410470#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 455057#L535-27 assume !(1 == ~t7_pc~0); 455054#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 455053#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 455052#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 455051#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 455050#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 455049#L554-27 assume !(1 == ~t8_pc~0); 455048#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 455047#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 455046#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 455045#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 455044#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 455043#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 455042#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 455041#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 446326#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 455040#L946-3 assume !(1 == ~T4_E~0); 455039#L951-3 assume !(1 == ~T5_E~0); 455038#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 455037#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 455036#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 455035#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 455034#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 455033#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 455032#L986-3 assume !(1 == ~E_4~0); 455031#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 446314#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 455030#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 410350#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 410351#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 409918#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 409908#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 409906#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 409903#L1291 assume !(0 == start_simulation_~tmp~3#1); 409899#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 409801#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 409799#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 409797#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 409794#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 409792#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 409793#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 453689#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 408289#L1272-2 [2022-11-16 12:34:22,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:22,337 INFO L85 PathProgramCache]: Analyzing trace with hash 478577725, now seen corresponding path program 1 times [2022-11-16 12:34:22,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:22,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524425548] [2022-11-16 12:34:22,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:22,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:22,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:22,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:22,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:22,409 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1524425548] [2022-11-16 12:34:22,409 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1524425548] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:22,409 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:22,409 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:34:22,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726543088] [2022-11-16 12:34:22,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:22,410 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:22,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:22,411 INFO L85 PathProgramCache]: Analyzing trace with hash -548387140, now seen corresponding path program 1 times [2022-11-16 12:34:22,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:22,411 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802024732] [2022-11-16 12:34:22,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:22,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:22,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:22,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:22,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:22,470 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802024732] [2022-11-16 12:34:22,470 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802024732] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:22,470 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:22,470 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:22,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [798307892] [2022-11-16 12:34:22,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:22,471 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:22,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:22,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:22,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:22,472 INFO L87 Difference]: Start difference. First operand 122872 states and 174167 transitions. cyclomatic complexity: 51359 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:23,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:23,568 INFO L93 Difference]: Finished difference Result 122872 states and 173517 transitions. [2022-11-16 12:34:23,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122872 states and 173517 transitions. [2022-11-16 12:34:24,052 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 122251 [2022-11-16 12:34:25,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122872 states to 122872 states and 173517 transitions. [2022-11-16 12:34:25,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122872 [2022-11-16 12:34:25,217 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122872 [2022-11-16 12:34:25,218 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122872 states and 173517 transitions. [2022-11-16 12:34:25,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:25,286 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122872 states and 173517 transitions. [2022-11-16 12:34:25,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122872 states and 173517 transitions. [2022-11-16 12:34:27,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122872 to 122872. [2022-11-16 12:34:27,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122872 states, 122872 states have (on average 1.4121768995377304) internal successors, (173517), 122871 states have internal predecessors, (173517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:27,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122872 states to 122872 states and 173517 transitions. [2022-11-16 12:34:27,464 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122872 states and 173517 transitions. [2022-11-16 12:34:27,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:27,465 INFO L428 stractBuchiCegarLoop]: Abstraction has 122872 states and 173517 transitions. [2022-11-16 12:34:27,465 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 12:34:27,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122872 states and 173517 transitions. [2022-11-16 12:34:27,797 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 122251 [2022-11-16 12:34:27,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:27,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:27,799 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:27,799 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:27,799 INFO L748 eck$LassoCheckResult]: Stem: 638596#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 638597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 638927#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 637998#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 637999#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 638264#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 638265#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 638822#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 638808#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 638337#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 638338#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 638574#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 638575#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 638422#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 638423#L838 assume !(0 == ~M_E~0); 638583#L838-2 assume !(0 == ~T1_E~0); 637959#L843-1 assume !(0 == ~T2_E~0); 637960#L848-1 assume !(0 == ~T3_E~0); 638079#L853-1 assume !(0 == ~T4_E~0); 638410#L858-1 assume !(0 == ~T5_E~0); 637909#L863-1 assume !(0 == ~T6_E~0); 637910#L868-1 assume !(0 == ~T7_E~0); 638879#L873-1 assume !(0 == ~T8_E~0); 638877#L878-1 assume !(0 == ~E_1~0); 638857#L883-1 assume !(0 == ~E_2~0); 638858#L888-1 assume !(0 == ~E_3~0); 638546#L893-1 assume !(0 == ~E_4~0); 638547#L898-1 assume !(0 == ~E_5~0); 638902#L903-1 assume !(0 == ~E_6~0); 638853#L908-1 assume !(0 == ~E_7~0); 638685#L913-1 assume !(0 == ~E_8~0); 637973#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 637974#L402 assume !(1 == ~m_pc~0); 638387#L402-2 is_master_triggered_~__retres1~0#1 := 0; 638101#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 638102#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 638344#L1035 assume !(0 != activate_threads_~tmp~1#1); 638345#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 638398#L421 assume !(1 == ~t1_pc~0); 638847#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 638883#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 638390#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 638391#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 638451#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 638893#L440 assume !(1 == ~t2_pc~0); 638952#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 638110#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 638111#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 638914#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 638700#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 638296#L459 assume !(1 == ~t3_pc~0); 638297#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 638841#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 638623#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 638094#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 638095#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 638105#L478 assume !(1 == ~t4_pc~0); 638106#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 638753#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 638821#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 638270#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 638020#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 638021#L497 assume !(1 == ~t5_pc~0); 638065#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 638066#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 638358#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 638359#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 638835#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 638836#L516 assume !(1 == ~t6_pc~0); 638768#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 638570#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 638571#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 638149#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 638150#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 638562#L535 assume !(1 == ~t7_pc~0); 638563#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 638641#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 638642#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 638672#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 638662#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 638663#L554 assume !(1 == ~t8_pc~0); 637935#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 637936#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 638721#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 638235#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 638236#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 637920#L931 assume !(1 == ~M_E~0); 637921#L931-2 assume !(1 == ~T1_E~0); 638869#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 638910#L941-1 assume !(1 == ~T3_E~0); 638399#L946-1 assume !(1 == ~T4_E~0); 638400#L951-1 assume !(1 == ~T5_E~0); 638164#L956-1 assume !(1 == ~T6_E~0); 638165#L961-1 assume !(1 == ~T7_E~0); 638548#L966-1 assume !(1 == ~T8_E~0); 638549#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 638921#L976-1 assume !(1 == ~E_2~0); 638922#L981-1 assume !(1 == ~E_3~0); 638404#L986-1 assume !(1 == ~E_4~0); 638405#L991-1 assume !(1 == ~E_5~0); 638193#L996-1 assume !(1 == ~E_6~0); 638935#L1001-1 assume !(1 == ~E_7~0); 638594#L1006-1 assume !(1 == ~E_8~0); 638595#L1011-1 assume { :end_inline_reset_delta_events } true; 652616#L1272-2 [2022-11-16 12:34:27,800 INFO L750 eck$LassoCheckResult]: Loop: 652616#L1272-2 assume !false; 700575#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 700571#L813 assume !false; 700570#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 700568#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 700560#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 700559#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 700557#L696 assume !(0 != eval_~tmp~0#1); 700558#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 704751#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 704750#L838-3 assume !(0 == ~M_E~0); 704749#L838-5 assume !(0 == ~T1_E~0); 704748#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 704747#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 704746#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 704745#L858-3 assume !(0 == ~T5_E~0); 704744#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 704743#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 704742#L873-3 assume !(0 == ~T8_E~0); 704741#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 704740#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 704739#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 704738#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 704737#L898-3 assume !(0 == ~E_5~0); 704736#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 704735#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 704734#L913-3 assume !(0 == ~E_8~0); 704733#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 704732#L402-27 assume !(1 == ~m_pc~0); 704731#L402-29 is_master_triggered_~__retres1~0#1 := 0; 704730#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 704729#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 704728#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 704727#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 704726#L421-27 assume !(1 == ~t1_pc~0); 704725#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 704724#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 704723#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 704722#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 704721#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 704720#L440-27 assume !(1 == ~t2_pc~0); 704719#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 704718#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 704717#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 704716#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 704715#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 704714#L459-27 assume 1 == ~t3_pc~0; 704712#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 704713#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 704752#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 704707#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 704706#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 704705#L478-27 assume !(1 == ~t4_pc~0); 704704#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 704703#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 704702#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 704701#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 704700#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 704699#L497-27 assume 1 == ~t5_pc~0; 704698#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 704696#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 704695#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 704694#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 704693#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 704692#L516-27 assume !(1 == ~t6_pc~0); 704691#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 704690#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 704689#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 704688#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 704687#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 704686#L535-27 assume !(1 == ~t7_pc~0); 704684#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 704683#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 704682#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 704681#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 704680#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 704679#L554-27 assume !(1 == ~t8_pc~0); 704678#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 704677#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 704676#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 704675#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 704674#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 704673#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 704672#L931-5 assume !(1 == ~T1_E~0); 704671#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 704228#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 704670#L946-3 assume !(1 == ~T4_E~0); 704669#L951-3 assume !(1 == ~T5_E~0); 704668#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 704667#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 704666#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 704665#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 704664#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 704663#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 704662#L986-3 assume !(1 == ~E_4~0); 704661#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 704216#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 704660#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 704659#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 704658#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 704657#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 704648#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 704647#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 704645#L1291 assume !(0 == start_simulation_~tmp~3#1); 704643#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 700582#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 700581#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 700580#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 700579#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 700578#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 700577#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 700576#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 652616#L1272-2 [2022-11-16 12:34:27,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:27,801 INFO L85 PathProgramCache]: Analyzing trace with hash -1109770177, now seen corresponding path program 1 times [2022-11-16 12:34:27,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:27,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114954803] [2022-11-16 12:34:27,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:27,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:27,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:27,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:27,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:27,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114954803] [2022-11-16 12:34:27,864 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1114954803] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:27,864 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:27,864 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:34:27,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140423758] [2022-11-16 12:34:27,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:27,865 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:27,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:27,866 INFO L85 PathProgramCache]: Analyzing trace with hash -73425084, now seen corresponding path program 1 times [2022-11-16 12:34:27,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:27,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886286100] [2022-11-16 12:34:27,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:27,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:27,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:27,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:27,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:27,922 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886286100] [2022-11-16 12:34:27,922 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886286100] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:27,922 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:27,922 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:27,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264573657] [2022-11-16 12:34:27,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:27,923 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:27,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:27,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:27,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:27,924 INFO L87 Difference]: Start difference. First operand 122872 states and 173517 transitions. cyclomatic complexity: 50709 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:29,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:29,248 INFO L93 Difference]: Finished difference Result 122861 states and 172955 transitions. [2022-11-16 12:34:29,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122861 states and 172955 transitions. [2022-11-16 12:34:29,781 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 122251 [2022-11-16 12:34:30,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122861 states to 122861 states and 172955 transitions. [2022-11-16 12:34:30,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122861 [2022-11-16 12:34:30,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122861 [2022-11-16 12:34:30,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122861 states and 172955 transitions. [2022-11-16 12:34:30,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:30,151 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122861 states and 172955 transitions. [2022-11-16 12:34:30,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122861 states and 172955 transitions. [2022-11-16 12:34:31,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122861 to 63233. [2022-11-16 12:34:31,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63233 states, 63233 states have (on average 1.405215631078709) internal successors, (88856), 63232 states have internal predecessors, (88856), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:31,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63233 states to 63233 states and 88856 transitions. [2022-11-16 12:34:31,738 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63233 states and 88856 transitions. [2022-11-16 12:34:31,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:31,740 INFO L428 stractBuchiCegarLoop]: Abstraction has 63233 states and 88856 transitions. [2022-11-16 12:34:31,740 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 12:34:31,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63233 states and 88856 transitions. [2022-11-16 12:34:31,895 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62875 [2022-11-16 12:34:31,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:31,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:31,897 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:31,897 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:31,897 INFO L748 eck$LassoCheckResult]: Stem: 884349#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 884350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 884676#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 883737#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 883738#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 884004#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 884005#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 884566#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 884554#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 884079#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 884080#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 884326#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 884327#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 884164#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 884165#L838 assume !(0 == ~M_E~0); 884336#L838-2 assume !(0 == ~T1_E~0); 883699#L843-1 assume !(0 == ~T2_E~0); 883700#L848-1 assume !(0 == ~T3_E~0); 883817#L853-1 assume !(0 == ~T4_E~0); 884152#L858-1 assume !(0 == ~T5_E~0); 883649#L863-1 assume !(0 == ~T6_E~0); 883650#L868-1 assume !(0 == ~T7_E~0); 884624#L873-1 assume !(0 == ~T8_E~0); 884622#L878-1 assume !(0 == ~E_1~0); 884598#L883-1 assume !(0 == ~E_2~0); 884599#L888-1 assume !(0 == ~E_3~0); 884298#L893-1 assume !(0 == ~E_4~0); 884299#L898-1 assume !(0 == ~E_5~0); 884649#L903-1 assume !(0 == ~E_6~0); 884595#L908-1 assume !(0 == ~E_7~0); 884435#L913-1 assume !(0 == ~E_8~0); 883713#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 883714#L402 assume !(1 == ~m_pc~0); 884130#L402-2 is_master_triggered_~__retres1~0#1 := 0; 883839#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 883840#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 884086#L1035 assume !(0 != activate_threads_~tmp~1#1); 884087#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 884141#L421 assume !(1 == ~t1_pc~0); 884589#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 884627#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 884133#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 884134#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 884194#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 884638#L440 assume !(1 == ~t2_pc~0); 884698#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 883848#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 883849#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 884661#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 884448#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 884039#L459 assume !(1 == ~t3_pc~0); 884040#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 884587#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 884374#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 883832#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 883833#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 883843#L478 assume !(1 == ~t4_pc~0); 883844#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 884497#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 884565#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 884010#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 883759#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 883760#L497 assume !(1 == ~t5_pc~0); 883803#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 883804#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 884100#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 884101#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 884581#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 884582#L516 assume !(1 == ~t6_pc~0); 884513#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 884323#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 884324#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 883887#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 883888#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 884315#L535 assume !(1 == ~t7_pc~0); 884316#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 884391#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 884392#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 884422#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 884413#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 884414#L554 assume !(1 == ~t8_pc~0); 883675#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 883676#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 884468#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 883975#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 883976#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 883660#L931 assume !(1 == ~M_E~0); 883661#L931-2 assume !(1 == ~T1_E~0); 884613#L936-1 assume !(1 == ~T2_E~0); 884657#L941-1 assume !(1 == ~T3_E~0); 884142#L946-1 assume !(1 == ~T4_E~0); 884143#L951-1 assume !(1 == ~T5_E~0); 883905#L956-1 assume !(1 == ~T6_E~0); 883906#L961-1 assume !(1 == ~T7_E~0); 884300#L966-1 assume !(1 == ~T8_E~0); 884301#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 884416#L976-1 assume !(1 == ~E_2~0); 884383#L981-1 assume !(1 == ~E_3~0); 884147#L986-1 assume !(1 == ~E_4~0); 883933#L991-1 assume !(1 == ~E_5~0); 883934#L996-1 assume !(1 == ~E_6~0); 884631#L1001-1 assume !(1 == ~E_7~0); 884347#L1006-1 assume !(1 == ~E_8~0); 884348#L1011-1 assume { :end_inline_reset_delta_events } true; 884588#L1272-2 [2022-11-16 12:34:31,897 INFO L750 eck$LassoCheckResult]: Loop: 884588#L1272-2 assume !false; 922550#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 922537#L813 assume !false; 922425#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 922298#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 922284#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 922239#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 922210#L696 assume !(0 != eval_~tmp~0#1); 922211#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 924377#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 924375#L838-3 assume !(0 == ~M_E~0); 924372#L838-5 assume !(0 == ~T1_E~0); 924370#L843-3 assume !(0 == ~T2_E~0); 924368#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 924366#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 924364#L858-3 assume !(0 == ~T5_E~0); 924362#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 924360#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 924358#L873-3 assume !(0 == ~T8_E~0); 924356#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 924353#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 924351#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 924349#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 924347#L898-3 assume !(0 == ~E_5~0); 924345#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 924342#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 924341#L913-3 assume !(0 == ~E_8~0); 924338#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 924336#L402-27 assume !(1 == ~m_pc~0); 924334#L402-29 is_master_triggered_~__retres1~0#1 := 0; 924332#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 924330#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 924328#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 924325#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 924323#L421-27 assume !(1 == ~t1_pc~0); 924321#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 924319#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 924317#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 924315#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 924312#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 924310#L440-27 assume !(1 == ~t2_pc~0); 924308#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 924306#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 924304#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 924303#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 924302#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 924301#L459-27 assume 1 == ~t3_pc~0; 924300#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 924298#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 924296#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 924293#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 924292#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 924290#L478-27 assume !(1 == ~t4_pc~0); 924287#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 924285#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 924283#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 924281#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 924279#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 924277#L497-27 assume 1 == ~t5_pc~0; 924276#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 924273#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 924271#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 924269#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 924267#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 924264#L516-27 assume !(1 == ~t6_pc~0); 924262#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 924260#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 924259#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 924258#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 924257#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 924256#L535-27 assume !(1 == ~t7_pc~0); 924254#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 924253#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 924251#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 924246#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 924241#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 924237#L554-27 assume !(1 == ~t8_pc~0); 924236#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 924235#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 924234#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 924233#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 924232#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 924231#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 924230#L931-5 assume !(1 == ~T1_E~0); 924229#L936-3 assume !(1 == ~T2_E~0); 924228#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 924227#L946-3 assume !(1 == ~T4_E~0); 924226#L951-3 assume !(1 == ~T5_E~0); 924225#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 924224#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 924223#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 924221#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 924220#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 924219#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 924217#L986-3 assume !(1 == ~E_4~0); 924216#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 924215#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 924213#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 924211#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 924209#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 923088#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 923078#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 923076#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 922583#L1291 assume !(0 == start_simulation_~tmp~3#1); 922577#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 922567#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 922565#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 922563#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 922561#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 922559#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 922557#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 922552#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 884588#L1272-2 [2022-11-16 12:34:31,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:31,898 INFO L85 PathProgramCache]: Analyzing trace with hash -2130838531, now seen corresponding path program 1 times [2022-11-16 12:34:31,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:31,898 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868187943] [2022-11-16 12:34:31,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:31,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:31,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:31,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:31,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:31,975 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1868187943] [2022-11-16 12:34:31,976 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1868187943] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:31,976 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:31,976 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:31,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434886080] [2022-11-16 12:34:31,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:31,977 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:31,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:31,978 INFO L85 PathProgramCache]: Analyzing trace with hash 1314598592, now seen corresponding path program 1 times [2022-11-16 12:34:31,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:31,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689497062] [2022-11-16 12:34:31,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:31,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:31,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:32,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:32,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:32,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689497062] [2022-11-16 12:34:32,027 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1689497062] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:32,027 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:32,028 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:32,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769022757] [2022-11-16 12:34:32,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:32,028 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:32,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:32,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:34:32,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:34:32,030 INFO L87 Difference]: Start difference. First operand 63233 states and 88856 transitions. cyclomatic complexity: 25655 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:33,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:33,476 INFO L93 Difference]: Finished difference Result 133866 states and 187259 transitions. [2022-11-16 12:34:33,476 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133866 states and 187259 transitions. [2022-11-16 12:34:34,222 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 133138 [2022-11-16 12:34:34,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133866 states to 133866 states and 187259 transitions. [2022-11-16 12:34:34,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 133866 [2022-11-16 12:34:34,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 133866 [2022-11-16 12:34:34,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133866 states and 187259 transitions. [2022-11-16 12:34:34,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:34,758 INFO L218 hiAutomatonCegarLoop]: Abstraction has 133866 states and 187259 transitions. [2022-11-16 12:34:34,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133866 states and 187259 transitions. [2022-11-16 12:34:36,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133866 to 71947. [2022-11-16 12:34:36,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71947 states, 71947 states have (on average 1.3988491528486247) internal successors, (100643), 71946 states have internal predecessors, (100643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:36,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71947 states to 71947 states and 100643 transitions. [2022-11-16 12:34:36,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 71947 states and 100643 transitions. [2022-11-16 12:34:36,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:34:36,402 INFO L428 stractBuchiCegarLoop]: Abstraction has 71947 states and 100643 transitions. [2022-11-16 12:34:36,402 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 12:34:36,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71947 states and 100643 transitions. [2022-11-16 12:34:36,588 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71511 [2022-11-16 12:34:36,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:36,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:36,589 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:36,589 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:36,590 INFO L748 eck$LassoCheckResult]: Stem: 1081457#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 1081458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1081832#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1080844#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1080845#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1081110#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1081111#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1081707#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1081694#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1081185#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1081186#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1081434#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1081435#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1081273#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1081274#L838 assume !(0 == ~M_E~0); 1081441#L838-2 assume !(0 == ~T1_E~0); 1080806#L843-1 assume !(0 == ~T2_E~0); 1080807#L848-1 assume !(0 == ~T3_E~0); 1080923#L853-1 assume !(0 == ~T4_E~0); 1081259#L858-1 assume !(0 == ~T5_E~0); 1080756#L863-1 assume !(0 == ~T6_E~0); 1080757#L868-1 assume !(0 == ~T7_E~0); 1081772#L873-1 assume !(0 == ~T8_E~0); 1081769#L878-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1081743#L883-1 assume !(0 == ~E_2~0); 1081744#L888-1 assume !(0 == ~E_3~0); 1081405#L893-1 assume !(0 == ~E_4~0); 1081406#L898-1 assume !(0 == ~E_5~0); 1081905#L903-1 assume !(0 == ~E_6~0); 1081741#L908-1 assume !(0 == ~E_7~0); 1081560#L913-1 assume !(0 == ~E_8~0); 1080820#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1080821#L402 assume !(1 == ~m_pc~0); 1081235#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1081236#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1081900#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1081899#L1035 assume !(0 != activate_threads_~tmp~1#1); 1081248#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1081249#L421 assume !(1 == ~t1_pc~0); 1081774#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1081775#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1081239#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1081240#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1081790#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1081791#L440 assume !(1 == ~t2_pc~0); 1081860#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1081861#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1081844#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1081845#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1081898#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1081144#L459 assume !(1 == ~t3_pc~0); 1081145#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1081897#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1081895#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1081892#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1081891#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1080949#L478 assume !(1 == ~t4_pc~0); 1080950#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1081705#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1081706#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1081116#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1081117#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1081459#L497 assume !(1 == ~t5_pc~0); 1081460#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1081495#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1081206#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1081207#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1081721#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1081722#L516 assume !(1 == ~t6_pc~0); 1081649#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1081650#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1081836#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1080992#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1080993#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1081511#L535 assume !(1 == ~t7_pc~0); 1081678#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1081509#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1081510#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1081886#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1081885#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1081713#L554 assume !(1 == ~t8_pc~0); 1080782#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1080783#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1081597#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1081598#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1081883#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1080768#L931 assume !(1 == ~M_E~0); 1080769#L931-2 assume !(1 == ~T1_E~0); 1081809#L936-1 assume !(1 == ~T2_E~0); 1081810#L941-1 assume !(1 == ~T3_E~0); 1081859#L946-1 assume !(1 == ~T4_E~0); 1081731#L951-1 assume !(1 == ~T5_E~0); 1081009#L956-1 assume !(1 == ~T6_E~0); 1081010#L961-1 assume !(1 == ~T7_E~0); 1081854#L966-1 assume !(1 == ~T8_E~0); 1081879#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1081540#L976-1 assume !(1 == ~E_2~0); 1081501#L981-1 assume !(1 == ~E_3~0); 1081256#L986-1 assume !(1 == ~E_4~0); 1081037#L991-1 assume !(1 == ~E_5~0); 1081038#L996-1 assume !(1 == ~E_6~0); 1081780#L1001-1 assume !(1 == ~E_7~0); 1081455#L1006-1 assume !(1 == ~E_8~0); 1081456#L1011-1 assume { :end_inline_reset_delta_events } true; 1081732#L1272-2 [2022-11-16 12:34:36,590 INFO L750 eck$LassoCheckResult]: Loop: 1081732#L1272-2 assume !false; 1132622#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1132617#L813 assume !false; 1132572#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1132521#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1132504#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1132502#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1132499#L696 assume !(0 != eval_~tmp~0#1); 1132500#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1133256#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1133254#L838-3 assume !(0 == ~M_E~0); 1133252#L838-5 assume !(0 == ~T1_E~0); 1133250#L843-3 assume !(0 == ~T2_E~0); 1133248#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1133245#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1133243#L858-3 assume !(0 == ~T5_E~0); 1133241#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1133239#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1133237#L873-3 assume !(0 == ~T8_E~0); 1133223#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1133222#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1133221#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1133220#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1133219#L898-3 assume !(0 == ~E_5~0); 1133218#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1133217#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1133216#L913-3 assume !(0 == ~E_8~0); 1133215#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1133214#L402-27 assume !(1 == ~m_pc~0); 1133213#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1133212#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1133211#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1133210#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1133209#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1133208#L421-27 assume !(1 == ~t1_pc~0); 1133207#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1133206#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1133205#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1133204#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1133203#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1133202#L440-27 assume !(1 == ~t2_pc~0); 1133201#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1133200#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1133199#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1133198#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1133197#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1133196#L459-27 assume !(1 == ~t3_pc~0); 1133195#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1133193#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1133191#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1133189#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1133187#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1133186#L478-27 assume !(1 == ~t4_pc~0); 1133185#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1133184#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1133183#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1133182#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1133181#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1133180#L497-27 assume 1 == ~t5_pc~0; 1133179#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1133177#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1133176#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1133175#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1133174#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1133173#L516-27 assume !(1 == ~t6_pc~0); 1133172#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1133171#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1133170#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1133169#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1133168#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1133167#L535-27 assume !(1 == ~t7_pc~0); 1133165#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1133164#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1133163#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1133162#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1133161#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1133160#L554-27 assume !(1 == ~t8_pc~0); 1133159#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1133158#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1133157#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1133156#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1133155#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1133154#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1133153#L931-5 assume !(1 == ~T1_E~0); 1133152#L936-3 assume !(1 == ~T2_E~0); 1133151#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1133150#L946-3 assume !(1 == ~T4_E~0); 1133149#L951-3 assume !(1 == ~T5_E~0); 1133148#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1133147#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1133146#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1133144#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1133140#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1133137#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1133134#L986-3 assume !(1 == ~E_4~0); 1133130#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1133125#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1133120#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1133117#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1133115#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1132901#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1132889#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1132885#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1132670#L1291 assume !(0 == start_simulation_~tmp~3#1); 1132663#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1132639#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1132636#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1132634#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1132632#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1132630#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1132628#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1132626#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1081732#L1272-2 [2022-11-16 12:34:36,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:36,591 INFO L85 PathProgramCache]: Analyzing trace with hash -1073000453, now seen corresponding path program 1 times [2022-11-16 12:34:36,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:36,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462987606] [2022-11-16 12:34:36,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:36,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:36,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:36,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:36,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:36,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [462987606] [2022-11-16 12:34:36,658 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [462987606] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:36,658 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:36,659 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:36,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487603321] [2022-11-16 12:34:36,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:36,659 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:36,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:36,660 INFO L85 PathProgramCache]: Analyzing trace with hash 815896285, now seen corresponding path program 1 times [2022-11-16 12:34:36,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:36,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520919595] [2022-11-16 12:34:36,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:36,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:36,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:36,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:36,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:36,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520919595] [2022-11-16 12:34:36,717 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520919595] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:36,717 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:36,717 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:36,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871182469] [2022-11-16 12:34:36,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:36,718 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:36,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:36,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:34:36,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:34:36,719 INFO L87 Difference]: Start difference. First operand 71947 states and 100643 transitions. cyclomatic complexity: 28728 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:37,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:37,098 INFO L93 Difference]: Finished difference Result 82849 states and 115976 transitions. [2022-11-16 12:34:37,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82849 states and 115976 transitions. [2022-11-16 12:34:38,274 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 82395 [2022-11-16 12:34:38,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82849 states to 82849 states and 115976 transitions. [2022-11-16 12:34:38,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82849 [2022-11-16 12:34:38,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82849 [2022-11-16 12:34:38,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82849 states and 115976 transitions. [2022-11-16 12:34:38,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:38,616 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82849 states and 115976 transitions. [2022-11-16 12:34:38,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82849 states and 115976 transitions. [2022-11-16 12:34:39,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82849 to 63233. [2022-11-16 12:34:39,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63233 states, 63233 states have (on average 1.3959799471794792) internal successors, (88272), 63232 states have internal predecessors, (88272), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:39,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63233 states to 63233 states and 88272 transitions. [2022-11-16 12:34:39,261 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63233 states and 88272 transitions. [2022-11-16 12:34:39,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:34:39,263 INFO L428 stractBuchiCegarLoop]: Abstraction has 63233 states and 88272 transitions. [2022-11-16 12:34:39,263 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-16 12:34:39,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63233 states and 88272 transitions. [2022-11-16 12:34:39,419 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62875 [2022-11-16 12:34:39,419 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:39,419 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:39,421 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:39,421 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:39,422 INFO L748 eck$LassoCheckResult]: Stem: 1236241#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 1236242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1236562#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1235649#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1235650#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1235916#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1235917#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1236471#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1236460#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1235988#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1235989#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1236222#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1236223#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1236073#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1236074#L838 assume !(0 == ~M_E~0); 1236229#L838-2 assume !(0 == ~T1_E~0); 1235611#L843-1 assume !(0 == ~T2_E~0); 1235612#L848-1 assume !(0 == ~T3_E~0); 1235729#L853-1 assume !(0 == ~T4_E~0); 1236061#L858-1 assume !(0 == ~T5_E~0); 1235564#L863-1 assume !(0 == ~T6_E~0); 1235565#L868-1 assume !(0 == ~T7_E~0); 1236521#L873-1 assume !(0 == ~T8_E~0); 1236518#L878-1 assume !(0 == ~E_1~0); 1236499#L883-1 assume !(0 == ~E_2~0); 1236500#L888-1 assume !(0 == ~E_3~0); 1236196#L893-1 assume !(0 == ~E_4~0); 1236197#L898-1 assume !(0 == ~E_5~0); 1236539#L903-1 assume !(0 == ~E_6~0); 1236498#L908-1 assume !(0 == ~E_7~0); 1236331#L913-1 assume !(0 == ~E_8~0); 1235625#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1235626#L402 assume !(1 == ~m_pc~0); 1236039#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1235751#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1235752#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1235996#L1035 assume !(0 != activate_threads_~tmp~1#1); 1235997#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1236050#L421 assume !(1 == ~t1_pc~0); 1236492#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1236524#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1236042#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1236043#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1236101#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1236535#L440 assume !(1 == ~t2_pc~0); 1236578#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1235761#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1235762#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1236552#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1236344#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1235950#L459 assume !(1 == ~t3_pc~0); 1235951#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1236490#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1236266#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1235744#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1235745#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1235755#L478 assume !(1 == ~t4_pc~0); 1235756#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1236399#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1236470#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1235922#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1235671#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1235672#L497 assume !(1 == ~t5_pc~0); 1235715#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1235716#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1236010#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1236011#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1236483#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1236484#L516 assume !(1 == ~t6_pc~0); 1236416#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1236219#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1236220#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1235800#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1235801#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1236211#L535 assume !(1 == ~t7_pc~0); 1236212#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1236283#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1236284#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1236319#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1236308#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1236309#L554 assume !(1 == ~t8_pc~0); 1235588#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1235589#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1236365#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1235888#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1235889#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1235574#L931 assume !(1 == ~M_E~0); 1235575#L931-2 assume !(1 == ~T1_E~0); 1236511#L936-1 assume !(1 == ~T2_E~0); 1236549#L941-1 assume !(1 == ~T3_E~0); 1236051#L946-1 assume !(1 == ~T4_E~0); 1236052#L951-1 assume !(1 == ~T5_E~0); 1235816#L956-1 assume !(1 == ~T6_E~0); 1235817#L961-1 assume !(1 == ~T7_E~0); 1236198#L966-1 assume !(1 == ~T8_E~0); 1236199#L971-1 assume !(1 == ~E_1~0); 1236311#L976-1 assume !(1 == ~E_2~0); 1236275#L981-1 assume !(1 == ~E_3~0); 1236056#L986-1 assume !(1 == ~E_4~0); 1235846#L991-1 assume !(1 == ~E_5~0); 1235847#L996-1 assume !(1 == ~E_6~0); 1236529#L1001-1 assume !(1 == ~E_7~0); 1236239#L1006-1 assume !(1 == ~E_8~0); 1236240#L1011-1 assume { :end_inline_reset_delta_events } true; 1236491#L1272-2 [2022-11-16 12:34:39,422 INFO L750 eck$LassoCheckResult]: Loop: 1236491#L1272-2 assume !false; 1263560#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1263555#L813 assume !false; 1263553#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1263549#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1263540#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1263538#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1263535#L696 assume !(0 != eval_~tmp~0#1); 1263536#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1263953#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1263952#L838-3 assume !(0 == ~M_E~0); 1263951#L838-5 assume !(0 == ~T1_E~0); 1263950#L843-3 assume !(0 == ~T2_E~0); 1263949#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1263948#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1263947#L858-3 assume !(0 == ~T5_E~0); 1263946#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1263945#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1263944#L873-3 assume !(0 == ~T8_E~0); 1263943#L878-3 assume !(0 == ~E_1~0); 1263942#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1263941#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1263940#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1263939#L898-3 assume !(0 == ~E_5~0); 1263938#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1263937#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1263936#L913-3 assume !(0 == ~E_8~0); 1263935#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1263934#L402-27 assume !(1 == ~m_pc~0); 1263933#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1263932#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1263931#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1263930#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1263929#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1263928#L421-27 assume !(1 == ~t1_pc~0); 1263927#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1263926#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1263925#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1263924#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1263923#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1263922#L440-27 assume !(1 == ~t2_pc~0); 1263921#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1263920#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1263919#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1263918#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1263917#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1263916#L459-27 assume !(1 == ~t3_pc~0); 1263915#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1263913#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1263911#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1263909#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1263907#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1263906#L478-27 assume !(1 == ~t4_pc~0); 1263905#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1263904#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1263903#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1263902#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1263901#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1263900#L497-27 assume 1 == ~t5_pc~0; 1263899#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1263897#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1263896#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1263895#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1263894#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1263893#L516-27 assume !(1 == ~t6_pc~0); 1263892#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1263890#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1263888#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1263886#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1263884#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1263882#L535-27 assume !(1 == ~t7_pc~0); 1263879#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1263877#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1263875#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1263873#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1263871#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1263869#L554-27 assume !(1 == ~t8_pc~0); 1263867#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1263864#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1263861#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1263858#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1263855#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1263852#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1263849#L931-5 assume !(1 == ~T1_E~0); 1263846#L936-3 assume !(1 == ~T2_E~0); 1263842#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1263838#L946-3 assume !(1 == ~T4_E~0); 1263834#L951-3 assume !(1 == ~T5_E~0); 1263830#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1263827#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1263824#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1263821#L971-3 assume !(1 == ~E_1~0); 1263818#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1263815#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1263812#L986-3 assume !(1 == ~E_4~0); 1263809#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1263806#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1263801#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1263797#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1263793#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1263755#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1263743#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1263631#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1263627#L1291 assume !(0 == start_simulation_~tmp~3#1); 1263624#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1263599#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1263595#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1263591#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1263585#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1263581#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1263575#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1263568#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1236491#L1272-2 [2022-11-16 12:34:39,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:39,423 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 1 times [2022-11-16 12:34:39,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:39,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835144354] [2022-11-16 12:34:39,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:39,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:39,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:34:39,439 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:34:39,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:34:39,511 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:34:39,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:39,512 INFO L85 PathProgramCache]: Analyzing trace with hash 355089121, now seen corresponding path program 1 times [2022-11-16 12:34:39,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:39,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807769510] [2022-11-16 12:34:39,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:39,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:39,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:39,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:39,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:39,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807769510] [2022-11-16 12:34:39,560 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807769510] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:39,560 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:39,561 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:39,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848503980] [2022-11-16 12:34:39,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:39,561 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:39,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:39,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:39,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:39,562 INFO L87 Difference]: Start difference. First operand 63233 states and 88272 transitions. cyclomatic complexity: 25071 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:40,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:40,476 INFO L93 Difference]: Finished difference Result 71983 states and 100316 transitions. [2022-11-16 12:34:40,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71983 states and 100316 transitions. [2022-11-16 12:34:40,712 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71547 [2022-11-16 12:34:40,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71983 states to 71983 states and 100316 transitions. [2022-11-16 12:34:40,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71983 [2022-11-16 12:34:40,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71983 [2022-11-16 12:34:40,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71983 states and 100316 transitions. [2022-11-16 12:34:40,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:40,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 71983 states and 100316 transitions. [2022-11-16 12:34:40,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71983 states and 100316 transitions. [2022-11-16 12:34:41,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71983 to 71983. [2022-11-16 12:34:41,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71983 states, 71983 states have (on average 1.3936068238334052) internal successors, (100316), 71982 states have internal predecessors, (100316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:42,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71983 states to 71983 states and 100316 transitions. [2022-11-16 12:34:42,354 INFO L240 hiAutomatonCegarLoop]: Abstraction has 71983 states and 100316 transitions. [2022-11-16 12:34:42,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:42,355 INFO L428 stractBuchiCegarLoop]: Abstraction has 71983 states and 100316 transitions. [2022-11-16 12:34:42,355 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-16 12:34:42,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71983 states and 100316 transitions. [2022-11-16 12:34:42,572 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71547 [2022-11-16 12:34:42,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:42,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:42,575 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:42,575 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:42,575 INFO L748 eck$LassoCheckResult]: Stem: 1371484#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 1371485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1371876#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1370872#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1370873#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1371137#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1371138#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1371738#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1371724#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1371211#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1371212#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1371461#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1371462#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1371297#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1371298#L838 assume !(0 == ~M_E~0); 1371470#L838-2 assume !(0 == ~T1_E~0); 1370834#L843-1 assume !(0 == ~T2_E~0); 1370835#L848-1 assume !(0 == ~T3_E~0); 1370952#L853-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1371284#L858-1 assume !(0 == ~T5_E~0); 1371285#L863-1 assume !(0 == ~T6_E~0); 1371804#L868-1 assume !(0 == ~T7_E~0); 1371805#L873-1 assume !(0 == ~T8_E~0); 1371798#L878-1 assume !(0 == ~E_1~0); 1371799#L883-1 assume !(0 == ~E_2~0); 1371839#L888-1 assume !(0 == ~E_3~0); 1371840#L893-1 assume !(0 == ~E_4~0); 1371841#L898-1 assume !(0 == ~E_5~0); 1371842#L903-1 assume !(0 == ~E_6~0); 1371772#L908-1 assume !(0 == ~E_7~0); 1371583#L913-1 assume !(0 == ~E_8~0); 1370848#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1370849#L402 assume !(1 == ~m_pc~0); 1371260#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1371261#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1371948#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1371947#L1035 assume !(0 != activate_threads_~tmp~1#1); 1371272#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1371273#L421 assume !(1 == ~t1_pc~0); 1371810#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1371811#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1371264#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1371265#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1371823#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1371824#L440 assume !(1 == ~t2_pc~0); 1371909#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1371910#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1371893#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1371894#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1371946#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1371171#L459 assume !(1 == ~t3_pc~0); 1371172#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1371944#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1371942#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1371940#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1371939#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1370978#L478 assume !(1 == ~t4_pc~0); 1370979#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1371736#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1371737#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1371143#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1371144#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1371486#L497 assume !(1 == ~t5_pc~0); 1371487#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1371522#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1371232#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1371233#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1371751#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1371752#L516 assume !(1 == ~t6_pc~0); 1371671#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1371672#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1371880#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1371022#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1371023#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1371538#L535 assume !(1 == ~t7_pc~0); 1371706#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1371536#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1371537#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1371934#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1371933#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1371743#L554 assume !(1 == ~t8_pc~0); 1370810#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1370811#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1371621#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1371109#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1371110#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1370796#L931 assume !(1 == ~M_E~0); 1370797#L931-2 assume !(1 == ~T1_E~0); 1371788#L936-1 assume !(1 == ~T2_E~0); 1371856#L941-1 assume !(1 == ~T3_E~0); 1371274#L946-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1371275#L951-1 assume !(1 == ~T5_E~0); 1371039#L956-1 assume !(1 == ~T6_E~0); 1371040#L961-1 assume !(1 == ~T7_E~0); 1371435#L966-1 assume !(1 == ~T8_E~0); 1371436#L971-1 assume !(1 == ~E_1~0); 1371565#L976-1 assume !(1 == ~E_2~0); 1371528#L981-1 assume !(1 == ~E_3~0); 1371279#L986-1 assume !(1 == ~E_4~0); 1371067#L991-1 assume !(1 == ~E_5~0); 1371068#L996-1 assume !(1 == ~E_6~0); 1371815#L1001-1 assume !(1 == ~E_7~0); 1371482#L1006-1 assume !(1 == ~E_8~0); 1371483#L1011-1 assume { :end_inline_reset_delta_events } true; 1371761#L1272-2 [2022-11-16 12:34:42,576 INFO L750 eck$LassoCheckResult]: Loop: 1371761#L1272-2 assume !false; 1399931#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1399819#L813 assume !false; 1399927#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1399919#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1399910#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1399908#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1399903#L696 assume !(0 != eval_~tmp~0#1); 1399905#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1421525#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1421523#L838-3 assume !(0 == ~M_E~0); 1421521#L838-5 assume !(0 == ~T1_E~0); 1421519#L843-3 assume !(0 == ~T2_E~0); 1421517#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1421514#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1421512#L858-3 assume !(0 == ~T5_E~0); 1421510#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1421508#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1421505#L873-3 assume !(0 == ~T8_E~0); 1421502#L878-3 assume !(0 == ~E_1~0); 1421500#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1421498#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1421496#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1421494#L898-3 assume !(0 == ~E_5~0); 1421492#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1421491#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1421489#L913-3 assume !(0 == ~E_8~0); 1421487#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1421485#L402-27 assume !(1 == ~m_pc~0); 1421483#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1421481#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1421478#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1421461#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1421450#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1421441#L421-27 assume !(1 == ~t1_pc~0); 1421437#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1421434#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1421433#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1421432#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1421431#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1421429#L440-27 assume !(1 == ~t2_pc~0); 1421428#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1421427#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1421426#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1421424#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1421422#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1421420#L459-27 assume !(1 == ~t3_pc~0); 1421416#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1421414#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1421412#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1421409#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1421406#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1421404#L478-27 assume !(1 == ~t4_pc~0); 1421402#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1421400#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1421398#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1421396#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1421394#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1421392#L497-27 assume !(1 == ~t5_pc~0); 1421367#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1421364#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1421362#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1421360#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1421358#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1421356#L516-27 assume !(1 == ~t6_pc~0); 1421354#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1421352#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1421350#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1421348#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1421332#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1421326#L535-27 assume !(1 == ~t7_pc~0); 1421319#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1421311#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1421304#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1421298#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1421292#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1421287#L554-27 assume !(1 == ~t8_pc~0); 1421282#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1421277#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1421271#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1421265#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1421259#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1421253#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1421245#L931-5 assume !(1 == ~T1_E~0); 1421236#L936-3 assume !(1 == ~T2_E~0); 1421228#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1421220#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1421211#L951-3 assume !(1 == ~T5_E~0); 1421203#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1421196#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1421189#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1421183#L971-3 assume !(1 == ~E_1~0); 1421177#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1421170#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1421163#L986-3 assume !(1 == ~E_4~0); 1421156#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1421150#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1421144#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1421137#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1421131#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1421019#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1421003#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1420996#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1420988#L1291 assume !(0 == start_simulation_~tmp~3#1); 1420980#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1399947#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1399945#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1399943#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1399941#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1399939#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1399937#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1399935#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1371761#L1272-2 [2022-11-16 12:34:42,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:42,577 INFO L85 PathProgramCache]: Analyzing trace with hash 1518911875, now seen corresponding path program 1 times [2022-11-16 12:34:42,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:42,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271195400] [2022-11-16 12:34:42,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:42,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:42,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:42,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:42,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:42,657 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271195400] [2022-11-16 12:34:42,657 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271195400] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:42,657 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:42,657 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:42,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630072133] [2022-11-16 12:34:42,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:42,658 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:42,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:42,659 INFO L85 PathProgramCache]: Analyzing trace with hash 395850754, now seen corresponding path program 1 times [2022-11-16 12:34:42,659 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:42,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518217163] [2022-11-16 12:34:42,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:42,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:42,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:42,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:42,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:42,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518217163] [2022-11-16 12:34:42,718 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [518217163] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:42,718 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:42,718 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:42,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143703526] [2022-11-16 12:34:42,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:42,719 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:42,719 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:42,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:34:42,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:34:42,720 INFO L87 Difference]: Start difference. First operand 71983 states and 100316 transitions. cyclomatic complexity: 28365 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:43,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:43,275 INFO L93 Difference]: Finished difference Result 126369 states and 176199 transitions. [2022-11-16 12:34:43,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126369 states and 176199 transitions. [2022-11-16 12:34:43,943 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 125750 [2022-11-16 12:34:44,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126369 states to 126369 states and 176199 transitions. [2022-11-16 12:34:44,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126369 [2022-11-16 12:34:45,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126369 [2022-11-16 12:34:45,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126369 states and 176199 transitions. [2022-11-16 12:34:45,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:45,368 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126369 states and 176199 transitions. [2022-11-16 12:34:45,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126369 states and 176199 transitions. [2022-11-16 12:34:46,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126369 to 63233. [2022-11-16 12:34:46,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63233 states, 63233 states have (on average 1.394256163711986) internal successors, (88163), 63232 states have internal predecessors, (88163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:46,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63233 states to 63233 states and 88163 transitions. [2022-11-16 12:34:46,213 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63233 states and 88163 transitions. [2022-11-16 12:34:46,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:34:46,214 INFO L428 stractBuchiCegarLoop]: Abstraction has 63233 states and 88163 transitions. [2022-11-16 12:34:46,214 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-16 12:34:46,214 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63233 states and 88163 transitions. [2022-11-16 12:34:46,399 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62875 [2022-11-16 12:34:46,400 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:46,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:46,402 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:46,402 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:46,404 INFO L748 eck$LassoCheckResult]: Stem: 1569851#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 1569852#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1570198#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1569234#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1569235#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1569506#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1569507#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1570098#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1570080#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1569577#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1569578#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1569828#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1569829#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1569663#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1569664#L838 assume !(0 == ~M_E~0); 1569836#L838-2 assume !(0 == ~T1_E~0); 1569196#L843-1 assume !(0 == ~T2_E~0); 1569197#L848-1 assume !(0 == ~T3_E~0); 1569314#L853-1 assume !(0 == ~T4_E~0); 1569648#L858-1 assume !(0 == ~T5_E~0); 1569146#L863-1 assume !(0 == ~T6_E~0); 1569147#L868-1 assume !(0 == ~T7_E~0); 1570157#L873-1 assume !(0 == ~T8_E~0); 1570155#L878-1 assume !(0 == ~E_1~0); 1570127#L883-1 assume !(0 == ~E_2~0); 1570128#L888-1 assume !(0 == ~E_3~0); 1569797#L893-1 assume !(0 == ~E_4~0); 1569798#L898-1 assume !(0 == ~E_5~0); 1570174#L903-1 assume !(0 == ~E_6~0); 1570126#L908-1 assume !(0 == ~E_7~0); 1569938#L913-1 assume !(0 == ~E_8~0); 1569210#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1569211#L402 assume !(1 == ~m_pc~0); 1569626#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1569336#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1569337#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1569584#L1035 assume !(0 != activate_threads_~tmp~1#1); 1569585#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1569639#L421 assume !(1 == ~t1_pc~0); 1570120#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1570158#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1569629#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1569630#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1569696#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1570168#L440 assume !(1 == ~t2_pc~0); 1570218#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1569346#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1569347#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1570186#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1569958#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1569534#L459 assume !(1 == ~t3_pc~0); 1569535#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1570118#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1569878#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1569329#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1569330#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1569340#L478 assume !(1 == ~t4_pc~0); 1569341#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1570018#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1570097#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1569512#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1569254#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1569255#L497 assume !(1 == ~t5_pc~0); 1569300#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1569301#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1569598#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1569599#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1570109#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1570110#L516 assume !(1 == ~t6_pc~0); 1570033#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1569826#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1569827#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1569386#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1569387#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1569818#L535 assume !(1 == ~t7_pc~0); 1569819#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1569896#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1569897#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1569929#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1569919#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1569920#L554 assume !(1 == ~t8_pc~0); 1569172#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1569173#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1569983#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1569471#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1569472#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1569158#L931 assume !(1 == ~M_E~0); 1569159#L931-2 assume !(1 == ~T1_E~0); 1570142#L936-1 assume !(1 == ~T2_E~0); 1570181#L941-1 assume !(1 == ~T3_E~0); 1569640#L946-1 assume !(1 == ~T4_E~0); 1569641#L951-1 assume !(1 == ~T5_E~0); 1569402#L956-1 assume !(1 == ~T6_E~0); 1569403#L961-1 assume !(1 == ~T7_E~0); 1569799#L966-1 assume !(1 == ~T8_E~0); 1569800#L971-1 assume !(1 == ~E_1~0); 1569922#L976-1 assume !(1 == ~E_2~0); 1569888#L981-1 assume !(1 == ~E_3~0); 1569645#L986-1 assume !(1 == ~E_4~0); 1569430#L991-1 assume !(1 == ~E_5~0); 1569431#L996-1 assume !(1 == ~E_6~0); 1570162#L1001-1 assume !(1 == ~E_7~0); 1569849#L1006-1 assume !(1 == ~E_8~0); 1569850#L1011-1 assume { :end_inline_reset_delta_events } true; 1570119#L1272-2 [2022-11-16 12:34:46,405 INFO L750 eck$LassoCheckResult]: Loop: 1570119#L1272-2 assume !false; 1595668#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1595664#L813 assume !false; 1595663#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1595661#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1595650#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1595648#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1595645#L696 assume !(0 != eval_~tmp~0#1); 1595646#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1595899#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1595896#L838-3 assume !(0 == ~M_E~0); 1595894#L838-5 assume !(0 == ~T1_E~0); 1595892#L843-3 assume !(0 == ~T2_E~0); 1595890#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1595888#L853-3 assume !(0 == ~T4_E~0); 1595886#L858-3 assume !(0 == ~T5_E~0); 1595884#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1595882#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1595880#L873-3 assume !(0 == ~T8_E~0); 1595878#L878-3 assume !(0 == ~E_1~0); 1595876#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1595874#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1595872#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1595870#L898-3 assume !(0 == ~E_5~0); 1595868#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1595866#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1595864#L913-3 assume !(0 == ~E_8~0); 1595862#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1595860#L402-27 assume !(1 == ~m_pc~0); 1595858#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1595856#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1595854#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1595852#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1595850#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1595848#L421-27 assume !(1 == ~t1_pc~0); 1595846#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1595844#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1595842#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1595841#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1595840#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1595839#L440-27 assume !(1 == ~t2_pc~0); 1595838#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1595837#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1595836#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1595835#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1595834#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1595833#L459-27 assume 1 == ~t3_pc~0; 1595832#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1595830#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1595828#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1595825#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1595824#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1595823#L478-27 assume !(1 == ~t4_pc~0); 1595822#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1595820#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1595818#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1595817#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1595816#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1595815#L497-27 assume !(1 == ~t5_pc~0); 1595813#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1595811#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1595809#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1595807#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1595805#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1595803#L516-27 assume !(1 == ~t6_pc~0); 1595801#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1595799#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1595797#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1595795#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1595793#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1595791#L535-27 assume !(1 == ~t7_pc~0); 1595788#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1595786#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1595784#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1595782#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1595780#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1595778#L554-27 assume !(1 == ~t8_pc~0); 1595776#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1595774#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1595771#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1595769#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1595767#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1595764#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1595762#L931-5 assume !(1 == ~T1_E~0); 1595760#L936-3 assume !(1 == ~T2_E~0); 1595758#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1595756#L946-3 assume !(1 == ~T4_E~0); 1595754#L951-3 assume !(1 == ~T5_E~0); 1595752#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1595750#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1595748#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1595745#L971-3 assume !(1 == ~E_1~0); 1595743#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1595741#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1595739#L986-3 assume !(1 == ~E_4~0); 1595737#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1595735#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1595733#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1595731#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1595729#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1595727#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1595717#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1595715#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1595711#L1291 assume !(0 == start_simulation_~tmp~3#1); 1595708#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1595690#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1595689#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1595685#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1595683#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1595681#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1595676#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1595673#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1570119#L1272-2 [2022-11-16 12:34:46,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:46,406 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 2 times [2022-11-16 12:34:46,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:46,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422769894] [2022-11-16 12:34:46,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:46,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:46,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:34:46,424 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:34:46,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:34:46,474 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:34:46,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:46,475 INFO L85 PathProgramCache]: Analyzing trace with hash -949810591, now seen corresponding path program 1 times [2022-11-16 12:34:46,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:46,475 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703971094] [2022-11-16 12:34:46,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:46,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:46,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:46,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:46,521 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:46,521 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703971094] [2022-11-16 12:34:46,521 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703971094] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:46,522 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:46,522 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:46,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663772494] [2022-11-16 12:34:46,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:46,522 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:46,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:46,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:34:46,523 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:34:46,523 INFO L87 Difference]: Start difference. First operand 63233 states and 88163 transitions. cyclomatic complexity: 24962 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:46,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:46,896 INFO L93 Difference]: Finished difference Result 93797 states and 130066 transitions. [2022-11-16 12:34:46,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93797 states and 130066 transitions. [2022-11-16 12:34:48,032 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 93291 [2022-11-16 12:34:48,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93797 states to 93797 states and 130066 transitions. [2022-11-16 12:34:48,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 93797 [2022-11-16 12:34:48,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 93797 [2022-11-16 12:34:48,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93797 states and 130066 transitions. [2022-11-16 12:34:48,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:48,269 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93797 states and 130066 transitions. [2022-11-16 12:34:48,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93797 states and 130066 transitions. [2022-11-16 12:34:48,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93797 to 93743. [2022-11-16 12:34:48,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93743 states, 93743 states have (on average 1.3868982217338894) internal successors, (130012), 93742 states have internal predecessors, (130012), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:49,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93743 states to 93743 states and 130012 transitions. [2022-11-16 12:34:49,775 INFO L240 hiAutomatonCegarLoop]: Abstraction has 93743 states and 130012 transitions. [2022-11-16 12:34:49,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:34:49,776 INFO L428 stractBuchiCegarLoop]: Abstraction has 93743 states and 130012 transitions. [2022-11-16 12:34:49,776 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-16 12:34:49,776 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93743 states and 130012 transitions. [2022-11-16 12:34:50,030 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 93237 [2022-11-16 12:34:50,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:34:50,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:34:50,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:50,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:34:50,032 INFO L748 eck$LassoCheckResult]: Stem: 1726883#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~T3_E~0 := 2;~T1_E~0 := 2;~t3_pc~0 := 0;~t5_pc~0 := 0;~T8_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T6_E~0 := 2;~t7_pc~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~m_i~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t3_i~0 := 0;~t2_i~0 := 0;~t5_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t5_st~0 := 0;~t4_pc~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t8_pc~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~t2_st~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_8~0 := 2; 1726884#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1727278#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1726270#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1726271#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1726537#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1726538#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1727141#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1727125#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1726611#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1726612#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1726860#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1726861#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1726697#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1726698#L838 assume !(0 == ~M_E~0); 1726869#L838-2 assume !(0 == ~T1_E~0); 1726232#L843-1 assume !(0 == ~T2_E~0); 1726233#L848-1 assume !(0 == ~T3_E~0); 1726350#L853-1 assume !(0 == ~T4_E~0); 1726683#L858-1 assume !(0 == ~T5_E~0); 1726182#L863-1 assume !(0 == ~T6_E~0); 1726183#L868-1 assume !(0 == ~T7_E~0); 1727212#L873-1 assume !(0 == ~T8_E~0); 1727210#L878-1 assume !(0 == ~E_1~0); 1727184#L883-1 assume !(0 == ~E_2~0); 1727185#L888-1 assume !(0 == ~E_3~0); 1726830#L893-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1726831#L898-1 assume !(0 == ~E_5~0); 1727244#L903-1 assume !(0 == ~E_6~0); 1727328#L908-1 assume !(0 == ~E_7~0); 1727361#L913-1 assume !(0 == ~E_8~0); 1727360#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1727359#L402 assume !(1 == ~m_pc~0); 1727358#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1726374#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1726375#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1726618#L1035 assume !(0 != activate_threads_~tmp~1#1); 1726619#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1727170#L421 assume !(1 == ~t1_pc~0); 1727171#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1727313#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1727314#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1726729#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1726730#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1727320#L440 assume !(1 == ~t2_pc~0); 1727321#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1726384#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1726385#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1727265#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1726996#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1726997#L459 assume !(1 == ~t3_pc~0); 1727164#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1727165#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1727363#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1726367#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1726368#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1727330#L478 assume !(1 == ~t4_pc~0); 1727059#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1727060#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1727261#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1727262#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1726290#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1726291#L497 assume !(1 == ~t5_pc~0); 1726335#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1726336#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1727348#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1727232#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1727233#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1727304#L516 assume !(1 == ~t6_pc~0); 1727305#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1726857#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1726858#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1727347#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1727346#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1726848#L535 assume !(1 == ~t7_pc~0); 1726849#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1727345#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1727080#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1726965#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1726954#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1726955#L554 assume !(1 == ~t8_pc~0); 1727342#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1727263#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1727264#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1726505#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1726506#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1726964#L931 assume !(1 == ~M_E~0); 1727197#L931-2 assume !(1 == ~T1_E~0); 1727198#L936-1 assume !(1 == ~T2_E~0); 1727316#L941-1 assume !(1 == ~T3_E~0); 1727317#L946-1 assume !(1 == ~T4_E~0); 1727166#L951-1 assume !(1 == ~T5_E~0); 1726438#L956-1 assume !(1 == ~T6_E~0); 1726439#L961-1 assume !(1 == ~T7_E~0); 1726833#L966-1 assume !(1 == ~T8_E~0); 1726834#L971-1 assume !(1 == ~E_1~0); 1726956#L976-1 assume !(1 == ~E_2~0); 1726922#L981-1 assume !(1 == ~E_3~0); 1726680#L986-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1726466#L991-1 assume !(1 == ~E_5~0); 1726467#L996-1 assume !(1 == ~E_6~0); 1727224#L1001-1 assume !(1 == ~E_7~0); 1726881#L1006-1 assume !(1 == ~E_8~0); 1726882#L1011-1 assume { :end_inline_reset_delta_events } true; 1727167#L1272-2 [2022-11-16 12:34:50,032 INFO L750 eck$LassoCheckResult]: Loop: 1727167#L1272-2 assume !false; 1764915#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1764688#L813 assume !false; 1764689#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1764671#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1764662#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1764660#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1764657#L696 assume !(0 != eval_~tmp~0#1); 1764658#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1781267#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1781265#L838-3 assume !(0 == ~M_E~0); 1781262#L838-5 assume !(0 == ~T1_E~0); 1781260#L843-3 assume !(0 == ~T2_E~0); 1781258#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1781256#L853-3 assume !(0 == ~T4_E~0); 1781254#L858-3 assume !(0 == ~T5_E~0); 1781250#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1777811#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1777801#L873-3 assume !(0 == ~T8_E~0); 1777799#L878-3 assume !(0 == ~E_1~0); 1777797#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1777795#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1777792#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1777790#L898-3 assume !(0 == ~E_5~0); 1777788#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1777786#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1777785#L913-3 assume !(0 == ~E_8~0); 1777784#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1777782#L402-27 assume !(1 == ~m_pc~0); 1777780#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1777778#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1777773#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1777771#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1777769#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1777768#L421-27 assume !(1 == ~t1_pc~0); 1777767#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1777766#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1777756#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1777754#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1777752#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1777749#L440-27 assume !(1 == ~t2_pc~0); 1777748#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1777745#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1777742#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1777737#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1777732#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1777728#L459-27 assume !(1 == ~t3_pc~0); 1777721#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1777716#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1777714#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1777711#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1777708#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1777705#L478-27 assume !(1 == ~t4_pc~0); 1777703#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1777701#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1777699#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1777697#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1777695#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1777693#L497-27 assume 1 == ~t5_pc~0; 1777646#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1777642#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1777640#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1777638#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1777636#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1777634#L516-27 assume !(1 == ~t6_pc~0); 1777632#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1777630#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1777628#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1777625#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1777623#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1777621#L535-27 assume 1 == ~t7_pc~0; 1777619#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1777616#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1777614#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1777612#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1777610#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1777607#L554-27 assume !(1 == ~t8_pc~0); 1777605#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1777603#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1777601#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1777599#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1777597#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1777595#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1777593#L931-5 assume !(1 == ~T1_E~0); 1777591#L936-3 assume !(1 == ~T2_E~0); 1777589#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1777587#L946-3 assume !(1 == ~T4_E~0); 1777585#L951-3 assume !(1 == ~T5_E~0); 1777583#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1777581#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1777579#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1777577#L971-3 assume !(1 == ~E_1~0); 1777575#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1777573#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1777571#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1777568#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1777566#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1777564#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1777562#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1777560#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1777558#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1777548#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1777546#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1777533#L1291 assume !(0 == start_simulation_~tmp~3#1); 1777201#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1764711#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1764709#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1764707#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1764705#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1764703#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1764700#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1764701#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1727167#L1272-2 [2022-11-16 12:34:50,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:50,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1947895171, now seen corresponding path program 1 times [2022-11-16 12:34:50,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:50,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142959159] [2022-11-16 12:34:50,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:50,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:50,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:50,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:50,096 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:50,096 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142959159] [2022-11-16 12:34:50,096 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142959159] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:50,096 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:50,097 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:34:50,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284245348] [2022-11-16 12:34:50,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:50,097 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 12:34:50,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:34:50,098 INFO L85 PathProgramCache]: Analyzing trace with hash -1696622334, now seen corresponding path program 1 times [2022-11-16 12:34:50,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:34:50,099 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043044861] [2022-11-16 12:34:50,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:34:50,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:34:50,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:34:50,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:34:50,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:34:50,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043044861] [2022-11-16 12:34:50,168 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043044861] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:34:50,168 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:34:50,168 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:34:50,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320097579] [2022-11-16 12:34:50,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:34:50,169 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:34:50,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:34:50,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:34:50,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:34:50,170 INFO L87 Difference]: Start difference. First operand 93743 states and 130012 transitions. cyclomatic complexity: 36301 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:34:50,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:34:50,820 INFO L93 Difference]: Finished difference Result 171771 states and 238818 transitions. [2022-11-16 12:34:50,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 171771 states and 238818 transitions. [2022-11-16 12:34:52,260 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 163372 [2022-11-16 12:34:52,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 171771 states to 171771 states and 238818 transitions. [2022-11-16 12:34:52,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 171771 [2022-11-16 12:34:52,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 171771 [2022-11-16 12:34:52,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171771 states and 238818 transitions. [2022-11-16 12:34:52,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:34:52,943 INFO L218 hiAutomatonCegarLoop]: Abstraction has 171771 states and 238818 transitions. [2022-11-16 12:34:53,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171771 states and 238818 transitions.