./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.13.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.13.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:56:20,896 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:56:20,901 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:56:20,948 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:56:20,951 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:56:20,954 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:56:20,958 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:56:20,965 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:56:20,970 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:56:20,972 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:56:20,975 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:56:20,978 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:56:20,981 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:56:20,985 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:56:20,989 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:56:20,994 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:56:20,996 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:56:21,003 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:56:21,006 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:56:21,011 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:56:21,016 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:56:21,019 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:56:21,023 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:56:21,025 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:56:21,035 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:56:21,036 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:56:21,036 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:56:21,039 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:56:21,040 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:56:21,042 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:56:21,043 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:56:21,044 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:56:21,047 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:56:21,049 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:56:21,052 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:56:21,052 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:56:21,054 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:56:21,054 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:56:21,055 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:56:21,056 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:56:21,057 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:56:21,059 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 11:56:21,125 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:56:21,126 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:56:21,127 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:56:21,127 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:56:21,129 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:56:21,130 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:56:21,130 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:56:21,131 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 11:56:21,131 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 11:56:21,131 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 11:56:21,133 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 11:56:21,133 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 11:56:21,134 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 11:56:21,134 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:56:21,135 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 11:56:21,135 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 11:56:21,135 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:56:21,136 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 11:56:21,136 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:56:21,136 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 11:56:21,137 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 11:56:21,137 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 11:56:21,137 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 11:56:21,138 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:56:21,138 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 11:56:21,138 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:56:21,139 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 11:56:21,139 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:56:21,139 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:56:21,140 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:56:21,140 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:56:21,142 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 11:56:21,142 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 [2022-11-16 11:56:21,611 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:56:21,665 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:56:21,669 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:56:21,670 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:56:21,671 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:56:21,673 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/transmitter.13.cil.c [2022-11-16 11:56:21,762 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/data/bf94b3295/b8d4212f89b147b587316b799f83aa61/FLAGb58a24a41 [2022-11-16 11:56:22,376 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:56:22,377 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/sv-benchmarks/c/systemc/transmitter.13.cil.c [2022-11-16 11:56:22,390 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/data/bf94b3295/b8d4212f89b147b587316b799f83aa61/FLAGb58a24a41 [2022-11-16 11:56:22,700 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/data/bf94b3295/b8d4212f89b147b587316b799f83aa61 [2022-11-16 11:56:22,705 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:56:22,706 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:56:22,713 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:56:22,713 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:56:22,717 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:56:22,717 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:56:22" (1/1) ... [2022-11-16 11:56:22,719 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@40bc6e95 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:22, skipping insertion in model container [2022-11-16 11:56:22,719 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:56:22" (1/1) ... [2022-11-16 11:56:22,726 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:56:22,802 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:56:23,040 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2022-11-16 11:56:23,261 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:56:23,276 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:56:23,294 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2022-11-16 11:56:23,396 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:56:23,432 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:56:23,432 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23 WrapperNode [2022-11-16 11:56:23,433 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:56:23,434 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:56:23,434 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:56:23,434 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:56:23,440 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,453 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,595 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2022-11-16 11:56:23,595 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:56:23,596 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:56:23,596 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:56:23,596 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:56:23,606 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,606 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,617 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,622 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,677 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,721 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,732 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,744 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,761 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:56:23,763 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:56:23,763 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:56:23,764 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:56:23,765 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (1/1) ... [2022-11-16 11:56:23,772 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:56:23,784 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:56:23,800 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:56:23,829 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e2601be1-4053-4e04-8399-ed6f871d5a38/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 11:56:23,849 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 11:56:23,850 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 11:56:23,850 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:56:23,850 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:56:24,000 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:56:24,003 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:56:26,791 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:56:26,817 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:56:26,817 INFO L300 CfgBuilder]: Removed 17 assume(true) statements. [2022-11-16 11:56:26,822 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:56:26 BoogieIcfgContainer [2022-11-16 11:56:26,823 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:56:26,824 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 11:56:26,824 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 11:56:26,829 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 11:56:26,830 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:56:26,830 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 11:56:22" (1/3) ... [2022-11-16 11:56:26,831 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@42b62c0f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:56:26, skipping insertion in model container [2022-11-16 11:56:26,832 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:56:26,832 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:56:23" (2/3) ... [2022-11-16 11:56:26,832 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@42b62c0f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:56:26, skipping insertion in model container [2022-11-16 11:56:26,832 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:56:26,833 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:56:26" (3/3) ... [2022-11-16 11:56:26,834 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.13.cil.c [2022-11-16 11:56:26,948 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 11:56:26,948 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 11:56:26,948 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 11:56:26,948 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 11:56:26,949 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 11:56:26,949 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 11:56:26,949 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 11:56:26,949 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 11:56:26,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:27,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2022-11-16 11:56:27,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:27,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:27,087 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:27,088 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:27,088 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 11:56:27,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:27,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2022-11-16 11:56:27,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:27,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:27,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:27,126 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:27,150 INFO L748 eck$LassoCheckResult]: Stem: 460#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1833#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 351#L1855true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200#L874true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1759#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1072#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1410#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 271#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1401#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 544#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 438#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 795#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 305#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 553#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 683#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 803#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 833#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 920#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 312#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1814#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1399#L1258-2true assume !(0 == ~T1_E~0); 489#L1263-1true assume !(0 == ~T2_E~0); 709#L1268-1true assume !(0 == ~T3_E~0); 1365#L1273-1true assume !(0 == ~T4_E~0); 1748#L1278-1true assume !(0 == ~T5_E~0); 1152#L1283-1true assume !(0 == ~T6_E~0); 1780#L1288-1true assume !(0 == ~T7_E~0); 1568#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1539#L1298-1true assume !(0 == ~T9_E~0); 1383#L1303-1true assume !(0 == ~T10_E~0); 214#L1308-1true assume !(0 == ~T11_E~0); 185#L1313-1true assume !(0 == ~T12_E~0); 1838#L1318-1true assume !(0 == ~T13_E~0); 188#L1323-1true assume !(0 == ~E_1~0); 276#L1328-1true assume !(0 == ~E_2~0); 1789#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 973#L1338-1true assume !(0 == ~E_4~0); 1112#L1343-1true assume !(0 == ~E_5~0); 1650#L1348-1true assume !(0 == ~E_6~0); 1667#L1353-1true assume !(0 == ~E_7~0); 725#L1358-1true assume !(0 == ~E_8~0); 999#L1363-1true assume !(0 == ~E_9~0); 1061#L1368-1true assume !(0 == ~E_10~0); 104#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 488#L1378-1true assume !(0 == ~E_12~0); 249#L1383-1true assume !(0 == ~E_13~0); 1101#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 729#L607true assume 1 == ~m_pc~0; 1009#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1108#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1626#L619true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 667#L1560true assume !(0 != activate_threads_~tmp~1#1); 1724#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 195#L626true assume !(1 == ~t1_pc~0); 1266#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 338#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 440#L638true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1907#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 146#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1336#L645true assume 1 == ~t2_pc~0; 204#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1300#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 583#L657true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1899#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 652#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1704#L664true assume 1 == ~t3_pc~0; 1633#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1126#L676true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 416#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1419#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1627#L683true assume !(1 == ~t4_pc~0); 986#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 785#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 810#L695true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1694#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 931#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 614#L702true assume 1 == ~t5_pc~0; 1684#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 925#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1343#L714true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1391#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1237#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89#L721true assume !(1 == ~t6_pc~0); 76#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 160#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 556#L733true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 421#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1524#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 867#L740true assume 1 == ~t7_pc~0; 115#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 757#L752true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 762#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 384#L759true assume !(1 == ~t8_pc~0); 1373#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1843#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 923#L771true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1083#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1670#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1567#L778true assume 1 == ~t9_pc~0; 1341#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1273#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72#L790true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 733#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 202#L797true assume !(1 == ~t10_pc~0); 264#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1306#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1181#L809true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 487#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 696#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1390#L816true assume 1 == ~t11_pc~0; 56#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 587#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 462#L828true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 426#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1511#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 802#L835true assume 1 == ~t12_pc~0; 705#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 150#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 221#L847true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1783#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 526#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1442#L854true assume !(1 == ~t13_pc~0); 306#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 335#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1081#L866true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 159#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1230#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1790#L1401true assume !(1 == ~M_E~0); 418#L1401-2true assume !(1 == ~T1_E~0); 1240#L1406-1true assume !(1 == ~T2_E~0); 858#L1411-1true assume !(1 == ~T3_E~0); 1611#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 594#L1421-1true assume !(1 == ~T5_E~0); 304#L1426-1true assume !(1 == ~T6_E~0); 1014#L1431-1true assume !(1 == ~T7_E~0); 74#L1436-1true assume !(1 == ~T8_E~0); 745#L1441-1true assume !(1 == ~T9_E~0); 482#L1446-1true assume !(1 == ~T10_E~0); 1772#L1451-1true assume !(1 == ~T11_E~0); 1107#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 744#L1461-1true assume !(1 == ~T13_E~0); 435#L1466-1true assume !(1 == ~E_1~0); 1767#L1471-1true assume !(1 == ~E_2~0); 1082#L1476-1true assume !(1 == ~E_3~0); 1314#L1481-1true assume !(1 == ~E_4~0); 1592#L1486-1true assume !(1 == ~E_5~0); 224#L1491-1true assume !(1 == ~E_6~0); 41#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 756#L1501-1true assume !(1 == ~E_8~0); 480#L1506-1true assume !(1 == ~E_9~0); 1037#L1511-1true assume !(1 == ~E_10~0); 453#L1516-1true assume !(1 == ~E_11~0); 13#L1521-1true assume !(1 == ~E_12~0); 40#L1526-1true assume !(1 == ~E_13~0); 318#L1531-1true assume { :end_inline_reset_delta_events } true; 1171#L1892-2true [2022-11-16 11:56:27,155 INFO L750 eck$LassoCheckResult]: Loop: 1171#L1892-2true assume !false; 1867#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1513#L1233true assume !true; 80#L1248true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 804#L874-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1629#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1898#L1258-5true assume !(0 == ~T1_E~0); 153#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1603#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1618#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1905#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1620#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 266#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1788#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1168#L1298-3true assume !(0 == ~T9_E~0); 1693#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1427#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1167#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 658#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 154#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1301#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1672#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 228#L1338-3true assume !(0 == ~E_4~0); 1055#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1540#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1311#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1352#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 626#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 339#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1884#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 884#L1378-3true assume !(0 == ~E_12~0); 1459#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1099#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1766#L607-42true assume !(1 == ~m_pc~0); 911#L607-44true is_master_triggered_~__retres1~0#1 := 0; 509#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1075#L619-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 348#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 697#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1219#L626-42true assume 1 == ~t1_pc~0; 398#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1471#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 599#L638-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1130#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 170#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1573#L645-42true assume 1 == ~t2_pc~0; 1415#L646-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1695#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1252#L657-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 277#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1661#L664-42true assume 1 == ~t3_pc~0; 456#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1623#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1474#L676-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 832#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1015#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1787#L683-42true assume 1 == ~t4_pc~0; 1698#L684-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 840#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1768#L695-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1411#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1903#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162#L702-42true assume !(1 == ~t5_pc~0); 394#L702-44true is_transmit5_triggered_~__retres1~5#1 := 0; 589#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1733#L714-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1287#L1600-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113#L721-42true assume 1 == ~t6_pc~0; 122#L722-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 367#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1619#L733-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1587#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 469#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 378#L740-42true assume !(1 == ~t7_pc~0); 235#L740-44true is_transmit7_triggered_~__retres1~7#1 := 0; 560#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 559#L752-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 458#L1616-42true assume !(0 != activate_threads_~tmp___6~0#1); 650#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1895#L759-42true assume 1 == ~t8_pc~0; 539#L760-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 492#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 673#L771-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 546#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 616#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1174#L778-42true assume 1 == ~t9_pc~0; 500#L779-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 808#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1749#L790-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 732#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1612#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 780#L797-42true assume !(1 == ~t10_pc~0); 1045#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 937#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1375#L809-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1876#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 809#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1708#L816-42true assume !(1 == ~t11_pc~0); 346#L816-44true is_transmit11_triggered_~__retres1~11#1 := 0; 1851#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 284#L828-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 485#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 327#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 586#L835-42true assume !(1 == ~t12_pc~0); 506#L835-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1243#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 313#L847-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1837#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1236#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 949#L854-42true assume !(1 == ~t13_pc~0); 283#L854-44true is_transmit13_triggered_~__retres1~13#1 := 0; 481#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85#L866-14true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 514#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 434#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1854#L1401-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1093#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 203#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 135#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1679#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 464#L1421-3true assume !(1 == ~T5_E~0); 1052#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 227#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 292#L1436-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 16#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1144#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1135#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 520#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 308#L1461-3true assume !(1 == ~T13_E~0); 1610#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1816#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 278#L1476-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1686#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 513#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 291#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1481#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 543#L1501-3true assume !(1 == ~E_8~0); 1594#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 881#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 874#L1516-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1718#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 629#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 969#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1842#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1880#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 760#L1032-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 493#L1911true assume !(0 == start_simulation_~tmp~3#1); 1304#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 906#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1024#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 842#L1032-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 106#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 519#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 223#L1874true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1348#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1171#L1892-2true [2022-11-16 11:56:27,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:27,164 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2022-11-16 11:56:27,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:27,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674602270] [2022-11-16 11:56:27,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:27,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:27,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:27,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:27,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:27,599 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1674602270] [2022-11-16 11:56:27,600 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1674602270] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:27,600 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:27,600 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:27,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984625036] [2022-11-16 11:56:27,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:27,607 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:27,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:27,608 INFO L85 PathProgramCache]: Analyzing trace with hash -691250693, now seen corresponding path program 1 times [2022-11-16 11:56:27,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:27,608 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418502633] [2022-11-16 11:56:27,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:27,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:27,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:27,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:27,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:27,667 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [418502633] [2022-11-16 11:56:27,668 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [418502633] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:27,668 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:27,668 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:56:27,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081075682] [2022-11-16 11:56:27,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:27,670 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:27,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:27,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-16 11:56:27,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 11:56:27,726 INFO L87 Difference]: Start difference. First operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:27,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:27,811 INFO L93 Difference]: Finished difference Result 1920 states and 2841 transitions. [2022-11-16 11:56:27,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1920 states and 2841 transitions. [2022-11-16 11:56:27,832 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:27,849 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1920 states to 1914 states and 2835 transitions. [2022-11-16 11:56:27,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:27,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:27,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2022-11-16 11:56:27,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:27,862 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-11-16 11:56:27,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2022-11-16 11:56:27,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:28,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:28,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2022-11-16 11:56:28,013 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-11-16 11:56:28,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-16 11:56:28,019 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-11-16 11:56:28,020 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 11:56:28,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2022-11-16 11:56:28,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:28,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:28,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:28,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:28,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:28,037 INFO L748 eck$LassoCheckResult]: Stem: 4711#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4531#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4247#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4248#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5424#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5425#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4383#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4384#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4838#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4673#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4674#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4450#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4451#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4849#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5026#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5180#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5217#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4461#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4462#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5637#L1258-2 assume !(0 == ~T1_E~0); 4756#L1263-1 assume !(0 == ~T2_E~0); 4757#L1268-1 assume !(0 == ~T3_E~0); 5060#L1273-1 assume !(0 == ~T4_E~0); 5619#L1278-1 assume !(0 == ~T5_E~0); 5480#L1283-1 assume !(0 == ~T6_E~0); 5481#L1288-1 assume !(0 == ~T7_E~0); 5717#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5705#L1298-1 assume !(0 == ~T9_E~0); 5631#L1303-1 assume !(0 == ~T10_E~0); 4276#L1308-1 assume !(0 == ~T11_E~0); 4218#L1313-1 assume !(0 == ~T12_E~0); 4219#L1318-1 assume !(0 == ~T13_E~0); 4225#L1323-1 assume !(0 == ~E_1~0); 4226#L1328-1 assume !(0 == ~E_2~0); 4393#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5352#L1338-1 assume !(0 == ~E_4~0); 5353#L1343-1 assume !(0 == ~E_5~0); 5454#L1348-1 assume !(0 == ~E_6~0); 5740#L1353-1 assume !(0 == ~E_7~0); 5079#L1358-1 assume !(0 == ~E_8~0); 5080#L1363-1 assume !(0 == ~E_9~0); 5370#L1368-1 assume !(0 == ~E_10~0); 4055#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4056#L1378-1 assume !(0 == ~E_12~0); 4342#L1383-1 assume !(0 == ~E_13~0); 4343#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5086#L607 assume 1 == ~m_pc~0; 5087#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4413#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5452#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5006#L1560 assume !(0 != activate_threads_~tmp~1#1); 5007#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4238#L626 assume !(1 == ~t1_pc~0); 4239#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4507#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4508#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4677#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4138#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4139#L645 assume 1 == ~t2_pc~0; 4255#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4212#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4889#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4890#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4982#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4983#L664 assume 1 == ~t3_pc~0; 5739#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3979#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3980#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4638#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4639#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5647#L683 assume !(1 == ~t4_pc~0); 5202#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5154#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5155#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5189#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5313#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4932#L702 assume 1 == ~t5_pc~0; 4933#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4858#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5308#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5606#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5547#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4027#L721 assume !(1 == ~t6_pc~0); 4001#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4002#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4165#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4647#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4648#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5249#L740 assume 1 == ~t7_pc~0; 4076#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3889#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3890#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3879#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3880#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4583#L759 assume !(1 == ~t8_pc~0); 4584#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4613#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5306#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5307#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5438#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5716#L778 assume 1 == ~t9_pc~0; 5603#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4054#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3994#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3923#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3924#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4251#L797 assume !(1 == ~t10_pc~0); 4252#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4370#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5504#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4754#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4755#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5044#L816 assume 1 == ~t11_pc~0; 3959#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3960#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4715#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4654#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4655#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5179#L835 assume 1 == ~t12_pc~0; 5057#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4123#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4145#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4286#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4811#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4812#L854 assume !(1 == ~t13_pc~0); 4452#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4453#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4503#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4163#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4164#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5543#L1401 assume !(1 == ~M_E~0); 4642#L1401-2 assume !(1 == ~T1_E~0); 4643#L1406-1 assume !(1 == ~T2_E~0); 5238#L1411-1 assume !(1 == ~T3_E~0); 5239#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4905#L1421-1 assume !(1 == ~T5_E~0); 4448#L1426-1 assume !(1 == ~T6_E~0); 4449#L1431-1 assume !(1 == ~T7_E~0); 3997#L1436-1 assume !(1 == ~T8_E~0); 3998#L1441-1 assume !(1 == ~T9_E~0); 4745#L1446-1 assume !(1 == ~T10_E~0); 4746#L1451-1 assume !(1 == ~T11_E~0); 5451#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5105#L1461-1 assume !(1 == ~T13_E~0); 4666#L1466-1 assume !(1 == ~E_1~0); 4667#L1471-1 assume !(1 == ~E_2~0); 5436#L1476-1 assume !(1 == ~E_3~0); 5437#L1481-1 assume !(1 == ~E_4~0); 5585#L1486-1 assume !(1 == ~E_5~0); 4291#L1491-1 assume !(1 == ~E_6~0); 3931#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3932#L1501-1 assume !(1 == ~E_8~0); 4743#L1506-1 assume !(1 == ~E_9~0); 4744#L1511-1 assume !(1 == ~E_10~0); 4700#L1516-1 assume !(1 == ~E_11~0); 3875#L1521-1 assume !(1 == ~E_12~0); 3876#L1526-1 assume !(1 == ~E_13~0); 3930#L1531-1 assume { :end_inline_reset_delta_events } true; 4473#L1892-2 [2022-11-16 11:56:28,038 INFO L750 eck$LassoCheckResult]: Loop: 4473#L1892-2 assume !false; 5496#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5694#L1233 assume !false; 5677#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5009#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4989#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5147#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3973#L1046 assume !(0 != eval_~tmp~0#1); 3975#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4009#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5181#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5738#L1258-5 assume !(0 == ~T1_E~0); 4151#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4152#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5730#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5736#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5737#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4375#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4376#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5493#L1298-3 assume !(0 == ~T9_E~0); 5494#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5653#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5492#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4993#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4153#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4154#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5577#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4296#L1338-3 assume !(0 == ~E_4~0); 4297#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5409#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5582#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5583#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4949#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4509#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4510#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5266#L1378-3 assume !(0 == ~E_12~0); 5267#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5448#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5449#L607-42 assume 1 == ~m_pc~0; 5062#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4790#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4791#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4523#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4524#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5045#L626-42 assume !(1 == ~t1_pc~0); 4609#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 4608#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4912#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4913#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4187#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4188#L645-42 assume !(1 == ~t2_pc~0); 5387#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5388#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5553#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4394#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3901#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3902#L664-42 assume 1 == ~t3_pc~0; 4704#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4429#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5680#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5215#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5216#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5381#L683-42 assume !(1 == ~t4_pc~0); 5089#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 5090#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5222#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5642#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5643#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5487#L702-42 assume !(1 == ~t5_pc~0); 4599#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4600#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4896#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5569#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3917#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3918#L721-42 assume 1 == ~t6_pc~0; 4071#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4091#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4555#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5722#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4727#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4573#L740-42 assume !(1 == ~t7_pc~0); 4310#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4311#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4852#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4707#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 4708#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4981#L759-42 assume 1 == ~t8_pc~0; 4830#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4762#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4763#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4841#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4842#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4937#L778-42 assume 1 == ~t9_pc~0; 4774#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4776#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5186#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5091#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5092#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5149#L797-42 assume 1 == ~t10_pc~0; 4316#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4317#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5318#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5627#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5187#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5188#L816-42 assume 1 == ~t11_pc~0; 3865#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3866#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4408#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4409#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4488#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4489#L835-42 assume !(1 == ~t12_pc~0); 4785#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4786#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4463#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4464#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5546#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5330#L854-42 assume 1 == ~t13_pc~0; 5331#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4407#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4017#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4018#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4664#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4665#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5443#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4254#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4118#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4119#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4718#L1421-3 assume !(1 == ~T5_E~0); 4719#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4294#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4295#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3881#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3882#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5471#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4802#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4455#L1461-3 assume !(1 == ~T13_E~0); 4456#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5733#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4395#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4396#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4796#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4423#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4424#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4836#L1501-3 assume !(1 == ~E_8~0); 4837#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5263#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5253#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5254#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4953#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4954#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5348#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4230#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5123#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4764#L1911 assume !(0 == start_simulation_~tmp~3#1); 4765#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5287#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4354#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5225#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4059#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4060#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4289#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4290#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4473#L1892-2 [2022-11-16 11:56:28,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:28,040 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2022-11-16 11:56:28,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:28,040 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342474906] [2022-11-16 11:56:28,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:28,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:28,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:28,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:28,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:28,200 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342474906] [2022-11-16 11:56:28,200 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1342474906] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:28,200 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:28,200 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:28,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944107622] [2022-11-16 11:56:28,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:28,201 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:28,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:28,202 INFO L85 PathProgramCache]: Analyzing trace with hash -423565315, now seen corresponding path program 1 times [2022-11-16 11:56:28,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:28,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428963634] [2022-11-16 11:56:28,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:28,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:28,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:28,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:28,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:28,316 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428963634] [2022-11-16 11:56:28,316 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428963634] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:28,317 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:28,317 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:28,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218330438] [2022-11-16 11:56:28,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:28,318 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:28,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:28,318 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:28,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:28,319 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:28,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:28,371 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-11-16 11:56:28,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2022-11-16 11:56:28,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:28,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-11-16 11:56:28,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:28,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:28,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2022-11-16 11:56:28,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:28,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-11-16 11:56:28,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2022-11-16 11:56:28,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:28,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:28,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-11-16 11:56:28,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-11-16 11:56:28,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:28,503 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-11-16 11:56:28,504 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 11:56:28,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2022-11-16 11:56:28,517 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:28,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:28,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:28,520 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:28,520 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:28,522 INFO L748 eck$LassoCheckResult]: Stem: 8546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8366#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8082#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8083#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9259#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9260#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8218#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8219#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8673#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8508#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8509#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8285#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8286#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8684#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8861#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9015#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9052#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8296#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8297#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9472#L1258-2 assume !(0 == ~T1_E~0); 8591#L1263-1 assume !(0 == ~T2_E~0); 8592#L1268-1 assume !(0 == ~T3_E~0); 8895#L1273-1 assume !(0 == ~T4_E~0); 9454#L1278-1 assume !(0 == ~T5_E~0); 9315#L1283-1 assume !(0 == ~T6_E~0); 9316#L1288-1 assume !(0 == ~T7_E~0); 9552#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9540#L1298-1 assume !(0 == ~T9_E~0); 9466#L1303-1 assume !(0 == ~T10_E~0); 8111#L1308-1 assume !(0 == ~T11_E~0); 8053#L1313-1 assume !(0 == ~T12_E~0); 8054#L1318-1 assume !(0 == ~T13_E~0); 8060#L1323-1 assume !(0 == ~E_1~0); 8061#L1328-1 assume !(0 == ~E_2~0); 8228#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9187#L1338-1 assume !(0 == ~E_4~0); 9188#L1343-1 assume !(0 == ~E_5~0); 9289#L1348-1 assume !(0 == ~E_6~0); 9575#L1353-1 assume !(0 == ~E_7~0); 8914#L1358-1 assume !(0 == ~E_8~0); 8915#L1363-1 assume !(0 == ~E_9~0); 9205#L1368-1 assume !(0 == ~E_10~0); 7890#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7891#L1378-1 assume !(0 == ~E_12~0); 8177#L1383-1 assume !(0 == ~E_13~0); 8178#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8921#L607 assume 1 == ~m_pc~0; 8922#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8248#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9287#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8841#L1560 assume !(0 != activate_threads_~tmp~1#1); 8842#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8073#L626 assume !(1 == ~t1_pc~0); 8074#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8342#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8343#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8512#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 7973#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7974#L645 assume 1 == ~t2_pc~0; 8090#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8047#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8724#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8725#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8817#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8818#L664 assume 1 == ~t3_pc~0; 9574#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7814#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7815#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8473#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8474#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9482#L683 assume !(1 == ~t4_pc~0); 9037#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8989#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8990#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9024#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9148#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8767#L702 assume 1 == ~t5_pc~0; 8768#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8693#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9143#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9441#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9382#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7862#L721 assume !(1 == ~t6_pc~0); 7836#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7837#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8000#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8482#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8483#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9084#L740 assume 1 == ~t7_pc~0; 7911#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7724#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7725#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7714#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7715#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8418#L759 assume !(1 == ~t8_pc~0); 8419#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8448#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9141#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9142#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9273#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9551#L778 assume 1 == ~t9_pc~0; 9438#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7889#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7829#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7758#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7759#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8086#L797 assume !(1 == ~t10_pc~0); 8087#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8205#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9339#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8589#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8590#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8879#L816 assume 1 == ~t11_pc~0; 7794#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7795#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8550#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8489#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8490#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9014#L835 assume 1 == ~t12_pc~0; 8892#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7958#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7980#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8121#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8646#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8647#L854 assume !(1 == ~t13_pc~0); 8287#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8288#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8338#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7998#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 7999#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9378#L1401 assume !(1 == ~M_E~0); 8477#L1401-2 assume !(1 == ~T1_E~0); 8478#L1406-1 assume !(1 == ~T2_E~0); 9073#L1411-1 assume !(1 == ~T3_E~0); 9074#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8740#L1421-1 assume !(1 == ~T5_E~0); 8283#L1426-1 assume !(1 == ~T6_E~0); 8284#L1431-1 assume !(1 == ~T7_E~0); 7832#L1436-1 assume !(1 == ~T8_E~0); 7833#L1441-1 assume !(1 == ~T9_E~0); 8580#L1446-1 assume !(1 == ~T10_E~0); 8581#L1451-1 assume !(1 == ~T11_E~0); 9286#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8940#L1461-1 assume !(1 == ~T13_E~0); 8501#L1466-1 assume !(1 == ~E_1~0); 8502#L1471-1 assume !(1 == ~E_2~0); 9271#L1476-1 assume !(1 == ~E_3~0); 9272#L1481-1 assume !(1 == ~E_4~0); 9420#L1486-1 assume !(1 == ~E_5~0); 8126#L1491-1 assume !(1 == ~E_6~0); 7766#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7767#L1501-1 assume !(1 == ~E_8~0); 8578#L1506-1 assume !(1 == ~E_9~0); 8579#L1511-1 assume !(1 == ~E_10~0); 8535#L1516-1 assume !(1 == ~E_11~0); 7710#L1521-1 assume !(1 == ~E_12~0); 7711#L1526-1 assume !(1 == ~E_13~0); 7765#L1531-1 assume { :end_inline_reset_delta_events } true; 8308#L1892-2 [2022-11-16 11:56:28,523 INFO L750 eck$LassoCheckResult]: Loop: 8308#L1892-2 assume !false; 9331#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9529#L1233 assume !false; 9512#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8844#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8824#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8982#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7808#L1046 assume !(0 != eval_~tmp~0#1); 7810#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7844#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9016#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9573#L1258-5 assume !(0 == ~T1_E~0); 7986#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7987#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9565#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9571#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9572#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8210#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8211#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9328#L1298-3 assume !(0 == ~T9_E~0); 9329#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9488#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9327#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8828#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7988#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7989#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9412#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8131#L1338-3 assume !(0 == ~E_4~0); 8132#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9244#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9417#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9418#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8784#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8344#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8345#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9101#L1378-3 assume !(0 == ~E_12~0); 9102#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9283#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9284#L607-42 assume 1 == ~m_pc~0; 8897#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8625#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8626#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8358#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8359#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8880#L626-42 assume 1 == ~t1_pc~0; 8442#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8443#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8747#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8748#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8022#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8023#L645-42 assume !(1 == ~t2_pc~0); 9222#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9223#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9388#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8229#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7736#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7737#L664-42 assume !(1 == ~t3_pc~0); 8263#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8264#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9515#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9050#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9051#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9216#L683-42 assume !(1 == ~t4_pc~0); 8924#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8925#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9057#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9477#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9478#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9322#L702-42 assume !(1 == ~t5_pc~0); 8434#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 8435#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8731#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9404#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7752#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7753#L721-42 assume 1 == ~t6_pc~0; 7906#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7926#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8390#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9557#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8562#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8408#L740-42 assume !(1 == ~t7_pc~0); 8145#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 8146#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8687#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8542#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 8543#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8816#L759-42 assume 1 == ~t8_pc~0; 8665#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8597#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8598#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8676#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8677#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8772#L778-42 assume 1 == ~t9_pc~0; 8609#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8611#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9021#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8926#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8927#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8984#L797-42 assume 1 == ~t10_pc~0; 8151#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8152#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9153#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9462#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9022#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9023#L816-42 assume 1 == ~t11_pc~0; 7700#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7701#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8243#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8244#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8323#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8324#L835-42 assume 1 == ~t12_pc~0; 8728#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8621#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8298#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8299#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9381#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9165#L854-42 assume !(1 == ~t13_pc~0); 8241#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 8242#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 7852#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7853#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8499#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9278#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8089#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7953#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7954#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8553#L1421-3 assume !(1 == ~T5_E~0); 8554#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8129#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8130#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7716#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7717#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9306#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8637#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8290#L1461-3 assume !(1 == ~T13_E~0); 8291#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9568#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8230#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8231#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8631#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8258#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8259#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8671#L1501-3 assume !(1 == ~E_8~0); 8672#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9098#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9088#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9089#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8788#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8789#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9183#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8065#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8958#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8599#L1911 assume !(0 == start_simulation_~tmp~3#1); 8600#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9122#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8189#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9060#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7894#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7895#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8124#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8125#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8308#L1892-2 [2022-11-16 11:56:28,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:28,527 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2022-11-16 11:56:28,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:28,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627407111] [2022-11-16 11:56:28,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:28,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:28,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:28,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:28,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:28,640 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1627407111] [2022-11-16 11:56:28,640 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1627407111] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:28,640 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:28,640 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:28,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146215020] [2022-11-16 11:56:28,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:28,641 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:28,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:28,642 INFO L85 PathProgramCache]: Analyzing trace with hash 168575421, now seen corresponding path program 1 times [2022-11-16 11:56:28,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:28,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101082178] [2022-11-16 11:56:28,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:28,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:28,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:28,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:28,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:28,764 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101082178] [2022-11-16 11:56:28,765 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101082178] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:28,765 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:28,765 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:28,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769786627] [2022-11-16 11:56:28,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:28,767 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:28,767 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:28,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:28,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:28,768 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:28,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:28,848 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-11-16 11:56:28,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2022-11-16 11:56:28,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:28,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-11-16 11:56:28,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:28,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:28,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2022-11-16 11:56:28,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:28,888 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-11-16 11:56:28,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2022-11-16 11:56:28,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:28,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:28,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-11-16 11:56:28,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-11-16 11:56:28,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:28,937 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-11-16 11:56:28,937 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 11:56:28,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2022-11-16 11:56:28,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:28,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:28,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:28,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:28,954 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:28,955 INFO L748 eck$LassoCheckResult]: Stem: 12381#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12201#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11917#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11918#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13094#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13095#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12053#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12054#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12508#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12343#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12344#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12120#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12121#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12519#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12696#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12850#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12887#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12131#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12132#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13307#L1258-2 assume !(0 == ~T1_E~0); 12426#L1263-1 assume !(0 == ~T2_E~0); 12427#L1268-1 assume !(0 == ~T3_E~0); 12730#L1273-1 assume !(0 == ~T4_E~0); 13289#L1278-1 assume !(0 == ~T5_E~0); 13150#L1283-1 assume !(0 == ~T6_E~0); 13151#L1288-1 assume !(0 == ~T7_E~0); 13387#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13375#L1298-1 assume !(0 == ~T9_E~0); 13301#L1303-1 assume !(0 == ~T10_E~0); 11946#L1308-1 assume !(0 == ~T11_E~0); 11888#L1313-1 assume !(0 == ~T12_E~0); 11889#L1318-1 assume !(0 == ~T13_E~0); 11895#L1323-1 assume !(0 == ~E_1~0); 11896#L1328-1 assume !(0 == ~E_2~0); 12063#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13022#L1338-1 assume !(0 == ~E_4~0); 13023#L1343-1 assume !(0 == ~E_5~0); 13124#L1348-1 assume !(0 == ~E_6~0); 13410#L1353-1 assume !(0 == ~E_7~0); 12749#L1358-1 assume !(0 == ~E_8~0); 12750#L1363-1 assume !(0 == ~E_9~0); 13040#L1368-1 assume !(0 == ~E_10~0); 11725#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11726#L1378-1 assume !(0 == ~E_12~0); 12012#L1383-1 assume !(0 == ~E_13~0); 12013#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12756#L607 assume 1 == ~m_pc~0; 12757#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12083#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13122#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12676#L1560 assume !(0 != activate_threads_~tmp~1#1); 12677#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11908#L626 assume !(1 == ~t1_pc~0); 11909#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12177#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12178#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12347#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11809#L645 assume 1 == ~t2_pc~0; 11925#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11882#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12559#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12560#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12652#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12653#L664 assume 1 == ~t3_pc~0; 13409#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11649#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11650#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12308#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12309#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13317#L683 assume !(1 == ~t4_pc~0); 12872#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12824#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12825#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12859#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12983#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12602#L702 assume 1 == ~t5_pc~0; 12603#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12528#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12978#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13276#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13217#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11697#L721 assume !(1 == ~t6_pc~0); 11671#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11672#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11835#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12317#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12318#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12919#L740 assume 1 == ~t7_pc~0; 11746#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11559#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11560#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11549#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11550#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12253#L759 assume !(1 == ~t8_pc~0); 12254#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12283#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12976#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12977#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13108#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13386#L778 assume 1 == ~t9_pc~0; 13273#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11724#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11664#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11593#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11594#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11921#L797 assume !(1 == ~t10_pc~0); 11922#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12040#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13174#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12424#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12425#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12714#L816 assume 1 == ~t11_pc~0; 11629#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11630#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12385#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12324#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12325#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12849#L835 assume 1 == ~t12_pc~0; 12727#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11793#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11815#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11956#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12481#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12482#L854 assume !(1 == ~t13_pc~0); 12122#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12123#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12173#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11833#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11834#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13213#L1401 assume !(1 == ~M_E~0); 12312#L1401-2 assume !(1 == ~T1_E~0); 12313#L1406-1 assume !(1 == ~T2_E~0); 12908#L1411-1 assume !(1 == ~T3_E~0); 12909#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12575#L1421-1 assume !(1 == ~T5_E~0); 12118#L1426-1 assume !(1 == ~T6_E~0); 12119#L1431-1 assume !(1 == ~T7_E~0); 11667#L1436-1 assume !(1 == ~T8_E~0); 11668#L1441-1 assume !(1 == ~T9_E~0); 12415#L1446-1 assume !(1 == ~T10_E~0); 12416#L1451-1 assume !(1 == ~T11_E~0); 13121#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12775#L1461-1 assume !(1 == ~T13_E~0); 12336#L1466-1 assume !(1 == ~E_1~0); 12337#L1471-1 assume !(1 == ~E_2~0); 13106#L1476-1 assume !(1 == ~E_3~0); 13107#L1481-1 assume !(1 == ~E_4~0); 13255#L1486-1 assume !(1 == ~E_5~0); 11961#L1491-1 assume !(1 == ~E_6~0); 11601#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11602#L1501-1 assume !(1 == ~E_8~0); 12413#L1506-1 assume !(1 == ~E_9~0); 12414#L1511-1 assume !(1 == ~E_10~0); 12370#L1516-1 assume !(1 == ~E_11~0); 11545#L1521-1 assume !(1 == ~E_12~0); 11546#L1526-1 assume !(1 == ~E_13~0); 11600#L1531-1 assume { :end_inline_reset_delta_events } true; 12143#L1892-2 [2022-11-16 11:56:28,956 INFO L750 eck$LassoCheckResult]: Loop: 12143#L1892-2 assume !false; 13166#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13364#L1233 assume !false; 13347#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12679#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12659#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12817#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11643#L1046 assume !(0 != eval_~tmp~0#1); 11645#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11679#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12851#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13408#L1258-5 assume !(0 == ~T1_E~0); 11821#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11822#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13400#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13406#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13407#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12045#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12046#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13163#L1298-3 assume !(0 == ~T9_E~0); 13164#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13323#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13162#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12663#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11823#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11824#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13247#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11966#L1338-3 assume !(0 == ~E_4~0); 11967#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13079#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13252#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13253#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12619#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12179#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12180#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12936#L1378-3 assume !(0 == ~E_12~0); 12937#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13118#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13119#L607-42 assume 1 == ~m_pc~0; 12732#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12460#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12461#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12193#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12194#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12715#L626-42 assume 1 == ~t1_pc~0; 12277#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12278#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12582#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12583#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11857#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11858#L645-42 assume !(1 == ~t2_pc~0); 13057#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13058#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13223#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12064#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11571#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11572#L664-42 assume !(1 == ~t3_pc~0); 12098#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12099#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13350#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12885#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12886#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13051#L683-42 assume !(1 == ~t4_pc~0); 12759#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12760#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12892#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13312#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13313#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13157#L702-42 assume 1 == ~t5_pc~0; 12645#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12270#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12566#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13239#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11587#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11588#L721-42 assume 1 == ~t6_pc~0; 11741#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11761#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12225#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13392#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12397#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12243#L740-42 assume 1 == ~t7_pc~0; 12244#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11981#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12522#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12377#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 12378#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12651#L759-42 assume 1 == ~t8_pc~0; 12500#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12432#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12433#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12511#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12512#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12607#L778-42 assume 1 == ~t9_pc~0; 12444#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12446#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12856#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12761#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12762#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12819#L797-42 assume 1 == ~t10_pc~0; 11986#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11987#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12988#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13297#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12857#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12858#L816-42 assume !(1 == ~t11_pc~0); 11537#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 11536#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12078#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12079#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12158#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12159#L835-42 assume 1 == ~t12_pc~0; 12563#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12456#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12133#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12134#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13216#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13000#L854-42 assume 1 == ~t13_pc~0; 13001#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12077#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11687#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11688#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12334#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12335#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13113#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11924#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11788#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11789#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12388#L1421-3 assume !(1 == ~T5_E~0); 12389#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11964#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11965#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11551#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11552#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13141#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12472#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12125#L1461-3 assume !(1 == ~T13_E~0); 12126#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13403#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12065#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12066#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12466#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12093#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12094#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12506#L1501-3 assume !(1 == ~E_8~0); 12507#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12933#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12923#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12924#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12623#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12624#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13018#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11900#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12793#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12434#L1911 assume !(0 == start_simulation_~tmp~3#1); 12435#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12957#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12024#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12895#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11729#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11730#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11959#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11960#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12143#L1892-2 [2022-11-16 11:56:28,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:28,957 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2022-11-16 11:56:28,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:28,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947587282] [2022-11-16 11:56:28,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:28,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:28,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:29,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:29,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:29,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947587282] [2022-11-16 11:56:29,049 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947587282] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:29,049 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:29,050 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:29,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1294337907] [2022-11-16 11:56:29,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:29,054 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:29,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:29,055 INFO L85 PathProgramCache]: Analyzing trace with hash 2046766079, now seen corresponding path program 1 times [2022-11-16 11:56:29,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:29,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046405652] [2022-11-16 11:56:29,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:29,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:29,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:29,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:29,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:29,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046405652] [2022-11-16 11:56:29,172 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046405652] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:29,172 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:29,172 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:29,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191429119] [2022-11-16 11:56:29,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:29,174 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:29,174 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:29,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:29,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:29,176 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:29,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:29,232 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-11-16 11:56:29,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2022-11-16 11:56:29,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:29,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-11-16 11:56:29,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:29,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:29,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2022-11-16 11:56:29,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:29,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-11-16 11:56:29,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2022-11-16 11:56:29,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:29,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:29,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-11-16 11:56:29,305 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-11-16 11:56:29,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:29,306 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-11-16 11:56:29,307 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 11:56:29,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2022-11-16 11:56:29,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:29,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:29,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:29,324 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:29,324 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:29,324 INFO L748 eck$LassoCheckResult]: Stem: 16216#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 16217#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16036#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15752#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15753#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 16929#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16930#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15888#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15889#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16343#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16178#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16179#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15955#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15956#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16354#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16531#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16685#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16722#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 15966#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15967#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17142#L1258-2 assume !(0 == ~T1_E~0); 16261#L1263-1 assume !(0 == ~T2_E~0); 16262#L1268-1 assume !(0 == ~T3_E~0); 16565#L1273-1 assume !(0 == ~T4_E~0); 17124#L1278-1 assume !(0 == ~T5_E~0); 16985#L1283-1 assume !(0 == ~T6_E~0); 16986#L1288-1 assume !(0 == ~T7_E~0); 17222#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17210#L1298-1 assume !(0 == ~T9_E~0); 17136#L1303-1 assume !(0 == ~T10_E~0); 15781#L1308-1 assume !(0 == ~T11_E~0); 15723#L1313-1 assume !(0 == ~T12_E~0); 15724#L1318-1 assume !(0 == ~T13_E~0); 15730#L1323-1 assume !(0 == ~E_1~0); 15731#L1328-1 assume !(0 == ~E_2~0); 15898#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16857#L1338-1 assume !(0 == ~E_4~0); 16858#L1343-1 assume !(0 == ~E_5~0); 16959#L1348-1 assume !(0 == ~E_6~0); 17245#L1353-1 assume !(0 == ~E_7~0); 16584#L1358-1 assume !(0 == ~E_8~0); 16585#L1363-1 assume !(0 == ~E_9~0); 16875#L1368-1 assume !(0 == ~E_10~0); 15560#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15561#L1378-1 assume !(0 == ~E_12~0); 15847#L1383-1 assume !(0 == ~E_13~0); 15848#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16591#L607 assume 1 == ~m_pc~0; 16592#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15918#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16957#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16511#L1560 assume !(0 != activate_threads_~tmp~1#1); 16512#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15743#L626 assume !(1 == ~t1_pc~0); 15744#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16012#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16013#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16182#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15643#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15644#L645 assume 1 == ~t2_pc~0; 15760#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15717#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16394#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16395#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16487#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16488#L664 assume 1 == ~t3_pc~0; 17244#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15484#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15485#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16143#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16144#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17152#L683 assume !(1 == ~t4_pc~0); 16707#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16659#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16660#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16694#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16818#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16437#L702 assume 1 == ~t5_pc~0; 16438#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16363#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16813#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17111#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17052#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15532#L721 assume !(1 == ~t6_pc~0); 15506#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15507#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15670#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16152#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16153#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16754#L740 assume 1 == ~t7_pc~0; 15581#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15394#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15395#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15384#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15385#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16088#L759 assume !(1 == ~t8_pc~0); 16089#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16118#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16811#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16812#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 16943#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17221#L778 assume 1 == ~t9_pc~0; 17108#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15559#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15499#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15428#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15429#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15756#L797 assume !(1 == ~t10_pc~0); 15757#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15875#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17009#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16259#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16260#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16549#L816 assume 1 == ~t11_pc~0; 15464#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15465#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16220#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16159#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16160#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16684#L835 assume 1 == ~t12_pc~0; 16562#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15628#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15650#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15791#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16316#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16317#L854 assume !(1 == ~t13_pc~0); 15957#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 15958#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16008#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15668#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15669#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17048#L1401 assume !(1 == ~M_E~0); 16147#L1401-2 assume !(1 == ~T1_E~0); 16148#L1406-1 assume !(1 == ~T2_E~0); 16743#L1411-1 assume !(1 == ~T3_E~0); 16744#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16410#L1421-1 assume !(1 == ~T5_E~0); 15953#L1426-1 assume !(1 == ~T6_E~0); 15954#L1431-1 assume !(1 == ~T7_E~0); 15502#L1436-1 assume !(1 == ~T8_E~0); 15503#L1441-1 assume !(1 == ~T9_E~0); 16250#L1446-1 assume !(1 == ~T10_E~0); 16251#L1451-1 assume !(1 == ~T11_E~0); 16956#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16610#L1461-1 assume !(1 == ~T13_E~0); 16171#L1466-1 assume !(1 == ~E_1~0); 16172#L1471-1 assume !(1 == ~E_2~0); 16941#L1476-1 assume !(1 == ~E_3~0); 16942#L1481-1 assume !(1 == ~E_4~0); 17090#L1486-1 assume !(1 == ~E_5~0); 15796#L1491-1 assume !(1 == ~E_6~0); 15436#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15437#L1501-1 assume !(1 == ~E_8~0); 16248#L1506-1 assume !(1 == ~E_9~0); 16249#L1511-1 assume !(1 == ~E_10~0); 16205#L1516-1 assume !(1 == ~E_11~0); 15380#L1521-1 assume !(1 == ~E_12~0); 15381#L1526-1 assume !(1 == ~E_13~0); 15435#L1531-1 assume { :end_inline_reset_delta_events } true; 15978#L1892-2 [2022-11-16 11:56:29,325 INFO L750 eck$LassoCheckResult]: Loop: 15978#L1892-2 assume !false; 17001#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17199#L1233 assume !false; 17182#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16514#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16494#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16652#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15478#L1046 assume !(0 != eval_~tmp~0#1); 15480#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15514#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16686#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17243#L1258-5 assume !(0 == ~T1_E~0); 15656#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15657#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17235#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17241#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17242#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15880#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15881#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16998#L1298-3 assume !(0 == ~T9_E~0); 16999#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17158#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16997#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16498#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15658#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15659#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17082#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15801#L1338-3 assume !(0 == ~E_4~0); 15802#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16914#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17087#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17088#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16454#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16014#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16015#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16771#L1378-3 assume !(0 == ~E_12~0); 16772#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16953#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16954#L607-42 assume 1 == ~m_pc~0; 16567#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16295#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16296#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16028#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16029#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16550#L626-42 assume 1 == ~t1_pc~0; 16112#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16113#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16417#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16418#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15692#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15693#L645-42 assume !(1 == ~t2_pc~0); 16892#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 16893#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17058#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15899#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15406#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15407#L664-42 assume 1 == ~t3_pc~0; 16209#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15934#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17185#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16720#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16721#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16886#L683-42 assume !(1 == ~t4_pc~0); 16594#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 16595#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16727#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17147#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17148#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16992#L702-42 assume 1 == ~t5_pc~0; 16480#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16105#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16401#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17074#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15422#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15423#L721-42 assume 1 == ~t6_pc~0; 15576#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15596#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16060#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17227#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16232#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16078#L740-42 assume !(1 == ~t7_pc~0); 15815#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 15816#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16357#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16212#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 16213#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16486#L759-42 assume !(1 == ~t8_pc~0); 16336#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 16267#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16268#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16346#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16347#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16442#L778-42 assume 1 == ~t9_pc~0; 16279#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16281#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16691#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16596#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16597#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16654#L797-42 assume 1 == ~t10_pc~0; 15821#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15822#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16823#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17132#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16692#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16693#L816-42 assume 1 == ~t11_pc~0; 15370#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15371#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15913#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15914#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 15993#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15994#L835-42 assume !(1 == ~t12_pc~0); 16290#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16291#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15968#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15969#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17051#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16835#L854-42 assume 1 == ~t13_pc~0; 16836#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 15912#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 15522#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15523#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16169#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16170#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16948#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15759#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15623#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15624#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16223#L1421-3 assume !(1 == ~T5_E~0); 16224#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15799#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15800#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15386#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15387#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16976#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16307#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15960#L1461-3 assume !(1 == ~T13_E~0); 15961#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17238#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15900#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15901#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16301#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15928#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15929#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16341#L1501-3 assume !(1 == ~E_8~0); 16342#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16768#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16758#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16759#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16458#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16459#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16853#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15735#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16628#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16269#L1911 assume !(0 == start_simulation_~tmp~3#1); 16270#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16792#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15859#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16730#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15564#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15565#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15794#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 15795#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 15978#L1892-2 [2022-11-16 11:56:29,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:29,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2022-11-16 11:56:29,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:29,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669276919] [2022-11-16 11:56:29,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:29,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:29,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:29,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:29,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:29,412 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669276919] [2022-11-16 11:56:29,412 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669276919] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:29,413 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:29,413 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:29,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1604099218] [2022-11-16 11:56:29,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:29,414 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:29,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:29,414 INFO L85 PathProgramCache]: Analyzing trace with hash 259811934, now seen corresponding path program 1 times [2022-11-16 11:56:29,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:29,415 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000331929] [2022-11-16 11:56:29,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:29,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:29,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:29,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:29,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:29,501 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000331929] [2022-11-16 11:56:29,501 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1000331929] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:29,501 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:29,501 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:29,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926980243] [2022-11-16 11:56:29,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:29,502 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:29,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:29,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:29,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:29,503 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:29,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:29,543 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-11-16 11:56:29,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2022-11-16 11:56:29,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:29,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-11-16 11:56:29,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:29,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:29,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2022-11-16 11:56:29,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:29,567 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-11-16 11:56:29,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2022-11-16 11:56:29,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:29,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:29,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-11-16 11:56:29,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-11-16 11:56:29,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:29,606 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-11-16 11:56:29,607 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 11:56:29,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2022-11-16 11:56:29,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:29,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:29,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:29,618 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:29,619 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:29,619 INFO L748 eck$LassoCheckResult]: Stem: 20051#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 20052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 19871#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19587#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19588#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20764#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20765#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19723#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19724#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20178#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20013#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20014#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19790#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19791#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20189#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20366#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20520#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20557#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19801#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19802#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20977#L1258-2 assume !(0 == ~T1_E~0); 20096#L1263-1 assume !(0 == ~T2_E~0); 20097#L1268-1 assume !(0 == ~T3_E~0); 20400#L1273-1 assume !(0 == ~T4_E~0); 20959#L1278-1 assume !(0 == ~T5_E~0); 20820#L1283-1 assume !(0 == ~T6_E~0); 20821#L1288-1 assume !(0 == ~T7_E~0); 21057#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21045#L1298-1 assume !(0 == ~T9_E~0); 20971#L1303-1 assume !(0 == ~T10_E~0); 19616#L1308-1 assume !(0 == ~T11_E~0); 19558#L1313-1 assume !(0 == ~T12_E~0); 19559#L1318-1 assume !(0 == ~T13_E~0); 19565#L1323-1 assume !(0 == ~E_1~0); 19566#L1328-1 assume !(0 == ~E_2~0); 19733#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20692#L1338-1 assume !(0 == ~E_4~0); 20693#L1343-1 assume !(0 == ~E_5~0); 20794#L1348-1 assume !(0 == ~E_6~0); 21080#L1353-1 assume !(0 == ~E_7~0); 20419#L1358-1 assume !(0 == ~E_8~0); 20420#L1363-1 assume !(0 == ~E_9~0); 20710#L1368-1 assume !(0 == ~E_10~0); 19395#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19396#L1378-1 assume !(0 == ~E_12~0); 19682#L1383-1 assume !(0 == ~E_13~0); 19683#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20426#L607 assume 1 == ~m_pc~0; 20427#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19753#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20792#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20346#L1560 assume !(0 != activate_threads_~tmp~1#1); 20347#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19578#L626 assume !(1 == ~t1_pc~0); 19579#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19847#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19848#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20017#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19478#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19479#L645 assume 1 == ~t2_pc~0; 19595#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19552#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20229#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20230#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20322#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20323#L664 assume 1 == ~t3_pc~0; 21079#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19319#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19320#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19978#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19979#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20987#L683 assume !(1 == ~t4_pc~0); 20542#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20494#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20495#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20529#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20653#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20272#L702 assume 1 == ~t5_pc~0; 20273#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20198#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20648#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20946#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20887#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19367#L721 assume !(1 == ~t6_pc~0); 19341#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19342#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19505#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19987#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19988#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20589#L740 assume 1 == ~t7_pc~0; 19416#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19229#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19230#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19219#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19220#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19923#L759 assume !(1 == ~t8_pc~0); 19924#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19953#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20646#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20647#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20778#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21056#L778 assume 1 == ~t9_pc~0; 20943#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19394#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19334#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19263#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19264#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19591#L797 assume !(1 == ~t10_pc~0); 19592#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19710#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20844#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20094#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20095#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20384#L816 assume 1 == ~t11_pc~0; 19299#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19300#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20055#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19994#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19995#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20519#L835 assume 1 == ~t12_pc~0; 20397#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19463#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19485#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19626#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20151#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20152#L854 assume !(1 == ~t13_pc~0); 19792#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19793#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19843#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19503#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19504#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20883#L1401 assume !(1 == ~M_E~0); 19982#L1401-2 assume !(1 == ~T1_E~0); 19983#L1406-1 assume !(1 == ~T2_E~0); 20578#L1411-1 assume !(1 == ~T3_E~0); 20579#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20245#L1421-1 assume !(1 == ~T5_E~0); 19788#L1426-1 assume !(1 == ~T6_E~0); 19789#L1431-1 assume !(1 == ~T7_E~0); 19337#L1436-1 assume !(1 == ~T8_E~0); 19338#L1441-1 assume !(1 == ~T9_E~0); 20085#L1446-1 assume !(1 == ~T10_E~0); 20086#L1451-1 assume !(1 == ~T11_E~0); 20791#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20445#L1461-1 assume !(1 == ~T13_E~0); 20006#L1466-1 assume !(1 == ~E_1~0); 20007#L1471-1 assume !(1 == ~E_2~0); 20776#L1476-1 assume !(1 == ~E_3~0); 20777#L1481-1 assume !(1 == ~E_4~0); 20925#L1486-1 assume !(1 == ~E_5~0); 19631#L1491-1 assume !(1 == ~E_6~0); 19271#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19272#L1501-1 assume !(1 == ~E_8~0); 20083#L1506-1 assume !(1 == ~E_9~0); 20084#L1511-1 assume !(1 == ~E_10~0); 20040#L1516-1 assume !(1 == ~E_11~0); 19215#L1521-1 assume !(1 == ~E_12~0); 19216#L1526-1 assume !(1 == ~E_13~0); 19270#L1531-1 assume { :end_inline_reset_delta_events } true; 19813#L1892-2 [2022-11-16 11:56:29,620 INFO L750 eck$LassoCheckResult]: Loop: 19813#L1892-2 assume !false; 20836#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21034#L1233 assume !false; 21017#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20349#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20329#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20487#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19313#L1046 assume !(0 != eval_~tmp~0#1); 19315#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19349#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20521#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21078#L1258-5 assume !(0 == ~T1_E~0); 19491#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19492#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21070#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21076#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21077#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19715#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19716#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20833#L1298-3 assume !(0 == ~T9_E~0); 20834#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20993#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20832#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20333#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19493#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19494#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20917#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19636#L1338-3 assume !(0 == ~E_4~0); 19637#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20749#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20922#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20923#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20289#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19849#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19850#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20606#L1378-3 assume !(0 == ~E_12~0); 20607#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20788#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20789#L607-42 assume 1 == ~m_pc~0; 20402#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20130#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20131#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19863#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19864#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20385#L626-42 assume 1 == ~t1_pc~0; 19947#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19948#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20252#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20253#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19527#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19528#L645-42 assume !(1 == ~t2_pc~0); 20727#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20728#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20893#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19734#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19241#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19242#L664-42 assume !(1 == ~t3_pc~0); 19768#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19769#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21020#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20555#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20556#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20721#L683-42 assume !(1 == ~t4_pc~0); 20429#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20430#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20562#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20982#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20983#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20827#L702-42 assume !(1 == ~t5_pc~0); 19939#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 19940#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20236#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20909#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19257#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19258#L721-42 assume 1 == ~t6_pc~0; 19411#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19431#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19895#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21062#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20067#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19913#L740-42 assume !(1 == ~t7_pc~0); 19650#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19651#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20192#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20047#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 20048#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20321#L759-42 assume 1 == ~t8_pc~0; 20170#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20102#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20103#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20181#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20182#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20277#L778-42 assume 1 == ~t9_pc~0; 20114#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20116#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20526#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20431#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20432#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20489#L797-42 assume 1 == ~t10_pc~0; 19656#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19657#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20658#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20967#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20527#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20528#L816-42 assume 1 == ~t11_pc~0; 19205#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19206#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19748#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19749#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19828#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19829#L835-42 assume 1 == ~t12_pc~0; 20233#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20126#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19803#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19804#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20886#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20670#L854-42 assume !(1 == ~t13_pc~0); 19746#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 19747#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19357#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19358#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20004#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20005#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20783#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19594#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19458#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19459#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20058#L1421-3 assume !(1 == ~T5_E~0); 20059#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19634#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19635#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19221#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19222#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20811#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20142#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19795#L1461-3 assume !(1 == ~T13_E~0); 19796#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21073#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19735#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19736#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20136#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19763#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19764#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20176#L1501-3 assume !(1 == ~E_8~0); 20177#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20603#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20593#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20594#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20293#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20294#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20688#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19570#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20463#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 20104#L1911 assume !(0 == start_simulation_~tmp~3#1); 20105#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20627#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19694#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20565#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19399#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19400#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19629#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19630#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19813#L1892-2 [2022-11-16 11:56:29,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:29,621 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2022-11-16 11:56:29,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:29,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865872964] [2022-11-16 11:56:29,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:29,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:29,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:29,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:29,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:29,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865872964] [2022-11-16 11:56:29,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865872964] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:29,683 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:29,683 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:29,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19602832] [2022-11-16 11:56:29,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:29,684 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:29,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:29,684 INFO L85 PathProgramCache]: Analyzing trace with hash 168575421, now seen corresponding path program 2 times [2022-11-16 11:56:29,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:29,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280951039] [2022-11-16 11:56:29,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:29,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:29,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:29,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:29,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:29,752 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280951039] [2022-11-16 11:56:29,752 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280951039] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:29,752 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:29,753 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:29,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799564876] [2022-11-16 11:56:29,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:29,754 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:29,754 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:29,754 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:29,754 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:29,755 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:29,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:29,794 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-11-16 11:56:29,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2022-11-16 11:56:29,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:29,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-11-16 11:56:29,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:29,848 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:29,848 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2022-11-16 11:56:29,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:29,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-11-16 11:56:29,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2022-11-16 11:56:29,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:29,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:29,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-11-16 11:56:29,890 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-11-16 11:56:29,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:29,891 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-11-16 11:56:29,892 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 11:56:29,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2022-11-16 11:56:29,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:29,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:29,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:29,903 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:29,904 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:29,904 INFO L748 eck$LassoCheckResult]: Stem: 23886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 23706#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23422#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23423#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24599#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24600#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23558#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23559#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24013#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23848#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23849#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23625#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23626#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24024#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24201#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24355#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24392#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23636#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23637#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 24812#L1258-2 assume !(0 == ~T1_E~0); 23931#L1263-1 assume !(0 == ~T2_E~0); 23932#L1268-1 assume !(0 == ~T3_E~0); 24235#L1273-1 assume !(0 == ~T4_E~0); 24794#L1278-1 assume !(0 == ~T5_E~0); 24655#L1283-1 assume !(0 == ~T6_E~0); 24656#L1288-1 assume !(0 == ~T7_E~0); 24892#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24880#L1298-1 assume !(0 == ~T9_E~0); 24806#L1303-1 assume !(0 == ~T10_E~0); 23451#L1308-1 assume !(0 == ~T11_E~0); 23393#L1313-1 assume !(0 == ~T12_E~0); 23394#L1318-1 assume !(0 == ~T13_E~0); 23400#L1323-1 assume !(0 == ~E_1~0); 23401#L1328-1 assume !(0 == ~E_2~0); 23568#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24527#L1338-1 assume !(0 == ~E_4~0); 24528#L1343-1 assume !(0 == ~E_5~0); 24629#L1348-1 assume !(0 == ~E_6~0); 24915#L1353-1 assume !(0 == ~E_7~0); 24254#L1358-1 assume !(0 == ~E_8~0); 24255#L1363-1 assume !(0 == ~E_9~0); 24545#L1368-1 assume !(0 == ~E_10~0); 23230#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23231#L1378-1 assume !(0 == ~E_12~0); 23517#L1383-1 assume !(0 == ~E_13~0); 23518#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24261#L607 assume 1 == ~m_pc~0; 24262#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23588#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24627#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24181#L1560 assume !(0 != activate_threads_~tmp~1#1); 24182#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23413#L626 assume !(1 == ~t1_pc~0); 23414#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23682#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23683#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23852#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23313#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23314#L645 assume 1 == ~t2_pc~0; 23430#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23387#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24064#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24065#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24157#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24158#L664 assume 1 == ~t3_pc~0; 24914#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23154#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23155#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23813#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23814#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24822#L683 assume !(1 == ~t4_pc~0); 24377#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24329#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24330#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24364#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24488#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24107#L702 assume 1 == ~t5_pc~0; 24108#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24033#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24483#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24781#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24722#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23202#L721 assume !(1 == ~t6_pc~0); 23176#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23177#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23340#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23822#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23823#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24424#L740 assume 1 == ~t7_pc~0; 23251#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23064#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23065#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23054#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23055#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23758#L759 assume !(1 == ~t8_pc~0); 23759#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23788#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24481#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24482#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24613#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24891#L778 assume 1 == ~t9_pc~0; 24778#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23229#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23169#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23098#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23099#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23426#L797 assume !(1 == ~t10_pc~0); 23427#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23545#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24679#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23929#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 23930#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24219#L816 assume 1 == ~t11_pc~0; 23134#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23135#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23890#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23829#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23830#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24354#L835 assume 1 == ~t12_pc~0; 24232#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23298#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23320#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23461#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 23986#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 23987#L854 assume !(1 == ~t13_pc~0); 23627#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23628#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23678#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23338#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23339#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24718#L1401 assume !(1 == ~M_E~0); 23817#L1401-2 assume !(1 == ~T1_E~0); 23818#L1406-1 assume !(1 == ~T2_E~0); 24413#L1411-1 assume !(1 == ~T3_E~0); 24414#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24080#L1421-1 assume !(1 == ~T5_E~0); 23623#L1426-1 assume !(1 == ~T6_E~0); 23624#L1431-1 assume !(1 == ~T7_E~0); 23172#L1436-1 assume !(1 == ~T8_E~0); 23173#L1441-1 assume !(1 == ~T9_E~0); 23920#L1446-1 assume !(1 == ~T10_E~0); 23921#L1451-1 assume !(1 == ~T11_E~0); 24626#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24280#L1461-1 assume !(1 == ~T13_E~0); 23841#L1466-1 assume !(1 == ~E_1~0); 23842#L1471-1 assume !(1 == ~E_2~0); 24611#L1476-1 assume !(1 == ~E_3~0); 24612#L1481-1 assume !(1 == ~E_4~0); 24760#L1486-1 assume !(1 == ~E_5~0); 23466#L1491-1 assume !(1 == ~E_6~0); 23106#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23107#L1501-1 assume !(1 == ~E_8~0); 23918#L1506-1 assume !(1 == ~E_9~0); 23919#L1511-1 assume !(1 == ~E_10~0); 23875#L1516-1 assume !(1 == ~E_11~0); 23050#L1521-1 assume !(1 == ~E_12~0); 23051#L1526-1 assume !(1 == ~E_13~0); 23105#L1531-1 assume { :end_inline_reset_delta_events } true; 23648#L1892-2 [2022-11-16 11:56:29,905 INFO L750 eck$LassoCheckResult]: Loop: 23648#L1892-2 assume !false; 24671#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24869#L1233 assume !false; 24852#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24184#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24164#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24322#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23148#L1046 assume !(0 != eval_~tmp~0#1); 23150#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23184#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24356#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24913#L1258-5 assume !(0 == ~T1_E~0); 23326#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23327#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24905#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24911#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24912#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23550#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23551#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24668#L1298-3 assume !(0 == ~T9_E~0); 24669#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24828#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24667#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24168#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23328#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23329#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24752#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23471#L1338-3 assume !(0 == ~E_4~0); 23472#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24584#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24757#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24758#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24124#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23684#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23685#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24441#L1378-3 assume !(0 == ~E_12~0); 24442#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24623#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24624#L607-42 assume 1 == ~m_pc~0; 24237#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23965#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23966#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23698#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23699#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24220#L626-42 assume 1 == ~t1_pc~0; 23782#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23783#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24087#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24088#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23362#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23363#L645-42 assume !(1 == ~t2_pc~0); 24562#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 24563#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24728#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23569#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23076#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23077#L664-42 assume !(1 == ~t3_pc~0); 23603#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 23604#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24855#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24390#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24391#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24556#L683-42 assume !(1 == ~t4_pc~0); 24264#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24265#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24397#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24817#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24818#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24662#L702-42 assume 1 == ~t5_pc~0; 24150#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23775#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24071#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24744#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23092#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23093#L721-42 assume 1 == ~t6_pc~0; 23246#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23266#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23730#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24897#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23902#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23748#L740-42 assume 1 == ~t7_pc~0; 23749#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23486#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24027#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23882#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 23883#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24156#L759-42 assume 1 == ~t8_pc~0; 24005#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23937#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23938#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24016#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24017#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24112#L778-42 assume 1 == ~t9_pc~0; 23949#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23951#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24361#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24266#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24267#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24324#L797-42 assume 1 == ~t10_pc~0; 23491#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23492#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24493#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24802#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24362#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24363#L816-42 assume 1 == ~t11_pc~0; 23040#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23041#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23583#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23584#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23663#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23664#L835-42 assume 1 == ~t12_pc~0; 24068#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23961#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23638#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23639#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24721#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24505#L854-42 assume 1 == ~t13_pc~0; 24506#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 23582#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23192#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23193#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23839#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23840#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24618#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23429#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23293#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23294#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23893#L1421-3 assume !(1 == ~T5_E~0); 23894#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23469#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23470#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23056#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23057#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24646#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23977#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23630#L1461-3 assume !(1 == ~T13_E~0); 23631#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24908#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23570#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23571#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23971#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23598#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23599#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24011#L1501-3 assume !(1 == ~E_8~0); 24012#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24438#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24428#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24429#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24128#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24129#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24523#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23405#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24298#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23939#L1911 assume !(0 == start_simulation_~tmp~3#1); 23940#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24462#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23529#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24400#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23234#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23235#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23464#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 23465#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23648#L1892-2 [2022-11-16 11:56:29,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:29,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2022-11-16 11:56:29,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:29,906 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775499142] [2022-11-16 11:56:29,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:29,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:29,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:29,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:29,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:29,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775499142] [2022-11-16 11:56:29,961 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775499142] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:29,961 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:29,961 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:29,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708128907] [2022-11-16 11:56:29,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:29,962 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:29,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:29,962 INFO L85 PathProgramCache]: Analyzing trace with hash -1106553824, now seen corresponding path program 1 times [2022-11-16 11:56:29,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:29,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096455708] [2022-11-16 11:56:29,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:29,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:29,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:30,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:30,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:30,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096455708] [2022-11-16 11:56:30,041 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096455708] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:30,041 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:30,041 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:30,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46727366] [2022-11-16 11:56:30,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:30,042 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:30,042 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:30,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:30,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:30,043 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:30,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:30,085 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-11-16 11:56:30,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2022-11-16 11:56:30,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:30,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-11-16 11:56:30,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:30,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:30,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2022-11-16 11:56:30,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:30,115 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-11-16 11:56:30,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2022-11-16 11:56:30,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:30,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:30,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-11-16 11:56:30,153 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-11-16 11:56:30,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:30,156 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-11-16 11:56:30,156 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 11:56:30,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2022-11-16 11:56:30,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:30,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:30,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:30,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:30,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:30,172 INFO L748 eck$LassoCheckResult]: Stem: 27721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 27541#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27257#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27258#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28434#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28435#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27393#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27394#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27848#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27683#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27684#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27460#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27461#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27859#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28036#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28190#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28227#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27471#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27472#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28647#L1258-2 assume !(0 == ~T1_E~0); 27766#L1263-1 assume !(0 == ~T2_E~0); 27767#L1268-1 assume !(0 == ~T3_E~0); 28070#L1273-1 assume !(0 == ~T4_E~0); 28629#L1278-1 assume !(0 == ~T5_E~0); 28490#L1283-1 assume !(0 == ~T6_E~0); 28491#L1288-1 assume !(0 == ~T7_E~0); 28727#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28715#L1298-1 assume !(0 == ~T9_E~0); 28641#L1303-1 assume !(0 == ~T10_E~0); 27286#L1308-1 assume !(0 == ~T11_E~0); 27228#L1313-1 assume !(0 == ~T12_E~0); 27229#L1318-1 assume !(0 == ~T13_E~0); 27235#L1323-1 assume !(0 == ~E_1~0); 27236#L1328-1 assume !(0 == ~E_2~0); 27403#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28362#L1338-1 assume !(0 == ~E_4~0); 28363#L1343-1 assume !(0 == ~E_5~0); 28464#L1348-1 assume !(0 == ~E_6~0); 28750#L1353-1 assume !(0 == ~E_7~0); 28089#L1358-1 assume !(0 == ~E_8~0); 28090#L1363-1 assume !(0 == ~E_9~0); 28380#L1368-1 assume !(0 == ~E_10~0); 27065#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27066#L1378-1 assume !(0 == ~E_12~0); 27352#L1383-1 assume !(0 == ~E_13~0); 27353#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28096#L607 assume 1 == ~m_pc~0; 28097#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27423#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28462#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28016#L1560 assume !(0 != activate_threads_~tmp~1#1); 28017#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27248#L626 assume !(1 == ~t1_pc~0); 27249#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27517#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27518#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27687#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27148#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27149#L645 assume 1 == ~t2_pc~0; 27265#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27222#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27899#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27900#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27992#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27993#L664 assume 1 == ~t3_pc~0; 28749#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26989#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26990#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27648#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27649#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28657#L683 assume !(1 == ~t4_pc~0); 28212#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28164#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28165#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28199#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28323#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27942#L702 assume 1 == ~t5_pc~0; 27943#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27868#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28318#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28616#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28557#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27037#L721 assume !(1 == ~t6_pc~0); 27011#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27012#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27175#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27657#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27658#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28259#L740 assume 1 == ~t7_pc~0; 27086#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26899#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26900#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26889#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26890#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27593#L759 assume !(1 == ~t8_pc~0); 27594#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27623#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28316#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28317#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28448#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28726#L778 assume 1 == ~t9_pc~0; 28613#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27064#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27004#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26933#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26934#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27261#L797 assume !(1 == ~t10_pc~0); 27262#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27380#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28514#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27764#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27765#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28054#L816 assume 1 == ~t11_pc~0; 26969#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26970#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27725#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27664#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27665#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28189#L835 assume 1 == ~t12_pc~0; 28067#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27133#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27155#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27296#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27821#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27822#L854 assume !(1 == ~t13_pc~0); 27462#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27463#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27513#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27173#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27174#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28553#L1401 assume !(1 == ~M_E~0); 27652#L1401-2 assume !(1 == ~T1_E~0); 27653#L1406-1 assume !(1 == ~T2_E~0); 28248#L1411-1 assume !(1 == ~T3_E~0); 28249#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27915#L1421-1 assume !(1 == ~T5_E~0); 27458#L1426-1 assume !(1 == ~T6_E~0); 27459#L1431-1 assume !(1 == ~T7_E~0); 27007#L1436-1 assume !(1 == ~T8_E~0); 27008#L1441-1 assume !(1 == ~T9_E~0); 27755#L1446-1 assume !(1 == ~T10_E~0); 27756#L1451-1 assume !(1 == ~T11_E~0); 28461#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28115#L1461-1 assume !(1 == ~T13_E~0); 27676#L1466-1 assume !(1 == ~E_1~0); 27677#L1471-1 assume !(1 == ~E_2~0); 28446#L1476-1 assume !(1 == ~E_3~0); 28447#L1481-1 assume !(1 == ~E_4~0); 28595#L1486-1 assume !(1 == ~E_5~0); 27301#L1491-1 assume !(1 == ~E_6~0); 26941#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26942#L1501-1 assume !(1 == ~E_8~0); 27753#L1506-1 assume !(1 == ~E_9~0); 27754#L1511-1 assume !(1 == ~E_10~0); 27710#L1516-1 assume !(1 == ~E_11~0); 26885#L1521-1 assume !(1 == ~E_12~0); 26886#L1526-1 assume !(1 == ~E_13~0); 26940#L1531-1 assume { :end_inline_reset_delta_events } true; 27483#L1892-2 [2022-11-16 11:56:30,173 INFO L750 eck$LassoCheckResult]: Loop: 27483#L1892-2 assume !false; 28506#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28704#L1233 assume !false; 28687#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28019#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27999#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28157#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26983#L1046 assume !(0 != eval_~tmp~0#1); 26985#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27019#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28191#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28748#L1258-5 assume !(0 == ~T1_E~0); 27161#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27162#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28740#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28746#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28747#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27385#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27386#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28503#L1298-3 assume !(0 == ~T9_E~0); 28504#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28663#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28502#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28003#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27163#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27164#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28587#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27306#L1338-3 assume !(0 == ~E_4~0); 27307#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28419#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28592#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28593#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27959#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27519#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27520#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28276#L1378-3 assume !(0 == ~E_12~0); 28277#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28458#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28459#L607-42 assume 1 == ~m_pc~0; 28072#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27800#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27801#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27533#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27534#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28055#L626-42 assume 1 == ~t1_pc~0; 27617#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27618#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27922#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27923#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27197#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27198#L645-42 assume 1 == ~t2_pc~0; 28656#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28398#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28563#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27404#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26911#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26912#L664-42 assume 1 == ~t3_pc~0; 27714#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27439#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28690#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28225#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28226#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28391#L683-42 assume !(1 == ~t4_pc~0); 28099#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28100#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28232#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28652#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28653#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28497#L702-42 assume 1 == ~t5_pc~0; 27985#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27610#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27906#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28579#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26927#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26928#L721-42 assume 1 == ~t6_pc~0; 27081#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27101#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27565#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28732#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27737#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27583#L740-42 assume 1 == ~t7_pc~0; 27584#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27321#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27862#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27717#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 27718#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27991#L759-42 assume 1 == ~t8_pc~0; 27840#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27772#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27773#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27851#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27852#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27947#L778-42 assume 1 == ~t9_pc~0; 27784#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27786#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28196#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28101#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28102#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28159#L797-42 assume !(1 == ~t10_pc~0); 27328#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 27327#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28328#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28637#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28197#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28198#L816-42 assume 1 == ~t11_pc~0; 26875#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26876#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27418#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27419#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27498#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27499#L835-42 assume !(1 == ~t12_pc~0); 27795#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 27796#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27473#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27474#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28556#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28340#L854-42 assume 1 == ~t13_pc~0; 28341#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27417#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27027#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27028#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27674#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27675#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28453#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27264#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27128#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27129#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27728#L1421-3 assume !(1 == ~T5_E~0); 27729#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27304#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27305#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26891#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26892#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28481#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27812#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27465#L1461-3 assume !(1 == ~T13_E~0); 27466#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28743#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27405#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27406#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27806#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27433#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27434#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27846#L1501-3 assume !(1 == ~E_8~0); 27847#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28273#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28263#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28264#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27963#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27964#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28358#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27240#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28133#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27774#L1911 assume !(0 == start_simulation_~tmp~3#1); 27775#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28297#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27364#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28235#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27069#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27070#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27299#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 27300#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27483#L1892-2 [2022-11-16 11:56:30,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:30,174 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2022-11-16 11:56:30,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:30,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46603500] [2022-11-16 11:56:30,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:30,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:30,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:30,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:30,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:30,235 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [46603500] [2022-11-16 11:56:30,237 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [46603500] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:30,237 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:30,238 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:30,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973496391] [2022-11-16 11:56:30,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:30,241 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:30,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:30,241 INFO L85 PathProgramCache]: Analyzing trace with hash 1867815776, now seen corresponding path program 1 times [2022-11-16 11:56:30,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:30,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779649190] [2022-11-16 11:56:30,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:30,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:30,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:30,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:30,329 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:30,329 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779649190] [2022-11-16 11:56:30,329 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779649190] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:30,330 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:30,330 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:30,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925881288] [2022-11-16 11:56:30,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:30,330 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:30,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:30,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:30,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:30,331 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:30,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:30,374 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-11-16 11:56:30,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2022-11-16 11:56:30,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:30,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-11-16 11:56:30,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:30,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:30,398 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2022-11-16 11:56:30,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:30,400 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-11-16 11:56:30,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2022-11-16 11:56:30,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:30,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:30,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-11-16 11:56:30,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-11-16 11:56:30,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:30,438 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-11-16 11:56:30,438 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 11:56:30,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2022-11-16 11:56:30,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:30,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:30,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:30,450 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:30,450 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:30,450 INFO L748 eck$LassoCheckResult]: Stem: 31556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 31376#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31092#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31093#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32269#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32270#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31228#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31229#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31683#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31518#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31519#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31295#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31296#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31694#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31871#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32025#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32062#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31306#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31307#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32482#L1258-2 assume !(0 == ~T1_E~0); 31601#L1263-1 assume !(0 == ~T2_E~0); 31602#L1268-1 assume !(0 == ~T3_E~0); 31905#L1273-1 assume !(0 == ~T4_E~0); 32464#L1278-1 assume !(0 == ~T5_E~0); 32325#L1283-1 assume !(0 == ~T6_E~0); 32326#L1288-1 assume !(0 == ~T7_E~0); 32562#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32550#L1298-1 assume !(0 == ~T9_E~0); 32476#L1303-1 assume !(0 == ~T10_E~0); 31121#L1308-1 assume !(0 == ~T11_E~0); 31063#L1313-1 assume !(0 == ~T12_E~0); 31064#L1318-1 assume !(0 == ~T13_E~0); 31070#L1323-1 assume !(0 == ~E_1~0); 31071#L1328-1 assume !(0 == ~E_2~0); 31238#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32197#L1338-1 assume !(0 == ~E_4~0); 32198#L1343-1 assume !(0 == ~E_5~0); 32299#L1348-1 assume !(0 == ~E_6~0); 32585#L1353-1 assume !(0 == ~E_7~0); 31924#L1358-1 assume !(0 == ~E_8~0); 31925#L1363-1 assume !(0 == ~E_9~0); 32215#L1368-1 assume !(0 == ~E_10~0); 30900#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 30901#L1378-1 assume !(0 == ~E_12~0); 31187#L1383-1 assume !(0 == ~E_13~0); 31188#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31931#L607 assume 1 == ~m_pc~0; 31932#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31258#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32297#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31851#L1560 assume !(0 != activate_threads_~tmp~1#1); 31852#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31083#L626 assume !(1 == ~t1_pc~0); 31084#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31352#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31353#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31522#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 30983#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30984#L645 assume 1 == ~t2_pc~0; 31100#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31057#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31734#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31735#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 31827#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31828#L664 assume 1 == ~t3_pc~0; 32584#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30824#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30825#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31483#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31484#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32492#L683 assume !(1 == ~t4_pc~0); 32047#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31999#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32000#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32034#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32158#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31777#L702 assume 1 == ~t5_pc~0; 31778#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31703#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32153#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32451#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32392#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30872#L721 assume !(1 == ~t6_pc~0); 30846#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30847#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31010#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31492#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31493#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32094#L740 assume 1 == ~t7_pc~0; 30921#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30734#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30735#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30724#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30725#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31428#L759 assume !(1 == ~t8_pc~0); 31429#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31458#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32151#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32152#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32283#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32561#L778 assume 1 == ~t9_pc~0; 32448#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30899#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30839#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30768#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30769#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31096#L797 assume !(1 == ~t10_pc~0); 31097#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31215#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32349#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31599#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31600#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31889#L816 assume 1 == ~t11_pc~0; 30804#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30805#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31560#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31499#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31500#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32024#L835 assume 1 == ~t12_pc~0; 31902#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30968#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30990#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31131#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31656#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31657#L854 assume !(1 == ~t13_pc~0); 31297#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31298#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31348#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31008#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31009#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32388#L1401 assume !(1 == ~M_E~0); 31487#L1401-2 assume !(1 == ~T1_E~0); 31488#L1406-1 assume !(1 == ~T2_E~0); 32083#L1411-1 assume !(1 == ~T3_E~0); 32084#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31750#L1421-1 assume !(1 == ~T5_E~0); 31293#L1426-1 assume !(1 == ~T6_E~0); 31294#L1431-1 assume !(1 == ~T7_E~0); 30842#L1436-1 assume !(1 == ~T8_E~0); 30843#L1441-1 assume !(1 == ~T9_E~0); 31590#L1446-1 assume !(1 == ~T10_E~0); 31591#L1451-1 assume !(1 == ~T11_E~0); 32296#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31950#L1461-1 assume !(1 == ~T13_E~0); 31511#L1466-1 assume !(1 == ~E_1~0); 31512#L1471-1 assume !(1 == ~E_2~0); 32281#L1476-1 assume !(1 == ~E_3~0); 32282#L1481-1 assume !(1 == ~E_4~0); 32430#L1486-1 assume !(1 == ~E_5~0); 31136#L1491-1 assume !(1 == ~E_6~0); 30776#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30777#L1501-1 assume !(1 == ~E_8~0); 31588#L1506-1 assume !(1 == ~E_9~0); 31589#L1511-1 assume !(1 == ~E_10~0); 31545#L1516-1 assume !(1 == ~E_11~0); 30720#L1521-1 assume !(1 == ~E_12~0); 30721#L1526-1 assume !(1 == ~E_13~0); 30775#L1531-1 assume { :end_inline_reset_delta_events } true; 31318#L1892-2 [2022-11-16 11:56:30,451 INFO L750 eck$LassoCheckResult]: Loop: 31318#L1892-2 assume !false; 32341#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32539#L1233 assume !false; 32522#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 31854#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31834#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31992#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30818#L1046 assume !(0 != eval_~tmp~0#1); 30820#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30854#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32026#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32583#L1258-5 assume !(0 == ~T1_E~0); 30996#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30997#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32575#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32581#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32582#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31220#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31221#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32338#L1298-3 assume !(0 == ~T9_E~0); 32339#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32498#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32337#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31838#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30998#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30999#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32422#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31141#L1338-3 assume !(0 == ~E_4~0); 31142#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32254#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32427#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32428#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31794#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31354#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31355#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32111#L1378-3 assume !(0 == ~E_12~0); 32112#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32293#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32294#L607-42 assume 1 == ~m_pc~0; 31907#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31635#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31636#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31368#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31369#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31890#L626-42 assume 1 == ~t1_pc~0; 31452#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31453#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31757#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31758#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31032#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31033#L645-42 assume !(1 == ~t2_pc~0); 32232#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32233#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32398#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31239#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30746#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30747#L664-42 assume !(1 == ~t3_pc~0); 31273#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 31274#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32525#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32060#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32061#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32226#L683-42 assume !(1 == ~t4_pc~0); 31934#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 31935#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32067#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32487#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32488#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32332#L702-42 assume !(1 == ~t5_pc~0); 31444#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 31445#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31741#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32414#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30762#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30763#L721-42 assume 1 == ~t6_pc~0; 30916#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30936#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31400#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32567#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31572#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31418#L740-42 assume !(1 == ~t7_pc~0); 31155#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31156#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31697#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31552#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 31553#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31826#L759-42 assume 1 == ~t8_pc~0; 31675#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31607#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31608#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31686#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31687#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31782#L778-42 assume 1 == ~t9_pc~0; 31619#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31621#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32031#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31936#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31937#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31994#L797-42 assume 1 == ~t10_pc~0; 31161#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31162#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32163#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32472#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32032#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32033#L816-42 assume 1 == ~t11_pc~0; 30710#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30711#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31253#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31254#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31333#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31334#L835-42 assume 1 == ~t12_pc~0; 31738#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31631#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31308#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31309#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32391#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32175#L854-42 assume 1 == ~t13_pc~0; 32176#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 31252#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30862#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30863#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31509#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31510#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32288#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31099#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30963#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30964#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31563#L1421-3 assume !(1 == ~T5_E~0); 31564#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31139#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31140#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30726#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30727#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32316#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31647#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31300#L1461-3 assume !(1 == ~T13_E~0); 31301#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32578#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31240#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31241#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31641#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31268#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31269#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31681#L1501-3 assume !(1 == ~E_8~0); 31682#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32108#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32098#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32099#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31798#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 31799#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32193#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31075#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31968#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31609#L1911 assume !(0 == start_simulation_~tmp~3#1); 31610#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32132#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31199#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32070#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30904#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30905#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31134#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 31135#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31318#L1892-2 [2022-11-16 11:56:30,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:30,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2022-11-16 11:56:30,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:30,452 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988722655] [2022-11-16 11:56:30,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:30,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:30,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:30,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:30,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:30,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988722655] [2022-11-16 11:56:30,500 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988722655] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:30,500 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:30,500 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:30,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1357438424] [2022-11-16 11:56:30,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:30,501 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:30,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:30,502 INFO L85 PathProgramCache]: Analyzing trace with hash 1476580190, now seen corresponding path program 1 times [2022-11-16 11:56:30,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:30,502 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108504556] [2022-11-16 11:56:30,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:30,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:30,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:30,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:30,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:30,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108504556] [2022-11-16 11:56:30,566 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108504556] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:30,566 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:30,567 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:30,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [87958359] [2022-11-16 11:56:30,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:30,567 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:30,567 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:30,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:30,568 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:30,568 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:30,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:30,607 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-11-16 11:56:30,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2022-11-16 11:56:30,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:30,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-11-16 11:56:30,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:30,628 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:30,628 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2022-11-16 11:56:30,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:30,631 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-11-16 11:56:30,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2022-11-16 11:56:30,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:30,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:30,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-11-16 11:56:30,667 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-11-16 11:56:30,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:30,668 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-11-16 11:56:30,668 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 11:56:30,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2022-11-16 11:56:30,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:30,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:30,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:30,680 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:30,680 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:30,680 INFO L748 eck$LassoCheckResult]: Stem: 35391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35211#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34927#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34928#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36104#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36105#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35063#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35064#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35522#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35353#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35354#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35130#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35131#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35529#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35706#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35861#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35897#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35143#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35144#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36317#L1258-2 assume !(0 == ~T1_E~0); 35436#L1263-1 assume !(0 == ~T2_E~0); 35437#L1268-1 assume !(0 == ~T3_E~0); 35740#L1273-1 assume !(0 == ~T4_E~0); 36299#L1278-1 assume !(0 == ~T5_E~0); 36160#L1283-1 assume !(0 == ~T6_E~0); 36161#L1288-1 assume !(0 == ~T7_E~0); 36398#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36385#L1298-1 assume !(0 == ~T9_E~0); 36311#L1303-1 assume !(0 == ~T10_E~0); 34956#L1308-1 assume !(0 == ~T11_E~0); 34901#L1313-1 assume !(0 == ~T12_E~0); 34902#L1318-1 assume !(0 == ~T13_E~0); 34907#L1323-1 assume !(0 == ~E_1~0); 34908#L1328-1 assume !(0 == ~E_2~0); 35073#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36032#L1338-1 assume !(0 == ~E_4~0); 36033#L1343-1 assume !(0 == ~E_5~0); 36134#L1348-1 assume !(0 == ~E_6~0); 36420#L1353-1 assume !(0 == ~E_7~0); 35759#L1358-1 assume !(0 == ~E_8~0); 35760#L1363-1 assume !(0 == ~E_9~0); 36051#L1368-1 assume !(0 == ~E_10~0); 34735#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34736#L1378-1 assume !(0 == ~E_12~0); 35024#L1383-1 assume !(0 == ~E_13~0); 35025#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35766#L607 assume 1 == ~m_pc~0; 35767#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35093#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36132#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35686#L1560 assume !(0 != activate_threads_~tmp~1#1); 35687#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34918#L626 assume !(1 == ~t1_pc~0); 34919#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35189#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35190#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35359#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34821#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34822#L645 assume 1 == ~t2_pc~0; 34935#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34892#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35572#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35573#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35662#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35663#L664 assume 1 == ~t3_pc~0; 36419#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34663#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34664#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35318#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35319#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36327#L683 assume !(1 == ~t4_pc~0); 35882#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35834#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35835#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35869#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35993#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35616#L702 assume 1 == ~t5_pc~0; 35617#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35539#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35988#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36287#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36228#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34707#L721 assume !(1 == ~t6_pc~0); 34681#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34682#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34845#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35327#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35328#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35929#L740 assume 1 == ~t7_pc~0; 34756#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34569#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34570#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34559#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34560#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35264#L759 assume !(1 == ~t8_pc~0); 35265#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35293#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35986#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35987#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36118#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36396#L778 assume 1 == ~t9_pc~0; 36285#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34734#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34674#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34603#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34604#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34932#L797 assume !(1 == ~t10_pc~0); 34933#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35050#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36184#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35434#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35435#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35724#L816 assume 1 == ~t11_pc~0; 34639#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34640#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35397#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35334#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35335#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35859#L835 assume 1 == ~t12_pc~0; 35737#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34803#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34825#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34966#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35491#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35492#L854 assume !(1 == ~t13_pc~0); 35132#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35133#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35185#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34843#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34844#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36223#L1401 assume !(1 == ~M_E~0); 35322#L1401-2 assume !(1 == ~T1_E~0); 35323#L1406-1 assume !(1 == ~T2_E~0); 35918#L1411-1 assume !(1 == ~T3_E~0); 35919#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35585#L1421-1 assume !(1 == ~T5_E~0); 35128#L1426-1 assume !(1 == ~T6_E~0); 35129#L1431-1 assume !(1 == ~T7_E~0); 34677#L1436-1 assume !(1 == ~T8_E~0); 34678#L1441-1 assume !(1 == ~T9_E~0); 35425#L1446-1 assume !(1 == ~T10_E~0); 35426#L1451-1 assume !(1 == ~T11_E~0); 36131#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35785#L1461-1 assume !(1 == ~T13_E~0); 35346#L1466-1 assume !(1 == ~E_1~0); 35347#L1471-1 assume !(1 == ~E_2~0); 36116#L1476-1 assume !(1 == ~E_3~0); 36117#L1481-1 assume !(1 == ~E_4~0); 36265#L1486-1 assume !(1 == ~E_5~0); 34971#L1491-1 assume !(1 == ~E_6~0); 34611#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34612#L1501-1 assume !(1 == ~E_8~0); 35423#L1506-1 assume !(1 == ~E_9~0); 35424#L1511-1 assume !(1 == ~E_10~0); 35380#L1516-1 assume !(1 == ~E_11~0); 34555#L1521-1 assume !(1 == ~E_12~0); 34556#L1526-1 assume !(1 == ~E_13~0); 34610#L1531-1 assume { :end_inline_reset_delta_events } true; 35153#L1892-2 [2022-11-16 11:56:30,681 INFO L750 eck$LassoCheckResult]: Loop: 35153#L1892-2 assume !false; 36176#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36374#L1233 assume !false; 36357#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35689#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35669#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35827#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34653#L1046 assume !(0 != eval_~tmp~0#1); 34655#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34689#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35860#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36418#L1258-5 assume !(0 == ~T1_E~0); 34831#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34832#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36410#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36416#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36417#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35055#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35056#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36173#L1298-3 assume !(0 == ~T9_E~0); 36174#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36333#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36172#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35673#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34833#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34834#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36257#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34976#L1338-3 assume !(0 == ~E_4~0); 34977#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36089#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36262#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36263#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35629#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35187#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35188#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35946#L1378-3 assume !(0 == ~E_12~0); 35947#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36128#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36129#L607-42 assume 1 == ~m_pc~0; 35742#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35470#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35471#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35203#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35204#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35725#L626-42 assume 1 == ~t1_pc~0; 35287#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35288#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35592#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35593#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34867#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34868#L645-42 assume !(1 == ~t2_pc~0); 36067#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36068#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36233#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35074#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34581#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34582#L664-42 assume !(1 == ~t3_pc~0); 35108#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 35109#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36360#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35895#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35896#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36061#L683-42 assume !(1 == ~t4_pc~0); 35769#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35770#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35902#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36322#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36323#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36167#L702-42 assume 1 == ~t5_pc~0; 35655#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35280#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35576#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36249#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34597#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34598#L721-42 assume !(1 == ~t6_pc~0); 34752#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34771#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35235#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36402#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35407#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35253#L740-42 assume 1 == ~t7_pc~0; 35254#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34991#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35532#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35387#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 35388#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35661#L759-42 assume 1 == ~t8_pc~0; 35510#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35442#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35443#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35520#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35521#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35615#L778-42 assume 1 == ~t9_pc~0; 35454#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35456#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35866#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35771#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35772#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35829#L797-42 assume 1 == ~t10_pc~0; 34996#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34997#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35998#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36307#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35867#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35868#L816-42 assume 1 == ~t11_pc~0; 34545#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34546#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35088#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35089#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35168#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35169#L835-42 assume 1 == ~t12_pc~0; 35571#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35466#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35141#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35142#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36226#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36010#L854-42 assume 1 == ~t13_pc~0; 36011#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35087#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34697#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34698#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35344#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35345#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36123#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34931#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34798#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34799#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35398#L1421-3 assume !(1 == ~T5_E~0); 35399#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34974#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34975#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34561#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34562#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36151#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35482#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35135#L1461-3 assume !(1 == ~T13_E~0); 35136#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36413#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35075#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35076#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35476#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35103#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35104#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35516#L1501-3 assume !(1 == ~E_8~0); 35517#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35943#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35933#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35934#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35633#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35634#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36028#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34910#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35803#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35444#L1911 assume !(0 == start_simulation_~tmp~3#1); 35445#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35967#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35034#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35905#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34739#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34740#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34969#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34970#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35153#L1892-2 [2022-11-16 11:56:30,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:30,682 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2022-11-16 11:56:30,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:30,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011581936] [2022-11-16 11:56:30,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:30,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:30,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:30,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:30,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:30,730 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011581936] [2022-11-16 11:56:30,730 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2011581936] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:30,731 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:30,731 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:30,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544464054] [2022-11-16 11:56:30,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:30,731 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:30,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:30,732 INFO L85 PathProgramCache]: Analyzing trace with hash 95640511, now seen corresponding path program 1 times [2022-11-16 11:56:30,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:30,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098778540] [2022-11-16 11:56:30,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:30,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:30,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:30,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:30,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:30,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098778540] [2022-11-16 11:56:30,831 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2098778540] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:30,831 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:30,832 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:30,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917642499] [2022-11-16 11:56:30,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:30,833 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:30,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:30,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:30,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:30,834 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:30,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:30,882 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-11-16 11:56:30,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2022-11-16 11:56:30,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:30,905 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-11-16 11:56:30,905 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:30,907 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:30,907 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2022-11-16 11:56:30,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:30,911 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-11-16 11:56:30,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2022-11-16 11:56:30,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:30,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:30,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-11-16 11:56:30,954 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-11-16 11:56:30,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:30,955 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-11-16 11:56:30,956 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 11:56:30,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2022-11-16 11:56:30,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:30,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:30,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:30,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:30,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:30,970 INFO L748 eck$LassoCheckResult]: Stem: 39226#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 39227#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39046#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38762#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38763#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 39939#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39940#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38898#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38899#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39357#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39188#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39189#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38965#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38966#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39364#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39541#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39695#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39732#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38978#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38979#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40152#L1258-2 assume !(0 == ~T1_E~0); 39271#L1263-1 assume !(0 == ~T2_E~0); 39272#L1268-1 assume !(0 == ~T3_E~0); 39575#L1273-1 assume !(0 == ~T4_E~0); 40134#L1278-1 assume !(0 == ~T5_E~0); 39995#L1283-1 assume !(0 == ~T6_E~0); 39996#L1288-1 assume !(0 == ~T7_E~0); 40233#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40220#L1298-1 assume !(0 == ~T9_E~0); 40146#L1303-1 assume !(0 == ~T10_E~0); 38791#L1308-1 assume !(0 == ~T11_E~0); 38733#L1313-1 assume !(0 == ~T12_E~0); 38734#L1318-1 assume !(0 == ~T13_E~0); 38742#L1323-1 assume !(0 == ~E_1~0); 38743#L1328-1 assume !(0 == ~E_2~0); 38908#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 39867#L1338-1 assume !(0 == ~E_4~0); 39868#L1343-1 assume !(0 == ~E_5~0); 39969#L1348-1 assume !(0 == ~E_6~0); 40255#L1353-1 assume !(0 == ~E_7~0); 39594#L1358-1 assume !(0 == ~E_8~0); 39595#L1363-1 assume !(0 == ~E_9~0); 39886#L1368-1 assume !(0 == ~E_10~0); 38570#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38571#L1378-1 assume !(0 == ~E_12~0); 38859#L1383-1 assume !(0 == ~E_13~0); 38860#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39601#L607 assume 1 == ~m_pc~0; 39602#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38928#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39967#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39521#L1560 assume !(0 != activate_threads_~tmp~1#1); 39522#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38753#L626 assume !(1 == ~t1_pc~0); 38754#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39024#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39025#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39194#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38655#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38656#L645 assume 1 == ~t2_pc~0; 38770#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38727#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39407#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39408#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39497#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39498#L664 assume 1 == ~t3_pc~0; 40254#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38498#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38499#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39153#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39154#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40162#L683 assume !(1 == ~t4_pc~0); 39717#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39669#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39670#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39704#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39828#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39451#L702 assume 1 == ~t5_pc~0; 39452#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39374#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39823#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40122#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40063#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38542#L721 assume !(1 == ~t6_pc~0); 38516#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38517#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38680#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39162#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39163#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39764#L740 assume 1 == ~t7_pc~0; 38591#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38404#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38405#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38394#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38395#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39099#L759 assume !(1 == ~t8_pc~0); 39100#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39128#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39821#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39822#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 39953#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40231#L778 assume 1 == ~t9_pc~0; 40120#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38569#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38509#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38438#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38439#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38767#L797 assume !(1 == ~t10_pc~0); 38768#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38885#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40019#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39269#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39270#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39559#L816 assume 1 == ~t11_pc~0; 38474#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38475#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39232#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39169#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39170#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39694#L835 assume 1 == ~t12_pc~0; 39572#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38638#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38660#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38801#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39326#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39327#L854 assume !(1 == ~t13_pc~0); 38967#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 38968#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39020#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38678#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38679#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40058#L1401 assume !(1 == ~M_E~0); 39157#L1401-2 assume !(1 == ~T1_E~0); 39158#L1406-1 assume !(1 == ~T2_E~0); 39753#L1411-1 assume !(1 == ~T3_E~0); 39754#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39420#L1421-1 assume !(1 == ~T5_E~0); 38963#L1426-1 assume !(1 == ~T6_E~0); 38964#L1431-1 assume !(1 == ~T7_E~0); 38512#L1436-1 assume !(1 == ~T8_E~0); 38513#L1441-1 assume !(1 == ~T9_E~0); 39262#L1446-1 assume !(1 == ~T10_E~0); 39263#L1451-1 assume !(1 == ~T11_E~0); 39966#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39620#L1461-1 assume !(1 == ~T13_E~0); 39181#L1466-1 assume !(1 == ~E_1~0); 39182#L1471-1 assume !(1 == ~E_2~0); 39951#L1476-1 assume !(1 == ~E_3~0); 39952#L1481-1 assume !(1 == ~E_4~0); 40100#L1486-1 assume !(1 == ~E_5~0); 38806#L1491-1 assume !(1 == ~E_6~0); 38446#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38447#L1501-1 assume !(1 == ~E_8~0); 39258#L1506-1 assume !(1 == ~E_9~0); 39259#L1511-1 assume !(1 == ~E_10~0); 39215#L1516-1 assume !(1 == ~E_11~0); 38392#L1521-1 assume !(1 == ~E_12~0); 38393#L1526-1 assume !(1 == ~E_13~0); 38445#L1531-1 assume { :end_inline_reset_delta_events } true; 38988#L1892-2 [2022-11-16 11:56:30,972 INFO L750 eck$LassoCheckResult]: Loop: 38988#L1892-2 assume !false; 40011#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40209#L1233 assume !false; 40192#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39524#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39504#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39662#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38488#L1046 assume !(0 != eval_~tmp~0#1); 38490#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38524#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39696#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40253#L1258-5 assume !(0 == ~T1_E~0); 38670#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38671#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40245#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40251#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40252#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38892#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38893#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40008#L1298-3 assume !(0 == ~T9_E~0); 40009#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40168#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40007#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39508#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38666#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38667#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40092#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38811#L1338-3 assume !(0 == ~E_4~0); 38812#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39924#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40097#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40098#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39464#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39022#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39023#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39781#L1378-3 assume !(0 == ~E_12~0); 39782#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 39963#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39964#L607-42 assume 1 == ~m_pc~0; 39577#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39305#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39306#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39038#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39039#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39560#L626-42 assume 1 == ~t1_pc~0; 39122#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39123#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39427#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39428#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38702#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38703#L645-42 assume 1 == ~t2_pc~0; 40161#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39903#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40068#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38909#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38416#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38417#L664-42 assume 1 == ~t3_pc~0; 39219#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38944#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40195#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39730#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39731#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39896#L683-42 assume !(1 == ~t4_pc~0); 39604#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39605#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39737#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40157#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40158#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40002#L702-42 assume 1 == ~t5_pc~0; 39490#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39115#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39411#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40084#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38432#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38433#L721-42 assume 1 == ~t6_pc~0; 38586#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38606#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39070#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40237#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39242#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39088#L740-42 assume 1 == ~t7_pc~0; 39089#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38826#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39367#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39222#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 39223#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39496#L759-42 assume 1 == ~t8_pc~0; 39345#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39277#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39278#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39355#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39356#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39450#L778-42 assume 1 == ~t9_pc~0; 39289#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39291#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39700#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39606#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39607#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39664#L797-42 assume !(1 == ~t10_pc~0); 38833#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 38832#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39833#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40142#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39702#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39703#L816-42 assume 1 == ~t11_pc~0; 38380#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38381#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38923#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38924#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39003#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39004#L835-42 assume !(1 == ~t12_pc~0); 39300#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39301#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38976#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38977#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40061#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39845#L854-42 assume 1 == ~t13_pc~0; 39846#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38920#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38532#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38533#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39179#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39180#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39958#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38766#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38633#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38634#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39233#L1421-3 assume !(1 == ~T5_E~0); 39234#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38809#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38810#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38396#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38397#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39986#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39317#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38970#L1461-3 assume !(1 == ~T13_E~0); 38971#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40248#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38910#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38911#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39311#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38938#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38939#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39351#L1501-3 assume !(1 == ~E_8~0); 39352#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39778#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39768#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39769#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39468#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39469#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39863#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38745#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39638#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39279#L1911 assume !(0 == start_simulation_~tmp~3#1); 39280#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39802#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38869#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39740#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38574#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38575#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38804#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 38805#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 38988#L1892-2 [2022-11-16 11:56:30,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:30,974 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2022-11-16 11:56:30,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:30,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256036575] [2022-11-16 11:56:30,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:30,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:30,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:31,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:31,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:31,037 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256036575] [2022-11-16 11:56:31,037 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256036575] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:31,037 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:31,037 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:31,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475883735] [2022-11-16 11:56:31,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:31,038 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:31,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:31,039 INFO L85 PathProgramCache]: Analyzing trace with hash 1867815776, now seen corresponding path program 2 times [2022-11-16 11:56:31,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:31,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135225758] [2022-11-16 11:56:31,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:31,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:31,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:31,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:31,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:31,119 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135225758] [2022-11-16 11:56:31,119 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135225758] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:31,120 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:31,120 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:31,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [662208437] [2022-11-16 11:56:31,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:31,121 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:31,121 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:31,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:31,122 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:31,122 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:31,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:31,170 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-11-16 11:56:31,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2022-11-16 11:56:31,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:31,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-11-16 11:56:31,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:31,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:31,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2022-11-16 11:56:31,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:31,198 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-11-16 11:56:31,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2022-11-16 11:56:31,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:31,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:31,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-11-16 11:56:31,234 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-11-16 11:56:31,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:31,235 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-11-16 11:56:31,235 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 11:56:31,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2022-11-16 11:56:31,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:31,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:31,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:31,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:31,246 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:31,246 INFO L748 eck$LassoCheckResult]: Stem: 43061#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 43062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42881#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42597#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42598#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43774#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43775#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42733#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42734#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43192#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43023#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43024#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42800#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42801#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43199#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43376#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43530#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43567#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42813#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42814#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43987#L1258-2 assume !(0 == ~T1_E~0); 43106#L1263-1 assume !(0 == ~T2_E~0); 43107#L1268-1 assume !(0 == ~T3_E~0); 43410#L1273-1 assume !(0 == ~T4_E~0); 43969#L1278-1 assume !(0 == ~T5_E~0); 43830#L1283-1 assume !(0 == ~T6_E~0); 43831#L1288-1 assume !(0 == ~T7_E~0); 44068#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44055#L1298-1 assume !(0 == ~T9_E~0); 43981#L1303-1 assume !(0 == ~T10_E~0); 42626#L1308-1 assume !(0 == ~T11_E~0); 42568#L1313-1 assume !(0 == ~T12_E~0); 42569#L1318-1 assume !(0 == ~T13_E~0); 42577#L1323-1 assume !(0 == ~E_1~0); 42578#L1328-1 assume !(0 == ~E_2~0); 42743#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43702#L1338-1 assume !(0 == ~E_4~0); 43703#L1343-1 assume !(0 == ~E_5~0); 43804#L1348-1 assume !(0 == ~E_6~0); 44090#L1353-1 assume !(0 == ~E_7~0); 43429#L1358-1 assume !(0 == ~E_8~0); 43430#L1363-1 assume !(0 == ~E_9~0); 43720#L1368-1 assume !(0 == ~E_10~0); 42405#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42406#L1378-1 assume !(0 == ~E_12~0); 42694#L1383-1 assume !(0 == ~E_13~0); 42695#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43436#L607 assume 1 == ~m_pc~0; 43437#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42763#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43802#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43356#L1560 assume !(0 != activate_threads_~tmp~1#1); 43357#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42588#L626 assume !(1 == ~t1_pc~0); 42589#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42857#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42858#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43029#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42490#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42491#L645 assume 1 == ~t2_pc~0; 42605#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42562#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43242#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43243#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43332#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43333#L664 assume 1 == ~t3_pc~0; 44089#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42333#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42334#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42988#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42989#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43997#L683 assume !(1 == ~t4_pc~0); 43552#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43504#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43505#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43539#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43663#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43286#L702 assume 1 == ~t5_pc~0; 43287#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43209#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43658#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43957#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43898#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42377#L721 assume !(1 == ~t6_pc~0); 42351#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42352#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42515#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42997#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42998#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43599#L740 assume 1 == ~t7_pc~0; 42426#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42239#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42240#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42229#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42230#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42934#L759 assume !(1 == ~t8_pc~0); 42935#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42963#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43656#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43657#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43788#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44066#L778 assume 1 == ~t9_pc~0; 43953#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42404#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42344#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42273#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42274#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42602#L797 assume !(1 == ~t10_pc~0); 42603#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42720#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43854#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43104#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43105#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43394#L816 assume 1 == ~t11_pc~0; 42309#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42310#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43067#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43004#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43005#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43529#L835 assume 1 == ~t12_pc~0; 43407#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42473#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42495#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42636#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43161#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43162#L854 assume !(1 == ~t13_pc~0); 42802#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42803#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42853#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42513#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42514#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43893#L1401 assume !(1 == ~M_E~0); 42992#L1401-2 assume !(1 == ~T1_E~0); 42993#L1406-1 assume !(1 == ~T2_E~0); 43588#L1411-1 assume !(1 == ~T3_E~0); 43589#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43255#L1421-1 assume !(1 == ~T5_E~0); 42798#L1426-1 assume !(1 == ~T6_E~0); 42799#L1431-1 assume !(1 == ~T7_E~0); 42347#L1436-1 assume !(1 == ~T8_E~0); 42348#L1441-1 assume !(1 == ~T9_E~0); 43097#L1446-1 assume !(1 == ~T10_E~0); 43098#L1451-1 assume !(1 == ~T11_E~0); 43801#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43455#L1461-1 assume !(1 == ~T13_E~0); 43016#L1466-1 assume !(1 == ~E_1~0); 43017#L1471-1 assume !(1 == ~E_2~0); 43786#L1476-1 assume !(1 == ~E_3~0); 43787#L1481-1 assume !(1 == ~E_4~0); 43935#L1486-1 assume !(1 == ~E_5~0); 42641#L1491-1 assume !(1 == ~E_6~0); 42281#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42282#L1501-1 assume !(1 == ~E_8~0); 43093#L1506-1 assume !(1 == ~E_9~0); 43094#L1511-1 assume !(1 == ~E_10~0); 43050#L1516-1 assume !(1 == ~E_11~0); 42227#L1521-1 assume !(1 == ~E_12~0); 42228#L1526-1 assume !(1 == ~E_13~0); 42280#L1531-1 assume { :end_inline_reset_delta_events } true; 42823#L1892-2 [2022-11-16 11:56:31,247 INFO L750 eck$LassoCheckResult]: Loop: 42823#L1892-2 assume !false; 43846#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44044#L1233 assume !false; 44027#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43359#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43339#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43497#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42323#L1046 assume !(0 != eval_~tmp~0#1); 42325#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42359#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43531#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44088#L1258-5 assume !(0 == ~T1_E~0); 42503#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42504#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44080#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44086#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44087#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42727#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42728#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43843#L1298-3 assume !(0 == ~T9_E~0); 43844#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44003#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43842#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43343#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42505#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42506#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43927#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42646#L1338-3 assume !(0 == ~E_4~0); 42647#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43759#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43933#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43934#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43301#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42859#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42860#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43616#L1378-3 assume !(0 == ~E_12~0); 43617#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43798#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43799#L607-42 assume 1 == ~m_pc~0; 43414#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43140#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43141#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42873#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42874#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43395#L626-42 assume 1 == ~t1_pc~0; 42957#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42958#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43262#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43263#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42537#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42538#L645-42 assume !(1 == ~t2_pc~0); 43736#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43737#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43903#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42744#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42251#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42252#L664-42 assume !(1 == ~t3_pc~0); 42778#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 42779#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44030#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43565#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43566#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43731#L683-42 assume 1 == ~t4_pc~0; 44096#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43440#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43571#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43992#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43993#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43837#L702-42 assume !(1 == ~t5_pc~0); 42949#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42950#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43246#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43919#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42267#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42268#L721-42 assume 1 == ~t6_pc~0; 42421#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42441#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42905#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44072#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43077#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42923#L740-42 assume !(1 == ~t7_pc~0); 42660#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 42661#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43202#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43057#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 43058#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43331#L759-42 assume 1 == ~t8_pc~0; 43180#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43112#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43113#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43190#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43191#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43285#L778-42 assume 1 == ~t9_pc~0; 43124#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43126#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43535#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43441#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43442#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43499#L797-42 assume 1 == ~t10_pc~0; 42666#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42667#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43668#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43977#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43537#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43538#L816-42 assume 1 == ~t11_pc~0; 42215#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42216#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42758#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42759#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42838#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42839#L835-42 assume 1 == ~t12_pc~0; 43241#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43135#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42811#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42812#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43896#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43680#L854-42 assume 1 == ~t13_pc~0; 43681#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42755#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42367#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42368#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43014#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43015#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43793#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42601#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42468#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42469#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43068#L1421-3 assume !(1 == ~T5_E~0); 43069#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42644#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42645#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42231#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42232#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43821#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43152#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42805#L1461-3 assume !(1 == ~T13_E~0); 42806#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44083#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42745#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42746#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43146#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42773#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42774#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43185#L1501-3 assume !(1 == ~E_8~0); 43186#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43613#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43603#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43604#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43303#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43304#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43698#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42580#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43473#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43114#L1911 assume !(0 == start_simulation_~tmp~3#1); 43115#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43637#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42704#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43575#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42409#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42410#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42639#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 42640#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42823#L1892-2 [2022-11-16 11:56:31,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:31,248 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2022-11-16 11:56:31,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:31,248 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891808117] [2022-11-16 11:56:31,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:31,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:31,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:31,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:31,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:31,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891808117] [2022-11-16 11:56:31,304 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891808117] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:31,304 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:31,304 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:31,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156569704] [2022-11-16 11:56:31,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:31,305 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:31,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:31,305 INFO L85 PathProgramCache]: Analyzing trace with hash -1815330241, now seen corresponding path program 1 times [2022-11-16 11:56:31,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:31,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46028651] [2022-11-16 11:56:31,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:31,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:31,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:31,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:31,367 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:31,367 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [46028651] [2022-11-16 11:56:31,368 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [46028651] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:31,368 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:31,368 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:31,368 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142267565] [2022-11-16 11:56:31,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:31,369 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:31,369 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:31,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:31,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:31,370 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:31,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:31,409 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-11-16 11:56:31,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2022-11-16 11:56:31,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:31,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-11-16 11:56:31,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:31,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:31,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2022-11-16 11:56:31,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:31,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-11-16 11:56:31,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2022-11-16 11:56:31,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:31,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:31,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-11-16 11:56:31,468 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-11-16 11:56:31,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:31,469 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-11-16 11:56:31,469 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 11:56:31,470 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2022-11-16 11:56:31,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:31,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:31,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:31,480 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:31,481 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:31,481 INFO L748 eck$LassoCheckResult]: Stem: 46896#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46716#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46432#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46433#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47609#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47610#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46568#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46569#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47027#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46858#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46859#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46635#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46636#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47034#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47211#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47365#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47402#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46648#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46649#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 47822#L1258-2 assume !(0 == ~T1_E~0); 46941#L1263-1 assume !(0 == ~T2_E~0); 46942#L1268-1 assume !(0 == ~T3_E~0); 47245#L1273-1 assume !(0 == ~T4_E~0); 47804#L1278-1 assume !(0 == ~T5_E~0); 47665#L1283-1 assume !(0 == ~T6_E~0); 47666#L1288-1 assume !(0 == ~T7_E~0); 47902#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47890#L1298-1 assume !(0 == ~T9_E~0); 47816#L1303-1 assume !(0 == ~T10_E~0); 46461#L1308-1 assume !(0 == ~T11_E~0); 46403#L1313-1 assume !(0 == ~T12_E~0); 46404#L1318-1 assume !(0 == ~T13_E~0); 46412#L1323-1 assume !(0 == ~E_1~0); 46413#L1328-1 assume !(0 == ~E_2~0); 46578#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47537#L1338-1 assume !(0 == ~E_4~0); 47538#L1343-1 assume !(0 == ~E_5~0); 47639#L1348-1 assume !(0 == ~E_6~0); 47925#L1353-1 assume !(0 == ~E_7~0); 47264#L1358-1 assume !(0 == ~E_8~0); 47265#L1363-1 assume !(0 == ~E_9~0); 47555#L1368-1 assume !(0 == ~E_10~0); 46240#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46241#L1378-1 assume !(0 == ~E_12~0); 46529#L1383-1 assume !(0 == ~E_13~0); 46530#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47271#L607 assume 1 == ~m_pc~0; 47272#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46598#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47637#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47191#L1560 assume !(0 != activate_threads_~tmp~1#1); 47192#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46423#L626 assume !(1 == ~t1_pc~0); 46424#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46692#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46693#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46862#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46325#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46326#L645 assume 1 == ~t2_pc~0; 46440#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46397#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47077#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47078#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47167#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47168#L664 assume 1 == ~t3_pc~0; 47924#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46166#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46167#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46823#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 46824#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47832#L683 assume !(1 == ~t4_pc~0); 47387#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47339#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47340#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47374#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47498#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47121#L702 assume 1 == ~t5_pc~0; 47122#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47044#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47493#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47792#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 47733#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46212#L721 assume !(1 == ~t6_pc~0); 46186#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46187#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46350#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46832#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 46833#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47434#L740 assume 1 == ~t7_pc~0; 46261#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46074#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46075#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46064#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46065#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46769#L759 assume !(1 == ~t8_pc~0); 46770#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46798#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47491#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47492#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47623#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47901#L778 assume 1 == ~t9_pc~0; 47788#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46239#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46179#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46108#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46109#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46437#L797 assume !(1 == ~t10_pc~0); 46438#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46555#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47689#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46939#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 46940#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47229#L816 assume 1 == ~t11_pc~0; 46144#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46145#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46902#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46839#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 46840#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47364#L835 assume 1 == ~t12_pc~0; 47242#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46308#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46330#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46471#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 46996#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46997#L854 assume !(1 == ~t13_pc~0); 46637#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46638#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46688#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46348#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46349#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47728#L1401 assume !(1 == ~M_E~0); 46827#L1401-2 assume !(1 == ~T1_E~0); 46828#L1406-1 assume !(1 == ~T2_E~0); 47423#L1411-1 assume !(1 == ~T3_E~0); 47424#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47090#L1421-1 assume !(1 == ~T5_E~0); 46633#L1426-1 assume !(1 == ~T6_E~0); 46634#L1431-1 assume !(1 == ~T7_E~0); 46182#L1436-1 assume !(1 == ~T8_E~0); 46183#L1441-1 assume !(1 == ~T9_E~0); 46932#L1446-1 assume !(1 == ~T10_E~0); 46933#L1451-1 assume !(1 == ~T11_E~0); 47636#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47290#L1461-1 assume !(1 == ~T13_E~0); 46851#L1466-1 assume !(1 == ~E_1~0); 46852#L1471-1 assume !(1 == ~E_2~0); 47621#L1476-1 assume !(1 == ~E_3~0); 47622#L1481-1 assume !(1 == ~E_4~0); 47770#L1486-1 assume !(1 == ~E_5~0); 46476#L1491-1 assume !(1 == ~E_6~0); 46116#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46117#L1501-1 assume !(1 == ~E_8~0); 46928#L1506-1 assume !(1 == ~E_9~0); 46929#L1511-1 assume !(1 == ~E_10~0); 46885#L1516-1 assume !(1 == ~E_11~0); 46062#L1521-1 assume !(1 == ~E_12~0); 46063#L1526-1 assume !(1 == ~E_13~0); 46115#L1531-1 assume { :end_inline_reset_delta_events } true; 46658#L1892-2 [2022-11-16 11:56:31,482 INFO L750 eck$LassoCheckResult]: Loop: 46658#L1892-2 assume !false; 47681#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47879#L1233 assume !false; 47862#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47194#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47174#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47332#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46158#L1046 assume !(0 != eval_~tmp~0#1); 46160#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46194#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47366#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47923#L1258-5 assume !(0 == ~T1_E~0); 46338#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46339#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47915#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47921#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47922#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46562#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46563#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47678#L1298-3 assume !(0 == ~T9_E~0); 47679#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47838#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47677#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47178#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46340#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46341#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47762#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46481#L1338-3 assume !(0 == ~E_4~0); 46482#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47594#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47768#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47769#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47136#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46694#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46695#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47451#L1378-3 assume !(0 == ~E_12~0); 47452#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47633#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47634#L607-42 assume 1 == ~m_pc~0; 47249#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46975#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46976#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46708#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46709#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47233#L626-42 assume 1 == ~t1_pc~0; 46795#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46796#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47097#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47098#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46372#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46373#L645-42 assume !(1 == ~t2_pc~0); 47572#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47573#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47738#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46579#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46086#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46087#L664-42 assume !(1 == ~t3_pc~0); 46610#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46611#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47865#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47400#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47401#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47566#L683-42 assume !(1 == ~t4_pc~0); 47273#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47274#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47406#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47827#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47828#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47672#L702-42 assume 1 == ~t5_pc~0; 47160#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46784#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47081#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47754#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46100#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46101#L721-42 assume 1 == ~t6_pc~0; 46256#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46276#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46740#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47907#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46912#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46758#L740-42 assume 1 == ~t7_pc~0; 46759#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46496#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47037#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46892#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 46893#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47166#L759-42 assume 1 == ~t8_pc~0; 47015#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46947#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46948#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47025#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47026#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47120#L778-42 assume !(1 == ~t9_pc~0); 46960#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 46961#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47370#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47275#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47276#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47334#L797-42 assume 1 == ~t10_pc~0; 46501#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46502#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47503#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47812#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47372#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47373#L816-42 assume 1 == ~t11_pc~0; 46050#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46051#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46593#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46594#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46673#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46674#L835-42 assume 1 == ~t12_pc~0; 47076#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46968#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46646#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46647#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47731#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47515#L854-42 assume 1 == ~t13_pc~0; 47516#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46590#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46202#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46203#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46849#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46850#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47628#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46436#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46303#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46304#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46903#L1421-3 assume !(1 == ~T5_E~0); 46904#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46479#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46480#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46066#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46067#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47656#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46987#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46640#L1461-3 assume !(1 == ~T13_E~0); 46641#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47918#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46580#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46581#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46981#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46608#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46609#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47020#L1501-3 assume !(1 == ~E_8~0); 47021#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47448#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47438#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47439#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47138#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47139#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47533#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46415#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47308#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46949#L1911 assume !(0 == start_simulation_~tmp~3#1); 46950#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47472#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46539#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47410#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46244#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46245#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46474#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46475#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46658#L1892-2 [2022-11-16 11:56:31,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:31,483 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2022-11-16 11:56:31,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:31,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159435381] [2022-11-16 11:56:31,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:31,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:31,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:31,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:31,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:31,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159435381] [2022-11-16 11:56:31,531 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1159435381] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:31,531 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:31,532 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:31,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160265377] [2022-11-16 11:56:31,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:31,532 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:31,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:31,533 INFO L85 PathProgramCache]: Analyzing trace with hash -199797377, now seen corresponding path program 1 times [2022-11-16 11:56:31,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:31,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197106123] [2022-11-16 11:56:31,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:31,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:31,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:31,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:31,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:31,624 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [197106123] [2022-11-16 11:56:31,624 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [197106123] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:31,625 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:31,625 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:31,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379074728] [2022-11-16 11:56:31,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:31,625 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:31,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:31,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:31,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:31,626 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:31,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:31,664 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-11-16 11:56:31,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2022-11-16 11:56:31,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:31,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-11-16 11:56:31,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 11:56:31,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 11:56:31,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2022-11-16 11:56:31,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:31,688 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-11-16 11:56:31,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2022-11-16 11:56:31,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 11:56:31,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:31,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-11-16 11:56:31,722 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-11-16 11:56:31,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:31,723 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-11-16 11:56:31,723 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 11:56:31,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2022-11-16 11:56:31,732 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 11:56:31,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:31,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:31,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:31,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:31,735 INFO L748 eck$LassoCheckResult]: Stem: 50731#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50732#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50551#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50267#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50268#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51444#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51445#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50403#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50404#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50860#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50693#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50694#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50470#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50471#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50869#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51046#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51200#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51237#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50483#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50484#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51657#L1258-2 assume !(0 == ~T1_E~0); 50776#L1263-1 assume !(0 == ~T2_E~0); 50777#L1268-1 assume !(0 == ~T3_E~0); 51080#L1273-1 assume !(0 == ~T4_E~0); 51639#L1278-1 assume !(0 == ~T5_E~0); 51500#L1283-1 assume !(0 == ~T6_E~0); 51501#L1288-1 assume !(0 == ~T7_E~0); 51737#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51725#L1298-1 assume !(0 == ~T9_E~0); 51651#L1303-1 assume !(0 == ~T10_E~0); 50296#L1308-1 assume !(0 == ~T11_E~0); 50238#L1313-1 assume !(0 == ~T12_E~0); 50239#L1318-1 assume !(0 == ~T13_E~0); 50247#L1323-1 assume !(0 == ~E_1~0); 50248#L1328-1 assume !(0 == ~E_2~0); 50413#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51372#L1338-1 assume !(0 == ~E_4~0); 51373#L1343-1 assume !(0 == ~E_5~0); 51474#L1348-1 assume !(0 == ~E_6~0); 51760#L1353-1 assume !(0 == ~E_7~0); 51099#L1358-1 assume !(0 == ~E_8~0); 51100#L1363-1 assume !(0 == ~E_9~0); 51390#L1368-1 assume !(0 == ~E_10~0); 50075#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50076#L1378-1 assume !(0 == ~E_12~0); 50364#L1383-1 assume !(0 == ~E_13~0); 50365#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51106#L607 assume 1 == ~m_pc~0; 51107#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50433#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51472#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51026#L1560 assume !(0 != activate_threads_~tmp~1#1); 51027#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50258#L626 assume !(1 == ~t1_pc~0); 50259#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50527#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50528#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50697#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50158#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50159#L645 assume 1 == ~t2_pc~0; 50275#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50232#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50912#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50913#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 51002#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51003#L664 assume 1 == ~t3_pc~0; 51759#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49999#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50000#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50658#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50659#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51667#L683 assume !(1 == ~t4_pc~0); 51222#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51174#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51175#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51209#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51333#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50956#L702 assume 1 == ~t5_pc~0; 50957#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50879#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51328#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51627#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51568#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50047#L721 assume !(1 == ~t6_pc~0); 50021#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50022#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50185#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50667#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50668#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51269#L740 assume 1 == ~t7_pc~0; 50096#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49909#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49910#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49899#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49900#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50604#L759 assume !(1 == ~t8_pc~0); 50605#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50633#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51326#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51327#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51458#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51736#L778 assume 1 == ~t9_pc~0; 51623#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50074#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50014#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49943#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49944#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50272#L797 assume !(1 == ~t10_pc~0); 50273#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50390#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51524#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50774#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50775#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51064#L816 assume 1 == ~t11_pc~0; 49979#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49980#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50737#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50674#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50675#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51199#L835 assume 1 == ~t12_pc~0; 51077#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50143#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50165#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50306#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50831#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50832#L854 assume !(1 == ~t13_pc~0); 50472#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50473#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50523#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50183#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50184#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51563#L1401 assume !(1 == ~M_E~0); 50662#L1401-2 assume !(1 == ~T1_E~0); 50663#L1406-1 assume !(1 == ~T2_E~0); 51258#L1411-1 assume !(1 == ~T3_E~0); 51259#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50925#L1421-1 assume !(1 == ~T5_E~0); 50468#L1426-1 assume !(1 == ~T6_E~0); 50469#L1431-1 assume !(1 == ~T7_E~0); 50017#L1436-1 assume !(1 == ~T8_E~0); 50018#L1441-1 assume !(1 == ~T9_E~0); 50767#L1446-1 assume !(1 == ~T10_E~0); 50768#L1451-1 assume !(1 == ~T11_E~0); 51471#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51125#L1461-1 assume !(1 == ~T13_E~0); 50686#L1466-1 assume !(1 == ~E_1~0); 50687#L1471-1 assume !(1 == ~E_2~0); 51456#L1476-1 assume !(1 == ~E_3~0); 51457#L1481-1 assume !(1 == ~E_4~0); 51605#L1486-1 assume !(1 == ~E_5~0); 50311#L1491-1 assume !(1 == ~E_6~0); 49951#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49952#L1501-1 assume !(1 == ~E_8~0); 50763#L1506-1 assume !(1 == ~E_9~0); 50764#L1511-1 assume !(1 == ~E_10~0); 50720#L1516-1 assume !(1 == ~E_11~0); 49895#L1521-1 assume !(1 == ~E_12~0); 49896#L1526-1 assume !(1 == ~E_13~0); 49950#L1531-1 assume { :end_inline_reset_delta_events } true; 50493#L1892-2 [2022-11-16 11:56:31,736 INFO L750 eck$LassoCheckResult]: Loop: 50493#L1892-2 assume !false; 51516#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51714#L1233 assume !false; 51697#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51029#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51009#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51167#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49993#L1046 assume !(0 != eval_~tmp~0#1); 49995#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50029#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51201#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51758#L1258-5 assume !(0 == ~T1_E~0); 50171#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50172#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51750#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51756#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51757#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50397#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50398#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51513#L1298-3 assume !(0 == ~T9_E~0); 51514#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51673#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51512#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51013#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50173#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50174#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51597#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50316#L1338-3 assume !(0 == ~E_4~0); 50317#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51429#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51603#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51604#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50971#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50529#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50530#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51286#L1378-3 assume !(0 == ~E_12~0); 51287#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51468#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51469#L607-42 assume 1 == ~m_pc~0; 51084#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50810#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50811#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50543#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50544#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51068#L626-42 assume 1 == ~t1_pc~0; 50630#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50631#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50932#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50933#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50207#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50208#L645-42 assume 1 == ~t2_pc~0; 51666#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51408#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51573#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50414#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49921#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49922#L664-42 assume !(1 == ~t3_pc~0); 50449#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 50450#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51700#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51235#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51236#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51401#L683-42 assume 1 == ~t4_pc~0; 51766#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51112#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51242#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51662#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51663#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51510#L702-42 assume 1 == ~t5_pc~0; 50998#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50620#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50918#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51589#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49935#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49936#L721-42 assume 1 == ~t6_pc~0; 50090#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50111#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50575#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51742#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50747#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50591#L740-42 assume 1 == ~t7_pc~0; 50592#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50328#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50872#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50727#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 50728#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51001#L759-42 assume 1 == ~t8_pc~0; 50850#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50782#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50783#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50858#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50859#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50955#L778-42 assume 1 == ~t9_pc~0; 50794#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50796#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51204#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51108#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51109#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51169#L797-42 assume 1 == ~t10_pc~0; 50336#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50337#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51338#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51647#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51207#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51208#L816-42 assume 1 == ~t11_pc~0; 49885#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49886#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50428#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50429#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50508#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50509#L835-42 assume !(1 == ~t12_pc~0); 50802#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50803#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50481#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50482#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51566#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51350#L854-42 assume 1 == ~t13_pc~0; 51351#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50425#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50037#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50038#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50684#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50685#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51463#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50271#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50138#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50139#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50738#L1421-3 assume !(1 == ~T5_E~0); 50739#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50314#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50315#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49901#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49902#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51491#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50822#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50475#L1461-3 assume !(1 == ~T13_E~0); 50476#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51753#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50415#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50416#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50816#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50443#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50444#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50855#L1501-3 assume !(1 == ~E_8~0); 50856#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51283#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51272#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51273#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50973#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50974#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51368#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50250#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51143#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50784#L1911 assume !(0 == start_simulation_~tmp~3#1); 50785#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51307#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50374#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51245#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50079#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50080#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50309#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 50310#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50493#L1892-2 [2022-11-16 11:56:31,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:31,737 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2022-11-16 11:56:31,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:31,737 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273132884] [2022-11-16 11:56:31,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:31,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:31,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:31,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:31,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:31,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273132884] [2022-11-16 11:56:31,799 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1273132884] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:31,799 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:31,799 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:56:31,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47127516] [2022-11-16 11:56:31,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:31,800 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:31,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:31,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1807690879, now seen corresponding path program 1 times [2022-11-16 11:56:31,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:31,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229894906] [2022-11-16 11:56:31,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:31,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:31,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:31,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:31,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:31,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229894906] [2022-11-16 11:56:31,861 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [229894906] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:31,862 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:31,862 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:31,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497039075] [2022-11-16 11:56:31,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:31,863 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:31,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:31,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:31,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:31,864 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:32,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:32,033 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-11-16 11:56:32,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2022-11-16 11:56:32,073 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-11-16 11:56:32,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-11-16 11:56:32,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2022-11-16 11:56:32,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2022-11-16 11:56:32,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2022-11-16 11:56:32,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:32,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-11-16 11:56:32,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2022-11-16 11:56:32,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2022-11-16 11:56:32,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:32,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-11-16 11:56:32,169 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-11-16 11:56:32,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:56:32,170 INFO L428 stractBuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-11-16 11:56:32,170 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 11:56:32,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2022-11-16 11:56:32,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-11-16 11:56:32,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:32,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:32,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:32,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:32,189 INFO L748 eck$LassoCheckResult]: Stem: 56211#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56030#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55745#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55746#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 56929#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56930#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55882#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55883#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56338#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56173#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56174#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55949#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55950#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56349#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56530#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56682#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56719#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 55960#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55961#L1258 assume !(0 == ~M_E~0); 57166#L1258-2 assume !(0 == ~T1_E~0); 56256#L1263-1 assume !(0 == ~T2_E~0); 56257#L1268-1 assume !(0 == ~T3_E~0); 56564#L1273-1 assume !(0 == ~T4_E~0); 57145#L1278-1 assume !(0 == ~T5_E~0); 56987#L1283-1 assume !(0 == ~T6_E~0); 56988#L1288-1 assume !(0 == ~T7_E~0); 57269#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57255#L1298-1 assume !(0 == ~T9_E~0); 57160#L1303-1 assume !(0 == ~T10_E~0); 55775#L1308-1 assume !(0 == ~T11_E~0); 55716#L1313-1 assume !(0 == ~T12_E~0); 55717#L1318-1 assume !(0 == ~T13_E~0); 55723#L1323-1 assume !(0 == ~E_1~0); 55724#L1328-1 assume !(0 == ~E_2~0); 55892#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 56856#L1338-1 assume !(0 == ~E_4~0); 56857#L1343-1 assume !(0 == ~E_5~0); 56960#L1348-1 assume !(0 == ~E_6~0); 57302#L1353-1 assume !(0 == ~E_7~0); 56583#L1358-1 assume !(0 == ~E_8~0); 56584#L1363-1 assume !(0 == ~E_9~0); 56875#L1368-1 assume !(0 == ~E_10~0); 55552#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55553#L1378-1 assume !(0 == ~E_12~0); 55841#L1383-1 assume !(0 == ~E_13~0); 55842#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56589#L607 assume !(1 == ~m_pc~0); 55911#L607-2 is_master_triggered_~__retres1~0#1 := 0; 55912#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56958#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56509#L1560 assume !(0 != activate_threads_~tmp~1#1); 56510#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55736#L626 assume !(1 == ~t1_pc~0); 55737#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56006#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56007#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56177#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 55635#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55636#L645 assume 1 == ~t2_pc~0; 55753#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55710#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56389#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56390#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56484#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56485#L664 assume 1 == ~t3_pc~0; 57299#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55475#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55476#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56138#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56139#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57177#L683 assume !(1 == ~t4_pc~0); 56704#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56656#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56657#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56691#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56817#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56432#L702 assume 1 == ~t5_pc~0; 56433#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56358#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56812#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57130#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57062#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55524#L721 assume !(1 == ~t6_pc~0); 55497#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55498#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55662#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56147#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56148#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56752#L740 assume 1 == ~t7_pc~0; 55573#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55385#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55386#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55375#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55376#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56083#L759 assume !(1 == ~t8_pc~0); 56084#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56113#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56810#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56811#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 56943#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57268#L778 assume 1 == ~t9_pc~0; 57127#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55551#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55490#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55419#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55420#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55749#L797 assume !(1 == ~t10_pc~0); 55750#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 55869#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57015#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56254#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56255#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56548#L816 assume 1 == ~t11_pc~0; 55455#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55456#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56215#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56154#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56155#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56681#L835 assume 1 == ~t12_pc~0; 56561#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55620#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55642#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55785#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56311#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56312#L854 assume !(1 == ~t13_pc~0); 55951#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 55952#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56002#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55660#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 55661#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57057#L1401 assume !(1 == ~M_E~0); 56142#L1401-2 assume !(1 == ~T1_E~0); 56143#L1406-1 assume !(1 == ~T2_E~0); 56741#L1411-1 assume !(1 == ~T3_E~0); 56742#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56405#L1421-1 assume !(1 == ~T5_E~0); 55947#L1426-1 assume !(1 == ~T6_E~0); 55948#L1431-1 assume !(1 == ~T7_E~0); 55493#L1436-1 assume !(1 == ~T8_E~0); 55494#L1441-1 assume !(1 == ~T9_E~0); 56245#L1446-1 assume !(1 == ~T10_E~0); 56246#L1451-1 assume !(1 == ~T11_E~0); 56957#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56607#L1461-1 assume !(1 == ~T13_E~0); 56166#L1466-1 assume !(1 == ~E_1~0); 56167#L1471-1 assume !(1 == ~E_2~0); 56941#L1476-1 assume !(1 == ~E_3~0); 56942#L1481-1 assume !(1 == ~E_4~0); 57107#L1486-1 assume !(1 == ~E_5~0); 55790#L1491-1 assume !(1 == ~E_6~0); 55427#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55428#L1501-1 assume !(1 == ~E_8~0); 56243#L1506-1 assume !(1 == ~E_9~0); 56244#L1511-1 assume !(1 == ~E_10~0); 56200#L1516-1 assume !(1 == ~E_11~0); 55371#L1521-1 assume !(1 == ~E_12~0); 55372#L1526-1 assume !(1 == ~E_13~0); 55426#L1531-1 assume { :end_inline_reset_delta_events } true; 55972#L1892-2 [2022-11-16 11:56:32,190 INFO L750 eck$LassoCheckResult]: Loop: 55972#L1892-2 assume !false; 57358#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57240#L1233 assume !false; 57241#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56491#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56649#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55469#L1046 assume !(0 != eval_~tmp~0#1); 55471#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58740#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58739#L1258-3 assume !(0 == ~M_E~0); 58738#L1258-5 assume !(0 == ~T1_E~0); 58737#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58736#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58735#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58734#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58733#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58732#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58731#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58730#L1298-3 assume !(0 == ~T9_E~0); 58729#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58728#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 58727#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 58726#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 58725#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58724#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58442#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58441#L1338-3 assume !(0 == ~E_4~0); 58413#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58412#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58410#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58408#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58405#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 58403#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 58401#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 58399#L1378-3 assume !(0 == ~E_12~0); 58397#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 58395#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58392#L607-42 assume !(1 == ~m_pc~0); 58389#L607-44 is_master_triggered_~__retres1~0#1 := 0; 58387#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58385#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58383#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58381#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58378#L626-42 assume 1 == ~t1_pc~0; 58375#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58373#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58372#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58371#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58370#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58369#L645-42 assume 1 == ~t2_pc~0; 58368#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58366#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58365#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58364#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58363#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58362#L664-42 assume 1 == ~t3_pc~0; 58360#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58359#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58358#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58357#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58356#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58355#L683-42 assume !(1 == ~t4_pc~0); 58350#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 58348#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58345#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58343#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58341#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58339#L702-42 assume 1 == ~t5_pc~0; 58336#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58334#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58333#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58332#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58286#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58285#L721-42 assume !(1 == ~t6_pc~0); 58282#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 58280#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58277#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58275#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58263#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58260#L740-42 assume 1 == ~t7_pc~0; 58257#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58255#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58253#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58251#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 58250#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58249#L759-42 assume 1 == ~t8_pc~0; 58247#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58246#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56517#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56341#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56342#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56437#L778-42 assume 1 == ~t9_pc~0; 56274#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56276#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56688#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56594#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 56595#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58233#L797-42 assume 1 == ~t10_pc~0; 58230#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58228#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58225#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58224#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58223#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58222#L816-42 assume !(1 == ~t11_pc~0); 58220#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 58219#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58218#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58216#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58214#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57883#L835-42 assume 1 == ~t12_pc~0; 57881#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 57065#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55962#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55963#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57061#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56834#L854-42 assume !(1 == ~t13_pc~0); 55905#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 55906#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55514#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55515#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56164#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56165#L1401-3 assume !(1 == ~M_E~0); 56948#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55752#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55615#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55616#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56218#L1421-3 assume !(1 == ~T5_E~0); 56219#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55793#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55794#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 55377#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55378#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 56978#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56302#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55954#L1461-3 assume !(1 == ~T13_E~0); 55955#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57852#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57851#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57850#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57849#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57848#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57220#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56336#L1501-3 assume !(1 == ~E_8~0); 56337#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57846#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57845#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 57844#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 57843#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 57842#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57735#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57728#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57726#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 57724#L1911 assume !(0 == start_simulation_~tmp~3#1); 57098#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56791#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 55853#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56727#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 55556#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55557#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55788#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 55789#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 55972#L1892-2 [2022-11-16 11:56:32,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:32,191 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2022-11-16 11:56:32,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:32,191 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535791408] [2022-11-16 11:56:32,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:32,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:32,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:32,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:32,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:32,277 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535791408] [2022-11-16 11:56:32,277 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535791408] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:32,277 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:32,277 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:32,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1817327478] [2022-11-16 11:56:32,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:32,278 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:32,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:32,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1550267110, now seen corresponding path program 1 times [2022-11-16 11:56:32,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:32,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84999294] [2022-11-16 11:56:32,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:32,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:32,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:32,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:32,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:32,341 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84999294] [2022-11-16 11:56:32,341 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84999294] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:32,341 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:32,341 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:32,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022614685] [2022-11-16 11:56:32,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:32,342 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:32,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:32,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:56:32,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:56:32,343 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:32,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:32,555 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-11-16 11:56:32,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6962 states and 10199 transitions. [2022-11-16 11:56:32,590 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-11-16 11:56:32,613 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-11-16 11:56:32,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6962 [2022-11-16 11:56:32,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6962 [2022-11-16 11:56:32,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6962 states and 10199 transitions. [2022-11-16 11:56:32,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:32,629 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-11-16 11:56:32,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6962 states and 10199 transitions. [2022-11-16 11:56:32,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6962 to 6962. [2022-11-16 11:56:32,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:32,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-11-16 11:56:32,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-11-16 11:56:32,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:56:32,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-11-16 11:56:32,753 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 11:56:32,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6962 states and 10199 transitions. [2022-11-16 11:56:32,781 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-11-16 11:56:32,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:32,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:32,784 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:32,784 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:32,785 INFO L748 eck$LassoCheckResult]: Stem: 66753#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66754#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 66565#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66272#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66273#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 67510#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67511#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66412#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66413#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66882#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66714#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66715#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66481#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66482#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66893#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67081#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67242#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67279#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 66494#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66495#L1258 assume !(0 == ~M_E~0); 67766#L1258-2 assume !(0 == ~T1_E~0); 66799#L1263-1 assume !(0 == ~T2_E~0); 66800#L1268-1 assume !(0 == ~T3_E~0); 67119#L1273-1 assume !(0 == ~T4_E~0); 67744#L1278-1 assume !(0 == ~T5_E~0); 67580#L1283-1 assume !(0 == ~T6_E~0); 67581#L1288-1 assume !(0 == ~T7_E~0); 67871#L1293-1 assume !(0 == ~T8_E~0); 67859#L1298-1 assume !(0 == ~T9_E~0); 67760#L1303-1 assume !(0 == ~T10_E~0); 66303#L1308-1 assume !(0 == ~T11_E~0); 66243#L1313-1 assume !(0 == ~T12_E~0); 66244#L1318-1 assume !(0 == ~T13_E~0); 66250#L1323-1 assume !(0 == ~E_1~0); 66251#L1328-1 assume !(0 == ~E_2~0); 66422#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 67426#L1338-1 assume !(0 == ~E_4~0); 67427#L1343-1 assume !(0 == ~E_5~0); 67550#L1348-1 assume !(0 == ~E_6~0); 67909#L1353-1 assume !(0 == ~E_7~0); 67138#L1358-1 assume !(0 == ~E_8~0); 67139#L1363-1 assume !(0 == ~E_9~0); 67447#L1368-1 assume !(0 == ~E_10~0); 66078#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 66079#L1378-1 assume !(0 == ~E_12~0); 66371#L1383-1 assume !(0 == ~E_13~0); 66372#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67144#L607 assume !(1 == ~m_pc~0); 66442#L607-2 is_master_triggered_~__retres1~0#1 := 0; 66443#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67548#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67058#L1560 assume !(0 != activate_threads_~tmp~1#1); 67059#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66263#L626 assume !(1 == ~t1_pc~0); 66264#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66541#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66542#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66718#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 66162#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66163#L645 assume 1 == ~t2_pc~0; 66281#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66237#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66938#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66939#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 67034#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67035#L664 assume 1 == ~t3_pc~0; 67905#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66003#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66004#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66675#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 66676#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67778#L683 assume !(1 == ~t4_pc~0); 67264#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67215#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67216#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67251#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67382#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66982#L702 assume 1 == ~t5_pc~0; 66983#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66904#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67377#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67732#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 67660#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66050#L721 assume !(1 == ~t6_pc~0); 66025#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66026#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66190#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66684#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 66685#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67317#L740 assume 1 == ~t7_pc~0; 66099#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65912#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65913#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65902#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 65903#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66620#L759 assume !(1 == ~t8_pc~0); 66621#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 66650#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67375#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67376#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 67525#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67870#L778 assume 1 == ~t9_pc~0; 67728#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66077#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66018#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65946#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 65947#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66278#L797 assume !(1 == ~t10_pc~0); 66279#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66399#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67611#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66797#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 66798#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67101#L816 assume 1 == ~t11_pc~0; 65983#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65984#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66759#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66693#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 66694#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67241#L835 assume 1 == ~t12_pc~0; 67115#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66147#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66170#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66314#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 66855#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66856#L854 assume !(1 == ~t13_pc~0); 66483#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 66484#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66536#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66188#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66189#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67656#L1401 assume !(1 == ~M_E~0); 66679#L1401-2 assume !(1 == ~T1_E~0); 66680#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67306#L1411-1 assume !(1 == ~T3_E~0); 67307#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66952#L1421-1 assume !(1 == ~T5_E~0); 66479#L1426-1 assume !(1 == ~T6_E~0); 66480#L1431-1 assume !(1 == ~T7_E~0); 66021#L1436-1 assume !(1 == ~T8_E~0); 66022#L1441-1 assume !(1 == ~T9_E~0); 66788#L1446-1 assume !(1 == ~T10_E~0); 66789#L1451-1 assume !(1 == ~T11_E~0); 67547#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67163#L1461-1 assume !(1 == ~T13_E~0); 66707#L1466-1 assume !(1 == ~E_1~0); 66708#L1471-1 assume !(1 == ~E_2~0); 67942#L1476-1 assume !(1 == ~E_3~0); 67706#L1481-1 assume !(1 == ~E_4~0); 67707#L1486-1 assume !(1 == ~E_5~0); 66319#L1491-1 assume !(1 == ~E_6~0); 65955#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 65956#L1501-1 assume !(1 == ~E_8~0); 66786#L1506-1 assume !(1 == ~E_9~0); 66787#L1511-1 assume !(1 == ~E_10~0); 66741#L1516-1 assume !(1 == ~E_11~0); 66742#L1521-1 assume !(1 == ~E_12~0); 65953#L1526-1 assume !(1 == ~E_13~0); 65954#L1531-1 assume { :end_inline_reset_delta_events } true; 68032#L1892-2 [2022-11-16 11:56:32,786 INFO L750 eck$LassoCheckResult]: Loop: 68032#L1892-2 assume !false; 68026#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68025#L1233 assume !false; 68024#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68009#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67994#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67992#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 67990#L1046 assume !(0 != eval_~tmp~0#1); 67987#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67985#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67982#L1258-3 assume !(0 == ~M_E~0); 67983#L1258-5 assume !(0 == ~T1_E~0); 72769#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67888#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67889#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67897#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67973#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66404#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66405#L1293-3 assume !(0 == ~T8_E~0); 72760#L1298-3 assume !(0 == ~T9_E~0); 72759#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67787#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 67788#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 72755#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 72754#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 72753#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 72752#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72751#L1338-3 assume !(0 == ~E_4~0); 72750#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 72749#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 72748#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 72747#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 72746#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 72745#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 72744#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 72743#L1378-3 assume !(0 == ~E_12~0); 72742#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 72741#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72740#L607-42 assume !(1 == ~m_pc~0); 72738#L607-44 is_master_triggered_~__retres1~0#1 := 0; 72737#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72736#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 72735#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72734#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72733#L626-42 assume 1 == ~t1_pc~0; 72731#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 72730#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72729#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72728#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72727#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72726#L645-42 assume 1 == ~t2_pc~0; 72725#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 72723#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72722#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72721#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65924#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65925#L664-42 assume !(1 == ~t3_pc~0); 66459#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 66460#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67824#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67277#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67278#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67461#L683-42 assume 1 == ~t4_pc~0; 67925#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 67148#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67943#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67772#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67773#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67590#L702-42 assume 1 == ~t5_pc~0; 67027#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66637#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66943#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67688#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65940#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65941#L721-42 assume !(1 == ~t6_pc~0); 66095#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 66114#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66589#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67878#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66769#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66610#L740-42 assume !(1 == ~t7_pc~0); 66339#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 66340#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66898#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66749#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 66750#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67033#L759-42 assume !(1 == ~t8_pc~0); 66875#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 66805#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66806#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66885#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66886#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66987#L778-42 assume 1 == ~t9_pc~0; 67605#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 72459#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72457#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72452#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 72450#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 72448#L797-42 assume 1 == ~t10_pc~0; 72445#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 72443#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67754#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67755#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 67249#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67250#L816-42 assume 1 == ~t11_pc~0; 65888#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65889#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66438#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66439#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66520#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 66521#L835-42 assume 1 == ~t12_pc~0; 66937#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66827#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66492#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66493#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 67659#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 67400#L854-42 assume 1 == ~t13_pc~0; 67401#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 72093#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 71492#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 71491#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 71490#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71482#L1401-3 assume !(1 == ~M_E~0); 71452#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71451#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66277#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 71450#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 71449#L1421-3 assume !(1 == ~T5_E~0); 70959#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70956#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70954#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66455#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69142#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69141#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69139#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69137#L1461-3 assume !(1 == ~T13_E~0); 69135#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69133#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69132#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69131#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69130#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69129#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69128#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69126#L1501-3 assume !(1 == ~E_8~0); 69123#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69121#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 69119#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69117#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69115#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69113#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68666#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68660#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68658#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 68656#L1911 assume !(0 == start_simulation_~tmp~3#1); 68653#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68651#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68627#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68619#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 68612#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68110#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68105#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68043#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 68032#L1892-2 [2022-11-16 11:56:32,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:32,787 INFO L85 PathProgramCache]: Analyzing trace with hash -1259435077, now seen corresponding path program 1 times [2022-11-16 11:56:32,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:32,787 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214652222] [2022-11-16 11:56:32,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:32,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:32,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:32,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:32,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:32,875 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214652222] [2022-11-16 11:56:32,875 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [214652222] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:32,876 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:32,876 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:32,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293509781] [2022-11-16 11:56:32,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:32,876 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:32,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:32,877 INFO L85 PathProgramCache]: Analyzing trace with hash 656341080, now seen corresponding path program 1 times [2022-11-16 11:56:32,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:32,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1377026958] [2022-11-16 11:56:32,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:32,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:32,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:32,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:32,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:32,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1377026958] [2022-11-16 11:56:32,937 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1377026958] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:32,937 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:32,937 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:32,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202898537] [2022-11-16 11:56:32,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:32,938 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:32,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:32,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:56:32,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:56:32,939 INFO L87 Difference]: Start difference. First operand 6962 states and 10199 transitions. cyclomatic complexity: 3239 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:33,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:33,206 INFO L93 Difference]: Finished difference Result 13360 states and 19568 transitions. [2022-11-16 11:56:33,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13360 states and 19568 transitions. [2022-11-16 11:56:33,330 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2022-11-16 11:56:33,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13360 states to 13360 states and 19568 transitions. [2022-11-16 11:56:33,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13360 [2022-11-16 11:56:33,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13360 [2022-11-16 11:56:33,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13360 states and 19568 transitions. [2022-11-16 11:56:33,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:33,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13360 states and 19568 transitions. [2022-11-16 11:56:33,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13360 states and 19568 transitions. [2022-11-16 11:56:33,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13360 to 13356. [2022-11-16 11:56:33,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13356 states, 13356 states have (on average 1.4648098233003894) internal successors, (19564), 13355 states have internal predecessors, (19564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:33,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13356 states to 13356 states and 19564 transitions. [2022-11-16 11:56:33,660 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13356 states and 19564 transitions. [2022-11-16 11:56:33,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:56:33,661 INFO L428 stractBuchiCegarLoop]: Abstraction has 13356 states and 19564 transitions. [2022-11-16 11:56:33,661 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 11:56:33,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13356 states and 19564 transitions. [2022-11-16 11:56:33,711 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2022-11-16 11:56:33,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:33,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:33,714 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:33,714 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:33,714 INFO L748 eck$LassoCheckResult]: Stem: 87092#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 87093#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86899#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86605#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86606#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 87895#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87896#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86743#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86744#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87225#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87049#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87050#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86813#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 86814#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87236#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 87434#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 87601#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 87642#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86824#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86825#L1258 assume !(0 == ~M_E~0); 88179#L1258-2 assume !(0 == ~T1_E~0); 87138#L1263-1 assume !(0 == ~T2_E~0); 87139#L1268-1 assume !(0 == ~T3_E~0); 87468#L1273-1 assume !(0 == ~T4_E~0); 88158#L1278-1 assume !(0 == ~T5_E~0); 87971#L1283-1 assume !(0 == ~T6_E~0); 87972#L1288-1 assume !(0 == ~T7_E~0); 88288#L1293-1 assume !(0 == ~T8_E~0); 88271#L1298-1 assume !(0 == ~T9_E~0); 88171#L1303-1 assume !(0 == ~T10_E~0); 86635#L1308-1 assume !(0 == ~T11_E~0); 86576#L1313-1 assume !(0 == ~T12_E~0); 86577#L1318-1 assume !(0 == ~T13_E~0); 86583#L1323-1 assume !(0 == ~E_1~0); 86584#L1328-1 assume !(0 == ~E_2~0); 86753#L1333-1 assume !(0 == ~E_3~0); 87802#L1338-1 assume !(0 == ~E_4~0); 87803#L1343-1 assume !(0 == ~E_5~0); 87936#L1348-1 assume !(0 == ~E_6~0); 88334#L1353-1 assume !(0 == ~E_7~0); 87489#L1358-1 assume !(0 == ~E_8~0); 87490#L1363-1 assume !(0 == ~E_9~0); 87827#L1368-1 assume !(0 == ~E_10~0); 86410#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 86411#L1378-1 assume !(0 == ~E_12~0); 86702#L1383-1 assume !(0 == ~E_13~0); 86703#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87495#L607 assume !(1 == ~m_pc~0); 86773#L607-2 is_master_triggered_~__retres1~0#1 := 0; 86774#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87934#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87407#L1560 assume !(0 != activate_threads_~tmp~1#1); 87408#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86596#L626 assume !(1 == ~t1_pc~0); 86597#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86873#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86874#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87053#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 86496#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86497#L645 assume 1 == ~t2_pc~0; 86614#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86570#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87282#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87283#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 87380#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87381#L664 assume 1 == ~t3_pc~0; 88328#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86335#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86336#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87014#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 87015#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88194#L683 assume !(1 == ~t4_pc~0); 87625#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 87571#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87572#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87612#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87752#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87326#L702 assume 1 == ~t5_pc~0; 87327#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87247#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87746#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88141#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 88051#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86382#L721 assume !(1 == ~t6_pc~0); 86357#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86358#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86523#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87023#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 87024#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87679#L740 assume 1 == ~t7_pc~0; 86431#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86244#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86245#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86234#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 86235#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86958#L759 assume !(1 == ~t8_pc~0); 86959#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 86989#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87744#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87745#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 87909#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88287#L778 assume 1 == ~t9_pc~0; 88138#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86409#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86350#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86278#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 86279#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86609#L797 assume !(1 == ~t10_pc~0); 86610#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86730#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87999#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87136#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 87137#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87452#L816 assume 1 == ~t11_pc~0; 86315#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86316#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87096#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87030#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 87031#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87600#L835 assume 1 == ~t12_pc~0; 87465#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 86481#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86503#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86645#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 87197#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87198#L854 assume !(1 == ~t13_pc~0); 86815#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 86816#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86869#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86521#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86522#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88046#L1401 assume !(1 == ~M_E~0); 87018#L1401-2 assume !(1 == ~T1_E~0); 87019#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88054#L1411-1 assume !(1 == ~T3_E~0); 88314#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88315#L1421-1 assume !(1 == ~T5_E~0); 86811#L1426-1 assume !(1 == ~T6_E~0); 86812#L1431-1 assume !(1 == ~T7_E~0); 86353#L1436-1 assume !(1 == ~T8_E~0); 86354#L1441-1 assume !(1 == ~T9_E~0); 96903#L1446-1 assume !(1 == ~T10_E~0); 96901#L1451-1 assume !(1 == ~T11_E~0); 96900#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 87515#L1461-1 assume !(1 == ~T13_E~0); 87516#L1466-1 assume !(1 == ~E_1~0); 88385#L1471-1 assume !(1 == ~E_2~0); 87907#L1476-1 assume !(1 == ~E_3~0); 87908#L1481-1 assume !(1 == ~E_4~0); 88110#L1486-1 assume !(1 == ~E_5~0); 86650#L1491-1 assume !(1 == ~E_6~0); 86286#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 86287#L1501-1 assume !(1 == ~E_8~0); 87125#L1506-1 assume !(1 == ~E_9~0); 87126#L1511-1 assume !(1 == ~E_10~0); 87080#L1516-1 assume !(1 == ~E_11~0); 86230#L1521-1 assume !(1 == ~E_12~0); 86231#L1526-1 assume !(1 == ~E_13~0); 86285#L1531-1 assume { :end_inline_reset_delta_events } true; 86836#L1892-2 [2022-11-16 11:56:33,715 INFO L750 eck$LassoCheckResult]: Loop: 86836#L1892-2 assume !false; 87989#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88255#L1233 assume !false; 88234#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 87410#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 87388#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98195#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 98192#L1046 assume !(0 != eval_~tmp~0#1); 98190#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98189#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98188#L1258-3 assume !(0 == ~M_E~0); 98187#L1258-5 assume !(0 == ~T1_E~0); 96042#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 96043#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 96603#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96597#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96595#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 96593#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 96577#L1293-3 assume !(0 == ~T8_E~0); 96574#L1298-3 assume !(0 == ~T9_E~0); 96571#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 96567#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 96564#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 96561#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 96557#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96554#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 96551#L1333-3 assume !(0 == ~E_3~0); 96548#L1338-3 assume !(0 == ~E_4~0); 96543#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96538#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 96533#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 96530#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 96319#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 96316#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 96314#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 96312#L1378-3 assume !(0 == ~E_12~0); 96310#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 96308#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96306#L607-42 assume !(1 == ~m_pc~0); 96302#L607-44 is_master_triggered_~__retres1~0#1 := 0; 96300#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96298#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96296#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96294#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96292#L626-42 assume 1 == ~t1_pc~0; 96269#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 96266#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96264#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96262#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96260#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96258#L645-42 assume 1 == ~t2_pc~0; 96255#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 96250#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96247#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96244#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 96241#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96238#L664-42 assume !(1 == ~t3_pc~0); 96235#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 96230#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88237#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88238#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 96213#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96210#L683-42 assume !(1 == ~t4_pc~0); 96205#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 96201#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96198#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96195#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96192#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96189#L702-42 assume !(1 == ~t5_pc~0); 96185#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 96176#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96175#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96170#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 96100#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96097#L721-42 assume 1 == ~t6_pc~0; 96095#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 96092#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96090#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96088#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96085#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96083#L740-42 assume !(1 == ~t7_pc~0); 96081#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 96078#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96076#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96075#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 96073#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96071#L759-42 assume 1 == ~t8_pc~0; 87216#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 87217#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96068#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87228#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 87229#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87331#L778-42 assume 1 == ~t9_pc~0; 87159#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87161#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96056#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96054#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 88316#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88317#L797-42 assume 1 == ~t10_pc~0; 86676#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 86677#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 90842#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 90841#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 90839#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 90836#L816-42 assume !(1 == ~t11_pc~0); 90833#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 90831#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 90829#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 90827#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 90825#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 90822#L835-42 assume 1 == ~t12_pc~0; 90819#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 90817#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 90815#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 90813#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 90811#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 90808#L854-42 assume !(1 == ~t13_pc~0); 90805#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 90803#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 90801#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 90799#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 90798#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90797#L1401-3 assume !(1 == ~M_E~0); 90794#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 90792#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86613#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90789#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90787#L1421-3 assume !(1 == ~T5_E~0); 90785#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 90783#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 90781#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86786#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 90778#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 90777#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 90776#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 90775#L1461-3 assume !(1 == ~T13_E~0); 90774#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 90773#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 90772#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 90771#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90770#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 90769#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 90768#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 90767#L1501-3 assume !(1 == ~E_8~0); 90766#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 90765#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 90764#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 90763#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 90761#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 90759#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 90748#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 90729#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 90727#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 90723#L1911 assume !(0 == start_simulation_~tmp~3#1); 88098#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 87724#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86714#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 87650#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 86414#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86415#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86648#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 86649#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 86836#L1892-2 [2022-11-16 11:56:33,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:33,716 INFO L85 PathProgramCache]: Analyzing trace with hash -312397191, now seen corresponding path program 1 times [2022-11-16 11:56:33,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:33,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299414078] [2022-11-16 11:56:33,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:33,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:33,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:33,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:33,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:33,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299414078] [2022-11-16 11:56:33,791 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299414078] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:33,791 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:33,791 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:33,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866803674] [2022-11-16 11:56:33,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:33,792 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:33,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:33,792 INFO L85 PathProgramCache]: Analyzing trace with hash 908171284, now seen corresponding path program 1 times [2022-11-16 11:56:33,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:33,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163199913] [2022-11-16 11:56:33,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:33,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:33,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:33,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:33,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:33,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163199913] [2022-11-16 11:56:33,966 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163199913] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:33,966 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:33,967 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:33,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673146885] [2022-11-16 11:56:33,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:33,967 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:33,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:33,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:56:33,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:56:33,968 INFO L87 Difference]: Start difference. First operand 13356 states and 19564 transitions. cyclomatic complexity: 6212 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:34,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:34,310 INFO L93 Difference]: Finished difference Result 25712 states and 37649 transitions. [2022-11-16 11:56:34,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25712 states and 37649 transitions. [2022-11-16 11:56:34,469 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2022-11-16 11:56:34,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25712 states to 25712 states and 37649 transitions. [2022-11-16 11:56:34,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25712 [2022-11-16 11:56:34,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25712 [2022-11-16 11:56:34,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25712 states and 37649 transitions. [2022-11-16 11:56:34,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:34,639 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25712 states and 37649 transitions. [2022-11-16 11:56:34,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25712 states and 37649 transitions. [2022-11-16 11:56:35,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25712 to 25704. [2022-11-16 11:56:35,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25704 states, 25704 states have (on average 1.4644024276377217) internal successors, (37641), 25703 states have internal predecessors, (37641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:35,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25704 states to 25704 states and 37641 transitions. [2022-11-16 11:56:35,297 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25704 states and 37641 transitions. [2022-11-16 11:56:35,297 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:56:35,298 INFO L428 stractBuchiCegarLoop]: Abstraction has 25704 states and 37641 transitions. [2022-11-16 11:56:35,298 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 11:56:35,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25704 states and 37641 transitions. [2022-11-16 11:56:35,386 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2022-11-16 11:56:35,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:35,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:35,389 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:35,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:35,389 INFO L748 eck$LassoCheckResult]: Stem: 126161#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 126162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 125970#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125682#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125683#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 126938#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126939#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125819#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125820#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126292#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 126120#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126121#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 125886#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 125887#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 126303#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 126498#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 126661#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 126701#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 125897#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125898#L1258 assume !(0 == ~M_E~0); 127211#L1258-2 assume !(0 == ~T1_E~0); 126208#L1263-1 assume !(0 == ~T2_E~0); 126209#L1268-1 assume !(0 == ~T3_E~0); 126532#L1273-1 assume !(0 == ~T4_E~0); 127188#L1278-1 assume !(0 == ~T5_E~0); 127011#L1283-1 assume !(0 == ~T6_E~0); 127012#L1288-1 assume !(0 == ~T7_E~0); 127314#L1293-1 assume !(0 == ~T8_E~0); 127301#L1298-1 assume !(0 == ~T9_E~0); 127202#L1303-1 assume !(0 == ~T10_E~0); 125711#L1308-1 assume !(0 == ~T11_E~0); 125653#L1313-1 assume !(0 == ~T12_E~0); 125654#L1318-1 assume !(0 == ~T13_E~0); 125660#L1323-1 assume !(0 == ~E_1~0); 125661#L1328-1 assume !(0 == ~E_2~0); 125829#L1333-1 assume !(0 == ~E_3~0); 126853#L1338-1 assume !(0 == ~E_4~0); 126854#L1343-1 assume !(0 == ~E_5~0); 126980#L1348-1 assume !(0 == ~E_6~0); 127357#L1353-1 assume !(0 == ~E_7~0); 126553#L1358-1 assume !(0 == ~E_8~0); 126554#L1363-1 assume !(0 == ~E_9~0); 126874#L1368-1 assume !(0 == ~E_10~0); 125490#L1373-1 assume !(0 == ~E_11~0); 125491#L1378-1 assume !(0 == ~E_12~0); 125778#L1383-1 assume !(0 == ~E_13~0); 125779#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126559#L607 assume !(1 == ~m_pc~0); 125848#L607-2 is_master_triggered_~__retres1~0#1 := 0; 125849#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126978#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 126472#L1560 assume !(0 != activate_threads_~tmp~1#1); 126473#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125673#L626 assume !(1 == ~t1_pc~0); 125674#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 125946#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125947#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126124#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 125573#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125574#L645 assume 1 == ~t2_pc~0; 125690#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 125647#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126344#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126345#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 126447#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126448#L664 assume 1 == ~t3_pc~0; 127350#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125413#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125414#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126085#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 126086#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127221#L683 assume !(1 == ~t4_pc~0); 126685#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126632#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126633#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126672#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126809#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126391#L702 assume 1 == ~t5_pc~0; 126392#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126312#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126804#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 127170#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 127094#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125462#L721 assume !(1 == ~t6_pc~0); 125435#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 125436#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125600#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 126094#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 126095#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 126739#L740 assume 1 == ~t7_pc~0; 125511#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125322#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125323#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125312#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 125313#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 126030#L759 assume !(1 == ~t8_pc~0); 126031#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 126060#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 126802#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 126803#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 126953#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 127313#L778 assume 1 == ~t9_pc~0; 127167#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 125489#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125428#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125356#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 125357#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125686#L797 assume !(1 == ~t10_pc~0); 125687#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 125806#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127039#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126206#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 126207#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 126516#L816 assume 1 == ~t11_pc~0; 125393#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 125394#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126165#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126101#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 126102#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 126660#L835 assume 1 == ~t12_pc~0; 126529#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125558#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125580#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125722#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 126265#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 126266#L854 assume !(1 == ~t13_pc~0); 125888#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 125889#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125942#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125598#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 125599#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127090#L1401 assume !(1 == ~M_E~0); 126089#L1401-2 assume !(1 == ~T1_E~0); 126090#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 127097#L1411-1 assume !(1 == ~T3_E~0); 136973#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 136971#L1421-1 assume !(1 == ~T5_E~0); 125884#L1426-1 assume !(1 == ~T6_E~0); 125885#L1431-1 assume !(1 == ~T7_E~0); 125431#L1436-1 assume !(1 == ~T8_E~0); 125432#L1441-1 assume !(1 == ~T9_E~0); 126580#L1446-1 assume !(1 == ~T10_E~0); 129225#L1451-1 assume !(1 == ~T11_E~0); 129223#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 126578#L1461-1 assume !(1 == ~T13_E~0); 126579#L1466-1 assume !(1 == ~E_1~0); 127387#L1471-1 assume !(1 == ~E_2~0); 127388#L1476-1 assume !(1 == ~E_3~0); 129216#L1481-1 assume !(1 == ~E_4~0); 129214#L1486-1 assume !(1 == ~E_5~0); 129212#L1491-1 assume !(1 == ~E_6~0); 129210#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 129207#L1501-1 assume !(1 == ~E_8~0); 129067#L1506-1 assume !(1 == ~E_9~0); 129062#L1511-1 assume !(1 == ~E_10~0); 129052#L1516-1 assume !(1 == ~E_11~0); 129046#L1521-1 assume !(1 == ~E_12~0); 129044#L1526-1 assume !(1 == ~E_13~0); 129042#L1531-1 assume { :end_inline_reset_delta_events } true; 129040#L1892-2 [2022-11-16 11:56:35,390 INFO L750 eck$LassoCheckResult]: Loop: 129040#L1892-2 assume !false; 129035#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129034#L1233 assume !false; 129033#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 129018#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 129003#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 129001#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 128998#L1046 assume !(0 != eval_~tmp~0#1); 128995#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 128993#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 128991#L1258-3 assume !(0 == ~M_E~0); 128988#L1258-5 assume !(0 == ~T1_E~0); 128986#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 128987#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 150267#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 150266#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 150265#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 150264#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 150263#L1293-3 assume !(0 == ~T8_E~0); 150262#L1298-3 assume !(0 == ~T9_E~0); 150261#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 150260#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 150259#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 150258#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 150257#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 150256#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 150255#L1333-3 assume !(0 == ~E_3~0); 150254#L1338-3 assume !(0 == ~E_4~0); 150253#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 150252#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 150251#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 150250#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 150249#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 150248#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 150247#L1373-3 assume !(0 == ~E_11~0); 150246#L1378-3 assume !(0 == ~E_12~0); 150245#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 150244#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150243#L607-42 assume !(1 == ~m_pc~0); 150241#L607-44 is_master_triggered_~__retres1~0#1 := 0; 150240#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150239#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 150238#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 150237#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 150236#L626-42 assume 1 == ~t1_pc~0; 150234#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 150233#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150232#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 150231#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 150230#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 150229#L645-42 assume !(1 == ~t2_pc~0); 150227#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 150226#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 150225#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 150224#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 150223#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150222#L664-42 assume 1 == ~t3_pc~0; 150220#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 150219#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 150218#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 150217#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 150216#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 150215#L683-42 assume 1 == ~t4_pc~0; 150214#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 150212#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 150211#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 150210#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 150209#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 150208#L702-42 assume 1 == ~t5_pc~0; 150206#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 150205#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 150204#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 150203#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 150202#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 150201#L721-42 assume !(1 == ~t6_pc~0); 150199#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 150197#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 150194#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 150193#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 150192#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 150191#L740-42 assume !(1 == ~t7_pc~0); 150190#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 150188#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 150187#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 150186#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 150185#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 150184#L759-42 assume 1 == ~t8_pc~0; 150182#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 150181#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 150180#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 150179#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 150178#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 150177#L778-42 assume !(1 == ~t9_pc~0); 150156#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 150154#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 150152#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 150151#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 150150#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 150147#L797-42 assume 1 == ~t10_pc~0; 150144#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 150142#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 150140#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 147326#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 147325#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 128907#L816-42 assume !(1 == ~t11_pc~0); 128905#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 128904#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128903#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126202#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 126203#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 128902#L835-42 assume !(1 == ~t12_pc~0); 128901#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 127100#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125899#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125900#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 127093#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 126829#L854-42 assume !(1 == ~t13_pc~0); 125842#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 125843#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125452#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125453#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 126111#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126112#L1401-3 assume !(1 == ~M_E~0); 126962#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 125689#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 125553#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 125554#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 126168#L1421-3 assume !(1 == ~T5_E~0); 126169#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 125730#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 125731#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 125314#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 125315#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 126999#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 127000#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 128692#L1461-3 assume !(1 == ~T13_E~0); 128691#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 128690#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 128689#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 128687#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 128688#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 147246#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 147243#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 147241#L1501-3 assume !(1 == ~E_8~0); 147239#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 147237#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 147235#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 138368#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 147231#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 147229#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 147201#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 147196#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 127712#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 127713#L1911 assume !(0 == start_simulation_~tmp~3#1); 129475#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 129437#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 129068#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 129053#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 129047#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 129045#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129043#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 129041#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 129040#L1892-2 [2022-11-16 11:56:35,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:35,391 INFO L85 PathProgramCache]: Analyzing trace with hash -645040329, now seen corresponding path program 1 times [2022-11-16 11:56:35,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:35,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756369940] [2022-11-16 11:56:35,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:35,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:35,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:35,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:35,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:35,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1756369940] [2022-11-16 11:56:35,610 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1756369940] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:35,611 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:35,611 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:35,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385801195] [2022-11-16 11:56:35,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:35,611 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:35,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:35,612 INFO L85 PathProgramCache]: Analyzing trace with hash -1152820431, now seen corresponding path program 1 times [2022-11-16 11:56:35,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:35,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715156010] [2022-11-16 11:56:35,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:35,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:35,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:35,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:35,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:35,685 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715156010] [2022-11-16 11:56:35,685 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715156010] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:35,685 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:35,686 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:35,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647239233] [2022-11-16 11:56:35,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:35,687 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:35,687 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:35,687 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:56:35,687 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:56:35,687 INFO L87 Difference]: Start difference. First operand 25704 states and 37641 transitions. cyclomatic complexity: 11945 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:36,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:36,399 INFO L93 Difference]: Finished difference Result 74990 states and 108892 transitions. [2022-11-16 11:56:36,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74990 states and 108892 transitions. [2022-11-16 11:56:36,727 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 73032 [2022-11-16 11:56:37,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74990 states to 74990 states and 108892 transitions. [2022-11-16 11:56:37,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74990 [2022-11-16 11:56:37,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74990 [2022-11-16 11:56:37,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74990 states and 108892 transitions. [2022-11-16 11:56:37,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:37,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74990 states and 108892 transitions. [2022-11-16 11:56:37,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74990 states and 108892 transitions. [2022-11-16 11:56:38,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74990 to 72678. [2022-11-16 11:56:38,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72678 states, 72678 states have (on average 1.454140179971931) internal successors, (105684), 72677 states have internal predecessors, (105684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:38,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72678 states to 72678 states and 105684 transitions. [2022-11-16 11:56:38,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72678 states and 105684 transitions. [2022-11-16 11:56:38,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:56:38,708 INFO L428 stractBuchiCegarLoop]: Abstraction has 72678 states and 105684 transitions. [2022-11-16 11:56:38,709 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 11:56:38,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72678 states and 105684 transitions. [2022-11-16 11:56:38,944 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 72352 [2022-11-16 11:56:38,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:38,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:38,949 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:38,950 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:38,950 INFO L748 eck$LassoCheckResult]: Stem: 226853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 226854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 226672#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 226386#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 226387#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 227614#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 227615#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 226524#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 226525#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 226983#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 226815#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 226816#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 226591#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 226592#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 226994#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 227175#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 227336#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 227375#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 226602#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 226603#L1258 assume !(0 == ~M_E~0); 227859#L1258-2 assume !(0 == ~T1_E~0); 226899#L1263-1 assume !(0 == ~T2_E~0); 226900#L1268-1 assume !(0 == ~T3_E~0); 227210#L1273-1 assume !(0 == ~T4_E~0); 227838#L1278-1 assume !(0 == ~T5_E~0); 227677#L1283-1 assume !(0 == ~T6_E~0); 227678#L1288-1 assume !(0 == ~T7_E~0); 227970#L1293-1 assume !(0 == ~T8_E~0); 227953#L1298-1 assume !(0 == ~T9_E~0); 227853#L1303-1 assume !(0 == ~T10_E~0); 226414#L1308-1 assume !(0 == ~T11_E~0); 226357#L1313-1 assume !(0 == ~T12_E~0); 226358#L1318-1 assume !(0 == ~T13_E~0); 226364#L1323-1 assume !(0 == ~E_1~0); 226365#L1328-1 assume !(0 == ~E_2~0); 226534#L1333-1 assume !(0 == ~E_3~0); 227528#L1338-1 assume !(0 == ~E_4~0); 227529#L1343-1 assume !(0 == ~E_5~0); 227649#L1348-1 assume !(0 == ~E_6~0); 228008#L1353-1 assume !(0 == ~E_7~0); 227229#L1358-1 assume !(0 == ~E_8~0); 227230#L1363-1 assume !(0 == ~E_9~0); 227551#L1368-1 assume !(0 == ~E_10~0); 226194#L1373-1 assume !(0 == ~E_11~0); 226195#L1378-1 assume !(0 == ~E_12~0); 226482#L1383-1 assume !(0 == ~E_13~0); 226483#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227236#L607 assume !(1 == ~m_pc~0); 226553#L607-2 is_master_triggered_~__retres1~0#1 := 0; 226554#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227647#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 227155#L1560 assume !(0 != activate_threads_~tmp~1#1); 227156#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226377#L626 assume !(1 == ~t1_pc~0); 226378#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 226648#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 226649#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 226819#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 226277#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226278#L645 assume !(1 == ~t2_pc~0); 226350#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 226351#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227035#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 227036#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 227130#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 227131#L664 assume 1 == ~t3_pc~0; 228003#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 226117#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 226118#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 226780#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 226781#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227874#L683 assume !(1 == ~t4_pc~0); 227360#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 227309#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 227310#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 227345#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 227485#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227078#L702 assume 1 == ~t5_pc~0; 227079#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 227004#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227480#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 227822#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 227750#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226166#L721 assume !(1 == ~t6_pc~0); 226139#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 226140#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226304#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 226789#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 226790#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 227410#L740 assume 1 == ~t7_pc~0; 226215#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226026#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 226027#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 226016#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 226017#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 226724#L759 assume !(1 == ~t8_pc~0); 226725#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 226755#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 227478#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 227479#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 227629#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 227969#L778 assume 1 == ~t9_pc~0; 227820#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 226193#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 226132#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 226060#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 226061#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 226390#L797 assume !(1 == ~t10_pc~0); 226391#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 226511#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227702#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 226897#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 226898#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227194#L816 assume 1 == ~t11_pc~0; 226097#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 226098#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 226857#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 226796#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 226797#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 227335#L835 assume 1 == ~t12_pc~0; 227207#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 226262#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 226284#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 226424#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 226955#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 226956#L854 assume !(1 == ~t13_pc~0); 226593#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 226594#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 226644#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 226302#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 226303#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227745#L1401 assume !(1 == ~M_E~0); 226784#L1401-2 assume !(1 == ~T1_E~0); 226785#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 227399#L1411-1 assume !(1 == ~T3_E~0); 227400#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 227051#L1421-1 assume !(1 == ~T5_E~0); 226589#L1426-1 assume !(1 == ~T6_E~0); 226590#L1431-1 assume !(1 == ~T7_E~0); 226135#L1436-1 assume !(1 == ~T8_E~0); 226136#L1441-1 assume !(1 == ~T9_E~0); 226888#L1446-1 assume !(1 == ~T10_E~0); 226889#L1451-1 assume !(1 == ~T11_E~0); 227646#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 227254#L1461-1 assume !(1 == ~T13_E~0); 226809#L1466-1 assume !(1 == ~E_1~0); 226810#L1471-1 assume !(1 == ~E_2~0); 227627#L1476-1 assume !(1 == ~E_3~0); 227628#L1481-1 assume !(1 == ~E_4~0); 288205#L1486-1 assume !(1 == ~E_5~0); 288204#L1491-1 assume !(1 == ~E_6~0); 226069#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 226070#L1501-1 assume !(1 == ~E_8~0); 227270#L1506-1 assume !(1 == ~E_9~0); 288196#L1511-1 assume !(1 == ~E_10~0); 288194#L1516-1 assume !(1 == ~E_11~0); 226842#L1521-1 assume !(1 == ~E_12~0); 226067#L1526-1 assume !(1 == ~E_13~0); 226068#L1531-1 assume { :end_inline_reset_delta_events } true; 226614#L1892-2 [2022-11-16 11:56:38,951 INFO L750 eck$LassoCheckResult]: Loop: 226614#L1892-2 assume !false; 296542#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 296541#L1233 assume !false; 296540#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 227158#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 227137#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 227300#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 226111#L1046 assume !(0 != eval_~tmp~0#1); 226113#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 296523#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 228001#L1258-3 assume !(0 == ~M_E~0); 228002#L1258-5 assume !(0 == ~T1_E~0); 297081#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 297080#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 297079#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 297078#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 297077#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 297076#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 297075#L1293-3 assume !(0 == ~T8_E~0); 297074#L1298-3 assume !(0 == ~T9_E~0); 228021#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 227886#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 227688#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 227141#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 226292#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 226293#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 227789#L1333-3 assume !(0 == ~E_3~0); 226435#L1338-3 assume !(0 == ~E_4~0); 226436#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 227598#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 227796#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 227797#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 227095#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 226650#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 226651#L1373-3 assume !(0 == ~E_11~0); 227430#L1378-3 assume !(0 == ~E_12~0); 227431#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 227643#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227644#L607-42 assume !(1 == ~m_pc~0); 227461#L607-44 is_master_triggered_~__retres1~0#1 := 0; 226934#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 226935#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 226664#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 226665#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 227195#L626-42 assume !(1 == ~t1_pc~0); 226751#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 226750#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 227058#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 227059#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 226326#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226327#L645-42 assume !(1 == ~t2_pc~0); 227570#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 227571#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227760#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 226535#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 226038#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 226039#L664-42 assume !(1 == ~t3_pc~0); 226569#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 226570#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 227918#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 227373#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 227374#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227562#L683-42 assume !(1 == ~t4_pc~0); 227238#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 227239#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 227381#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 227866#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 227867#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227683#L702-42 assume 1 == ~t5_pc~0; 227121#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 226742#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227042#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 227781#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 226054#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226055#L721-42 assume !(1 == ~t6_pc~0); 226211#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 226230#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226695#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 227981#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 226869#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 226714#L740-42 assume !(1 == ~t7_pc~0); 226450#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 226451#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 226998#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 226849#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 226850#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 227129#L759-42 assume !(1 == ~t8_pc~0); 226976#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 226905#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 226906#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 226986#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 226987#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 227083#L778-42 assume !(1 == ~t9_pc~0); 226919#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 226920#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 227342#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 227240#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 227241#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 227302#L797-42 assume !(1 == ~t10_pc~0); 226458#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 226457#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227490#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 227848#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 227343#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227344#L816-42 assume 1 == ~t11_pc~0; 226002#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 226003#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 226549#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 226550#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 226629#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 226630#L835-42 assume !(1 == ~t12_pc~0); 226929#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 226930#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 226604#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 226605#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 227749#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 227504#L854-42 assume !(1 == ~t13_pc~0); 226547#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 226548#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 226157#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 226158#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 226807#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 226808#L1401-3 assume !(1 == ~M_E~0); 228069#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 296889#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 253636#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 296888#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 296887#L1421-3 assume !(1 == ~T5_E~0); 296886#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 296885#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 296884#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 283058#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 296883#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 296882#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 296881#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 296879#L1461-3 assume !(1 == ~T13_E~0); 296877#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 296875#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 296873#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 266942#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 226940#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 226564#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 226565#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 226981#L1501-3 assume !(1 == ~E_8~0); 226982#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 227426#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 227427#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 290472#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 296856#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 296853#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 228067#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 226369#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 227275#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 226907#L1911 assume !(0 == start_simulation_~tmp~3#1); 226908#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 227790#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 296555#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 296554#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 296553#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 296552#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 296551#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 296549#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 226614#L1892-2 [2022-11-16 11:56:38,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:38,952 INFO L85 PathProgramCache]: Analyzing trace with hash -1648097194, now seen corresponding path program 1 times [2022-11-16 11:56:38,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:38,952 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843814164] [2022-11-16 11:56:38,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:38,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:38,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:39,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:39,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:39,200 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843814164] [2022-11-16 11:56:39,200 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843814164] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:39,200 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:39,201 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:39,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921678633] [2022-11-16 11:56:39,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:39,202 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:39,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:39,203 INFO L85 PathProgramCache]: Analyzing trace with hash -786125715, now seen corresponding path program 1 times [2022-11-16 11:56:39,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:39,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290048936] [2022-11-16 11:56:39,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:39,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:39,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:39,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:39,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:39,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290048936] [2022-11-16 11:56:39,289 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290048936] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:39,290 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:39,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:39,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144958039] [2022-11-16 11:56:39,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:39,291 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:39,292 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:39,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:56:39,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:56:39,293 INFO L87 Difference]: Start difference. First operand 72678 states and 105684 transitions. cyclomatic complexity: 33022 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:40,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:40,550 INFO L93 Difference]: Finished difference Result 210029 states and 303417 transitions. [2022-11-16 11:56:40,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 210029 states and 303417 transitions. [2022-11-16 11:56:41,698 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 206072 [2022-11-16 11:56:42,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 210029 states to 210029 states and 303417 transitions. [2022-11-16 11:56:42,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 210029 [2022-11-16 11:56:42,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 210029 [2022-11-16 11:56:42,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210029 states and 303417 transitions. [2022-11-16 11:56:42,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:42,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 210029 states and 303417 transitions. [2022-11-16 11:56:43,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210029 states and 303417 transitions. [2022-11-16 11:56:44,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210029 to 202813. [2022-11-16 11:56:45,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 202813 states, 202813 states have (on average 1.4468944298442408) internal successors, (293449), 202812 states have internal predecessors, (293449), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:46,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202813 states to 202813 states and 293449 transitions. [2022-11-16 11:56:46,165 INFO L240 hiAutomatonCegarLoop]: Abstraction has 202813 states and 293449 transitions. [2022-11-16 11:56:46,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:56:46,171 INFO L428 stractBuchiCegarLoop]: Abstraction has 202813 states and 293449 transitions. [2022-11-16 11:56:46,172 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 11:56:46,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 202813 states and 293449 transitions. [2022-11-16 11:56:46,733 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 202328 [2022-11-16 11:56:46,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:46,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:46,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:46,743 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:46,743 INFO L748 eck$LassoCheckResult]: Stem: 509578#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 509579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 509389#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 509100#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 509101#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 510357#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 510358#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 509238#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 509239#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 509709#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 509537#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 509538#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 509307#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 509308#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 509720#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 509906#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 510067#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 510105#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 509318#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 509319#L1258 assume !(0 == ~M_E~0); 510607#L1258-2 assume !(0 == ~T1_E~0); 509623#L1263-1 assume !(0 == ~T2_E~0); 509624#L1268-1 assume !(0 == ~T3_E~0); 509940#L1273-1 assume !(0 == ~T4_E~0); 510586#L1278-1 assume !(0 == ~T5_E~0); 510418#L1283-1 assume !(0 == ~T6_E~0); 510419#L1288-1 assume !(0 == ~T7_E~0); 510722#L1293-1 assume !(0 == ~T8_E~0); 510703#L1298-1 assume !(0 == ~T9_E~0); 510598#L1303-1 assume !(0 == ~T10_E~0); 509128#L1308-1 assume !(0 == ~T11_E~0); 509071#L1313-1 assume !(0 == ~T12_E~0); 509072#L1318-1 assume !(0 == ~T13_E~0); 509078#L1323-1 assume !(0 == ~E_1~0); 509079#L1328-1 assume !(0 == ~E_2~0); 509248#L1333-1 assume !(0 == ~E_3~0); 510264#L1338-1 assume !(0 == ~E_4~0); 510265#L1343-1 assume !(0 == ~E_5~0); 510389#L1348-1 assume !(0 == ~E_6~0); 510765#L1353-1 assume !(0 == ~E_7~0); 509960#L1358-1 assume !(0 == ~E_8~0); 509961#L1363-1 assume !(0 == ~E_9~0); 510289#L1368-1 assume !(0 == ~E_10~0); 508908#L1373-1 assume !(0 == ~E_11~0); 508909#L1378-1 assume !(0 == ~E_12~0); 509195#L1383-1 assume !(0 == ~E_13~0); 509196#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 509967#L607 assume !(1 == ~m_pc~0); 509268#L607-2 is_master_triggered_~__retres1~0#1 := 0; 509269#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 510387#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 509883#L1560 assume !(0 != activate_threads_~tmp~1#1); 509884#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 509091#L626 assume !(1 == ~t1_pc~0); 509092#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 509365#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 509366#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 509541#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 508991#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508992#L645 assume !(1 == ~t2_pc~0); 509064#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 509065#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509761#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 509762#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 509859#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 509860#L664 assume !(1 == ~t3_pc~0); 510314#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 508832#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508833#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 509503#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 509504#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 510625#L683 assume !(1 == ~t4_pc~0); 510090#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 510041#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 510042#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 510076#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 510217#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 509805#L702 assume 1 == ~t5_pc~0; 509806#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 509730#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510212#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 510568#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 510494#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508879#L721 assume !(1 == ~t6_pc~0); 508854#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 508855#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 509018#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 509512#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 509513#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 510142#L740 assume 1 == ~t7_pc~0; 508929#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 508743#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 508744#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 508733#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 508734#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509444#L759 assume !(1 == ~t8_pc~0); 509445#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 509474#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 510210#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 510211#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 510372#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 510721#L778 assume 1 == ~t9_pc~0; 510566#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 508906#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 508847#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 508776#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 508777#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 509104#L797 assume !(1 == ~t10_pc~0); 509105#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 509225#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 510444#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 509621#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 509622#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 509924#L816 assume 1 == ~t11_pc~0; 508812#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 508813#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 509582#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 509519#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 509520#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 510066#L835 assume 1 == ~t12_pc~0; 509937#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 508976#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 508998#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 509138#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 509681#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 509682#L854 assume !(1 == ~t13_pc~0); 509309#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 509310#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 509360#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 509016#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 509017#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 510486#L1401 assume !(1 == ~M_E~0); 509507#L1401-2 assume !(1 == ~T1_E~0); 509508#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 510497#L1411-1 assume !(1 == ~T3_E~0); 510756#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 510757#L1421-1 assume !(1 == ~T5_E~0); 509305#L1426-1 assume !(1 == ~T6_E~0); 509306#L1431-1 assume !(1 == ~T7_E~0); 508850#L1436-1 assume !(1 == ~T8_E~0); 508851#L1441-1 assume !(1 == ~T9_E~0); 588617#L1446-1 assume !(1 == ~T10_E~0); 588616#L1451-1 assume !(1 == ~T11_E~0); 588615#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 588614#L1461-1 assume !(1 == ~T13_E~0); 588613#L1466-1 assume !(1 == ~E_1~0); 588612#L1471-1 assume !(1 == ~E_2~0); 510370#L1476-1 assume !(1 == ~E_3~0); 510371#L1481-1 assume !(1 == ~E_4~0); 510547#L1486-1 assume !(1 == ~E_5~0); 510739#L1491-1 assume !(1 == ~E_6~0); 508784#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 508785#L1501-1 assume !(1 == ~E_8~0); 509610#L1506-1 assume !(1 == ~E_9~0); 509611#L1511-1 assume !(1 == ~E_10~0); 509564#L1516-1 assume !(1 == ~E_11~0); 509565#L1521-1 assume !(1 == ~E_12~0); 630556#L1526-1 assume !(1 == ~E_13~0); 630554#L1531-1 assume { :end_inline_reset_delta_events } true; 630551#L1892-2 [2022-11-16 11:56:46,744 INFO L750 eck$LassoCheckResult]: Loop: 630551#L1892-2 assume !false; 617016#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 617014#L1233 assume !false; 617011#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 616979#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 616978#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 616977#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 616975#L1046 assume !(0 != eval_~tmp~0#1); 616976#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 633805#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 633803#L1258-3 assume !(0 == ~M_E~0); 633801#L1258-5 assume !(0 == ~T1_E~0); 633799#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 633796#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 633794#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 633792#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 633790#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 633788#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 633786#L1293-3 assume !(0 == ~T8_E~0); 633783#L1298-3 assume !(0 == ~T9_E~0); 633781#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 633779#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 633777#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 633775#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 633773#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 633770#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 633768#L1333-3 assume !(0 == ~E_3~0); 633766#L1338-3 assume !(0 == ~E_4~0); 633764#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 633762#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 633760#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 633757#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 633755#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 633753#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 633751#L1373-3 assume !(0 == ~E_11~0); 633749#L1378-3 assume !(0 == ~E_12~0); 633747#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 633744#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 633742#L607-42 assume !(1 == ~m_pc~0); 633740#L607-44 is_master_triggered_~__retres1~0#1 := 0; 633738#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 633736#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 633734#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 633731#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 633729#L626-42 assume !(1 == ~t1_pc~0); 633727#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 633724#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 633722#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 633720#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 633717#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 633715#L645-42 assume !(1 == ~t2_pc~0); 633713#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 633711#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 633709#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 633707#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 633704#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 633702#L664-42 assume !(1 == ~t3_pc~0); 633700#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 633698#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 633696#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 633694#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 633693#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 633692#L683-42 assume 1 == ~t4_pc~0; 633691#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 633689#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 633688#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 633687#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 633686#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 633685#L702-42 assume 1 == ~t5_pc~0; 633683#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 633682#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 633681#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 633680#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 633679#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 633678#L721-42 assume !(1 == ~t6_pc~0); 633675#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 633673#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 633671#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 633669#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 633667#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 633665#L740-42 assume !(1 == ~t7_pc~0); 633663#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 633660#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 633658#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 633656#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 633654#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 633652#L759-42 assume 1 == ~t8_pc~0; 633649#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 633647#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 633645#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 633643#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 633641#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 633639#L778-42 assume 1 == ~t9_pc~0; 633637#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 633634#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 633632#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 633630#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 633628#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 633626#L797-42 assume !(1 == ~t10_pc~0); 633624#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 633621#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 633619#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 633617#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 633615#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 633613#L816-42 assume 1 == ~t11_pc~0; 633611#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 633608#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 633606#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 633604#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 633602#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 633600#L835-42 assume !(1 == ~t12_pc~0); 633597#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 633594#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 633592#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 633590#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 633588#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 633586#L854-42 assume !(1 == ~t13_pc~0); 633583#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 633581#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 633579#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 633577#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 633575#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 633573#L1401-3 assume !(1 == ~M_E~0); 630924#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 633570#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 587359#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 633563#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 633561#L1421-3 assume !(1 == ~T5_E~0); 633559#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 633556#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 633554#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 633550#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 633548#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 633546#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 633544#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 633541#L1461-3 assume !(1 == ~T13_E~0); 633539#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 633537#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 633535#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 633531#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 633529#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 633526#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 633524#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 633522#L1501-3 assume !(1 == ~E_8~0); 633520#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 633518#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 633516#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 628688#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 633512#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 633510#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 630608#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 630603#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 630601#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 630599#L1911 assume !(0 == start_simulation_~tmp~3#1); 630583#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 630581#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 630566#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 630563#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 630559#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 630558#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 630557#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 630553#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 630551#L1892-2 [2022-11-16 11:56:46,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:46,745 INFO L85 PathProgramCache]: Analyzing trace with hash -1375101771, now seen corresponding path program 1 times [2022-11-16 11:56:46,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:46,746 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142247755] [2022-11-16 11:56:46,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:46,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:46,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:46,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:46,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:46,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142247755] [2022-11-16 11:56:46,857 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [142247755] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:46,857 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:46,857 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:56:46,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440845954] [2022-11-16 11:56:46,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:46,858 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:46,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:46,859 INFO L85 PathProgramCache]: Analyzing trace with hash -768943152, now seen corresponding path program 1 times [2022-11-16 11:56:46,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:46,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091555657] [2022-11-16 11:56:46,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:46,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:46,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:46,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:46,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:46,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091555657] [2022-11-16 11:56:46,936 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091555657] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:46,936 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:46,936 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:46,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202215312] [2022-11-16 11:56:46,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:46,937 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:46,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:46,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:56:46,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:56:46,938 INFO L87 Difference]: Start difference. First operand 202813 states and 293449 transitions. cyclomatic complexity: 90668 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:49,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:56:49,877 INFO L93 Difference]: Finished difference Result 547726 states and 795256 transitions. [2022-11-16 11:56:49,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 547726 states and 795256 transitions. [2022-11-16 11:56:52,326 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 546472 [2022-11-16 11:56:54,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 547726 states to 547726 states and 795256 transitions. [2022-11-16 11:56:54,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 547726 [2022-11-16 11:56:54,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 547726 [2022-11-16 11:56:54,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 547726 states and 795256 transitions. [2022-11-16 11:56:54,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:56:54,648 INFO L218 hiAutomatonCegarLoop]: Abstraction has 547726 states and 795256 transitions. [2022-11-16 11:56:54,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547726 states and 795256 transitions. [2022-11-16 11:56:57,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547726 to 207976. [2022-11-16 11:56:57,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207976 states, 207976 states have (on average 1.4358002846482287) internal successors, (298612), 207975 states have internal predecessors, (298612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:56:58,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207976 states to 207976 states and 298612 transitions. [2022-11-16 11:56:58,810 INFO L240 hiAutomatonCegarLoop]: Abstraction has 207976 states and 298612 transitions. [2022-11-16 11:56:58,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 11:56:58,811 INFO L428 stractBuchiCegarLoop]: Abstraction has 207976 states and 298612 transitions. [2022-11-16 11:56:58,811 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-16 11:56:58,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 207976 states and 298612 transitions. [2022-11-16 11:56:59,283 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 207488 [2022-11-16 11:56:59,283 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:56:59,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:56:59,286 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:59,286 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:56:59,286 INFO L748 eck$LassoCheckResult]: Stem: 1260126#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1260127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1259943#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1259653#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1259654#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1260907#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260908#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1259792#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1259793#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1260259#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1260087#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1260088#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1259860#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1259861#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1260267#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1260451#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1260617#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1260658#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1259875#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1259876#L1258 assume !(0 == ~M_E~0); 1261169#L1258-2 assume !(0 == ~T1_E~0); 1260171#L1263-1 assume !(0 == ~T2_E~0); 1260172#L1268-1 assume !(0 == ~T3_E~0); 1260488#L1273-1 assume !(0 == ~T4_E~0); 1261142#L1278-1 assume !(0 == ~T5_E~0); 1260968#L1283-1 assume !(0 == ~T6_E~0); 1260969#L1288-1 assume !(0 == ~T7_E~0); 1261294#L1293-1 assume !(0 == ~T8_E~0); 1261276#L1298-1 assume !(0 == ~T9_E~0); 1261158#L1303-1 assume !(0 == ~T10_E~0); 1259681#L1308-1 assume !(0 == ~T11_E~0); 1259624#L1313-1 assume !(0 == ~T12_E~0); 1259625#L1318-1 assume !(0 == ~T13_E~0); 1259633#L1323-1 assume !(0 == ~E_1~0); 1259634#L1328-1 assume !(0 == ~E_2~0); 1259803#L1333-1 assume !(0 == ~E_3~0); 1260818#L1338-1 assume !(0 == ~E_4~0); 1260819#L1343-1 assume !(0 == ~E_5~0); 1260940#L1348-1 assume !(0 == ~E_6~0); 1261330#L1353-1 assume !(0 == ~E_7~0); 1260506#L1358-1 assume !(0 == ~E_8~0); 1260507#L1363-1 assume !(0 == ~E_9~0); 1260845#L1368-1 assume !(0 == ~E_10~0); 1259461#L1373-1 assume !(0 == ~E_11~0); 1259462#L1378-1 assume !(0 == ~E_12~0); 1259750#L1383-1 assume !(0 == ~E_13~0); 1259751#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1260513#L607 assume !(1 == ~m_pc~0); 1259822#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1259823#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1260938#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1260431#L1560 assume !(0 != activate_threads_~tmp~1#1); 1260432#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1259644#L626 assume !(1 == ~t1_pc~0); 1259645#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1259921#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1259922#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260093#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1259547#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259548#L645 assume !(1 == ~t2_pc~0); 1259617#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1259618#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1260312#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1260313#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1260407#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1260408#L664 assume !(1 == ~t3_pc~0); 1260870#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1259389#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1259390#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1260052#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1260053#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1261184#L683 assume !(1 == ~t4_pc~0); 1260642#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1260591#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1260592#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1261354#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1260770#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1260357#L702 assume 1 == ~t5_pc~0; 1260358#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1260278#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1260765#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1261124#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1261050#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1259432#L721 assume !(1 == ~t6_pc~0); 1259407#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1259408#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1259571#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1260061#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1260062#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1260697#L740 assume 1 == ~t7_pc~0; 1259482#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1259295#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1259296#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1259285#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1259286#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1259996#L759 assume !(1 == ~t8_pc~0); 1259997#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1260025#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1260763#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1260764#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1260921#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1261292#L778 assume 1 == ~t9_pc~0; 1261122#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1259460#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1259400#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1259328#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1259329#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1259658#L797 assume !(1 == ~t10_pc~0); 1259659#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1259779#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1260996#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1260169#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1260170#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1260470#L816 assume 1 == ~t11_pc~0; 1259365#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259366#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1260132#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1260068#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1260069#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1260616#L835 assume 1 == ~t12_pc~0; 1260484#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1259529#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1259551#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1259691#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1260227#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1260228#L854 assume !(1 == ~t13_pc~0); 1259862#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1259863#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1259917#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1259569#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1259570#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1261040#L1401 assume !(1 == ~M_E~0); 1260056#L1401-2 assume !(1 == ~T1_E~0); 1260057#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1260686#L1411-1 assume !(1 == ~T3_E~0); 1260687#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1260325#L1421-1 assume !(1 == ~T5_E~0); 1259858#L1426-1 assume !(1 == ~T6_E~0); 1259859#L1431-1 assume !(1 == ~T7_E~0); 1259403#L1436-1 assume !(1 == ~T8_E~0); 1259404#L1441-1 assume !(1 == ~T9_E~0); 1260162#L1446-1 assume !(1 == ~T10_E~0); 1260163#L1451-1 assume !(1 == ~T11_E~0); 1260936#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1260937#L1461-1 assume !(1 == ~T13_E~0); 1260081#L1466-1 assume !(1 == ~E_1~0); 1260082#L1471-1 assume !(1 == ~E_2~0); 1260919#L1476-1 assume !(1 == ~E_3~0); 1260920#L1481-1 assume !(1 == ~E_4~0); 1261101#L1486-1 assume !(1 == ~E_5~0); 1259698#L1491-1 assume !(1 == ~E_6~0); 1259337#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1259338#L1501-1 assume !(1 == ~E_8~0); 1260158#L1506-1 assume !(1 == ~E_9~0); 1260159#L1511-1 assume !(1 == ~E_10~0); 1260113#L1516-1 assume !(1 == ~E_11~0); 1260114#L1521-1 assume !(1 == ~E_12~0); 1259335#L1526-1 assume !(1 == ~E_13~0); 1259336#L1531-1 assume { :end_inline_reset_delta_events } true; 1259885#L1892-2 [2022-11-16 11:56:59,287 INFO L750 eck$LassoCheckResult]: Loop: 1259885#L1892-2 assume !false; 1465798#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1465794#L1233 assume !false; 1465790#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1465730#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1465725#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1465719#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1465713#L1046 assume !(0 != eval_~tmp~0#1); 1465714#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1466341#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1466340#L1258-3 assume !(0 == ~M_E~0); 1466339#L1258-5 assume !(0 == ~T1_E~0); 1466338#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1466337#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1466336#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1466335#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1466334#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1466333#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1466332#L1293-3 assume !(0 == ~T8_E~0); 1466139#L1298-3 assume !(0 == ~T9_E~0); 1465866#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1465865#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1465864#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1465849#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1465847#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1465845#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1465843#L1333-3 assume !(0 == ~E_3~0); 1465841#L1338-3 assume !(0 == ~E_4~0); 1465832#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1465824#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1465807#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1465797#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1465793#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1465789#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1465788#L1373-3 assume !(0 == ~E_11~0); 1465787#L1378-3 assume !(0 == ~E_12~0); 1465786#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1465785#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1465784#L607-42 assume !(1 == ~m_pc~0); 1465783#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1465782#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1465781#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1259935#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1259936#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1261028#L626-42 assume 1 == ~t1_pc~0; 1260019#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1260020#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1465778#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260954#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1259593#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259594#L645-42 assume !(1 == ~t2_pc~0); 1260865#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1260866#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1261355#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1465773#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1465772#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1465771#L664-42 assume !(1 == ~t3_pc~0); 1465770#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1465769#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1465768#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1260656#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1260657#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1261389#L683-42 assume 1 == ~t4_pc~0; 1261391#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1465766#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1465764#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1465762#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1465760#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1465758#L702-42 assume !(1 == ~t5_pc~0); 1465756#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1465752#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1465750#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1465748#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1465727#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1465723#L721-42 assume !(1 == ~t6_pc~0); 1465716#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1465711#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1465707#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1465700#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1260142#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1259985#L740-42 assume 1 == ~t7_pc~0; 1259986#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1259717#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1260271#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1260122#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 1260123#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1260405#L759-42 assume 1 == ~t8_pc~0; 1260247#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1260177#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1260178#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1260257#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1260258#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1260356#L778-42 assume !(1 == ~t9_pc~0); 1260190#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1260191#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1260623#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1260518#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1260519#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1260584#L797-42 assume 1 == ~t10_pc~0; 1259722#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1259723#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1260777#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1261153#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1260624#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1260625#L816-42 assume 1 == ~t11_pc~0; 1259271#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259272#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1259818#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1259819#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1259900#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1259901#L835-42 assume 1 == ~t12_pc~0; 1260311#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1260202#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1259873#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1259874#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1261048#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1260792#L854-42 assume !(1 == ~t13_pc~0); 1259814#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1259815#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1259423#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1259424#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1260079#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1260080#L1401-3 assume !(1 == ~M_E~0); 1260927#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1259657#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1259524#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1259525#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1260133#L1421-3 assume !(1 == ~T5_E~0); 1260134#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1259699#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1259700#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1259287#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1259288#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1260959#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1260218#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1259865#L1461-3 assume !(1 == ~T13_E~0); 1259866#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1261317#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1259805#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1259806#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1463878#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1463872#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1463865#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1463845#L1501-3 assume !(1 == ~E_8~0); 1463840#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1463835#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1463829#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1418142#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1463784#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1463777#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1261406#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1259636#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1260553#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1260179#L1911 assume !(0 == start_simulation_~tmp~3#1); 1260180#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1465863#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1465848#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1465846#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1465844#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1465842#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1465833#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1465825#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1259885#L1892-2 [2022-11-16 11:56:59,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:59,288 INFO L85 PathProgramCache]: Analyzing trace with hash 1040734579, now seen corresponding path program 1 times [2022-11-16 11:56:59,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:59,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188936782] [2022-11-16 11:56:59,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:59,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:59,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:59,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:59,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:59,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188936782] [2022-11-16 11:56:59,353 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188936782] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:59,353 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:59,353 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:56:59,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1921444547] [2022-11-16 11:56:59,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:59,354 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 11:56:59,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:56:59,355 INFO L85 PathProgramCache]: Analyzing trace with hash -1025425518, now seen corresponding path program 1 times [2022-11-16 11:56:59,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:56:59,355 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268993131] [2022-11-16 11:56:59,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:56:59,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:56:59,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:56:59,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:56:59,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:56:59,415 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268993131] [2022-11-16 11:56:59,416 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268993131] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:56:59,416 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:56:59,416 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:56:59,416 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705065920] [2022-11-16 11:56:59,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:56:59,417 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:56:59,417 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:56:59,417 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:56:59,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:56:59,418 INFO L87 Difference]: Start difference. First operand 207976 states and 298612 transitions. cyclomatic complexity: 90668 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:57:01,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:57:01,439 INFO L93 Difference]: Finished difference Result 399423 states and 571771 transitions. [2022-11-16 11:57:01,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 399423 states and 571771 transitions. [2022-11-16 11:57:03,684 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 398408 [2022-11-16 11:57:04,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 399423 states to 399423 states and 571771 transitions. [2022-11-16 11:57:04,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 399423 [2022-11-16 11:57:04,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 399423 [2022-11-16 11:57:04,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 399423 states and 571771 transitions. [2022-11-16 11:57:05,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:57:05,406 INFO L218 hiAutomatonCegarLoop]: Abstraction has 399423 states and 571771 transitions. [2022-11-16 11:57:05,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399423 states and 571771 transitions.