./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 10:56:49,189 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 10:56:49,191 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 10:56:49,212 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 10:56:49,213 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 10:56:49,214 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 10:56:49,216 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 10:56:49,218 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 10:56:49,220 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 10:56:49,221 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 10:56:49,222 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 10:56:49,223 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 10:56:49,224 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 10:56:49,225 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 10:56:49,226 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 10:56:49,228 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 10:56:49,229 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 10:56:49,230 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 10:56:49,232 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 10:56:49,234 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 10:56:49,236 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 10:56:49,237 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 10:56:49,238 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 10:56:49,239 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 10:56:49,243 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 10:56:49,243 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 10:56:49,244 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 10:56:49,245 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 10:56:49,246 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 10:56:49,247 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 10:56:49,247 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 10:56:49,248 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 10:56:49,249 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 10:56:49,250 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 10:56:49,252 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 10:56:49,252 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 10:56:49,253 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 10:56:49,253 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 10:56:49,254 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 10:56:49,255 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 10:56:49,256 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 10:56:49,263 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 10:56:49,310 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 10:56:49,310 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 10:56:49,311 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 10:56:49,311 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 10:56:49,312 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 10:56:49,312 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 10:56:49,313 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 10:56:49,313 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 10:56:49,313 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 10:56:49,313 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 10:56:49,314 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 10:56:49,314 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 10:56:49,315 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 10:56:49,315 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 10:56:49,315 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 10:56:49,315 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 10:56:49,315 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 10:56:49,316 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 10:56:49,316 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 10:56:49,316 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 10:56:49,316 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 10:56:49,316 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 10:56:49,317 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 10:56:49,317 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 10:56:49,317 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 10:56:49,317 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 10:56:49,317 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 10:56:49,318 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 10:56:49,318 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 10:56:49,318 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 10:56:49,318 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 10:56:49,319 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 10:56:49,319 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2022-11-16 10:56:49,641 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 10:56:49,671 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 10:56:49,676 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 10:56:49,678 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 10:56:49,678 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 10:56:49,680 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-11-16 10:56:49,749 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/data/2cb64bf16/5d70b9c882d148d7bc9ffd57c05a4739/FLAG537b03852 [2022-11-16 10:56:50,261 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 10:56:50,262 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-11-16 10:56:50,288 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/data/2cb64bf16/5d70b9c882d148d7bc9ffd57c05a4739/FLAG537b03852 [2022-11-16 10:56:50,573 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/data/2cb64bf16/5d70b9c882d148d7bc9ffd57c05a4739 [2022-11-16 10:56:50,576 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 10:56:50,578 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 10:56:50,583 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 10:56:50,584 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 10:56:50,587 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 10:56:50,588 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 10:56:50" (1/1) ... [2022-11-16 10:56:50,589 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@41f65372 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:50, skipping insertion in model container [2022-11-16 10:56:50,589 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 10:56:50" (1/1) ... [2022-11-16 10:56:50,596 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 10:56:50,658 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 10:56:50,873 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-11-16 10:56:51,074 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 10:56:51,083 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 10:56:51,094 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-11-16 10:56:51,155 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 10:56:51,174 INFO L208 MainTranslator]: Completed translation [2022-11-16 10:56:51,174 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51 WrapperNode [2022-11-16 10:56:51,174 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 10:56:51,175 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 10:56:51,176 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 10:56:51,176 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 10:56:51,193 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,205 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,316 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2022-11-16 10:56:51,316 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 10:56:51,317 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 10:56:51,317 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 10:56:51,317 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 10:56:51,326 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,326 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,337 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,337 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,393 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,436 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,442 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,453 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,476 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 10:56:51,477 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 10:56:51,477 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 10:56:51,477 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 10:56:51,481 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (1/1) ... [2022-11-16 10:56:51,488 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 10:56:51,499 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 10:56:51,520 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 10:56:51,548 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_538ce620-1922-40e2-b298-3556c0282f50/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 10:56:51,571 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 10:56:51,571 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 10:56:51,571 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 10:56:51,571 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 10:56:51,779 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 10:56:51,781 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 10:56:54,266 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 10:56:54,290 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 10:56:54,291 INFO L300 CfgBuilder]: Removed 17 assume(true) statements. [2022-11-16 10:56:54,296 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 10:56:54 BoogieIcfgContainer [2022-11-16 10:56:54,297 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 10:56:54,299 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 10:56:54,299 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 10:56:54,303 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 10:56:54,304 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 10:56:54,304 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 10:56:50" (1/3) ... [2022-11-16 10:56:54,305 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4153aa2b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 10:56:54, skipping insertion in model container [2022-11-16 10:56:54,305 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 10:56:54,305 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 10:56:51" (2/3) ... [2022-11-16 10:56:54,306 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4153aa2b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 10:56:54, skipping insertion in model container [2022-11-16 10:56:54,306 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 10:56:54,306 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 10:56:54" (3/3) ... [2022-11-16 10:56:54,307 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.15.cil.c [2022-11-16 10:56:54,401 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 10:56:54,402 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 10:56:54,402 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 10:56:54,402 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 10:56:54,402 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 10:56:54,402 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 10:56:54,402 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 10:56:54,403 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 10:56:54,414 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:54,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2022-11-16 10:56:54,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:54,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:54,503 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:54,503 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:54,503 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 10:56:54,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:54,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2022-11-16 10:56:54,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:54,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:54,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:54,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:54,589 INFO L748 eck$LassoCheckResult]: Stem: 460#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1832#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 351#L1855true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200#L874true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1758#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1071#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1409#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 271#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1400#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 544#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 438#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 794#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 305#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 553#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 682#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 802#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 832#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 919#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 312#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1813#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1398#L1258-2true assume !(0 == ~T1_E~0); 489#L1263-1true assume !(0 == ~T2_E~0); 708#L1268-1true assume !(0 == ~T3_E~0); 1364#L1273-1true assume !(0 == ~T4_E~0); 1747#L1278-1true assume !(0 == ~T5_E~0); 1151#L1283-1true assume !(0 == ~T6_E~0); 1779#L1288-1true assume !(0 == ~T7_E~0); 1567#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1538#L1298-1true assume !(0 == ~T9_E~0); 1382#L1303-1true assume !(0 == ~T10_E~0); 214#L1308-1true assume !(0 == ~T11_E~0); 185#L1313-1true assume !(0 == ~T12_E~0); 1837#L1318-1true assume !(0 == ~T13_E~0); 188#L1323-1true assume !(0 == ~E_1~0); 276#L1328-1true assume !(0 == ~E_2~0); 1788#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 972#L1338-1true assume !(0 == ~E_4~0); 1111#L1343-1true assume !(0 == ~E_5~0); 1649#L1348-1true assume !(0 == ~E_6~0); 1666#L1353-1true assume !(0 == ~E_7~0); 724#L1358-1true assume !(0 == ~E_8~0); 998#L1363-1true assume !(0 == ~E_9~0); 1060#L1368-1true assume !(0 == ~E_10~0); 104#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 488#L1378-1true assume !(0 == ~E_12~0); 249#L1383-1true assume !(0 == ~E_13~0); 1100#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728#L607true assume 1 == ~m_pc~0; 1008#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1107#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1625#L619true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 666#L1560true assume !(0 != activate_threads_~tmp~1#1); 1723#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 195#L626true assume !(1 == ~t1_pc~0); 1265#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 338#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 440#L638true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1906#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 146#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1335#L645true assume 1 == ~t2_pc~0; 204#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1299#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 583#L657true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1898#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 651#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1703#L664true assume 1 == ~t3_pc~0; 1632#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1125#L676true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 416#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1418#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1626#L683true assume !(1 == ~t4_pc~0); 985#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 784#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 809#L695true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1693#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 930#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 614#L702true assume 1 == ~t5_pc~0; 1683#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 924#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1342#L714true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1390#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1236#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89#L721true assume !(1 == ~t6_pc~0); 76#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 160#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 556#L733true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 421#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1523#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 866#L740true assume 1 == ~t7_pc~0; 115#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 756#L752true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 761#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 384#L759true assume !(1 == ~t8_pc~0); 1372#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1842#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 922#L771true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1082#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1669#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1566#L778true assume 1 == ~t9_pc~0; 1340#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1272#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72#L790true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 732#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 202#L797true assume !(1 == ~t10_pc~0); 264#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1305#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1180#L809true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 487#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 695#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1389#L816true assume 1 == ~t11_pc~0; 56#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 587#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 462#L828true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 426#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1510#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 801#L835true assume 1 == ~t12_pc~0; 704#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 150#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 221#L847true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1782#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 526#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1441#L854true assume !(1 == ~t13_pc~0); 306#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 335#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1080#L866true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 159#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1229#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1789#L1401true assume !(1 == ~M_E~0); 418#L1401-2true assume !(1 == ~T1_E~0); 1239#L1406-1true assume !(1 == ~T2_E~0); 857#L1411-1true assume !(1 == ~T3_E~0); 1610#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 594#L1421-1true assume !(1 == ~T5_E~0); 304#L1426-1true assume !(1 == ~T6_E~0); 1013#L1431-1true assume !(1 == ~T7_E~0); 74#L1436-1true assume !(1 == ~T8_E~0); 744#L1441-1true assume !(1 == ~T9_E~0); 482#L1446-1true assume !(1 == ~T10_E~0); 1771#L1451-1true assume !(1 == ~T11_E~0); 1106#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 743#L1461-1true assume !(1 == ~T13_E~0); 435#L1466-1true assume !(1 == ~E_1~0); 1766#L1471-1true assume !(1 == ~E_2~0); 1081#L1476-1true assume !(1 == ~E_3~0); 1313#L1481-1true assume !(1 == ~E_4~0); 1591#L1486-1true assume !(1 == ~E_5~0); 224#L1491-1true assume !(1 == ~E_6~0); 41#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 755#L1501-1true assume !(1 == ~E_8~0); 480#L1506-1true assume !(1 == ~E_9~0); 1036#L1511-1true assume !(1 == ~E_10~0); 453#L1516-1true assume !(1 == ~E_11~0); 13#L1521-1true assume !(1 == ~E_12~0); 40#L1526-1true assume !(1 == ~E_13~0); 318#L1531-1true assume { :end_inline_reset_delta_events } true; 1170#L1892-2true [2022-11-16 10:56:54,599 INFO L750 eck$LassoCheckResult]: Loop: 1170#L1892-2true assume !false; 1866#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1512#L1233true assume !true; 80#L1248true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 803#L874-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1628#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1897#L1258-5true assume !(0 == ~T1_E~0); 153#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1602#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1617#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1904#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1619#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 266#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1787#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1167#L1298-3true assume !(0 == ~T9_E~0); 1692#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1426#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1166#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 657#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 154#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1300#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1671#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 228#L1338-3true assume !(0 == ~E_4~0); 1054#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1539#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1310#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1351#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 626#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 339#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1883#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 883#L1378-3true assume !(0 == ~E_12~0); 1458#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1098#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1765#L607-42true assume !(1 == ~m_pc~0); 910#L607-44true is_master_triggered_~__retres1~0#1 := 0; 509#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1074#L619-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 348#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 696#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1218#L626-42true assume 1 == ~t1_pc~0; 398#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1470#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 599#L638-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1129#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 170#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1572#L645-42true assume !(1 == ~t2_pc~0); 1022#L645-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1694#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1251#L657-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 277#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1660#L664-42true assume 1 == ~t3_pc~0; 456#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1622#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1473#L676-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 831#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1014#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1786#L683-42true assume 1 == ~t4_pc~0; 1697#L684-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 839#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1767#L695-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1410#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1902#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1161#L702-42true assume 1 == ~t5_pc~0; 645#L703-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 589#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1732#L714-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1286#L1600-42true assume !(0 != activate_threads_~tmp___4~0#1); 32#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113#L721-42true assume 1 == ~t6_pc~0; 122#L722-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 367#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1618#L733-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1586#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 469#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 378#L740-42true assume !(1 == ~t7_pc~0); 235#L740-44true is_transmit7_triggered_~__retres1~7#1 := 0; 560#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 559#L752-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 458#L1616-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 649#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1894#L759-42true assume !(1 == ~t8_pc~0); 1355#L759-44true is_transmit8_triggered_~__retres1~8#1 := 0; 492#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 672#L771-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 546#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 616#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1173#L778-42true assume 1 == ~t9_pc~0; 500#L779-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 807#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1748#L790-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 731#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1611#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 779#L797-42true assume !(1 == ~t10_pc~0); 1044#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 936#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1374#L809-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1875#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 808#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1707#L816-42true assume !(1 == ~t11_pc~0); 346#L816-44true is_transmit11_triggered_~__retres1~11#1 := 0; 1850#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 284#L828-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 485#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 327#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 586#L835-42true assume 1 == ~t12_pc~0; 844#L836-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1242#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 313#L847-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1836#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1235#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 948#L854-42true assume !(1 == ~t13_pc~0); 283#L854-44true is_transmit13_triggered_~__retres1~13#1 := 0; 481#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85#L866-14true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 514#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 434#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1853#L1401-3true assume !(1 == ~M_E~0); 1092#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 203#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 135#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1678#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 464#L1421-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1051#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 227#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 292#L1436-3true assume !(1 == ~T8_E~0); 16#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1143#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1134#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 520#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 308#L1461-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1609#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1815#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 278#L1476-3true assume !(1 == ~E_3~0); 1685#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 513#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 291#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1480#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 543#L1501-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1593#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 880#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 873#L1516-3true assume !(1 == ~E_11~0); 1717#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 629#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 968#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1841#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1879#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 759#L1032-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 493#L1911true assume !(0 == start_simulation_~tmp~3#1); 1303#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 905#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1023#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 841#L1032-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 106#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 519#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 223#L1874true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1347#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1170#L1892-2true [2022-11-16 10:56:54,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:54,610 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2022-11-16 10:56:54,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:54,620 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538947650] [2022-11-16 10:56:54,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:54,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:54,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:55,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:55,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:55,117 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538947650] [2022-11-16 10:56:55,118 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [538947650] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:55,118 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:55,119 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:55,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [487215872] [2022-11-16 10:56:55,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:55,127 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:55,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:55,130 INFO L85 PathProgramCache]: Analyzing trace with hash 699417164, now seen corresponding path program 1 times [2022-11-16 10:56:55,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:55,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921079846] [2022-11-16 10:56:55,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:55,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:55,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:55,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:55,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:55,272 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921079846] [2022-11-16 10:56:55,272 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921079846] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:55,272 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:55,272 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 10:56:55,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508331784] [2022-11-16 10:56:55,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:55,274 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:55,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:55,320 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-16 10:56:55,321 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 10:56:55,326 INFO L87 Difference]: Start difference. First operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:55,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:55,431 INFO L93 Difference]: Finished difference Result 1919 states and 2840 transitions. [2022-11-16 10:56:55,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1919 states and 2840 transitions. [2022-11-16 10:56:55,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:55,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1919 states to 1914 states and 2835 transitions. [2022-11-16 10:56:55,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:55,477 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:55,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2022-11-16 10:56:55,489 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:55,490 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-11-16 10:56:55,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2022-11-16 10:56:55,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:55,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:55,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2022-11-16 10:56:55,584 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-11-16 10:56:55,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-16 10:56:55,588 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-11-16 10:56:55,588 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 10:56:55,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2022-11-16 10:56:55,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:55,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:55,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:55,629 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:55,629 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:55,630 INFO L748 eck$LassoCheckResult]: Stem: 4709#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4710#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4529#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4245#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4246#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5422#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5423#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4381#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4382#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4836#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4671#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4672#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4448#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4449#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4847#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5024#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5178#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5215#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4459#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4460#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5635#L1258-2 assume !(0 == ~T1_E~0); 4754#L1263-1 assume !(0 == ~T2_E~0); 4755#L1268-1 assume !(0 == ~T3_E~0); 5058#L1273-1 assume !(0 == ~T4_E~0); 5617#L1278-1 assume !(0 == ~T5_E~0); 5478#L1283-1 assume !(0 == ~T6_E~0); 5479#L1288-1 assume !(0 == ~T7_E~0); 5715#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5703#L1298-1 assume !(0 == ~T9_E~0); 5629#L1303-1 assume !(0 == ~T10_E~0); 4274#L1308-1 assume !(0 == ~T11_E~0); 4216#L1313-1 assume !(0 == ~T12_E~0); 4217#L1318-1 assume !(0 == ~T13_E~0); 4223#L1323-1 assume !(0 == ~E_1~0); 4224#L1328-1 assume !(0 == ~E_2~0); 4391#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5350#L1338-1 assume !(0 == ~E_4~0); 5351#L1343-1 assume !(0 == ~E_5~0); 5452#L1348-1 assume !(0 == ~E_6~0); 5738#L1353-1 assume !(0 == ~E_7~0); 5077#L1358-1 assume !(0 == ~E_8~0); 5078#L1363-1 assume !(0 == ~E_9~0); 5368#L1368-1 assume !(0 == ~E_10~0); 4053#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4054#L1378-1 assume !(0 == ~E_12~0); 4340#L1383-1 assume !(0 == ~E_13~0); 4341#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5084#L607 assume 1 == ~m_pc~0; 5085#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4411#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5450#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5004#L1560 assume !(0 != activate_threads_~tmp~1#1); 5005#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4236#L626 assume !(1 == ~t1_pc~0); 4237#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4505#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4506#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4675#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4136#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4137#L645 assume 1 == ~t2_pc~0; 4253#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4210#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4887#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4888#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4980#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4981#L664 assume 1 == ~t3_pc~0; 5737#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3977#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3978#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4636#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4637#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5645#L683 assume !(1 == ~t4_pc~0); 5200#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5152#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5153#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5187#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5311#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4930#L702 assume 1 == ~t5_pc~0; 4931#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4856#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5306#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5604#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5545#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4025#L721 assume !(1 == ~t6_pc~0); 3999#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4000#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4163#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4645#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4646#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5247#L740 assume 1 == ~t7_pc~0; 4074#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3887#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3888#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3877#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3878#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4581#L759 assume !(1 == ~t8_pc~0); 4582#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4611#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5304#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5305#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5436#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5714#L778 assume 1 == ~t9_pc~0; 5601#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4052#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3992#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3921#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3922#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4249#L797 assume !(1 == ~t10_pc~0); 4250#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4368#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5502#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4752#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4753#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5042#L816 assume 1 == ~t11_pc~0; 3957#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3958#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4713#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4652#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4653#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5177#L835 assume 1 == ~t12_pc~0; 5055#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4121#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4143#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4284#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4809#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4810#L854 assume !(1 == ~t13_pc~0); 4450#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4451#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4501#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4161#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4162#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5541#L1401 assume !(1 == ~M_E~0); 4640#L1401-2 assume !(1 == ~T1_E~0); 4641#L1406-1 assume !(1 == ~T2_E~0); 5236#L1411-1 assume !(1 == ~T3_E~0); 5237#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4903#L1421-1 assume !(1 == ~T5_E~0); 4446#L1426-1 assume !(1 == ~T6_E~0); 4447#L1431-1 assume !(1 == ~T7_E~0); 3995#L1436-1 assume !(1 == ~T8_E~0); 3996#L1441-1 assume !(1 == ~T9_E~0); 4743#L1446-1 assume !(1 == ~T10_E~0); 4744#L1451-1 assume !(1 == ~T11_E~0); 5449#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5103#L1461-1 assume !(1 == ~T13_E~0); 4664#L1466-1 assume !(1 == ~E_1~0); 4665#L1471-1 assume !(1 == ~E_2~0); 5434#L1476-1 assume !(1 == ~E_3~0); 5435#L1481-1 assume !(1 == ~E_4~0); 5583#L1486-1 assume !(1 == ~E_5~0); 4289#L1491-1 assume !(1 == ~E_6~0); 3929#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3930#L1501-1 assume !(1 == ~E_8~0); 4741#L1506-1 assume !(1 == ~E_9~0); 4742#L1511-1 assume !(1 == ~E_10~0); 4698#L1516-1 assume !(1 == ~E_11~0); 3873#L1521-1 assume !(1 == ~E_12~0); 3874#L1526-1 assume !(1 == ~E_13~0); 3928#L1531-1 assume { :end_inline_reset_delta_events } true; 4471#L1892-2 [2022-11-16 10:56:55,631 INFO L750 eck$LassoCheckResult]: Loop: 4471#L1892-2 assume !false; 5494#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5692#L1233 assume !false; 5675#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5007#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4987#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5145#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3971#L1046 assume !(0 != eval_~tmp~0#1); 3973#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4007#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5179#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5736#L1258-5 assume !(0 == ~T1_E~0); 4149#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4150#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5728#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5734#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5735#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4373#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4374#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5491#L1298-3 assume !(0 == ~T9_E~0); 5492#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5651#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5490#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4991#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4151#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4152#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5575#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4294#L1338-3 assume !(0 == ~E_4~0); 4295#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5407#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5580#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5581#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4947#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4507#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4508#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5264#L1378-3 assume !(0 == ~E_12~0); 5265#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5446#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5447#L607-42 assume 1 == ~m_pc~0; 5060#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4788#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4789#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4521#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4522#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5043#L626-42 assume 1 == ~t1_pc~0; 4605#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4606#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4910#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4911#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4185#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4186#L645-42 assume !(1 == ~t2_pc~0); 5385#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5386#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5551#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4392#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3899#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3900#L664-42 assume !(1 == ~t3_pc~0); 4426#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4427#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5678#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5213#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5214#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5379#L683-42 assume 1 == ~t4_pc~0; 5744#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5088#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5220#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5640#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5641#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5485#L702-42 assume !(1 == ~t5_pc~0); 4597#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4598#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4894#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5567#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 3915#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3916#L721-42 assume 1 == ~t6_pc~0; 4069#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4089#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4553#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5720#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4725#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4571#L740-42 assume !(1 == ~t7_pc~0); 4308#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4309#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4850#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4705#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4706#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4979#L759-42 assume 1 == ~t8_pc~0; 4828#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4760#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4761#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4839#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4840#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4935#L778-42 assume 1 == ~t9_pc~0; 4772#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4774#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5184#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5089#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5090#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5147#L797-42 assume 1 == ~t10_pc~0; 4314#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4315#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5316#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5625#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5185#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5186#L816-42 assume 1 == ~t11_pc~0; 3863#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3864#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4406#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4407#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4486#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4487#L835-42 assume 1 == ~t12_pc~0; 4891#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4784#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4461#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4462#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5544#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5328#L854-42 assume 1 == ~t13_pc~0; 5329#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4405#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4015#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4016#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4662#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4663#L1401-3 assume !(1 == ~M_E~0); 5441#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4252#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4116#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4117#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4716#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4717#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4292#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4293#L1436-3 assume !(1 == ~T8_E~0); 3879#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3880#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5469#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4800#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4453#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4454#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5731#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4393#L1476-3 assume !(1 == ~E_3~0); 4394#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4794#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4421#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4422#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4834#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4835#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5261#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5251#L1516-3 assume !(1 == ~E_11~0); 5252#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4951#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4952#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5346#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4228#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5121#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4762#L1911 assume !(0 == start_simulation_~tmp~3#1); 4763#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5285#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4353#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5223#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4057#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4058#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4287#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4288#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4471#L1892-2 [2022-11-16 10:56:55,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:55,632 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2022-11-16 10:56:55,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:55,632 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520016551] [2022-11-16 10:56:55,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:55,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:55,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:55,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:55,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:55,705 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520016551] [2022-11-16 10:56:55,705 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520016551] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:55,705 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:55,705 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:55,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447176154] [2022-11-16 10:56:55,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:55,706 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:55,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:55,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1475252753, now seen corresponding path program 1 times [2022-11-16 10:56:55,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:55,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031870192] [2022-11-16 10:56:55,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:55,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:55,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:55,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:55,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:55,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031870192] [2022-11-16 10:56:55,820 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031870192] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:55,820 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:55,820 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:55,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813722051] [2022-11-16 10:56:55,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:55,821 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:55,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:55,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:55,822 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:55,822 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:55,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:55,887 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-11-16 10:56:55,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2022-11-16 10:56:55,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:55,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-11-16 10:56:55,910 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:55,912 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:55,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2022-11-16 10:56:55,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:55,916 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-11-16 10:56:55,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2022-11-16 10:56:55,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:55,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:55,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-11-16 10:56:55,949 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-11-16 10:56:55,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:55,951 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-11-16 10:56:55,951 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 10:56:55,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2022-11-16 10:56:55,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:55,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:55,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:55,962 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:55,963 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:55,964 INFO L748 eck$LassoCheckResult]: Stem: 8544#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8364#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8080#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8081#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9257#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9258#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8216#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8217#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8671#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8506#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8507#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8283#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8284#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8682#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8859#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9013#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9050#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8294#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8295#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9470#L1258-2 assume !(0 == ~T1_E~0); 8589#L1263-1 assume !(0 == ~T2_E~0); 8590#L1268-1 assume !(0 == ~T3_E~0); 8893#L1273-1 assume !(0 == ~T4_E~0); 9452#L1278-1 assume !(0 == ~T5_E~0); 9313#L1283-1 assume !(0 == ~T6_E~0); 9314#L1288-1 assume !(0 == ~T7_E~0); 9550#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9538#L1298-1 assume !(0 == ~T9_E~0); 9464#L1303-1 assume !(0 == ~T10_E~0); 8109#L1308-1 assume !(0 == ~T11_E~0); 8051#L1313-1 assume !(0 == ~T12_E~0); 8052#L1318-1 assume !(0 == ~T13_E~0); 8058#L1323-1 assume !(0 == ~E_1~0); 8059#L1328-1 assume !(0 == ~E_2~0); 8226#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9185#L1338-1 assume !(0 == ~E_4~0); 9186#L1343-1 assume !(0 == ~E_5~0); 9287#L1348-1 assume !(0 == ~E_6~0); 9573#L1353-1 assume !(0 == ~E_7~0); 8912#L1358-1 assume !(0 == ~E_8~0); 8913#L1363-1 assume !(0 == ~E_9~0); 9203#L1368-1 assume !(0 == ~E_10~0); 7888#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7889#L1378-1 assume !(0 == ~E_12~0); 8175#L1383-1 assume !(0 == ~E_13~0); 8176#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8919#L607 assume 1 == ~m_pc~0; 8920#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8246#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9285#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8839#L1560 assume !(0 != activate_threads_~tmp~1#1); 8840#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8071#L626 assume !(1 == ~t1_pc~0); 8072#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8340#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8341#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8510#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 7971#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7972#L645 assume 1 == ~t2_pc~0; 8088#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8045#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8722#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8723#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8815#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8816#L664 assume 1 == ~t3_pc~0; 9572#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7812#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7813#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8471#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8472#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9480#L683 assume !(1 == ~t4_pc~0); 9035#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8987#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8988#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9022#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9146#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8765#L702 assume 1 == ~t5_pc~0; 8766#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8691#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9141#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9439#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9380#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7860#L721 assume !(1 == ~t6_pc~0); 7834#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7835#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7998#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8480#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8481#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9082#L740 assume 1 == ~t7_pc~0; 7909#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7722#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7723#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7712#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7713#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8416#L759 assume !(1 == ~t8_pc~0); 8417#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8446#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9139#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9140#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9271#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9549#L778 assume 1 == ~t9_pc~0; 9436#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7887#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7827#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7756#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7757#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8084#L797 assume !(1 == ~t10_pc~0); 8085#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8203#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9337#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8587#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8588#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8877#L816 assume 1 == ~t11_pc~0; 7792#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7793#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8548#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8487#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8488#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9012#L835 assume 1 == ~t12_pc~0; 8890#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7956#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7978#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8119#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8644#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8645#L854 assume !(1 == ~t13_pc~0); 8285#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8286#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8336#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7996#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 7997#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9376#L1401 assume !(1 == ~M_E~0); 8475#L1401-2 assume !(1 == ~T1_E~0); 8476#L1406-1 assume !(1 == ~T2_E~0); 9071#L1411-1 assume !(1 == ~T3_E~0); 9072#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8738#L1421-1 assume !(1 == ~T5_E~0); 8281#L1426-1 assume !(1 == ~T6_E~0); 8282#L1431-1 assume !(1 == ~T7_E~0); 7830#L1436-1 assume !(1 == ~T8_E~0); 7831#L1441-1 assume !(1 == ~T9_E~0); 8578#L1446-1 assume !(1 == ~T10_E~0); 8579#L1451-1 assume !(1 == ~T11_E~0); 9284#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8938#L1461-1 assume !(1 == ~T13_E~0); 8499#L1466-1 assume !(1 == ~E_1~0); 8500#L1471-1 assume !(1 == ~E_2~0); 9269#L1476-1 assume !(1 == ~E_3~0); 9270#L1481-1 assume !(1 == ~E_4~0); 9418#L1486-1 assume !(1 == ~E_5~0); 8124#L1491-1 assume !(1 == ~E_6~0); 7764#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7765#L1501-1 assume !(1 == ~E_8~0); 8576#L1506-1 assume !(1 == ~E_9~0); 8577#L1511-1 assume !(1 == ~E_10~0); 8533#L1516-1 assume !(1 == ~E_11~0); 7708#L1521-1 assume !(1 == ~E_12~0); 7709#L1526-1 assume !(1 == ~E_13~0); 7763#L1531-1 assume { :end_inline_reset_delta_events } true; 8306#L1892-2 [2022-11-16 10:56:55,965 INFO L750 eck$LassoCheckResult]: Loop: 8306#L1892-2 assume !false; 9329#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9527#L1233 assume !false; 9510#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8842#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8822#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8980#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7806#L1046 assume !(0 != eval_~tmp~0#1); 7808#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7842#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9014#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9571#L1258-5 assume !(0 == ~T1_E~0); 7984#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7985#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9563#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9569#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9570#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8208#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8209#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9326#L1298-3 assume !(0 == ~T9_E~0); 9327#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9486#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9325#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8826#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7986#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7987#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9410#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8129#L1338-3 assume !(0 == ~E_4~0); 8130#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9242#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9415#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9416#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8782#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8342#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8343#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9099#L1378-3 assume !(0 == ~E_12~0); 9100#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9281#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9282#L607-42 assume !(1 == ~m_pc~0); 8896#L607-44 is_master_triggered_~__retres1~0#1 := 0; 8623#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8624#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8356#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8357#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8878#L626-42 assume 1 == ~t1_pc~0; 8440#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8441#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8745#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8746#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8020#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8021#L645-42 assume !(1 == ~t2_pc~0); 9220#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9221#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9386#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8227#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7734#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7735#L664-42 assume !(1 == ~t3_pc~0); 8261#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8262#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9513#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9048#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9049#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9214#L683-42 assume !(1 == ~t4_pc~0); 8922#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8923#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9055#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9475#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9476#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9320#L702-42 assume !(1 == ~t5_pc~0); 8432#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 8433#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8729#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9402#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 7750#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7751#L721-42 assume 1 == ~t6_pc~0; 7904#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7924#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8388#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9555#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8560#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8406#L740-42 assume 1 == ~t7_pc~0; 8407#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8144#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8685#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8540#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8541#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8814#L759-42 assume 1 == ~t8_pc~0; 8663#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8595#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8596#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8674#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8675#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8770#L778-42 assume !(1 == ~t9_pc~0); 8608#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 8609#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9019#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8924#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8925#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8982#L797-42 assume 1 == ~t10_pc~0; 8149#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8150#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9151#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9460#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9020#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9021#L816-42 assume 1 == ~t11_pc~0; 7698#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7699#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8241#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8242#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8321#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8322#L835-42 assume 1 == ~t12_pc~0; 8726#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8619#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8296#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8297#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9379#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9163#L854-42 assume 1 == ~t13_pc~0; 9164#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8240#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 7850#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7851#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8497#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8498#L1401-3 assume !(1 == ~M_E~0); 9276#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8087#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7951#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7952#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8551#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8552#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8127#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8128#L1436-3 assume !(1 == ~T8_E~0); 7714#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7715#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9304#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8635#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8288#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8289#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9566#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8228#L1476-3 assume !(1 == ~E_3~0); 8229#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8629#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8256#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8257#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8669#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8670#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9096#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9086#L1516-3 assume !(1 == ~E_11~0); 9087#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8786#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8787#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9181#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8063#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8956#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8597#L1911 assume !(0 == start_simulation_~tmp~3#1); 8598#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9120#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8188#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9058#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7892#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7893#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8122#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8123#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8306#L1892-2 [2022-11-16 10:56:55,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:55,966 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2022-11-16 10:56:55,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:55,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771164779] [2022-11-16 10:56:55,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:55,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:55,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:56,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:56,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:56,082 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771164779] [2022-11-16 10:56:56,082 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771164779] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:56,082 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:56,083 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:56,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436275618] [2022-11-16 10:56:56,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:56,086 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:56,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:56,086 INFO L85 PathProgramCache]: Analyzing trace with hash 673979855, now seen corresponding path program 1 times [2022-11-16 10:56:56,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:56,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311546867] [2022-11-16 10:56:56,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:56,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:56,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:56,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:56,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:56,188 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311546867] [2022-11-16 10:56:56,189 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1311546867] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:56,189 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:56,189 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:56,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1736456061] [2022-11-16 10:56:56,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:56,191 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:56,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:56,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:56,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:56,192 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:56,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:56,237 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-11-16 10:56:56,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2022-11-16 10:56:56,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:56,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-11-16 10:56:56,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:56,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:56,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2022-11-16 10:56:56,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:56,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-11-16 10:56:56,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2022-11-16 10:56:56,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:56,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:56,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-11-16 10:56:56,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-11-16 10:56:56,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:56,300 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-11-16 10:56:56,300 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 10:56:56,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2022-11-16 10:56:56,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:56,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:56,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:56,312 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:56,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:56,313 INFO L748 eck$LassoCheckResult]: Stem: 12379#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12380#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12199#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11915#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11916#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13092#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13093#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12051#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12052#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12506#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12341#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12342#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12118#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12119#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12517#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12694#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12848#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12885#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12129#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12130#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13305#L1258-2 assume !(0 == ~T1_E~0); 12424#L1263-1 assume !(0 == ~T2_E~0); 12425#L1268-1 assume !(0 == ~T3_E~0); 12728#L1273-1 assume !(0 == ~T4_E~0); 13287#L1278-1 assume !(0 == ~T5_E~0); 13148#L1283-1 assume !(0 == ~T6_E~0); 13149#L1288-1 assume !(0 == ~T7_E~0); 13385#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13373#L1298-1 assume !(0 == ~T9_E~0); 13299#L1303-1 assume !(0 == ~T10_E~0); 11944#L1308-1 assume !(0 == ~T11_E~0); 11886#L1313-1 assume !(0 == ~T12_E~0); 11887#L1318-1 assume !(0 == ~T13_E~0); 11893#L1323-1 assume !(0 == ~E_1~0); 11894#L1328-1 assume !(0 == ~E_2~0); 12061#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13020#L1338-1 assume !(0 == ~E_4~0); 13021#L1343-1 assume !(0 == ~E_5~0); 13122#L1348-1 assume !(0 == ~E_6~0); 13408#L1353-1 assume !(0 == ~E_7~0); 12747#L1358-1 assume !(0 == ~E_8~0); 12748#L1363-1 assume !(0 == ~E_9~0); 13038#L1368-1 assume !(0 == ~E_10~0); 11723#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11724#L1378-1 assume !(0 == ~E_12~0); 12010#L1383-1 assume !(0 == ~E_13~0); 12011#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12754#L607 assume 1 == ~m_pc~0; 12755#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12081#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13120#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12674#L1560 assume !(0 != activate_threads_~tmp~1#1); 12675#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11906#L626 assume !(1 == ~t1_pc~0); 11907#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12175#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12176#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12345#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11806#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11807#L645 assume 1 == ~t2_pc~0; 11923#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11880#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12557#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12558#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12650#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12651#L664 assume 1 == ~t3_pc~0; 13407#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11647#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11648#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12306#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12307#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13315#L683 assume !(1 == ~t4_pc~0); 12870#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12822#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12823#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12857#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12981#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12600#L702 assume 1 == ~t5_pc~0; 12601#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12526#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12976#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13274#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13215#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11695#L721 assume !(1 == ~t6_pc~0); 11669#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11670#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11833#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12315#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12316#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12917#L740 assume 1 == ~t7_pc~0; 11744#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11557#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11558#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11547#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11548#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12251#L759 assume !(1 == ~t8_pc~0); 12252#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12281#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12974#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12975#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13106#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13384#L778 assume 1 == ~t9_pc~0; 13271#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11722#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11662#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11591#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11592#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11919#L797 assume !(1 == ~t10_pc~0); 11920#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12038#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13172#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12422#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12423#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12712#L816 assume 1 == ~t11_pc~0; 11627#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11628#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12383#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12322#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12323#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12847#L835 assume 1 == ~t12_pc~0; 12725#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11791#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11813#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11954#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12479#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12480#L854 assume !(1 == ~t13_pc~0); 12120#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12121#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12171#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11831#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11832#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13211#L1401 assume !(1 == ~M_E~0); 12310#L1401-2 assume !(1 == ~T1_E~0); 12311#L1406-1 assume !(1 == ~T2_E~0); 12906#L1411-1 assume !(1 == ~T3_E~0); 12907#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12573#L1421-1 assume !(1 == ~T5_E~0); 12116#L1426-1 assume !(1 == ~T6_E~0); 12117#L1431-1 assume !(1 == ~T7_E~0); 11665#L1436-1 assume !(1 == ~T8_E~0); 11666#L1441-1 assume !(1 == ~T9_E~0); 12413#L1446-1 assume !(1 == ~T10_E~0); 12414#L1451-1 assume !(1 == ~T11_E~0); 13119#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12773#L1461-1 assume !(1 == ~T13_E~0); 12334#L1466-1 assume !(1 == ~E_1~0); 12335#L1471-1 assume !(1 == ~E_2~0); 13104#L1476-1 assume !(1 == ~E_3~0); 13105#L1481-1 assume !(1 == ~E_4~0); 13253#L1486-1 assume !(1 == ~E_5~0); 11959#L1491-1 assume !(1 == ~E_6~0); 11599#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11600#L1501-1 assume !(1 == ~E_8~0); 12411#L1506-1 assume !(1 == ~E_9~0); 12412#L1511-1 assume !(1 == ~E_10~0); 12368#L1516-1 assume !(1 == ~E_11~0); 11543#L1521-1 assume !(1 == ~E_12~0); 11544#L1526-1 assume !(1 == ~E_13~0); 11598#L1531-1 assume { :end_inline_reset_delta_events } true; 12141#L1892-2 [2022-11-16 10:56:56,314 INFO L750 eck$LassoCheckResult]: Loop: 12141#L1892-2 assume !false; 13164#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13362#L1233 assume !false; 13345#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12677#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12657#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12815#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11641#L1046 assume !(0 != eval_~tmp~0#1); 11643#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11677#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12849#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13406#L1258-5 assume !(0 == ~T1_E~0); 11819#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11820#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13398#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13404#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13405#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12043#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12044#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13161#L1298-3 assume !(0 == ~T9_E~0); 13162#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13321#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13160#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12661#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11821#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11822#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13245#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11964#L1338-3 assume !(0 == ~E_4~0); 11965#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13077#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13250#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13251#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12617#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12177#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12178#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12934#L1378-3 assume !(0 == ~E_12~0); 12935#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13116#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13117#L607-42 assume 1 == ~m_pc~0; 12730#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12458#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12459#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12191#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12192#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12713#L626-42 assume 1 == ~t1_pc~0; 12275#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12276#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12580#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12581#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11855#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11856#L645-42 assume 1 == ~t2_pc~0; 13314#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13056#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13221#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12062#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11569#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11570#L664-42 assume !(1 == ~t3_pc~0); 12096#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12097#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13348#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12883#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12884#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13049#L683-42 assume !(1 == ~t4_pc~0); 12757#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12758#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12890#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13310#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13311#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13155#L702-42 assume 1 == ~t5_pc~0; 12643#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12268#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12564#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13237#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 11585#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11586#L721-42 assume 1 == ~t6_pc~0; 11739#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11759#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12223#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13390#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12395#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12241#L740-42 assume 1 == ~t7_pc~0; 12242#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11979#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12520#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12375#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12376#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12649#L759-42 assume 1 == ~t8_pc~0; 12498#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12430#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12431#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12509#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12510#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12605#L778-42 assume 1 == ~t9_pc~0; 12442#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12444#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12854#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12759#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12760#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12817#L797-42 assume 1 == ~t10_pc~0; 11984#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11985#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12986#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13295#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12855#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12856#L816-42 assume 1 == ~t11_pc~0; 11533#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11534#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12076#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12077#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12156#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12157#L835-42 assume 1 == ~t12_pc~0; 12561#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12454#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12131#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12132#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13214#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12998#L854-42 assume 1 == ~t13_pc~0; 12999#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12075#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11685#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11686#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12332#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12333#L1401-3 assume !(1 == ~M_E~0); 13111#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11922#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11786#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11787#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12386#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12387#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11962#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11963#L1436-3 assume !(1 == ~T8_E~0); 11549#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11550#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13139#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12470#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12123#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12124#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13401#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12063#L1476-3 assume !(1 == ~E_3~0); 12064#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12464#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12091#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12092#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12504#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12505#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12931#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12921#L1516-3 assume !(1 == ~E_11~0); 12922#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12621#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12622#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13016#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11898#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12791#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12432#L1911 assume !(0 == start_simulation_~tmp~3#1); 12433#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12955#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12023#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12893#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11727#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11728#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11957#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11958#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12141#L1892-2 [2022-11-16 10:56:56,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:56,315 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2022-11-16 10:56:56,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:56,316 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047463929] [2022-11-16 10:56:56,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:56,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:56,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:56,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:56,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:56,385 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047463929] [2022-11-16 10:56:56,386 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047463929] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:56,386 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:56,387 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:56,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763214722] [2022-11-16 10:56:56,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:56,391 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:56,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:56,392 INFO L85 PathProgramCache]: Analyzing trace with hash 1181403475, now seen corresponding path program 1 times [2022-11-16 10:56:56,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:56,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495857931] [2022-11-16 10:56:56,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:56,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:56,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:56,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:56,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:56,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1495857931] [2022-11-16 10:56:56,536 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1495857931] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:56,536 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:56,536 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:56,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271903314] [2022-11-16 10:56:56,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:56,537 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:56,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:56,539 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:56,539 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:56,539 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:56,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:56,589 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-11-16 10:56:56,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2022-11-16 10:56:56,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:56,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-11-16 10:56:56,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:56,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:56,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2022-11-16 10:56:56,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:56,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-11-16 10:56:56,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2022-11-16 10:56:56,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:56,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:56,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-11-16 10:56:56,650 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-11-16 10:56:56,651 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:56,651 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-11-16 10:56:56,652 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 10:56:56,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2022-11-16 10:56:56,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:56,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:56,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:56,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:56,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:56,666 INFO L748 eck$LassoCheckResult]: Stem: 16214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 16215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16034#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15750#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15751#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 16927#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16928#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15886#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15887#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16341#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16176#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16177#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15953#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15954#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16352#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16529#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16683#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16720#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 15964#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15965#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17140#L1258-2 assume !(0 == ~T1_E~0); 16259#L1263-1 assume !(0 == ~T2_E~0); 16260#L1268-1 assume !(0 == ~T3_E~0); 16563#L1273-1 assume !(0 == ~T4_E~0); 17122#L1278-1 assume !(0 == ~T5_E~0); 16983#L1283-1 assume !(0 == ~T6_E~0); 16984#L1288-1 assume !(0 == ~T7_E~0); 17220#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17208#L1298-1 assume !(0 == ~T9_E~0); 17134#L1303-1 assume !(0 == ~T10_E~0); 15779#L1308-1 assume !(0 == ~T11_E~0); 15721#L1313-1 assume !(0 == ~T12_E~0); 15722#L1318-1 assume !(0 == ~T13_E~0); 15728#L1323-1 assume !(0 == ~E_1~0); 15729#L1328-1 assume !(0 == ~E_2~0); 15896#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16855#L1338-1 assume !(0 == ~E_4~0); 16856#L1343-1 assume !(0 == ~E_5~0); 16957#L1348-1 assume !(0 == ~E_6~0); 17243#L1353-1 assume !(0 == ~E_7~0); 16582#L1358-1 assume !(0 == ~E_8~0); 16583#L1363-1 assume !(0 == ~E_9~0); 16873#L1368-1 assume !(0 == ~E_10~0); 15558#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15559#L1378-1 assume !(0 == ~E_12~0); 15845#L1383-1 assume !(0 == ~E_13~0); 15846#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16589#L607 assume 1 == ~m_pc~0; 16590#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15916#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16955#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16509#L1560 assume !(0 != activate_threads_~tmp~1#1); 16510#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15741#L626 assume !(1 == ~t1_pc~0); 15742#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16010#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16011#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16180#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15641#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15642#L645 assume 1 == ~t2_pc~0; 15758#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15715#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16392#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16393#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16485#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16486#L664 assume 1 == ~t3_pc~0; 17242#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15482#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15483#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16141#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16142#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17150#L683 assume !(1 == ~t4_pc~0); 16705#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16657#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16658#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16692#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16816#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16435#L702 assume 1 == ~t5_pc~0; 16436#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16361#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16811#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17109#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17050#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15530#L721 assume !(1 == ~t6_pc~0); 15504#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15505#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15668#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16150#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16151#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16752#L740 assume 1 == ~t7_pc~0; 15579#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15392#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15393#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15382#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15383#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16086#L759 assume !(1 == ~t8_pc~0); 16087#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16116#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16809#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16810#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 16941#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17219#L778 assume 1 == ~t9_pc~0; 17106#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15557#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15497#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15426#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15427#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15754#L797 assume !(1 == ~t10_pc~0); 15755#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15873#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17007#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16257#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16258#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16547#L816 assume 1 == ~t11_pc~0; 15462#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15463#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16218#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16157#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16158#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16682#L835 assume 1 == ~t12_pc~0; 16560#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15626#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15648#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15789#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16314#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16315#L854 assume !(1 == ~t13_pc~0); 15955#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 15956#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16006#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15666#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15667#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17046#L1401 assume !(1 == ~M_E~0); 16145#L1401-2 assume !(1 == ~T1_E~0); 16146#L1406-1 assume !(1 == ~T2_E~0); 16741#L1411-1 assume !(1 == ~T3_E~0); 16742#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16408#L1421-1 assume !(1 == ~T5_E~0); 15951#L1426-1 assume !(1 == ~T6_E~0); 15952#L1431-1 assume !(1 == ~T7_E~0); 15500#L1436-1 assume !(1 == ~T8_E~0); 15501#L1441-1 assume !(1 == ~T9_E~0); 16248#L1446-1 assume !(1 == ~T10_E~0); 16249#L1451-1 assume !(1 == ~T11_E~0); 16954#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16608#L1461-1 assume !(1 == ~T13_E~0); 16169#L1466-1 assume !(1 == ~E_1~0); 16170#L1471-1 assume !(1 == ~E_2~0); 16939#L1476-1 assume !(1 == ~E_3~0); 16940#L1481-1 assume !(1 == ~E_4~0); 17088#L1486-1 assume !(1 == ~E_5~0); 15794#L1491-1 assume !(1 == ~E_6~0); 15434#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15435#L1501-1 assume !(1 == ~E_8~0); 16246#L1506-1 assume !(1 == ~E_9~0); 16247#L1511-1 assume !(1 == ~E_10~0); 16203#L1516-1 assume !(1 == ~E_11~0); 15378#L1521-1 assume !(1 == ~E_12~0); 15379#L1526-1 assume !(1 == ~E_13~0); 15433#L1531-1 assume { :end_inline_reset_delta_events } true; 15976#L1892-2 [2022-11-16 10:56:56,666 INFO L750 eck$LassoCheckResult]: Loop: 15976#L1892-2 assume !false; 16999#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17197#L1233 assume !false; 17180#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16492#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16650#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15476#L1046 assume !(0 != eval_~tmp~0#1); 15478#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15512#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16684#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17241#L1258-5 assume !(0 == ~T1_E~0); 15654#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15655#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17233#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17239#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17240#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15878#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15879#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16996#L1298-3 assume !(0 == ~T9_E~0); 16997#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17156#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16995#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16496#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15656#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15657#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17080#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15799#L1338-3 assume !(0 == ~E_4~0); 15800#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16912#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17085#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17086#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16452#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16012#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16013#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16769#L1378-3 assume !(0 == ~E_12~0); 16770#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16951#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16952#L607-42 assume 1 == ~m_pc~0; 16565#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16293#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16294#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16026#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16027#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16548#L626-42 assume !(1 == ~t1_pc~0); 16112#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 16111#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16415#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16416#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15690#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15691#L645-42 assume !(1 == ~t2_pc~0); 16890#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 16891#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17056#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15897#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15404#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15405#L664-42 assume !(1 == ~t3_pc~0); 15931#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 15932#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17183#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16718#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16719#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16884#L683-42 assume !(1 == ~t4_pc~0); 16592#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 16593#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16725#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17145#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17146#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16990#L702-42 assume !(1 == ~t5_pc~0); 16102#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 16103#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16399#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17072#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 15420#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15421#L721-42 assume 1 == ~t6_pc~0; 15574#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15594#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16058#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17225#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16230#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16076#L740-42 assume !(1 == ~t7_pc~0); 15813#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 15814#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16355#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16210#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16211#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16484#L759-42 assume 1 == ~t8_pc~0; 16333#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16265#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16266#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16344#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16345#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16440#L778-42 assume 1 == ~t9_pc~0; 16277#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16279#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16689#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16594#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16595#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16652#L797-42 assume 1 == ~t10_pc~0; 15819#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15820#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16821#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17130#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16690#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16691#L816-42 assume 1 == ~t11_pc~0; 15368#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15369#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15911#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15912#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 15991#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15992#L835-42 assume !(1 == ~t12_pc~0); 16288#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16289#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15966#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15967#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17049#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16833#L854-42 assume 1 == ~t13_pc~0; 16834#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 15910#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 15520#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15521#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16167#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16168#L1401-3 assume !(1 == ~M_E~0); 16946#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15757#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15621#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15622#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16221#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16222#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15797#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15798#L1436-3 assume !(1 == ~T8_E~0); 15384#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15385#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16974#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16305#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15958#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 15959#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17236#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15898#L1476-3 assume !(1 == ~E_3~0); 15899#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16299#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15926#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15927#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16339#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16340#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16766#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16756#L1516-3 assume !(1 == ~E_11~0); 16757#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16456#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16457#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16851#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15733#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16626#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16267#L1911 assume !(0 == start_simulation_~tmp~3#1); 16268#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16790#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15858#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16728#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15562#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15563#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15792#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 15793#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 15976#L1892-2 [2022-11-16 10:56:56,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:56,667 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2022-11-16 10:56:56,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:56,668 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542239068] [2022-11-16 10:56:56,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:56,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:56,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:56,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:56,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:56,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542239068] [2022-11-16 10:56:56,725 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542239068] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:56,725 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:56,726 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:56,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858665377] [2022-11-16 10:56:56,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:56,726 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:56,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:56,727 INFO L85 PathProgramCache]: Analyzing trace with hash -1106627154, now seen corresponding path program 1 times [2022-11-16 10:56:56,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:56,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026057661] [2022-11-16 10:56:56,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:56,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:56,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:56,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:56,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:56,825 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026057661] [2022-11-16 10:56:56,826 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1026057661] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:56,826 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:56,826 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:56,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241369940] [2022-11-16 10:56:56,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:56,827 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:56,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:56,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:56,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:56,828 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:56,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:56,882 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-11-16 10:56:56,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2022-11-16 10:56:56,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:56,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-11-16 10:56:56,905 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:56,907 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:56,907 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2022-11-16 10:56:56,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:56,910 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-11-16 10:56:56,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2022-11-16 10:56:56,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:56,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:56,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-11-16 10:56:56,953 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-11-16 10:56:56,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:56,955 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-11-16 10:56:56,955 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 10:56:56,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2022-11-16 10:56:56,964 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:56,964 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:56,964 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:56,968 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:56,968 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:56,968 INFO L748 eck$LassoCheckResult]: Stem: 20049#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 20050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 19869#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19585#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19586#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20762#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20763#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19721#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19722#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20176#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20011#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20012#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19788#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19789#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20187#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20364#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20518#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20555#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19799#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19800#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20975#L1258-2 assume !(0 == ~T1_E~0); 20094#L1263-1 assume !(0 == ~T2_E~0); 20095#L1268-1 assume !(0 == ~T3_E~0); 20398#L1273-1 assume !(0 == ~T4_E~0); 20957#L1278-1 assume !(0 == ~T5_E~0); 20818#L1283-1 assume !(0 == ~T6_E~0); 20819#L1288-1 assume !(0 == ~T7_E~0); 21055#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21043#L1298-1 assume !(0 == ~T9_E~0); 20969#L1303-1 assume !(0 == ~T10_E~0); 19614#L1308-1 assume !(0 == ~T11_E~0); 19556#L1313-1 assume !(0 == ~T12_E~0); 19557#L1318-1 assume !(0 == ~T13_E~0); 19563#L1323-1 assume !(0 == ~E_1~0); 19564#L1328-1 assume !(0 == ~E_2~0); 19731#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20690#L1338-1 assume !(0 == ~E_4~0); 20691#L1343-1 assume !(0 == ~E_5~0); 20792#L1348-1 assume !(0 == ~E_6~0); 21078#L1353-1 assume !(0 == ~E_7~0); 20417#L1358-1 assume !(0 == ~E_8~0); 20418#L1363-1 assume !(0 == ~E_9~0); 20708#L1368-1 assume !(0 == ~E_10~0); 19393#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19394#L1378-1 assume !(0 == ~E_12~0); 19680#L1383-1 assume !(0 == ~E_13~0); 19681#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20424#L607 assume 1 == ~m_pc~0; 20425#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19751#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20790#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20344#L1560 assume !(0 != activate_threads_~tmp~1#1); 20345#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19576#L626 assume !(1 == ~t1_pc~0); 19577#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19845#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19846#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20015#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19476#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19477#L645 assume 1 == ~t2_pc~0; 19593#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19550#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20227#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20228#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20320#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20321#L664 assume 1 == ~t3_pc~0; 21077#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19317#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19318#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19976#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19977#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20985#L683 assume !(1 == ~t4_pc~0); 20540#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20492#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20493#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20527#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20651#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20270#L702 assume 1 == ~t5_pc~0; 20271#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20196#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20646#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20944#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20885#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19365#L721 assume !(1 == ~t6_pc~0); 19339#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19340#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19503#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19985#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19986#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20587#L740 assume 1 == ~t7_pc~0; 19414#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19227#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19228#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19217#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19218#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19921#L759 assume !(1 == ~t8_pc~0); 19922#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19951#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20644#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20645#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20776#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21054#L778 assume 1 == ~t9_pc~0; 20941#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19392#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19332#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19261#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19262#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19589#L797 assume !(1 == ~t10_pc~0); 19590#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19708#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20842#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20092#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20093#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20382#L816 assume 1 == ~t11_pc~0; 19297#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19298#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20053#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19992#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19993#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20517#L835 assume 1 == ~t12_pc~0; 20395#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19461#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19483#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19624#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20149#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20150#L854 assume !(1 == ~t13_pc~0); 19790#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19791#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19841#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19501#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19502#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20881#L1401 assume !(1 == ~M_E~0); 19980#L1401-2 assume !(1 == ~T1_E~0); 19981#L1406-1 assume !(1 == ~T2_E~0); 20576#L1411-1 assume !(1 == ~T3_E~0); 20577#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20243#L1421-1 assume !(1 == ~T5_E~0); 19786#L1426-1 assume !(1 == ~T6_E~0); 19787#L1431-1 assume !(1 == ~T7_E~0); 19335#L1436-1 assume !(1 == ~T8_E~0); 19336#L1441-1 assume !(1 == ~T9_E~0); 20083#L1446-1 assume !(1 == ~T10_E~0); 20084#L1451-1 assume !(1 == ~T11_E~0); 20789#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20443#L1461-1 assume !(1 == ~T13_E~0); 20004#L1466-1 assume !(1 == ~E_1~0); 20005#L1471-1 assume !(1 == ~E_2~0); 20774#L1476-1 assume !(1 == ~E_3~0); 20775#L1481-1 assume !(1 == ~E_4~0); 20923#L1486-1 assume !(1 == ~E_5~0); 19629#L1491-1 assume !(1 == ~E_6~0); 19269#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19270#L1501-1 assume !(1 == ~E_8~0); 20081#L1506-1 assume !(1 == ~E_9~0); 20082#L1511-1 assume !(1 == ~E_10~0); 20038#L1516-1 assume !(1 == ~E_11~0); 19213#L1521-1 assume !(1 == ~E_12~0); 19214#L1526-1 assume !(1 == ~E_13~0); 19268#L1531-1 assume { :end_inline_reset_delta_events } true; 19811#L1892-2 [2022-11-16 10:56:56,969 INFO L750 eck$LassoCheckResult]: Loop: 19811#L1892-2 assume !false; 20834#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21032#L1233 assume !false; 21015#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20347#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20327#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20485#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19311#L1046 assume !(0 != eval_~tmp~0#1); 19313#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19347#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20519#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21076#L1258-5 assume !(0 == ~T1_E~0); 19489#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19490#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21068#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21074#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21075#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19713#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19714#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20831#L1298-3 assume !(0 == ~T9_E~0); 20832#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20991#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20830#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20331#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19491#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19492#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20915#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19634#L1338-3 assume !(0 == ~E_4~0); 19635#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20747#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20920#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20921#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20287#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19847#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19848#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20604#L1378-3 assume !(0 == ~E_12~0); 20605#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20786#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20787#L607-42 assume 1 == ~m_pc~0; 20400#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20128#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20129#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19861#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19862#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20383#L626-42 assume 1 == ~t1_pc~0; 19945#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19946#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20250#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20251#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19525#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19526#L645-42 assume !(1 == ~t2_pc~0); 20725#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20726#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20891#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19732#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19239#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19240#L664-42 assume !(1 == ~t3_pc~0); 19766#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19767#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21018#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20553#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20554#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20719#L683-42 assume !(1 == ~t4_pc~0); 20427#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20428#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20560#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20980#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20981#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20825#L702-42 assume !(1 == ~t5_pc~0); 19937#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 19938#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20234#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20907#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 19255#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19256#L721-42 assume 1 == ~t6_pc~0; 19409#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19429#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19893#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21060#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20065#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19911#L740-42 assume !(1 == ~t7_pc~0); 19648#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19649#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20190#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20045#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20046#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20319#L759-42 assume 1 == ~t8_pc~0; 20168#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20100#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20101#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20179#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20180#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20275#L778-42 assume 1 == ~t9_pc~0; 20112#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20114#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20524#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20429#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20430#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20487#L797-42 assume 1 == ~t10_pc~0; 19654#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19655#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20656#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20965#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20525#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20526#L816-42 assume 1 == ~t11_pc~0; 19203#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19204#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19746#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19747#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19826#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19827#L835-42 assume 1 == ~t12_pc~0; 20231#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20124#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19801#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19802#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20884#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20668#L854-42 assume !(1 == ~t13_pc~0); 19744#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 19745#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19355#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19356#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20002#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20003#L1401-3 assume !(1 == ~M_E~0); 20781#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19592#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19456#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19457#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20056#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20057#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19632#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19633#L1436-3 assume !(1 == ~T8_E~0); 19219#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19220#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20809#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20140#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19793#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 19794#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21071#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19733#L1476-3 assume !(1 == ~E_3~0); 19734#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20134#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19761#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19762#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20174#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20175#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20601#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20591#L1516-3 assume !(1 == ~E_11~0); 20592#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20291#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20292#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20686#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19568#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20461#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 20102#L1911 assume !(0 == start_simulation_~tmp~3#1); 20103#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20625#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19693#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20563#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19397#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19398#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19627#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19628#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19811#L1892-2 [2022-11-16 10:56:56,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:56,971 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2022-11-16 10:56:56,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:56,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290978287] [2022-11-16 10:56:56,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:56,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:56,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:57,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:57,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:57,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290978287] [2022-11-16 10:56:57,038 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290978287] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:57,039 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:57,039 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:57,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55683824] [2022-11-16 10:56:57,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:57,040 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:57,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:57,040 INFO L85 PathProgramCache]: Analyzing trace with hash -835808881, now seen corresponding path program 1 times [2022-11-16 10:56:57,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:57,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922518672] [2022-11-16 10:56:57,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:57,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:57,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:57,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:57,127 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:57,127 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922518672] [2022-11-16 10:56:57,127 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1922518672] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:57,127 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:57,127 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:57,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259921484] [2022-11-16 10:56:57,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:57,128 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:57,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:57,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:57,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:57,129 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:57,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:57,170 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-11-16 10:56:57,170 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2022-11-16 10:56:57,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:57,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-11-16 10:56:57,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:57,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:57,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2022-11-16 10:56:57,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:57,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-11-16 10:56:57,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2022-11-16 10:56:57,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:57,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:57,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-11-16 10:56:57,229 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-11-16 10:56:57,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:57,230 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-11-16 10:56:57,230 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-16 10:56:57,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2022-11-16 10:56:57,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:57,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:57,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:57,240 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:57,240 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:57,241 INFO L748 eck$LassoCheckResult]: Stem: 23884#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23885#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 23704#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23420#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23421#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24597#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24598#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23556#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23557#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24011#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23846#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23847#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23623#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23624#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24022#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24199#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24353#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24390#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23634#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23635#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 24810#L1258-2 assume !(0 == ~T1_E~0); 23929#L1263-1 assume !(0 == ~T2_E~0); 23930#L1268-1 assume !(0 == ~T3_E~0); 24233#L1273-1 assume !(0 == ~T4_E~0); 24792#L1278-1 assume !(0 == ~T5_E~0); 24653#L1283-1 assume !(0 == ~T6_E~0); 24654#L1288-1 assume !(0 == ~T7_E~0); 24890#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24878#L1298-1 assume !(0 == ~T9_E~0); 24804#L1303-1 assume !(0 == ~T10_E~0); 23449#L1308-1 assume !(0 == ~T11_E~0); 23391#L1313-1 assume !(0 == ~T12_E~0); 23392#L1318-1 assume !(0 == ~T13_E~0); 23398#L1323-1 assume !(0 == ~E_1~0); 23399#L1328-1 assume !(0 == ~E_2~0); 23566#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24525#L1338-1 assume !(0 == ~E_4~0); 24526#L1343-1 assume !(0 == ~E_5~0); 24627#L1348-1 assume !(0 == ~E_6~0); 24913#L1353-1 assume !(0 == ~E_7~0); 24252#L1358-1 assume !(0 == ~E_8~0); 24253#L1363-1 assume !(0 == ~E_9~0); 24543#L1368-1 assume !(0 == ~E_10~0); 23228#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23229#L1378-1 assume !(0 == ~E_12~0); 23515#L1383-1 assume !(0 == ~E_13~0); 23516#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24259#L607 assume 1 == ~m_pc~0; 24260#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23586#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24625#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24179#L1560 assume !(0 != activate_threads_~tmp~1#1); 24180#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23411#L626 assume !(1 == ~t1_pc~0); 23412#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23680#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23681#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23850#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23311#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23312#L645 assume 1 == ~t2_pc~0; 23428#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23385#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24062#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24063#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24155#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24156#L664 assume 1 == ~t3_pc~0; 24912#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23152#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23153#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23811#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23812#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24820#L683 assume !(1 == ~t4_pc~0); 24375#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24327#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24328#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24362#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24486#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24105#L702 assume 1 == ~t5_pc~0; 24106#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24031#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24481#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24779#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24720#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23200#L721 assume !(1 == ~t6_pc~0); 23174#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23175#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23338#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23820#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23821#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24422#L740 assume 1 == ~t7_pc~0; 23249#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23062#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23063#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23052#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23053#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23756#L759 assume !(1 == ~t8_pc~0); 23757#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23786#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24479#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24480#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24611#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24889#L778 assume 1 == ~t9_pc~0; 24776#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23227#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23167#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23096#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23097#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23424#L797 assume !(1 == ~t10_pc~0); 23425#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23543#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24677#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23927#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 23928#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24217#L816 assume 1 == ~t11_pc~0; 23132#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23133#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23888#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23827#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23828#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24352#L835 assume 1 == ~t12_pc~0; 24230#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23296#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23318#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23459#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 23984#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 23985#L854 assume !(1 == ~t13_pc~0); 23625#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23626#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23676#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23336#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23337#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24716#L1401 assume !(1 == ~M_E~0); 23815#L1401-2 assume !(1 == ~T1_E~0); 23816#L1406-1 assume !(1 == ~T2_E~0); 24411#L1411-1 assume !(1 == ~T3_E~0); 24412#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24078#L1421-1 assume !(1 == ~T5_E~0); 23621#L1426-1 assume !(1 == ~T6_E~0); 23622#L1431-1 assume !(1 == ~T7_E~0); 23170#L1436-1 assume !(1 == ~T8_E~0); 23171#L1441-1 assume !(1 == ~T9_E~0); 23918#L1446-1 assume !(1 == ~T10_E~0); 23919#L1451-1 assume !(1 == ~T11_E~0); 24624#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24278#L1461-1 assume !(1 == ~T13_E~0); 23839#L1466-1 assume !(1 == ~E_1~0); 23840#L1471-1 assume !(1 == ~E_2~0); 24609#L1476-1 assume !(1 == ~E_3~0); 24610#L1481-1 assume !(1 == ~E_4~0); 24758#L1486-1 assume !(1 == ~E_5~0); 23464#L1491-1 assume !(1 == ~E_6~0); 23104#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23105#L1501-1 assume !(1 == ~E_8~0); 23916#L1506-1 assume !(1 == ~E_9~0); 23917#L1511-1 assume !(1 == ~E_10~0); 23873#L1516-1 assume !(1 == ~E_11~0); 23048#L1521-1 assume !(1 == ~E_12~0); 23049#L1526-1 assume !(1 == ~E_13~0); 23103#L1531-1 assume { :end_inline_reset_delta_events } true; 23646#L1892-2 [2022-11-16 10:56:57,241 INFO L750 eck$LassoCheckResult]: Loop: 23646#L1892-2 assume !false; 24669#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24867#L1233 assume !false; 24850#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24182#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24162#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24320#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23146#L1046 assume !(0 != eval_~tmp~0#1); 23148#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23182#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24354#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24911#L1258-5 assume !(0 == ~T1_E~0); 23324#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23325#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24903#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24909#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24910#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23548#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23549#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24666#L1298-3 assume !(0 == ~T9_E~0); 24667#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24826#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24665#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24166#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23326#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23327#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24750#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23469#L1338-3 assume !(0 == ~E_4~0); 23470#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24582#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24755#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24756#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24122#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23682#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23683#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24439#L1378-3 assume !(0 == ~E_12~0); 24440#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24621#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24622#L607-42 assume 1 == ~m_pc~0; 24235#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23963#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23964#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23696#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23697#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24218#L626-42 assume 1 == ~t1_pc~0; 23780#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23781#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24085#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24086#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23360#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23361#L645-42 assume !(1 == ~t2_pc~0); 24560#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 24561#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24726#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23567#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23074#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23075#L664-42 assume !(1 == ~t3_pc~0); 23601#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 23602#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24853#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24388#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24389#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24554#L683-42 assume !(1 == ~t4_pc~0); 24262#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24263#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24395#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24815#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24816#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24660#L702-42 assume 1 == ~t5_pc~0; 24148#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23773#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24069#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24742#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 23090#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23091#L721-42 assume 1 == ~t6_pc~0; 23244#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23264#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23728#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24895#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23900#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23746#L740-42 assume 1 == ~t7_pc~0; 23747#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23484#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24025#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23880#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23881#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24154#L759-42 assume 1 == ~t8_pc~0; 24003#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23935#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23936#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24014#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24015#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24110#L778-42 assume 1 == ~t9_pc~0; 23947#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23949#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24359#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24264#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24265#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24322#L797-42 assume 1 == ~t10_pc~0; 23489#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23490#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24491#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24800#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24360#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24361#L816-42 assume !(1 == ~t11_pc~0); 23040#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 23039#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23581#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23582#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23661#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23662#L835-42 assume 1 == ~t12_pc~0; 24066#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23959#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23636#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23637#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24719#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24503#L854-42 assume 1 == ~t13_pc~0; 24504#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 23580#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23190#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23191#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23837#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23838#L1401-3 assume !(1 == ~M_E~0); 24616#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23427#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23291#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23292#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23891#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23892#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23467#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23468#L1436-3 assume !(1 == ~T8_E~0); 23054#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23055#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24644#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23975#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23628#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 23629#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24906#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23568#L1476-3 assume !(1 == ~E_3~0); 23569#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23969#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23596#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23597#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24009#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24010#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24436#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24426#L1516-3 assume !(1 == ~E_11~0); 24427#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24126#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24127#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24521#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23403#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24296#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23937#L1911 assume !(0 == start_simulation_~tmp~3#1); 23938#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24460#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23528#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24398#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23232#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23233#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23462#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 23463#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23646#L1892-2 [2022-11-16 10:56:57,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:57,242 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2022-11-16 10:56:57,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:57,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1499230945] [2022-11-16 10:56:57,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:57,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:57,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:57,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:57,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:57,295 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1499230945] [2022-11-16 10:56:57,295 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1499230945] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:57,295 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:57,295 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:57,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345972281] [2022-11-16 10:56:57,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:57,296 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:57,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:57,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1042381777, now seen corresponding path program 1 times [2022-11-16 10:56:57,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:57,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529961035] [2022-11-16 10:56:57,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:57,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:57,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:57,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:57,363 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:57,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529961035] [2022-11-16 10:56:57,364 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529961035] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:57,364 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:57,364 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:57,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625832911] [2022-11-16 10:56:57,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:57,365 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:57,365 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:57,365 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:57,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:57,366 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:57,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:57,410 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-11-16 10:56:57,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2022-11-16 10:56:57,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:57,460 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-11-16 10:56:57,460 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:57,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:57,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2022-11-16 10:56:57,464 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:57,464 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-11-16 10:56:57,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2022-11-16 10:56:57,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:57,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:57,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-11-16 10:56:57,499 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-11-16 10:56:57,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:57,500 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-11-16 10:56:57,500 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-16 10:56:57,500 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2022-11-16 10:56:57,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:57,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:57,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:57,510 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:57,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:57,510 INFO L748 eck$LassoCheckResult]: Stem: 27719#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 27539#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27255#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27256#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28432#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28433#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27391#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27392#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27846#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27681#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27682#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27458#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27459#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27857#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28034#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28188#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28225#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27469#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27470#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28645#L1258-2 assume !(0 == ~T1_E~0); 27764#L1263-1 assume !(0 == ~T2_E~0); 27765#L1268-1 assume !(0 == ~T3_E~0); 28068#L1273-1 assume !(0 == ~T4_E~0); 28627#L1278-1 assume !(0 == ~T5_E~0); 28488#L1283-1 assume !(0 == ~T6_E~0); 28489#L1288-1 assume !(0 == ~T7_E~0); 28725#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28713#L1298-1 assume !(0 == ~T9_E~0); 28639#L1303-1 assume !(0 == ~T10_E~0); 27284#L1308-1 assume !(0 == ~T11_E~0); 27226#L1313-1 assume !(0 == ~T12_E~0); 27227#L1318-1 assume !(0 == ~T13_E~0); 27233#L1323-1 assume !(0 == ~E_1~0); 27234#L1328-1 assume !(0 == ~E_2~0); 27401#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28360#L1338-1 assume !(0 == ~E_4~0); 28361#L1343-1 assume !(0 == ~E_5~0); 28462#L1348-1 assume !(0 == ~E_6~0); 28748#L1353-1 assume !(0 == ~E_7~0); 28087#L1358-1 assume !(0 == ~E_8~0); 28088#L1363-1 assume !(0 == ~E_9~0); 28378#L1368-1 assume !(0 == ~E_10~0); 27063#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27064#L1378-1 assume !(0 == ~E_12~0); 27350#L1383-1 assume !(0 == ~E_13~0); 27351#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28094#L607 assume 1 == ~m_pc~0; 28095#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27421#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28460#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28014#L1560 assume !(0 != activate_threads_~tmp~1#1); 28015#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27246#L626 assume !(1 == ~t1_pc~0); 27247#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27515#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27516#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27685#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27146#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27147#L645 assume 1 == ~t2_pc~0; 27263#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27220#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27897#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27898#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27990#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27991#L664 assume 1 == ~t3_pc~0; 28747#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26987#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26988#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27646#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27647#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28655#L683 assume !(1 == ~t4_pc~0); 28210#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28162#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28163#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28197#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28321#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27940#L702 assume 1 == ~t5_pc~0; 27941#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27866#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28316#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28614#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28555#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27035#L721 assume !(1 == ~t6_pc~0); 27009#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27010#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27173#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27655#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27656#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28257#L740 assume 1 == ~t7_pc~0; 27084#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26897#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26898#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26887#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26888#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27591#L759 assume !(1 == ~t8_pc~0); 27592#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27621#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28314#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28315#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28446#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28724#L778 assume 1 == ~t9_pc~0; 28611#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27062#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27002#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26931#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26932#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27259#L797 assume !(1 == ~t10_pc~0); 27260#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27378#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28512#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27762#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27763#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28052#L816 assume 1 == ~t11_pc~0; 26967#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26968#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27723#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27662#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27663#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28187#L835 assume 1 == ~t12_pc~0; 28065#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27131#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27153#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27294#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27819#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27820#L854 assume !(1 == ~t13_pc~0); 27460#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27461#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27511#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27171#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27172#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28551#L1401 assume !(1 == ~M_E~0); 27650#L1401-2 assume !(1 == ~T1_E~0); 27651#L1406-1 assume !(1 == ~T2_E~0); 28246#L1411-1 assume !(1 == ~T3_E~0); 28247#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27913#L1421-1 assume !(1 == ~T5_E~0); 27456#L1426-1 assume !(1 == ~T6_E~0); 27457#L1431-1 assume !(1 == ~T7_E~0); 27005#L1436-1 assume !(1 == ~T8_E~0); 27006#L1441-1 assume !(1 == ~T9_E~0); 27753#L1446-1 assume !(1 == ~T10_E~0); 27754#L1451-1 assume !(1 == ~T11_E~0); 28459#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28113#L1461-1 assume !(1 == ~T13_E~0); 27674#L1466-1 assume !(1 == ~E_1~0); 27675#L1471-1 assume !(1 == ~E_2~0); 28444#L1476-1 assume !(1 == ~E_3~0); 28445#L1481-1 assume !(1 == ~E_4~0); 28593#L1486-1 assume !(1 == ~E_5~0); 27299#L1491-1 assume !(1 == ~E_6~0); 26939#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26940#L1501-1 assume !(1 == ~E_8~0); 27751#L1506-1 assume !(1 == ~E_9~0); 27752#L1511-1 assume !(1 == ~E_10~0); 27708#L1516-1 assume !(1 == ~E_11~0); 26883#L1521-1 assume !(1 == ~E_12~0); 26884#L1526-1 assume !(1 == ~E_13~0); 26938#L1531-1 assume { :end_inline_reset_delta_events } true; 27481#L1892-2 [2022-11-16 10:56:57,511 INFO L750 eck$LassoCheckResult]: Loop: 27481#L1892-2 assume !false; 28504#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28702#L1233 assume !false; 28685#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28017#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27997#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28155#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26981#L1046 assume !(0 != eval_~tmp~0#1); 26983#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27017#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28189#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28746#L1258-5 assume !(0 == ~T1_E~0); 27159#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27160#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28738#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28744#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28745#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27383#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27384#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28501#L1298-3 assume !(0 == ~T9_E~0); 28502#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28661#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28500#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28001#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27161#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27162#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28585#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27304#L1338-3 assume !(0 == ~E_4~0); 27305#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28417#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28590#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28591#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27957#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27517#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27518#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28274#L1378-3 assume !(0 == ~E_12~0); 28275#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28456#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28457#L607-42 assume 1 == ~m_pc~0; 28070#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27798#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27799#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27531#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27532#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28053#L626-42 assume !(1 == ~t1_pc~0); 27617#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 27616#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27920#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27921#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27195#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27196#L645-42 assume !(1 == ~t2_pc~0); 28395#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 28396#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28561#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27402#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26909#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26910#L664-42 assume 1 == ~t3_pc~0; 27712#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27437#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28688#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28223#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28224#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28389#L683-42 assume !(1 == ~t4_pc~0); 28097#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28098#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28230#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28650#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28651#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28495#L702-42 assume !(1 == ~t5_pc~0); 27607#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 27608#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27904#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28577#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 26925#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26926#L721-42 assume 1 == ~t6_pc~0; 27079#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27099#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27563#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28730#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27735#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27581#L740-42 assume !(1 == ~t7_pc~0); 27318#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 27319#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27860#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27715#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27716#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27989#L759-42 assume 1 == ~t8_pc~0; 27838#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27770#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27771#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27849#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27850#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27945#L778-42 assume 1 == ~t9_pc~0; 27782#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27784#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28194#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28099#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28100#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28157#L797-42 assume 1 == ~t10_pc~0; 27324#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27325#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28326#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28635#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28195#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28196#L816-42 assume 1 == ~t11_pc~0; 26873#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26874#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27416#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27417#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27496#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27497#L835-42 assume !(1 == ~t12_pc~0); 27793#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 27794#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27471#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27472#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28554#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28338#L854-42 assume 1 == ~t13_pc~0; 28339#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27415#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27025#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27026#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27672#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27673#L1401-3 assume !(1 == ~M_E~0); 28451#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27262#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27126#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27127#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27726#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27727#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27302#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27303#L1436-3 assume !(1 == ~T8_E~0); 26889#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26890#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28479#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27810#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27463#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 27464#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28741#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27403#L1476-3 assume !(1 == ~E_3~0); 27404#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27804#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27431#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27432#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27844#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27845#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28271#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28261#L1516-3 assume !(1 == ~E_11~0); 28262#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27961#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27962#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28356#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27238#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28131#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27772#L1911 assume !(0 == start_simulation_~tmp~3#1); 27773#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28295#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27363#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28233#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27067#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27068#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27297#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 27298#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27481#L1892-2 [2022-11-16 10:56:57,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:57,512 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2022-11-16 10:56:57,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:57,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952718104] [2022-11-16 10:56:57,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:57,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:57,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:57,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:57,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:57,563 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952718104] [2022-11-16 10:56:57,564 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952718104] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:57,564 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:57,564 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:57,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922223639] [2022-11-16 10:56:57,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:57,565 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:57,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:57,565 INFO L85 PathProgramCache]: Analyzing trace with hash -1427949617, now seen corresponding path program 1 times [2022-11-16 10:56:57,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:57,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826361197] [2022-11-16 10:56:57,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:57,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:57,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:57,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:57,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:57,631 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826361197] [2022-11-16 10:56:57,631 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826361197] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:57,631 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:57,631 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:57,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988884150] [2022-11-16 10:56:57,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:57,632 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:57,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:57,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:57,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:57,633 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:57,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:57,675 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-11-16 10:56:57,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2022-11-16 10:56:57,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:57,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-11-16 10:56:57,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:57,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:57,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2022-11-16 10:56:57,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:57,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-11-16 10:56:57,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2022-11-16 10:56:57,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:57,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:57,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-11-16 10:56:57,731 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-11-16 10:56:57,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:57,732 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-11-16 10:56:57,732 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-16 10:56:57,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2022-11-16 10:56:57,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:57,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:57,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:57,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:57,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:57,743 INFO L748 eck$LassoCheckResult]: Stem: 31554#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 31374#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31090#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31091#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32267#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32268#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31226#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31227#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31681#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31516#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31517#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31293#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31294#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31692#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31869#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32023#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32060#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31304#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31305#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32480#L1258-2 assume !(0 == ~T1_E~0); 31599#L1263-1 assume !(0 == ~T2_E~0); 31600#L1268-1 assume !(0 == ~T3_E~0); 31903#L1273-1 assume !(0 == ~T4_E~0); 32462#L1278-1 assume !(0 == ~T5_E~0); 32323#L1283-1 assume !(0 == ~T6_E~0); 32324#L1288-1 assume !(0 == ~T7_E~0); 32560#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32548#L1298-1 assume !(0 == ~T9_E~0); 32474#L1303-1 assume !(0 == ~T10_E~0); 31119#L1308-1 assume !(0 == ~T11_E~0); 31061#L1313-1 assume !(0 == ~T12_E~0); 31062#L1318-1 assume !(0 == ~T13_E~0); 31068#L1323-1 assume !(0 == ~E_1~0); 31069#L1328-1 assume !(0 == ~E_2~0); 31236#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32195#L1338-1 assume !(0 == ~E_4~0); 32196#L1343-1 assume !(0 == ~E_5~0); 32297#L1348-1 assume !(0 == ~E_6~0); 32583#L1353-1 assume !(0 == ~E_7~0); 31922#L1358-1 assume !(0 == ~E_8~0); 31923#L1363-1 assume !(0 == ~E_9~0); 32213#L1368-1 assume !(0 == ~E_10~0); 30898#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 30899#L1378-1 assume !(0 == ~E_12~0); 31185#L1383-1 assume !(0 == ~E_13~0); 31186#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31929#L607 assume 1 == ~m_pc~0; 31930#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31256#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32295#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31849#L1560 assume !(0 != activate_threads_~tmp~1#1); 31850#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31081#L626 assume !(1 == ~t1_pc~0); 31082#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31350#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31351#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31520#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 30981#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30982#L645 assume 1 == ~t2_pc~0; 31098#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31055#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31732#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31733#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 31825#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31826#L664 assume 1 == ~t3_pc~0; 32582#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30822#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30823#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31481#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31482#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32490#L683 assume !(1 == ~t4_pc~0); 32045#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31997#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31998#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32032#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32156#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31775#L702 assume 1 == ~t5_pc~0; 31776#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31701#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32151#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32449#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32390#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30870#L721 assume !(1 == ~t6_pc~0); 30844#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30845#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31008#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31490#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31491#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32092#L740 assume 1 == ~t7_pc~0; 30919#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30732#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30733#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30722#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30723#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31426#L759 assume !(1 == ~t8_pc~0); 31427#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31456#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32149#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32150#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32281#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32559#L778 assume 1 == ~t9_pc~0; 32446#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30897#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30837#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30766#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30767#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31094#L797 assume !(1 == ~t10_pc~0); 31095#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31213#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32347#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31597#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31598#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31887#L816 assume 1 == ~t11_pc~0; 30802#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30803#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31558#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31497#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31498#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32022#L835 assume 1 == ~t12_pc~0; 31900#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30966#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30988#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31129#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31654#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31655#L854 assume !(1 == ~t13_pc~0); 31295#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31296#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31346#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31006#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31007#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32386#L1401 assume !(1 == ~M_E~0); 31485#L1401-2 assume !(1 == ~T1_E~0); 31486#L1406-1 assume !(1 == ~T2_E~0); 32081#L1411-1 assume !(1 == ~T3_E~0); 32082#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31748#L1421-1 assume !(1 == ~T5_E~0); 31291#L1426-1 assume !(1 == ~T6_E~0); 31292#L1431-1 assume !(1 == ~T7_E~0); 30840#L1436-1 assume !(1 == ~T8_E~0); 30841#L1441-1 assume !(1 == ~T9_E~0); 31588#L1446-1 assume !(1 == ~T10_E~0); 31589#L1451-1 assume !(1 == ~T11_E~0); 32294#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31948#L1461-1 assume !(1 == ~T13_E~0); 31509#L1466-1 assume !(1 == ~E_1~0); 31510#L1471-1 assume !(1 == ~E_2~0); 32279#L1476-1 assume !(1 == ~E_3~0); 32280#L1481-1 assume !(1 == ~E_4~0); 32428#L1486-1 assume !(1 == ~E_5~0); 31134#L1491-1 assume !(1 == ~E_6~0); 30774#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30775#L1501-1 assume !(1 == ~E_8~0); 31586#L1506-1 assume !(1 == ~E_9~0); 31587#L1511-1 assume !(1 == ~E_10~0); 31543#L1516-1 assume !(1 == ~E_11~0); 30718#L1521-1 assume !(1 == ~E_12~0); 30719#L1526-1 assume !(1 == ~E_13~0); 30773#L1531-1 assume { :end_inline_reset_delta_events } true; 31316#L1892-2 [2022-11-16 10:56:57,743 INFO L750 eck$LassoCheckResult]: Loop: 31316#L1892-2 assume !false; 32339#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32537#L1233 assume !false; 32520#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 31852#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31832#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31990#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30816#L1046 assume !(0 != eval_~tmp~0#1); 30818#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30852#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32024#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32581#L1258-5 assume !(0 == ~T1_E~0); 30994#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30995#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32573#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32579#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32580#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31218#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31219#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32336#L1298-3 assume !(0 == ~T9_E~0); 32337#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32496#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32335#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31836#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30996#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30997#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32420#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31139#L1338-3 assume !(0 == ~E_4~0); 31140#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32252#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32425#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32426#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31792#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31352#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31353#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32109#L1378-3 assume !(0 == ~E_12~0); 32110#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32291#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32292#L607-42 assume 1 == ~m_pc~0; 31905#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31633#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31634#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31366#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31367#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31888#L626-42 assume 1 == ~t1_pc~0; 31450#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31451#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31755#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31756#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31030#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31031#L645-42 assume !(1 == ~t2_pc~0); 32230#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32231#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32396#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31237#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30744#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30745#L664-42 assume !(1 == ~t3_pc~0); 31271#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 31272#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32523#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32058#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32059#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32224#L683-42 assume !(1 == ~t4_pc~0); 31932#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 31933#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32065#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32485#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32486#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32330#L702-42 assume !(1 == ~t5_pc~0); 31442#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 31443#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31739#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32412#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 30760#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30761#L721-42 assume 1 == ~t6_pc~0; 30914#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30934#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31398#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32565#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31570#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31416#L740-42 assume !(1 == ~t7_pc~0); 31153#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31154#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31695#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31550#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31551#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31824#L759-42 assume 1 == ~t8_pc~0; 31673#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31605#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31606#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31684#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31685#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31780#L778-42 assume 1 == ~t9_pc~0; 31617#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31619#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32029#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31934#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31935#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31992#L797-42 assume 1 == ~t10_pc~0; 31159#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31160#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32161#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32470#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32030#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32031#L816-42 assume 1 == ~t11_pc~0; 30708#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30709#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31251#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31252#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31331#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31332#L835-42 assume 1 == ~t12_pc~0; 31736#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31629#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31306#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31307#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32389#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32173#L854-42 assume !(1 == ~t13_pc~0); 31249#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 31250#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30860#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30861#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31507#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31508#L1401-3 assume !(1 == ~M_E~0); 32286#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31097#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30961#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30962#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31561#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31562#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31137#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31138#L1436-3 assume !(1 == ~T8_E~0); 30724#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30725#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32314#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31645#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31298#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 31299#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32576#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31238#L1476-3 assume !(1 == ~E_3~0); 31239#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31639#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31266#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31267#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31679#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31680#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32106#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32096#L1516-3 assume !(1 == ~E_11~0); 32097#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31796#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 31797#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32191#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31073#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31966#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31607#L1911 assume !(0 == start_simulation_~tmp~3#1); 31608#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32130#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31198#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32068#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30902#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30903#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31132#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 31133#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31316#L1892-2 [2022-11-16 10:56:57,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:57,744 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2022-11-16 10:56:57,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:57,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455594329] [2022-11-16 10:56:57,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:57,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:57,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:57,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:57,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:57,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455594329] [2022-11-16 10:56:57,795 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455594329] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:57,795 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:57,795 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:57,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931554238] [2022-11-16 10:56:57,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:57,796 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:57,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:57,797 INFO L85 PathProgramCache]: Analyzing trace with hash -835808881, now seen corresponding path program 2 times [2022-11-16 10:56:57,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:57,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170343052] [2022-11-16 10:56:57,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:57,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:57,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:57,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:57,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:57,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170343052] [2022-11-16 10:56:57,862 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170343052] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:57,862 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:57,863 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:57,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470510496] [2022-11-16 10:56:57,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:57,868 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:57,868 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:57,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:57,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:57,869 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:57,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:57,910 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-11-16 10:56:57,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2022-11-16 10:56:57,920 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:57,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-11-16 10:56:57,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:57,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:57,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2022-11-16 10:56:57,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:57,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-11-16 10:56:57,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2022-11-16 10:56:57,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:57,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:57,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-11-16 10:56:57,996 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-11-16 10:56:57,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:57,997 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-11-16 10:56:57,997 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-16 10:56:57,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2022-11-16 10:56:58,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:58,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:58,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:58,007 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:58,007 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:58,008 INFO L748 eck$LassoCheckResult]: Stem: 35389#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35209#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34925#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34926#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36102#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36103#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35061#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35062#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35520#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35351#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35352#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35128#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35129#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35527#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35704#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35859#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35895#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35141#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35142#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36315#L1258-2 assume !(0 == ~T1_E~0); 35434#L1263-1 assume !(0 == ~T2_E~0); 35435#L1268-1 assume !(0 == ~T3_E~0); 35738#L1273-1 assume !(0 == ~T4_E~0); 36297#L1278-1 assume !(0 == ~T5_E~0); 36158#L1283-1 assume !(0 == ~T6_E~0); 36159#L1288-1 assume !(0 == ~T7_E~0); 36396#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36383#L1298-1 assume !(0 == ~T9_E~0); 36309#L1303-1 assume !(0 == ~T10_E~0); 34954#L1308-1 assume !(0 == ~T11_E~0); 34899#L1313-1 assume !(0 == ~T12_E~0); 34900#L1318-1 assume !(0 == ~T13_E~0); 34905#L1323-1 assume !(0 == ~E_1~0); 34906#L1328-1 assume !(0 == ~E_2~0); 35071#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36030#L1338-1 assume !(0 == ~E_4~0); 36031#L1343-1 assume !(0 == ~E_5~0); 36132#L1348-1 assume !(0 == ~E_6~0); 36418#L1353-1 assume !(0 == ~E_7~0); 35757#L1358-1 assume !(0 == ~E_8~0); 35758#L1363-1 assume !(0 == ~E_9~0); 36049#L1368-1 assume !(0 == ~E_10~0); 34733#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34734#L1378-1 assume !(0 == ~E_12~0); 35022#L1383-1 assume !(0 == ~E_13~0); 35023#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35764#L607 assume 1 == ~m_pc~0; 35765#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35091#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36130#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35684#L1560 assume !(0 != activate_threads_~tmp~1#1); 35685#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34916#L626 assume !(1 == ~t1_pc~0); 34917#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35187#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35188#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35357#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34819#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34820#L645 assume 1 == ~t2_pc~0; 34933#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34890#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35570#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35571#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35660#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35661#L664 assume 1 == ~t3_pc~0; 36417#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34661#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34662#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35316#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35317#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36325#L683 assume !(1 == ~t4_pc~0); 35880#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35832#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35833#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35867#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35991#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35614#L702 assume 1 == ~t5_pc~0; 35615#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35537#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35986#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36285#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36226#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34705#L721 assume !(1 == ~t6_pc~0); 34679#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34680#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34843#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35325#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35326#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35927#L740 assume 1 == ~t7_pc~0; 34754#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34567#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34568#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34557#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34558#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35262#L759 assume !(1 == ~t8_pc~0); 35263#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35291#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35984#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35985#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36116#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36394#L778 assume 1 == ~t9_pc~0; 36283#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34732#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34672#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34601#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34602#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34930#L797 assume !(1 == ~t10_pc~0); 34931#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35048#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36182#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35432#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35433#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35722#L816 assume 1 == ~t11_pc~0; 34637#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34638#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35395#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35332#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35333#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35857#L835 assume 1 == ~t12_pc~0; 35735#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34801#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34823#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34964#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35489#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35490#L854 assume !(1 == ~t13_pc~0); 35130#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35131#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35183#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34841#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34842#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36221#L1401 assume !(1 == ~M_E~0); 35320#L1401-2 assume !(1 == ~T1_E~0); 35321#L1406-1 assume !(1 == ~T2_E~0); 35916#L1411-1 assume !(1 == ~T3_E~0); 35917#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35583#L1421-1 assume !(1 == ~T5_E~0); 35126#L1426-1 assume !(1 == ~T6_E~0); 35127#L1431-1 assume !(1 == ~T7_E~0); 34675#L1436-1 assume !(1 == ~T8_E~0); 34676#L1441-1 assume !(1 == ~T9_E~0); 35423#L1446-1 assume !(1 == ~T10_E~0); 35424#L1451-1 assume !(1 == ~T11_E~0); 36129#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35783#L1461-1 assume !(1 == ~T13_E~0); 35344#L1466-1 assume !(1 == ~E_1~0); 35345#L1471-1 assume !(1 == ~E_2~0); 36114#L1476-1 assume !(1 == ~E_3~0); 36115#L1481-1 assume !(1 == ~E_4~0); 36263#L1486-1 assume !(1 == ~E_5~0); 34969#L1491-1 assume !(1 == ~E_6~0); 34609#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34610#L1501-1 assume !(1 == ~E_8~0); 35421#L1506-1 assume !(1 == ~E_9~0); 35422#L1511-1 assume !(1 == ~E_10~0); 35378#L1516-1 assume !(1 == ~E_11~0); 34553#L1521-1 assume !(1 == ~E_12~0); 34554#L1526-1 assume !(1 == ~E_13~0); 34608#L1531-1 assume { :end_inline_reset_delta_events } true; 35151#L1892-2 [2022-11-16 10:56:58,009 INFO L750 eck$LassoCheckResult]: Loop: 35151#L1892-2 assume !false; 36174#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36372#L1233 assume !false; 36355#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35687#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35667#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35825#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34651#L1046 assume !(0 != eval_~tmp~0#1); 34653#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34687#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35858#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36416#L1258-5 assume !(0 == ~T1_E~0); 34829#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34830#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36408#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36414#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36415#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35053#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35054#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36171#L1298-3 assume !(0 == ~T9_E~0); 36172#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36331#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36170#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35671#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34831#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34832#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36255#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34974#L1338-3 assume !(0 == ~E_4~0); 34975#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36087#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36260#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36261#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35627#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35185#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35186#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35944#L1378-3 assume !(0 == ~E_12~0); 35945#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36126#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36127#L607-42 assume 1 == ~m_pc~0; 35740#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35468#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35469#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35201#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35202#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35723#L626-42 assume 1 == ~t1_pc~0; 35285#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35286#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35590#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35591#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34865#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34866#L645-42 assume !(1 == ~t2_pc~0); 36065#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36066#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36231#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35072#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34579#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34580#L664-42 assume !(1 == ~t3_pc~0); 35106#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 35107#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36358#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35893#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35894#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36059#L683-42 assume !(1 == ~t4_pc~0); 35767#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35768#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35900#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36320#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36321#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36165#L702-42 assume 1 == ~t5_pc~0; 35653#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35278#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35574#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36247#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 34595#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34596#L721-42 assume 1 == ~t6_pc~0; 34749#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34769#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35233#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36400#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35405#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35251#L740-42 assume 1 == ~t7_pc~0; 35252#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34989#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35530#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35385#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35386#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35659#L759-42 assume 1 == ~t8_pc~0; 35508#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35440#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35441#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35518#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35519#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35613#L778-42 assume 1 == ~t9_pc~0; 35452#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35454#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35864#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35769#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35770#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35827#L797-42 assume 1 == ~t10_pc~0; 34994#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34995#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35996#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36305#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35865#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35866#L816-42 assume !(1 == ~t11_pc~0); 34545#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 34544#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35086#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35087#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35166#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35167#L835-42 assume 1 == ~t12_pc~0; 35569#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35464#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35139#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35140#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36224#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36008#L854-42 assume 1 == ~t13_pc~0; 36009#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35085#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34695#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34696#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35342#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35343#L1401-3 assume !(1 == ~M_E~0); 36121#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34929#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34796#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34797#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35396#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35397#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34972#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34973#L1436-3 assume !(1 == ~T8_E~0); 34559#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34560#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36149#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35480#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35133#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 35134#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36411#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35073#L1476-3 assume !(1 == ~E_3~0); 35074#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35474#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35101#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35102#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35514#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35515#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35941#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35931#L1516-3 assume !(1 == ~E_11~0); 35932#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35631#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35632#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36026#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34908#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35801#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35442#L1911 assume !(0 == start_simulation_~tmp~3#1); 35443#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35965#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35033#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35903#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34737#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34738#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34967#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34968#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35151#L1892-2 [2022-11-16 10:56:58,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:58,010 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2022-11-16 10:56:58,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:58,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031582841] [2022-11-16 10:56:58,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:58,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:58,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:58,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:58,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:58,072 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1031582841] [2022-11-16 10:56:58,072 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1031582841] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:58,073 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:58,073 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:58,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128840840] [2022-11-16 10:56:58,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:58,074 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:58,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:58,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1042381777, now seen corresponding path program 2 times [2022-11-16 10:56:58,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:58,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865293539] [2022-11-16 10:56:58,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:58,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:58,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:58,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:58,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:58,146 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865293539] [2022-11-16 10:56:58,146 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [865293539] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:58,146 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:58,147 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:58,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949923983] [2022-11-16 10:56:58,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:58,147 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:58,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:58,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:58,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:58,149 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:58,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:58,190 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-11-16 10:56:58,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2022-11-16 10:56:58,199 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:58,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-11-16 10:56:58,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:58,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:58,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2022-11-16 10:56:58,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:58,221 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-11-16 10:56:58,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2022-11-16 10:56:58,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:58,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:58,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-11-16 10:56:58,269 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-11-16 10:56:58,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:58,271 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-11-16 10:56:58,271 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-16 10:56:58,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2022-11-16 10:56:58,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:58,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:58,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:58,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:58,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:58,281 INFO L748 eck$LassoCheckResult]: Stem: 39224#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 39225#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39044#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38760#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38761#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 39937#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39938#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38896#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38897#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39355#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39186#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39187#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38963#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38964#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39362#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39539#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39693#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39730#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38976#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38977#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40150#L1258-2 assume !(0 == ~T1_E~0); 39269#L1263-1 assume !(0 == ~T2_E~0); 39270#L1268-1 assume !(0 == ~T3_E~0); 39573#L1273-1 assume !(0 == ~T4_E~0); 40132#L1278-1 assume !(0 == ~T5_E~0); 39993#L1283-1 assume !(0 == ~T6_E~0); 39994#L1288-1 assume !(0 == ~T7_E~0); 40231#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40218#L1298-1 assume !(0 == ~T9_E~0); 40144#L1303-1 assume !(0 == ~T10_E~0); 38789#L1308-1 assume !(0 == ~T11_E~0); 38731#L1313-1 assume !(0 == ~T12_E~0); 38732#L1318-1 assume !(0 == ~T13_E~0); 38740#L1323-1 assume !(0 == ~E_1~0); 38741#L1328-1 assume !(0 == ~E_2~0); 38906#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 39865#L1338-1 assume !(0 == ~E_4~0); 39866#L1343-1 assume !(0 == ~E_5~0); 39967#L1348-1 assume !(0 == ~E_6~0); 40253#L1353-1 assume !(0 == ~E_7~0); 39592#L1358-1 assume !(0 == ~E_8~0); 39593#L1363-1 assume !(0 == ~E_9~0); 39884#L1368-1 assume !(0 == ~E_10~0); 38568#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38569#L1378-1 assume !(0 == ~E_12~0); 38857#L1383-1 assume !(0 == ~E_13~0); 38858#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39599#L607 assume 1 == ~m_pc~0; 39600#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38926#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39965#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39519#L1560 assume !(0 != activate_threads_~tmp~1#1); 39520#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38751#L626 assume !(1 == ~t1_pc~0); 38752#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39022#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39023#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39192#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38653#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38654#L645 assume 1 == ~t2_pc~0; 38768#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38725#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39405#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39406#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39495#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39496#L664 assume 1 == ~t3_pc~0; 40252#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38496#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38497#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39151#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39152#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40160#L683 assume !(1 == ~t4_pc~0); 39715#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39667#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39668#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39702#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39826#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39449#L702 assume 1 == ~t5_pc~0; 39450#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39372#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39821#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40120#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40061#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38540#L721 assume !(1 == ~t6_pc~0); 38514#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38515#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38678#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39160#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39161#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39762#L740 assume 1 == ~t7_pc~0; 38589#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38402#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38403#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38392#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38393#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39097#L759 assume !(1 == ~t8_pc~0); 39098#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39126#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39819#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39820#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 39951#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40229#L778 assume 1 == ~t9_pc~0; 40118#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38567#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38507#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38436#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38437#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38765#L797 assume !(1 == ~t10_pc~0); 38766#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38883#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40017#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39267#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39268#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39557#L816 assume 1 == ~t11_pc~0; 38472#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38473#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39230#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39167#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39168#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39692#L835 assume 1 == ~t12_pc~0; 39570#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38636#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38658#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38799#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39324#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39325#L854 assume !(1 == ~t13_pc~0); 38965#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 38966#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39018#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38676#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38677#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40056#L1401 assume !(1 == ~M_E~0); 39155#L1401-2 assume !(1 == ~T1_E~0); 39156#L1406-1 assume !(1 == ~T2_E~0); 39751#L1411-1 assume !(1 == ~T3_E~0); 39752#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39418#L1421-1 assume !(1 == ~T5_E~0); 38961#L1426-1 assume !(1 == ~T6_E~0); 38962#L1431-1 assume !(1 == ~T7_E~0); 38510#L1436-1 assume !(1 == ~T8_E~0); 38511#L1441-1 assume !(1 == ~T9_E~0); 39260#L1446-1 assume !(1 == ~T10_E~0); 39261#L1451-1 assume !(1 == ~T11_E~0); 39964#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39618#L1461-1 assume !(1 == ~T13_E~0); 39179#L1466-1 assume !(1 == ~E_1~0); 39180#L1471-1 assume !(1 == ~E_2~0); 39949#L1476-1 assume !(1 == ~E_3~0); 39950#L1481-1 assume !(1 == ~E_4~0); 40098#L1486-1 assume !(1 == ~E_5~0); 38804#L1491-1 assume !(1 == ~E_6~0); 38444#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38445#L1501-1 assume !(1 == ~E_8~0); 39256#L1506-1 assume !(1 == ~E_9~0); 39257#L1511-1 assume !(1 == ~E_10~0); 39213#L1516-1 assume !(1 == ~E_11~0); 38390#L1521-1 assume !(1 == ~E_12~0); 38391#L1526-1 assume !(1 == ~E_13~0); 38443#L1531-1 assume { :end_inline_reset_delta_events } true; 38986#L1892-2 [2022-11-16 10:56:58,282 INFO L750 eck$LassoCheckResult]: Loop: 38986#L1892-2 assume !false; 40009#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40207#L1233 assume !false; 40190#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39522#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39502#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39660#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38486#L1046 assume !(0 != eval_~tmp~0#1); 38488#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38522#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39694#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40251#L1258-5 assume !(0 == ~T1_E~0); 38666#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38667#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40243#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40249#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40250#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38890#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38891#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40006#L1298-3 assume !(0 == ~T9_E~0); 40007#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40166#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40005#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39506#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38668#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38669#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40090#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38809#L1338-3 assume !(0 == ~E_4~0); 38810#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39922#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40095#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40096#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39462#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39020#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39021#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39779#L1378-3 assume !(0 == ~E_12~0); 39780#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 39961#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39962#L607-42 assume 1 == ~m_pc~0; 39575#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39303#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39304#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39036#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39037#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39558#L626-42 assume 1 == ~t1_pc~0; 39120#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39121#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39425#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39426#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38700#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38701#L645-42 assume !(1 == ~t2_pc~0); 39900#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 39901#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40066#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38907#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38414#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38415#L664-42 assume 1 == ~t3_pc~0; 39217#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38942#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40193#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39728#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39729#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39894#L683-42 assume !(1 == ~t4_pc~0); 39602#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39603#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39735#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40155#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40156#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40000#L702-42 assume 1 == ~t5_pc~0; 39488#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39113#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39409#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40082#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 38430#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38431#L721-42 assume 1 == ~t6_pc~0; 38584#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38604#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39068#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40235#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39240#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39086#L740-42 assume !(1 == ~t7_pc~0); 38823#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38824#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39365#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39220#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39221#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39494#L759-42 assume !(1 == ~t8_pc~0); 39344#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 39275#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39276#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39353#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39354#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39448#L778-42 assume 1 == ~t9_pc~0; 39287#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39289#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39698#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39604#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39605#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39662#L797-42 assume 1 == ~t10_pc~0; 38829#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38830#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39831#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40140#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39700#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39701#L816-42 assume 1 == ~t11_pc~0; 38378#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38379#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38921#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38922#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39001#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39002#L835-42 assume !(1 == ~t12_pc~0); 39298#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39299#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38974#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38975#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40059#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39843#L854-42 assume 1 == ~t13_pc~0; 39844#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38918#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38530#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38531#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39177#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39178#L1401-3 assume !(1 == ~M_E~0); 39956#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38764#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38631#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38632#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39231#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39232#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38807#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38808#L1436-3 assume !(1 == ~T8_E~0); 38394#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38395#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39984#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39315#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38968#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38969#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40246#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38908#L1476-3 assume !(1 == ~E_3~0); 38909#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39309#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38936#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38937#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39349#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39350#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39776#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39766#L1516-3 assume !(1 == ~E_11~0); 39767#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39466#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39467#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39861#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38743#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39636#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39277#L1911 assume !(0 == start_simulation_~tmp~3#1); 39278#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39800#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38868#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39738#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38572#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38573#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38802#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 38803#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 38986#L1892-2 [2022-11-16 10:56:58,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:58,283 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2022-11-16 10:56:58,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:58,284 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384218541] [2022-11-16 10:56:58,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:58,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:58,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:58,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:58,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:58,335 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384218541] [2022-11-16 10:56:58,335 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [384218541] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:58,335 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:58,336 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:58,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1819638591] [2022-11-16 10:56:58,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:58,336 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:58,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:58,337 INFO L85 PathProgramCache]: Analyzing trace with hash -744572368, now seen corresponding path program 1 times [2022-11-16 10:56:58,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:58,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253664797] [2022-11-16 10:56:58,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:58,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:58,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:58,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:58,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:58,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [253664797] [2022-11-16 10:56:58,401 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [253664797] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:58,402 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:58,402 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:58,402 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765834903] [2022-11-16 10:56:58,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:58,403 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:58,403 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:58,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:58,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:58,404 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:58,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:58,445 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-11-16 10:56:58,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2022-11-16 10:56:58,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:58,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-11-16 10:56:58,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:58,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:58,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2022-11-16 10:56:58,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:58,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-11-16 10:56:58,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2022-11-16 10:56:58,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:58,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:58,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-11-16 10:56:58,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-11-16 10:56:58,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:58,544 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-11-16 10:56:58,544 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-16 10:56:58,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2022-11-16 10:56:58,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:58,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:58,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:58,554 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:58,554 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:58,555 INFO L748 eck$LassoCheckResult]: Stem: 43059#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 43060#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42879#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42595#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42596#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43772#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43773#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42731#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42732#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43190#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43021#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43022#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42798#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42799#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43197#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43374#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43528#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43565#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42811#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42812#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43985#L1258-2 assume !(0 == ~T1_E~0); 43104#L1263-1 assume !(0 == ~T2_E~0); 43105#L1268-1 assume !(0 == ~T3_E~0); 43408#L1273-1 assume !(0 == ~T4_E~0); 43967#L1278-1 assume !(0 == ~T5_E~0); 43828#L1283-1 assume !(0 == ~T6_E~0); 43829#L1288-1 assume !(0 == ~T7_E~0); 44066#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44053#L1298-1 assume !(0 == ~T9_E~0); 43979#L1303-1 assume !(0 == ~T10_E~0); 42624#L1308-1 assume !(0 == ~T11_E~0); 42566#L1313-1 assume !(0 == ~T12_E~0); 42567#L1318-1 assume !(0 == ~T13_E~0); 42575#L1323-1 assume !(0 == ~E_1~0); 42576#L1328-1 assume !(0 == ~E_2~0); 42741#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43700#L1338-1 assume !(0 == ~E_4~0); 43701#L1343-1 assume !(0 == ~E_5~0); 43802#L1348-1 assume !(0 == ~E_6~0); 44088#L1353-1 assume !(0 == ~E_7~0); 43427#L1358-1 assume !(0 == ~E_8~0); 43428#L1363-1 assume !(0 == ~E_9~0); 43718#L1368-1 assume !(0 == ~E_10~0); 42403#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42404#L1378-1 assume !(0 == ~E_12~0); 42692#L1383-1 assume !(0 == ~E_13~0); 42693#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43434#L607 assume 1 == ~m_pc~0; 43435#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42761#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43800#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43354#L1560 assume !(0 != activate_threads_~tmp~1#1); 43355#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42586#L626 assume !(1 == ~t1_pc~0); 42587#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42855#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42856#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43027#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42488#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42489#L645 assume 1 == ~t2_pc~0; 42603#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42560#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43240#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43241#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43330#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43331#L664 assume 1 == ~t3_pc~0; 44087#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42331#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42332#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42986#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42987#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43995#L683 assume !(1 == ~t4_pc~0); 43550#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43502#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43503#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43537#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43661#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43284#L702 assume 1 == ~t5_pc~0; 43285#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43207#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43656#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43955#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43896#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42375#L721 assume !(1 == ~t6_pc~0); 42349#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42350#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42513#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42995#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42996#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43597#L740 assume 1 == ~t7_pc~0; 42424#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42237#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42238#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42227#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42228#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42932#L759 assume !(1 == ~t8_pc~0); 42933#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42961#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43654#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43655#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43786#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44064#L778 assume 1 == ~t9_pc~0; 43951#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42402#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42342#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42271#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42272#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42600#L797 assume !(1 == ~t10_pc~0); 42601#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42718#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43852#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43102#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43103#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43392#L816 assume 1 == ~t11_pc~0; 42307#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42308#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43065#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43002#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43003#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43527#L835 assume 1 == ~t12_pc~0; 43405#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42471#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42493#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42634#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43159#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43160#L854 assume !(1 == ~t13_pc~0); 42800#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42801#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42851#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42511#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42512#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43891#L1401 assume !(1 == ~M_E~0); 42990#L1401-2 assume !(1 == ~T1_E~0); 42991#L1406-1 assume !(1 == ~T2_E~0); 43586#L1411-1 assume !(1 == ~T3_E~0); 43587#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43253#L1421-1 assume !(1 == ~T5_E~0); 42796#L1426-1 assume !(1 == ~T6_E~0); 42797#L1431-1 assume !(1 == ~T7_E~0); 42345#L1436-1 assume !(1 == ~T8_E~0); 42346#L1441-1 assume !(1 == ~T9_E~0); 43095#L1446-1 assume !(1 == ~T10_E~0); 43096#L1451-1 assume !(1 == ~T11_E~0); 43799#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43453#L1461-1 assume !(1 == ~T13_E~0); 43014#L1466-1 assume !(1 == ~E_1~0); 43015#L1471-1 assume !(1 == ~E_2~0); 43784#L1476-1 assume !(1 == ~E_3~0); 43785#L1481-1 assume !(1 == ~E_4~0); 43933#L1486-1 assume !(1 == ~E_5~0); 42639#L1491-1 assume !(1 == ~E_6~0); 42279#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42280#L1501-1 assume !(1 == ~E_8~0); 43091#L1506-1 assume !(1 == ~E_9~0); 43092#L1511-1 assume !(1 == ~E_10~0); 43048#L1516-1 assume !(1 == ~E_11~0); 42225#L1521-1 assume !(1 == ~E_12~0); 42226#L1526-1 assume !(1 == ~E_13~0); 42278#L1531-1 assume { :end_inline_reset_delta_events } true; 42821#L1892-2 [2022-11-16 10:56:58,555 INFO L750 eck$LassoCheckResult]: Loop: 42821#L1892-2 assume !false; 43844#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44042#L1233 assume !false; 44025#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43357#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43337#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43495#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42321#L1046 assume !(0 != eval_~tmp~0#1); 42323#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42357#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43529#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44086#L1258-5 assume !(0 == ~T1_E~0); 42501#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42502#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44078#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44084#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44085#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42725#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42726#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43841#L1298-3 assume !(0 == ~T9_E~0); 43842#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44001#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43840#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43341#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42503#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42504#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43925#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42644#L1338-3 assume !(0 == ~E_4~0); 42645#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43757#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43931#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43932#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43299#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42857#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42858#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43614#L1378-3 assume !(0 == ~E_12~0); 43615#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43796#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43797#L607-42 assume 1 == ~m_pc~0; 43412#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43138#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43139#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42871#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42872#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43393#L626-42 assume 1 == ~t1_pc~0; 42955#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42956#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43260#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43261#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42535#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42536#L645-42 assume !(1 == ~t2_pc~0); 43734#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43735#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43901#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42742#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42249#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42250#L664-42 assume !(1 == ~t3_pc~0); 42776#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 42777#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44028#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43563#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43564#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43729#L683-42 assume !(1 == ~t4_pc~0); 43437#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43438#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43569#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43990#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43991#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43835#L702-42 assume !(1 == ~t5_pc~0); 42947#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42948#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43244#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43917#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 42265#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42266#L721-42 assume 1 == ~t6_pc~0; 42419#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42439#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42903#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44070#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43075#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42921#L740-42 assume !(1 == ~t7_pc~0); 42658#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 42659#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43200#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43055#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43056#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43329#L759-42 assume 1 == ~t8_pc~0; 43178#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43110#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43111#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43188#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43189#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43283#L778-42 assume 1 == ~t9_pc~0; 43122#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43124#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43533#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43439#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43440#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43497#L797-42 assume 1 == ~t10_pc~0; 42664#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42665#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43666#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43975#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43535#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43536#L816-42 assume 1 == ~t11_pc~0; 42213#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42214#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42756#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42757#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42836#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42837#L835-42 assume 1 == ~t12_pc~0; 43239#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43133#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42809#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42810#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43894#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43678#L854-42 assume !(1 == ~t13_pc~0); 42752#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 42753#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42365#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42366#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43012#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43013#L1401-3 assume !(1 == ~M_E~0); 43791#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42599#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42466#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42467#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43066#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43067#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42642#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42643#L1436-3 assume !(1 == ~T8_E~0); 42229#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42230#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43819#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43150#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42803#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42804#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44081#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42743#L1476-3 assume !(1 == ~E_3~0); 42744#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43144#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42771#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42772#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43183#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43184#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43611#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43601#L1516-3 assume !(1 == ~E_11~0); 43602#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43301#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43302#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43696#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42578#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43471#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43112#L1911 assume !(0 == start_simulation_~tmp~3#1); 43113#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43635#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42703#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43573#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42407#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42408#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42637#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 42638#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42821#L1892-2 [2022-11-16 10:56:58,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:58,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2022-11-16 10:56:58,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:58,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56376999] [2022-11-16 10:56:58,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:58,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:58,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:58,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:58,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:58,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56376999] [2022-11-16 10:56:58,632 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56376999] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:58,633 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:58,633 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:58,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139276644] [2022-11-16 10:56:58,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:58,633 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:58,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:58,634 INFO L85 PathProgramCache]: Analyzing trace with hash -835808881, now seen corresponding path program 3 times [2022-11-16 10:56:58,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:58,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335343557] [2022-11-16 10:56:58,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:58,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:58,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:58,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:58,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:58,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335343557] [2022-11-16 10:56:58,703 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335343557] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:58,703 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:58,703 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:58,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352474670] [2022-11-16 10:56:58,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:58,704 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:58,704 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:58,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:58,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:58,705 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:58,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:58,745 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-11-16 10:56:58,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2022-11-16 10:56:58,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:58,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-11-16 10:56:58,761 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:58,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:58,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2022-11-16 10:56:58,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:58,764 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-11-16 10:56:58,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2022-11-16 10:56:58,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:58,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:58,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-11-16 10:56:58,797 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-11-16 10:56:58,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:58,799 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-11-16 10:56:58,799 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-16 10:56:58,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2022-11-16 10:56:58,807 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:58,807 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:58,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:58,809 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:58,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:58,810 INFO L748 eck$LassoCheckResult]: Stem: 46894#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46714#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46430#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46431#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47607#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47608#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46566#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46567#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47025#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46856#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46857#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46633#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46634#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47032#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47209#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47363#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47400#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46646#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46647#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 47820#L1258-2 assume !(0 == ~T1_E~0); 46939#L1263-1 assume !(0 == ~T2_E~0); 46940#L1268-1 assume !(0 == ~T3_E~0); 47243#L1273-1 assume !(0 == ~T4_E~0); 47802#L1278-1 assume !(0 == ~T5_E~0); 47663#L1283-1 assume !(0 == ~T6_E~0); 47664#L1288-1 assume !(0 == ~T7_E~0); 47900#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47888#L1298-1 assume !(0 == ~T9_E~0); 47814#L1303-1 assume !(0 == ~T10_E~0); 46459#L1308-1 assume !(0 == ~T11_E~0); 46401#L1313-1 assume !(0 == ~T12_E~0); 46402#L1318-1 assume !(0 == ~T13_E~0); 46410#L1323-1 assume !(0 == ~E_1~0); 46411#L1328-1 assume !(0 == ~E_2~0); 46576#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47535#L1338-1 assume !(0 == ~E_4~0); 47536#L1343-1 assume !(0 == ~E_5~0); 47637#L1348-1 assume !(0 == ~E_6~0); 47923#L1353-1 assume !(0 == ~E_7~0); 47262#L1358-1 assume !(0 == ~E_8~0); 47263#L1363-1 assume !(0 == ~E_9~0); 47553#L1368-1 assume !(0 == ~E_10~0); 46238#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46239#L1378-1 assume !(0 == ~E_12~0); 46527#L1383-1 assume !(0 == ~E_13~0); 46528#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47269#L607 assume 1 == ~m_pc~0; 47270#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46596#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47635#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47189#L1560 assume !(0 != activate_threads_~tmp~1#1); 47190#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46421#L626 assume !(1 == ~t1_pc~0); 46422#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46690#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46691#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46860#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46323#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46324#L645 assume 1 == ~t2_pc~0; 46438#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46395#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47075#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47076#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47165#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47166#L664 assume 1 == ~t3_pc~0; 47922#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46164#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46165#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46821#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 46822#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47830#L683 assume !(1 == ~t4_pc~0); 47385#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47337#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47338#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47372#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47496#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47119#L702 assume 1 == ~t5_pc~0; 47120#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47042#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47491#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47790#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 47731#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46210#L721 assume !(1 == ~t6_pc~0); 46184#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46185#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46348#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46830#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 46831#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47432#L740 assume 1 == ~t7_pc~0; 46259#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46072#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46073#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46062#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46063#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46767#L759 assume !(1 == ~t8_pc~0); 46768#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46796#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47489#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47490#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47621#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47899#L778 assume 1 == ~t9_pc~0; 47786#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46237#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46177#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46106#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46107#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46435#L797 assume !(1 == ~t10_pc~0); 46436#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46553#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47687#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46937#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 46938#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47227#L816 assume 1 == ~t11_pc~0; 46142#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46143#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46900#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46837#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 46838#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47362#L835 assume 1 == ~t12_pc~0; 47240#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46306#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46328#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46469#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 46994#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46995#L854 assume !(1 == ~t13_pc~0); 46635#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46636#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46686#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46346#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46347#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47726#L1401 assume !(1 == ~M_E~0); 46825#L1401-2 assume !(1 == ~T1_E~0); 46826#L1406-1 assume !(1 == ~T2_E~0); 47421#L1411-1 assume !(1 == ~T3_E~0); 47422#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47088#L1421-1 assume !(1 == ~T5_E~0); 46631#L1426-1 assume !(1 == ~T6_E~0); 46632#L1431-1 assume !(1 == ~T7_E~0); 46180#L1436-1 assume !(1 == ~T8_E~0); 46181#L1441-1 assume !(1 == ~T9_E~0); 46930#L1446-1 assume !(1 == ~T10_E~0); 46931#L1451-1 assume !(1 == ~T11_E~0); 47634#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47288#L1461-1 assume !(1 == ~T13_E~0); 46849#L1466-1 assume !(1 == ~E_1~0); 46850#L1471-1 assume !(1 == ~E_2~0); 47619#L1476-1 assume !(1 == ~E_3~0); 47620#L1481-1 assume !(1 == ~E_4~0); 47768#L1486-1 assume !(1 == ~E_5~0); 46474#L1491-1 assume !(1 == ~E_6~0); 46114#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46115#L1501-1 assume !(1 == ~E_8~0); 46926#L1506-1 assume !(1 == ~E_9~0); 46927#L1511-1 assume !(1 == ~E_10~0); 46883#L1516-1 assume !(1 == ~E_11~0); 46060#L1521-1 assume !(1 == ~E_12~0); 46061#L1526-1 assume !(1 == ~E_13~0); 46113#L1531-1 assume { :end_inline_reset_delta_events } true; 46656#L1892-2 [2022-11-16 10:56:58,811 INFO L750 eck$LassoCheckResult]: Loop: 46656#L1892-2 assume !false; 47679#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47877#L1233 assume !false; 47860#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47192#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47172#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47330#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46156#L1046 assume !(0 != eval_~tmp~0#1); 46158#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46192#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47364#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47921#L1258-5 assume !(0 == ~T1_E~0); 46336#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46337#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47913#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47919#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47920#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46560#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46561#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47676#L1298-3 assume !(0 == ~T9_E~0); 47677#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47836#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47675#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47176#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46338#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46339#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47760#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46479#L1338-3 assume !(0 == ~E_4~0); 46480#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47592#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47766#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47767#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47134#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46692#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46693#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47449#L1378-3 assume !(0 == ~E_12~0); 47450#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47631#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47632#L607-42 assume !(1 == ~m_pc~0); 47248#L607-44 is_master_triggered_~__retres1~0#1 := 0; 46973#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46974#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46706#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46707#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47231#L626-42 assume 1 == ~t1_pc~0; 46793#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46794#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47095#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47096#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46370#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46371#L645-42 assume !(1 == ~t2_pc~0); 47570#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47571#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47736#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46577#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46084#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46085#L664-42 assume !(1 == ~t3_pc~0); 46608#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46609#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47863#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47398#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47399#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47564#L683-42 assume !(1 == ~t4_pc~0); 47271#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47272#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47404#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47825#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47826#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47670#L702-42 assume 1 == ~t5_pc~0; 47158#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46782#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47079#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47752#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 46098#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46099#L721-42 assume 1 == ~t6_pc~0; 46254#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46274#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46738#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47905#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46910#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46756#L740-42 assume 1 == ~t7_pc~0; 46757#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46494#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47035#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46890#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46891#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47164#L759-42 assume 1 == ~t8_pc~0; 47013#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46945#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46946#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47023#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47024#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47118#L778-42 assume 1 == ~t9_pc~0; 46957#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46959#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47368#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47273#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47274#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47332#L797-42 assume 1 == ~t10_pc~0; 46499#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46500#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47501#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47810#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47370#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47371#L816-42 assume 1 == ~t11_pc~0; 46048#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46049#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46591#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46592#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46671#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46672#L835-42 assume 1 == ~t12_pc~0; 47074#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46966#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46644#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46645#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47729#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47513#L854-42 assume 1 == ~t13_pc~0; 47514#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46588#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46200#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46201#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46847#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46848#L1401-3 assume !(1 == ~M_E~0); 47626#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46434#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46301#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46302#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46901#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46902#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46477#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46478#L1436-3 assume !(1 == ~T8_E~0); 46064#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46065#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47654#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46985#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46638#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46639#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47916#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46578#L1476-3 assume !(1 == ~E_3~0); 46579#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46979#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46606#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46607#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47018#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47019#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47446#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47436#L1516-3 assume !(1 == ~E_11~0); 47437#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47136#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47137#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47531#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46413#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47306#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46947#L1911 assume !(0 == start_simulation_~tmp~3#1); 46948#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47470#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46538#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47408#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46242#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46243#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46472#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46473#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46656#L1892-2 [2022-11-16 10:56:58,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:58,812 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2022-11-16 10:56:58,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:58,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460517224] [2022-11-16 10:56:58,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:58,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:58,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:58,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:58,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:58,868 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460517224] [2022-11-16 10:56:58,868 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460517224] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:58,868 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:58,869 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:58,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779551806] [2022-11-16 10:56:58,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:58,870 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:58,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:58,871 INFO L85 PathProgramCache]: Analyzing trace with hash -505772015, now seen corresponding path program 1 times [2022-11-16 10:56:58,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:58,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55430084] [2022-11-16 10:56:58,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:58,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:58,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:58,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:58,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:58,943 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55430084] [2022-11-16 10:56:58,944 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55430084] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:58,944 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:58,944 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:58,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662969301] [2022-11-16 10:56:58,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:58,945 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:58,945 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:58,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:58,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:58,946 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:58,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:58,988 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-11-16 10:56:58,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2022-11-16 10:56:58,998 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:59,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-11-16 10:56:59,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-11-16 10:56:59,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-11-16 10:56:59,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2022-11-16 10:56:59,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:59,020 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-11-16 10:56:59,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2022-11-16 10:56:59,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-11-16 10:56:59,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:59,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-11-16 10:56:59,090 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-11-16 10:56:59,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:59,094 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-11-16 10:56:59,095 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-16 10:56:59,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2022-11-16 10:56:59,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-11-16 10:56:59,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:59,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:59,107 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:59,107 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:59,108 INFO L748 eck$LassoCheckResult]: Stem: 50729#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50549#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50265#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50266#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51442#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51443#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50401#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50402#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50858#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50691#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50692#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50468#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50469#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50867#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51044#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51198#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51235#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50481#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50482#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51655#L1258-2 assume !(0 == ~T1_E~0); 50774#L1263-1 assume !(0 == ~T2_E~0); 50775#L1268-1 assume !(0 == ~T3_E~0); 51078#L1273-1 assume !(0 == ~T4_E~0); 51637#L1278-1 assume !(0 == ~T5_E~0); 51498#L1283-1 assume !(0 == ~T6_E~0); 51499#L1288-1 assume !(0 == ~T7_E~0); 51735#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51723#L1298-1 assume !(0 == ~T9_E~0); 51649#L1303-1 assume !(0 == ~T10_E~0); 50294#L1308-1 assume !(0 == ~T11_E~0); 50236#L1313-1 assume !(0 == ~T12_E~0); 50237#L1318-1 assume !(0 == ~T13_E~0); 50245#L1323-1 assume !(0 == ~E_1~0); 50246#L1328-1 assume !(0 == ~E_2~0); 50411#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51370#L1338-1 assume !(0 == ~E_4~0); 51371#L1343-1 assume !(0 == ~E_5~0); 51472#L1348-1 assume !(0 == ~E_6~0); 51758#L1353-1 assume !(0 == ~E_7~0); 51097#L1358-1 assume !(0 == ~E_8~0); 51098#L1363-1 assume !(0 == ~E_9~0); 51388#L1368-1 assume !(0 == ~E_10~0); 50073#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50074#L1378-1 assume !(0 == ~E_12~0); 50362#L1383-1 assume !(0 == ~E_13~0); 50363#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51104#L607 assume 1 == ~m_pc~0; 51105#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50431#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51470#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51024#L1560 assume !(0 != activate_threads_~tmp~1#1); 51025#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50256#L626 assume !(1 == ~t1_pc~0); 50257#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50525#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50526#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50695#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50156#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50157#L645 assume 1 == ~t2_pc~0; 50273#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50230#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50910#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50911#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 51000#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51001#L664 assume 1 == ~t3_pc~0; 51757#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49997#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49998#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50656#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50657#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51665#L683 assume !(1 == ~t4_pc~0); 51220#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51172#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51173#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51207#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51331#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50954#L702 assume 1 == ~t5_pc~0; 50955#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50877#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51326#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51625#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51566#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50045#L721 assume !(1 == ~t6_pc~0); 50019#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50020#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50183#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50665#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50666#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51267#L740 assume 1 == ~t7_pc~0; 50094#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49907#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49908#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49897#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49898#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50602#L759 assume !(1 == ~t8_pc~0); 50603#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50631#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51324#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51325#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51456#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51734#L778 assume 1 == ~t9_pc~0; 51621#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50072#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50012#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49941#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49942#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50270#L797 assume !(1 == ~t10_pc~0); 50271#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50388#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51522#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50772#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50773#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51062#L816 assume 1 == ~t11_pc~0; 49977#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49978#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50735#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50672#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50673#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51197#L835 assume 1 == ~t12_pc~0; 51075#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50141#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50163#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50304#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50829#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50830#L854 assume !(1 == ~t13_pc~0); 50470#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50471#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50521#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50181#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50182#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51561#L1401 assume !(1 == ~M_E~0); 50660#L1401-2 assume !(1 == ~T1_E~0); 50661#L1406-1 assume !(1 == ~T2_E~0); 51256#L1411-1 assume !(1 == ~T3_E~0); 51257#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50923#L1421-1 assume !(1 == ~T5_E~0); 50466#L1426-1 assume !(1 == ~T6_E~0); 50467#L1431-1 assume !(1 == ~T7_E~0); 50015#L1436-1 assume !(1 == ~T8_E~0); 50016#L1441-1 assume !(1 == ~T9_E~0); 50765#L1446-1 assume !(1 == ~T10_E~0); 50766#L1451-1 assume !(1 == ~T11_E~0); 51469#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51123#L1461-1 assume !(1 == ~T13_E~0); 50684#L1466-1 assume !(1 == ~E_1~0); 50685#L1471-1 assume !(1 == ~E_2~0); 51454#L1476-1 assume !(1 == ~E_3~0); 51455#L1481-1 assume !(1 == ~E_4~0); 51603#L1486-1 assume !(1 == ~E_5~0); 50309#L1491-1 assume !(1 == ~E_6~0); 49949#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49950#L1501-1 assume !(1 == ~E_8~0); 50761#L1506-1 assume !(1 == ~E_9~0); 50762#L1511-1 assume !(1 == ~E_10~0); 50718#L1516-1 assume !(1 == ~E_11~0); 49893#L1521-1 assume !(1 == ~E_12~0); 49894#L1526-1 assume !(1 == ~E_13~0); 49948#L1531-1 assume { :end_inline_reset_delta_events } true; 50491#L1892-2 [2022-11-16 10:56:59,109 INFO L750 eck$LassoCheckResult]: Loop: 50491#L1892-2 assume !false; 51514#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51712#L1233 assume !false; 51695#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51027#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51007#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51165#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49991#L1046 assume !(0 != eval_~tmp~0#1); 49993#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50027#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51199#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51756#L1258-5 assume !(0 == ~T1_E~0); 50169#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50170#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51748#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51754#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51755#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50393#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50394#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51511#L1298-3 assume !(0 == ~T9_E~0); 51512#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51671#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51510#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51011#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50171#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50172#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51595#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50314#L1338-3 assume !(0 == ~E_4~0); 50315#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51427#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51601#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51602#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50969#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50527#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50528#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51284#L1378-3 assume !(0 == ~E_12~0); 51285#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51466#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51467#L607-42 assume 1 == ~m_pc~0; 51082#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50808#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50809#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50541#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50542#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51066#L626-42 assume 1 == ~t1_pc~0; 50628#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50629#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50930#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50931#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50205#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50206#L645-42 assume 1 == ~t2_pc~0; 51664#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51406#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51571#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50412#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49919#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49920#L664-42 assume 1 == ~t3_pc~0; 50724#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50448#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51698#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51233#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51234#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51399#L683-42 assume 1 == ~t4_pc~0; 51764#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51110#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51240#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51660#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51661#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51508#L702-42 assume 1 == ~t5_pc~0; 50996#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50618#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50916#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51587#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 49933#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49934#L721-42 assume 1 == ~t6_pc~0; 50088#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50109#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50573#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51740#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50745#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50589#L740-42 assume !(1 == ~t7_pc~0); 50325#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 50326#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50870#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50725#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50726#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50999#L759-42 assume 1 == ~t8_pc~0; 50848#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50780#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50781#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50856#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50857#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50953#L778-42 assume 1 == ~t9_pc~0; 50792#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50794#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51202#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51106#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51107#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51167#L797-42 assume !(1 == ~t10_pc~0); 50336#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 50335#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51336#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51645#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51205#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51206#L816-42 assume 1 == ~t11_pc~0; 49883#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49884#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50426#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50427#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50506#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50507#L835-42 assume !(1 == ~t12_pc~0); 50800#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50801#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50479#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50480#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51564#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51348#L854-42 assume 1 == ~t13_pc~0; 51349#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50423#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50035#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50036#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50682#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50683#L1401-3 assume !(1 == ~M_E~0); 51461#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50269#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50136#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50137#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50736#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50737#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50312#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50313#L1436-3 assume !(1 == ~T8_E~0); 49899#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49900#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51489#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50820#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50473#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50474#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51751#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50413#L1476-3 assume !(1 == ~E_3~0); 50414#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50814#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50441#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50442#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50853#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50854#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51281#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51270#L1516-3 assume !(1 == ~E_11~0); 51271#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50971#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50972#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51366#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50248#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51141#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50782#L1911 assume !(0 == start_simulation_~tmp~3#1); 50783#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51305#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50373#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51243#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50077#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50078#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50307#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 50308#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50491#L1892-2 [2022-11-16 10:56:59,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:59,110 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2022-11-16 10:56:59,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:59,110 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239798479] [2022-11-16 10:56:59,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:59,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:59,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:59,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:59,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:59,194 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239798479] [2022-11-16 10:56:59,194 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239798479] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:59,195 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:59,195 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 10:56:59,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562242871] [2022-11-16 10:56:59,195 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:59,197 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:59,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:59,198 INFO L85 PathProgramCache]: Analyzing trace with hash -118340366, now seen corresponding path program 1 times [2022-11-16 10:56:59,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:59,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267075900] [2022-11-16 10:56:59,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:59,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:59,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:59,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:59,278 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:59,278 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267075900] [2022-11-16 10:56:59,278 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267075900] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:59,278 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:59,279 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:59,279 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560654318] [2022-11-16 10:56:59,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:59,280 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:59,280 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:59,281 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:56:59,281 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:56:59,281 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:59,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:56:59,553 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-11-16 10:56:59,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2022-11-16 10:56:59,575 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-11-16 10:56:59,594 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-11-16 10:56:59,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2022-11-16 10:56:59,597 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2022-11-16 10:56:59,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2022-11-16 10:56:59,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:56:59,603 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-11-16 10:56:59,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2022-11-16 10:56:59,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2022-11-16 10:56:59,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:56:59,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-11-16 10:56:59,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-11-16 10:56:59,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 10:56:59,689 INFO L428 stractBuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-11-16 10:56:59,689 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-16 10:56:59,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2022-11-16 10:56:59,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-11-16 10:56:59,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:56:59,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:56:59,713 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:59,713 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:56:59,714 INFO L748 eck$LassoCheckResult]: Stem: 56208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56027#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55741#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55742#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 56940#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56941#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55878#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55879#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56337#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56170#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56171#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55946#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55947#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56348#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56531#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56683#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56722#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 55957#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55958#L1258 assume !(0 == ~M_E~0); 57173#L1258-2 assume !(0 == ~T1_E~0); 56254#L1263-1 assume !(0 == ~T2_E~0); 56255#L1268-1 assume !(0 == ~T3_E~0); 56565#L1273-1 assume !(0 == ~T4_E~0); 57152#L1278-1 assume !(0 == ~T5_E~0); 57000#L1283-1 assume !(0 == ~T6_E~0); 57001#L1288-1 assume !(0 == ~T7_E~0); 57267#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57255#L1298-1 assume !(0 == ~T9_E~0); 57165#L1303-1 assume !(0 == ~T10_E~0); 55770#L1308-1 assume !(0 == ~T11_E~0); 55712#L1313-1 assume !(0 == ~T12_E~0); 55713#L1318-1 assume !(0 == ~T13_E~0); 55719#L1323-1 assume !(0 == ~E_1~0); 55720#L1328-1 assume !(0 == ~E_2~0); 55889#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 56863#L1338-1 assume !(0 == ~E_4~0); 56864#L1343-1 assume !(0 == ~E_5~0); 56972#L1348-1 assume !(0 == ~E_6~0); 57295#L1353-1 assume !(0 == ~E_7~0); 56584#L1358-1 assume !(0 == ~E_8~0); 56585#L1363-1 assume !(0 == ~E_9~0); 56882#L1368-1 assume !(0 == ~E_10~0); 55549#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55550#L1378-1 assume !(0 == ~E_12~0); 55837#L1383-1 assume !(0 == ~E_13~0); 55838#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56590#L607 assume !(1 == ~m_pc~0); 55908#L607-2 is_master_triggered_~__retres1~0#1 := 0; 55909#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56970#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56509#L1560 assume !(0 != activate_threads_~tmp~1#1); 56510#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55732#L626 assume !(1 == ~t1_pc~0); 55733#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56003#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56004#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56174#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 55632#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55633#L645 assume 1 == ~t2_pc~0; 55749#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55706#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56389#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56390#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56485#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56486#L664 assume 1 == ~t3_pc~0; 57293#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55473#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55474#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56135#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56136#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57183#L683 assume !(1 == ~t4_pc~0); 56707#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56657#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56658#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56693#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56822#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56432#L702 assume 1 == ~t5_pc~0; 56433#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56358#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56817#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57137#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57072#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55521#L721 assume !(1 == ~t6_pc~0); 55495#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55496#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55659#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56144#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56145#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56755#L740 assume 1 == ~t7_pc~0; 55570#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55383#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55384#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55373#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55374#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56079#L759 assume !(1 == ~t8_pc~0); 56080#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56110#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56815#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56816#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 56955#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57266#L778 assume 1 == ~t9_pc~0; 57134#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55548#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55488#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55417#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55418#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55745#L797 assume !(1 == ~t10_pc~0); 55746#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 55865#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57027#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56252#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56253#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56549#L816 assume 1 == ~t11_pc~0; 55453#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55454#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56212#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56151#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56152#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56682#L835 assume 1 == ~t12_pc~0; 56562#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55617#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55639#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55780#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56310#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56311#L854 assume !(1 == ~t13_pc~0); 55948#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 55949#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55999#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55657#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 55658#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57067#L1401 assume !(1 == ~M_E~0); 56139#L1401-2 assume !(1 == ~T1_E~0); 56140#L1406-1 assume !(1 == ~T2_E~0); 56744#L1411-1 assume !(1 == ~T3_E~0); 56745#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56405#L1421-1 assume !(1 == ~T5_E~0); 55944#L1426-1 assume !(1 == ~T6_E~0); 55945#L1431-1 assume !(1 == ~T7_E~0); 55491#L1436-1 assume !(1 == ~T8_E~0); 55492#L1441-1 assume !(1 == ~T9_E~0); 56243#L1446-1 assume !(1 == ~T10_E~0); 56244#L1451-1 assume !(1 == ~T11_E~0); 56969#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56609#L1461-1 assume !(1 == ~T13_E~0); 56163#L1466-1 assume !(1 == ~E_1~0); 56164#L1471-1 assume !(1 == ~E_2~0); 56953#L1476-1 assume !(1 == ~E_3~0); 56954#L1481-1 assume !(1 == ~E_4~0); 57115#L1486-1 assume !(1 == ~E_5~0); 55785#L1491-1 assume !(1 == ~E_6~0); 55425#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55426#L1501-1 assume !(1 == ~E_8~0); 56241#L1506-1 assume !(1 == ~E_9~0); 56242#L1511-1 assume !(1 == ~E_10~0); 56197#L1516-1 assume !(1 == ~E_11~0); 55369#L1521-1 assume !(1 == ~E_12~0); 55370#L1526-1 assume !(1 == ~E_13~0); 55424#L1531-1 assume { :end_inline_reset_delta_events } true; 55969#L1892-2 [2022-11-16 10:56:59,715 INFO L750 eck$LassoCheckResult]: Loop: 55969#L1892-2 assume !false; 57386#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57384#L1233 assume !false; 57218#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56492#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56650#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55467#L1046 assume !(0 != eval_~tmp~0#1); 55469#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58593#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58592#L1258-3 assume !(0 == ~M_E~0); 57333#L1258-5 assume !(0 == ~T1_E~0); 55645#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55646#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57281#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57288#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57289#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55870#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55871#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57013#L1298-3 assume !(0 == ~T9_E~0); 57014#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 57190#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 57012#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56496#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 55647#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55648#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57106#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55790#L1338-3 assume !(0 == ~E_4~0); 55791#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56923#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57112#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57113#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 56450#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 56005#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 56006#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 56775#L1378-3 assume !(0 == ~E_12~0); 56776#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 56966#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56967#L607-42 assume !(1 == ~m_pc~0); 56568#L607-44 is_master_triggered_~__retres1~0#1 := 0; 58412#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58411#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58410#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58409#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58408#L626-42 assume 1 == ~t1_pc~0; 58406#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58405#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58404#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58403#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58402#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58401#L645-42 assume 1 == ~t2_pc~0; 58400#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58398#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58397#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58396#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58395#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58394#L664-42 assume 1 == ~t3_pc~0; 58392#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58391#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58390#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58389#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58388#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58387#L683-42 assume !(1 == ~t4_pc~0); 58385#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 58384#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58383#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58382#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58381#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58380#L702-42 assume 1 == ~t5_pc~0; 58378#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58377#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58376#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58375#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 58374#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58373#L721-42 assume 1 == ~t6_pc~0; 58371#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58370#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58369#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58368#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58367#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58366#L740-42 assume 1 == ~t7_pc~0; 58364#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58363#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58362#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58361#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58360#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58359#L759-42 assume 1 == ~t8_pc~0; 58357#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58356#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58355#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58354#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58353#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58352#L778-42 assume 1 == ~t9_pc~0; 56272#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56274#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58350#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58348#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58345#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58343#L797-42 assume 1 == ~t10_pc~0; 58340#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56827#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56828#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57161#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 57331#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58327#L816-42 assume !(1 == ~t11_pc~0); 58323#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 58321#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58320#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58319#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58318#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58317#L835-42 assume 1 == ~t12_pc~0; 58315#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58314#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58313#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58312#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58311#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58310#L854-42 assume !(1 == ~t13_pc~0); 58308#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 58307#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58306#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58305#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58304#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57326#L1401-3 assume !(1 == ~M_E~0); 57327#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58805#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58096#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58095#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58093#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58090#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58088#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58086#L1436-3 assume !(1 == ~T8_E~0); 58084#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 58082#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58080#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58077#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58075#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58073#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 58071#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58070#L1476-3 assume !(1 == ~E_3~0); 58069#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58068#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58067#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58066#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58065#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58064#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 58063#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58062#L1516-3 assume !(1 == ~E_11~0); 58061#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58060#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58059#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57867#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57332#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56626#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 56262#L1911 assume !(0 == start_simulation_~tmp~3#1); 56263#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57473#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57458#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57455#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 57453#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57451#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57449#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57447#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 55969#L1892-2 [2022-11-16 10:56:59,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:59,716 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2022-11-16 10:56:59,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:59,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864497597] [2022-11-16 10:56:59,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:59,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:59,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:59,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:59,820 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:59,820 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864497597] [2022-11-16 10:56:59,820 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864497597] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:59,820 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:59,820 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:59,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401210722] [2022-11-16 10:56:59,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:59,821 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:56:59,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:56:59,822 INFO L85 PathProgramCache]: Analyzing trace with hash 1909928847, now seen corresponding path program 1 times [2022-11-16 10:56:59,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:56:59,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239300168] [2022-11-16 10:56:59,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:56:59,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:56:59,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:56:59,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:56:59,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:56:59,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239300168] [2022-11-16 10:56:59,893 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239300168] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:56:59,893 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:56:59,894 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:56:59,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932694649] [2022-11-16 10:56:59,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:56:59,894 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:56:59,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:56:59,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:56:59,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:56:59,897 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:00,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:57:00,084 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-11-16 10:57:00,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6962 states and 10199 transitions. [2022-11-16 10:57:00,117 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-11-16 10:57:00,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-11-16 10:57:00,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6962 [2022-11-16 10:57:00,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6962 [2022-11-16 10:57:00,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6962 states and 10199 transitions. [2022-11-16 10:57:00,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:57:00,157 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-11-16 10:57:00,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6962 states and 10199 transitions. [2022-11-16 10:57:00,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6962 to 6962. [2022-11-16 10:57:00,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:00,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-11-16 10:57:00,330 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-11-16 10:57:00,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 10:57:00,332 INFO L428 stractBuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-11-16 10:57:00,332 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-16 10:57:00,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6962 states and 10199 transitions. [2022-11-16 10:57:00,359 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-11-16 10:57:00,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:57:00,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:57:00,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:00,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:00,363 INFO L748 eck$LassoCheckResult]: Stem: 66743#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66744#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 66559#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66270#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66271#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 67472#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67473#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66410#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66411#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66871#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66704#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66705#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66477#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66478#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66882#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67059#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67212#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67249#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 66490#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66491#L1258 assume !(0 == ~M_E~0); 67704#L1258-2 assume !(0 == ~T1_E~0); 66789#L1263-1 assume !(0 == ~T2_E~0); 66790#L1268-1 assume !(0 == ~T3_E~0); 67093#L1273-1 assume !(0 == ~T4_E~0); 67684#L1278-1 assume !(0 == ~T5_E~0); 67530#L1283-1 assume !(0 == ~T6_E~0); 67531#L1288-1 assume !(0 == ~T7_E~0); 67800#L1293-1 assume !(0 == ~T8_E~0); 67785#L1298-1 assume !(0 == ~T9_E~0); 67698#L1303-1 assume !(0 == ~T10_E~0); 66299#L1308-1 assume !(0 == ~T11_E~0); 66241#L1313-1 assume !(0 == ~T12_E~0); 66242#L1318-1 assume !(0 == ~T13_E~0); 66248#L1323-1 assume !(0 == ~E_1~0); 66249#L1328-1 assume !(0 == ~E_2~0); 66420#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 67395#L1338-1 assume !(0 == ~E_4~0); 67396#L1343-1 assume !(0 == ~E_5~0); 67502#L1348-1 assume !(0 == ~E_6~0); 67832#L1353-1 assume !(0 == ~E_7~0); 67112#L1358-1 assume !(0 == ~E_8~0); 67113#L1363-1 assume !(0 == ~E_9~0); 67414#L1368-1 assume !(0 == ~E_10~0); 66078#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 66079#L1378-1 assume !(0 == ~E_12~0); 66367#L1383-1 assume !(0 == ~E_13~0); 66368#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67118#L607 assume !(1 == ~m_pc~0); 66439#L607-2 is_master_triggered_~__retres1~0#1 := 0; 66440#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67500#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67039#L1560 assume !(0 != activate_threads_~tmp~1#1); 67040#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66261#L626 assume !(1 == ~t1_pc~0); 66262#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66535#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66536#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66708#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 66161#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66162#L645 assume 1 == ~t2_pc~0; 66278#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66235#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66924#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66925#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 67015#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67016#L664 assume 1 == ~t3_pc~0; 67828#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66001#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66002#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66669#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 66670#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67717#L683 assume !(1 == ~t4_pc~0); 67234#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67186#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67187#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67221#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67355#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66965#L702 assume 1 == ~t5_pc~0; 66966#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66891#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67350#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67670#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 67602#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66050#L721 assume !(1 == ~t6_pc~0); 66024#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66025#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66188#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66678#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 66679#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67283#L740 assume 1 == ~t7_pc~0; 66099#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65910#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65911#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65900#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 65901#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66611#L759 assume !(1 == ~t8_pc~0); 66612#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 66644#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67348#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67349#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 67486#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67799#L778 assume 1 == ~t9_pc~0; 67666#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66077#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66016#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65944#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 65945#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66275#L797 assume !(1 == ~t10_pc~0); 66276#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66397#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67555#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66787#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 66788#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67077#L816 assume 1 == ~t11_pc~0; 65981#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65982#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66749#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66685#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 66686#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67211#L835 assume 1 == ~t12_pc~0; 67090#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66146#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66168#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66310#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 66844#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66845#L854 assume !(1 == ~t13_pc~0); 66479#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 66480#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66531#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66186#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66187#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67597#L1401 assume !(1 == ~M_E~0); 66673#L1401-2 assume !(1 == ~T1_E~0); 66674#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67605#L1411-1 assume !(1 == ~T3_E~0); 68028#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68027#L1421-1 assume !(1 == ~T5_E~0); 68026#L1426-1 assume !(1 == ~T6_E~0); 68025#L1431-1 assume !(1 == ~T7_E~0); 68024#L1436-1 assume !(1 == ~T8_E~0); 66020#L1441-1 assume !(1 == ~T9_E~0); 68023#L1446-1 assume !(1 == ~T10_E~0); 68022#L1451-1 assume !(1 == ~T11_E~0); 68021#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 68020#L1461-1 assume !(1 == ~T13_E~0); 68019#L1466-1 assume !(1 == ~E_1~0); 68018#L1471-1 assume !(1 == ~E_2~0); 68017#L1476-1 assume !(1 == ~E_3~0); 68016#L1481-1 assume !(1 == ~E_4~0); 68015#L1486-1 assume !(1 == ~E_5~0); 68014#L1491-1 assume !(1 == ~E_6~0); 68013#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 68012#L1501-1 assume !(1 == ~E_8~0); 68011#L1506-1 assume !(1 == ~E_9~0); 68010#L1511-1 assume !(1 == ~E_10~0); 68009#L1516-1 assume !(1 == ~E_11~0); 65896#L1521-1 assume !(1 == ~E_12~0); 65897#L1526-1 assume !(1 == ~E_13~0); 67952#L1531-1 assume { :end_inline_reset_delta_events } true; 67938#L1892-2 [2022-11-16 10:57:00,363 INFO L750 eck$LassoCheckResult]: Loop: 67938#L1892-2 assume !false; 67927#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67921#L1233 assume !false; 67920#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 67904#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67889#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67887#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 67884#L1046 assume !(0 != eval_~tmp~0#1); 67881#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67879#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67877#L1258-3 assume !(0 == ~M_E~0); 67874#L1258-5 assume !(0 == ~T1_E~0); 67873#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67816#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67817#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67825#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67826#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66402#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66403#L1293-3 assume !(0 == ~T8_E~0); 67544#L1298-3 assume !(0 == ~T9_E~0); 67545#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67723#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 67543#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 67026#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 66176#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66177#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67636#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66320#L1338-3 assume !(0 == ~E_4~0); 66321#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67456#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67642#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67643#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66982#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 66537#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 66538#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67302#L1378-3 assume !(0 == ~E_12~0); 67303#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 67496#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67497#L607-42 assume !(1 == ~m_pc~0); 67096#L607-44 is_master_triggered_~__retres1~0#1 := 0; 66823#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66824#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66551#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66552#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67078#L626-42 assume !(1 == ~t1_pc~0); 66640#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 66639#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66945#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66946#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66210#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66211#L645-42 assume 1 == ~t2_pc~0; 67714#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 67433#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67610#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66421#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65922#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65923#L664-42 assume 1 == ~t3_pc~0; 66736#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66456#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67754#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67247#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67248#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67425#L683-42 assume !(1 == ~t4_pc~0); 67121#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 67122#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67254#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67710#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67711#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67538#L702-42 assume 1 == ~t5_pc~0; 67008#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66631#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66929#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67628#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 65938#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65939#L721-42 assume !(1 == ~t6_pc~0); 66095#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 66114#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66583#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67805#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66759#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66601#L740-42 assume 1 == ~t7_pc~0; 66602#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66336#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66885#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66739#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66740#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67014#L759-42 assume !(1 == ~t8_pc~0); 66864#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 66795#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66796#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66874#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66875#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66970#L778-42 assume 1 == ~t9_pc~0; 66807#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66809#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67218#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 67123#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 67124#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67180#L797-42 assume 1 == ~t10_pc~0; 66341#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 66342#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67360#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67693#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 67219#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67220#L816-42 assume !(1 == ~t11_pc~0); 65888#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 65887#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66435#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66436#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66515#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 66516#L835-42 assume 1 == ~t12_pc~0; 66923#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66816#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66488#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66489#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 67601#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 67373#L854-42 assume !(1 == ~t13_pc~0); 66431#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 66432#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66041#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66042#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66695#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66696#L1401-3 assume !(1 == ~M_E~0); 67491#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66274#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66139#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66140#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66750#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66751#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66318#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 66319#L1436-3 assume !(1 == ~T8_E~0); 65902#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65903#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 67519#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 66835#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 66482#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 66483#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67820#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66422#L1476-3 assume !(1 == ~E_3~0); 66423#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66829#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66450#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 66451#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66868#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 66869#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 67297#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 67288#L1516-3 assume !(1 == ~E_11~0); 67289#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69451#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69450#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68626#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68622#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68620#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 68523#L1911 assume !(0 == start_simulation_~tmp~3#1); 68514#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68008#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67991#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67989#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 67987#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 67986#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67985#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 67951#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 67938#L1892-2 [2022-11-16 10:57:00,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:00,365 INFO L85 PathProgramCache]: Analyzing trace with hash -1259435077, now seen corresponding path program 1 times [2022-11-16 10:57:00,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:00,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802660815] [2022-11-16 10:57:00,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:00,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:00,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:00,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:00,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:00,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802660815] [2022-11-16 10:57:00,456 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [802660815] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:00,456 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:00,456 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:00,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034277789] [2022-11-16 10:57:00,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:00,457 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:57:00,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:00,457 INFO L85 PathProgramCache]: Analyzing trace with hash -1642693526, now seen corresponding path program 1 times [2022-11-16 10:57:00,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:00,458 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607203175] [2022-11-16 10:57:00,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:00,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:00,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:00,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:00,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:00,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607203175] [2022-11-16 10:57:00,523 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607203175] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:00,524 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:00,524 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:00,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132276668] [2022-11-16 10:57:00,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:00,524 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:57:00,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:57:00,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:57:00,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:57:00,526 INFO L87 Difference]: Start difference. First operand 6962 states and 10199 transitions. cyclomatic complexity: 3239 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:00,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:57:00,802 INFO L93 Difference]: Finished difference Result 13360 states and 19568 transitions. [2022-11-16 10:57:00,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13360 states and 19568 transitions. [2022-11-16 10:57:00,869 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2022-11-16 10:57:00,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13360 states to 13360 states and 19568 transitions. [2022-11-16 10:57:00,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13360 [2022-11-16 10:57:00,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13360 [2022-11-16 10:57:00,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13360 states and 19568 transitions. [2022-11-16 10:57:00,941 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:57:00,941 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13360 states and 19568 transitions. [2022-11-16 10:57:00,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13360 states and 19568 transitions. [2022-11-16 10:57:01,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13360 to 13356. [2022-11-16 10:57:01,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13356 states, 13356 states have (on average 1.4648098233003894) internal successors, (19564), 13355 states have internal predecessors, (19564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:01,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13356 states to 13356 states and 19564 transitions. [2022-11-16 10:57:01,264 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13356 states and 19564 transitions. [2022-11-16 10:57:01,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 10:57:01,265 INFO L428 stractBuchiCegarLoop]: Abstraction has 13356 states and 19564 transitions. [2022-11-16 10:57:01,266 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-16 10:57:01,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13356 states and 19564 transitions. [2022-11-16 10:57:01,314 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2022-11-16 10:57:01,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:57:01,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:57:01,317 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:01,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:01,318 INFO L748 eck$LassoCheckResult]: Stem: 87074#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 87075#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86888#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86600#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86601#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 87808#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87809#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86738#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86739#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87208#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87036#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87037#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86807#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 86808#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87219#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 87398#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 87553#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 87590#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86818#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86819#L1258 assume !(0 == ~M_E~0); 88043#L1258-2 assume !(0 == ~T1_E~0); 87121#L1263-1 assume !(0 == ~T2_E~0); 87122#L1268-1 assume !(0 == ~T3_E~0); 87432#L1273-1 assume !(0 == ~T4_E~0); 88021#L1278-1 assume !(0 == ~T5_E~0); 87867#L1283-1 assume !(0 == ~T6_E~0); 87868#L1288-1 assume !(0 == ~T7_E~0); 88139#L1293-1 assume !(0 == ~T8_E~0); 88127#L1298-1 assume !(0 == ~T9_E~0); 88037#L1303-1 assume !(0 == ~T10_E~0); 86630#L1308-1 assume !(0 == ~T11_E~0); 86571#L1313-1 assume !(0 == ~T12_E~0); 86572#L1318-1 assume !(0 == ~T13_E~0); 86578#L1323-1 assume !(0 == ~E_1~0); 86579#L1328-1 assume !(0 == ~E_2~0); 86748#L1333-1 assume !(0 == ~E_3~0); 87734#L1338-1 assume !(0 == ~E_4~0); 87735#L1343-1 assume !(0 == ~E_5~0); 87841#L1348-1 assume !(0 == ~E_6~0); 88165#L1353-1 assume !(0 == ~E_7~0); 87453#L1358-1 assume !(0 == ~E_8~0); 87454#L1363-1 assume !(0 == ~E_9~0); 87752#L1368-1 assume !(0 == ~E_10~0); 86407#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 86408#L1378-1 assume !(0 == ~E_12~0); 86697#L1383-1 assume !(0 == ~E_13~0); 86698#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87459#L607 assume !(1 == ~m_pc~0); 86767#L607-2 is_master_triggered_~__retres1~0#1 := 0; 86768#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87839#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87378#L1560 assume !(0 != activate_threads_~tmp~1#1); 87379#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86591#L626 assume !(1 == ~t1_pc~0); 86592#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86864#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86865#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87040#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 86491#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86492#L645 assume 1 == ~t2_pc~0; 86609#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86565#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87259#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87260#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 87354#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87355#L664 assume 1 == ~t3_pc~0; 88163#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86332#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86333#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86999#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 87000#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88053#L683 assume !(1 == ~t4_pc~0); 87575#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 87527#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87528#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87562#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87693#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87303#L702 assume 1 == ~t5_pc~0; 87304#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87228#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87688#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88005#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 87938#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86379#L721 assume !(1 == ~t6_pc~0); 86354#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86355#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86518#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87008#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 87009#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87626#L740 assume 1 == ~t7_pc~0; 86428#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86242#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86243#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86232#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 86233#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86944#L759 assume !(1 == ~t8_pc~0); 86945#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 86974#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87686#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87687#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 87823#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88138#L778 assume 1 == ~t9_pc~0; 88002#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86406#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86347#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86276#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 86277#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86604#L797 assume !(1 == ~t10_pc~0); 86605#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86725#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87893#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87119#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 87120#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87416#L816 assume 1 == ~t11_pc~0; 86312#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86313#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87079#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87017#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 87018#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87552#L835 assume 1 == ~t12_pc~0; 87429#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 86475#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86498#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86640#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 87181#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87182#L854 assume !(1 == ~t13_pc~0); 86809#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 86810#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86860#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86516#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86517#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87933#L1401 assume !(1 == ~M_E~0); 87003#L1401-2 assume !(1 == ~T1_E~0); 87004#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87615#L1411-1 assume !(1 == ~T3_E~0); 87616#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87275#L1421-1 assume !(1 == ~T5_E~0); 87276#L1426-1 assume !(1 == ~T6_E~0); 87763#L1431-1 assume !(1 == ~T7_E~0); 86350#L1436-1 assume !(1 == ~T8_E~0); 86351#L1441-1 assume !(1 == ~T9_E~0); 89573#L1446-1 assume !(1 == ~T10_E~0); 89572#L1451-1 assume !(1 == ~T11_E~0); 89570#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 89568#L1461-1 assume !(1 == ~T13_E~0); 89567#L1466-1 assume !(1 == ~E_1~0); 88186#L1471-1 assume !(1 == ~E_2~0); 88187#L1476-1 assume !(1 == ~E_3~0); 89475#L1481-1 assume !(1 == ~E_4~0); 89455#L1486-1 assume !(1 == ~E_5~0); 89408#L1491-1 assume !(1 == ~E_6~0); 89366#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 89364#L1501-1 assume !(1 == ~E_8~0); 89341#L1506-1 assume !(1 == ~E_9~0); 89315#L1511-1 assume !(1 == ~E_10~0); 89303#L1516-1 assume !(1 == ~E_11~0); 89293#L1521-1 assume !(1 == ~E_12~0); 89284#L1526-1 assume !(1 == ~E_13~0); 89276#L1531-1 assume { :end_inline_reset_delta_events } true; 89269#L1892-2 [2022-11-16 10:57:01,319 INFO L750 eck$LassoCheckResult]: Loop: 89269#L1892-2 assume !false; 89264#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89263#L1233 assume !false; 89262#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89248#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 89247#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89246#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 89244#L1046 assume !(0 != eval_~tmp~0#1); 89243#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89242#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89241#L1258-3 assume !(0 == ~M_E~0); 89240#L1258-5 assume !(0 == ~T1_E~0); 89238#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 89237#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89236#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 89235#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 89234#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 89232#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 89233#L1293-3 assume !(0 == ~T8_E~0); 91637#L1298-3 assume !(0 == ~T9_E~0); 91635#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 91463#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 91310#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 91308#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 91306#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 91304#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 91302#L1333-3 assume !(0 == ~E_3~0); 91300#L1338-3 assume !(0 == ~E_4~0); 91298#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 91296#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 91294#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 91293#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 91132#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 91130#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 91128#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 91126#L1378-3 assume !(0 == ~E_12~0); 91124#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 91122#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90919#L607-42 assume !(1 == ~m_pc~0); 90916#L607-44 is_master_triggered_~__retres1~0#1 := 0; 90913#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90911#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 90909#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 90907#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 90905#L626-42 assume !(1 == ~t1_pc~0); 90903#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 90899#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90897#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 90895#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 90893#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90891#L645-42 assume 1 == ~t2_pc~0; 90889#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 90887#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90886#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 90885#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 90884#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 90883#L664-42 assume !(1 == ~t3_pc~0); 90881#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 90877#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90875#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90873#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 90871#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 90869#L683-42 assume 1 == ~t4_pc~0; 90864#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 90861#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 90859#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 90650#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 90649#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90422#L702-42 assume 1 == ~t5_pc~0; 90419#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 90417#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 90415#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 90414#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 90413#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90410#L721-42 assume 1 == ~t6_pc~0; 90407#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 90405#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 90403#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 90401#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 90399#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90396#L740-42 assume 1 == ~t7_pc~0; 90393#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 90392#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 90391#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 90390#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 90389#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 90388#L759-42 assume 1 == ~t8_pc~0; 90385#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 90383#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 90380#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 90378#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 90376#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 90374#L778-42 assume !(1 == ~t9_pc~0); 90371#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 90369#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 90366#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 90364#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 90362#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 90360#L797-42 assume 1 == ~t10_pc~0; 90357#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 90355#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 90352#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 90350#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 90349#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 90348#L816-42 assume 1 == ~t11_pc~0; 90347#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 90345#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 90344#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 90342#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 90340#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 90338#L835-42 assume 1 == ~t12_pc~0; 90333#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 90331#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 90329#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 90327#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 90325#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 90324#L854-42 assume 1 == ~t13_pc~0; 90155#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 90000#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 89885#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 89883#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 89881#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89796#L1401-3 assume !(1 == ~M_E~0); 89793#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89792#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86608#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89790#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89711#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89709#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 89707#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 89636#L1436-3 assume !(1 == ~T8_E~0); 89635#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 89633#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 89631#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 89629#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 89627#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 89625#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 89623#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 89580#L1476-3 assume !(1 == ~E_3~0); 89576#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89529#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89527#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 89482#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89480#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 89458#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 89424#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 89423#L1516-3 assume !(1 == ~E_11~0); 89422#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 89421#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 89420#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89380#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 89375#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89373#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 89369#L1911 assume !(0 == start_simulation_~tmp~3#1); 89342#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89340#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 89314#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89313#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 89302#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89292#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89283#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 89275#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 89269#L1892-2 [2022-11-16 10:57:01,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:01,319 INFO L85 PathProgramCache]: Analyzing trace with hash -312397191, now seen corresponding path program 1 times [2022-11-16 10:57:01,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:01,320 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431141419] [2022-11-16 10:57:01,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:01,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:01,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:01,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:01,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:01,503 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431141419] [2022-11-16 10:57:01,503 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431141419] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:01,503 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:01,504 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:01,504 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [730888846] [2022-11-16 10:57:01,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:01,504 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:57:01,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:01,505 INFO L85 PathProgramCache]: Analyzing trace with hash -2120296373, now seen corresponding path program 1 times [2022-11-16 10:57:01,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:01,506 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349585640] [2022-11-16 10:57:01,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:01,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:01,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:01,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:01,569 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:01,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349585640] [2022-11-16 10:57:01,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1349585640] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:01,569 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:01,569 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:01,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [91833013] [2022-11-16 10:57:01,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:01,570 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:57:01,570 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:57:01,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:57:01,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:57:01,571 INFO L87 Difference]: Start difference. First operand 13356 states and 19564 transitions. cyclomatic complexity: 6212 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:01,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:57:01,874 INFO L93 Difference]: Finished difference Result 25712 states and 37649 transitions. [2022-11-16 10:57:01,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25712 states and 37649 transitions. [2022-11-16 10:57:02,074 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2022-11-16 10:57:02,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25712 states to 25712 states and 37649 transitions. [2022-11-16 10:57:02,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25712 [2022-11-16 10:57:02,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25712 [2022-11-16 10:57:02,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25712 states and 37649 transitions. [2022-11-16 10:57:02,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:57:02,221 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25712 states and 37649 transitions. [2022-11-16 10:57:02,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25712 states and 37649 transitions. [2022-11-16 10:57:02,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25712 to 25704. [2022-11-16 10:57:02,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25704 states, 25704 states have (on average 1.4644024276377217) internal successors, (37641), 25703 states have internal predecessors, (37641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:02,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25704 states to 25704 states and 37641 transitions. [2022-11-16 10:57:02,859 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25704 states and 37641 transitions. [2022-11-16 10:57:02,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 10:57:02,860 INFO L428 stractBuchiCegarLoop]: Abstraction has 25704 states and 37641 transitions. [2022-11-16 10:57:02,860 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-16 10:57:02,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25704 states and 37641 transitions. [2022-11-16 10:57:02,940 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2022-11-16 10:57:02,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:57:02,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:57:02,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:02,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:02,943 INFO L748 eck$LassoCheckResult]: Stem: 126168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 126169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 125975#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125681#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125682#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 126965#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126966#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125821#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125822#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126307#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 126127#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126128#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 125892#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 125893#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 126318#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 126512#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 126679#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 126722#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 125903#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125904#L1258 assume !(0 == ~M_E~0); 127253#L1258-2 assume !(0 == ~T1_E~0); 126216#L1263-1 assume !(0 == ~T2_E~0); 126217#L1268-1 assume !(0 == ~T3_E~0); 126546#L1273-1 assume !(0 == ~T4_E~0); 127224#L1278-1 assume !(0 == ~T5_E~0); 127040#L1283-1 assume !(0 == ~T6_E~0); 127041#L1288-1 assume !(0 == ~T7_E~0); 127366#L1293-1 assume !(0 == ~T8_E~0); 127349#L1298-1 assume !(0 == ~T9_E~0); 127243#L1303-1 assume !(0 == ~T10_E~0); 125711#L1308-1 assume !(0 == ~T11_E~0); 125652#L1313-1 assume !(0 == ~T12_E~0); 125653#L1318-1 assume !(0 == ~T13_E~0); 125659#L1323-1 assume !(0 == ~E_1~0); 125660#L1328-1 assume !(0 == ~E_2~0); 125832#L1333-1 assume !(0 == ~E_3~0); 126878#L1338-1 assume !(0 == ~E_4~0); 126879#L1343-1 assume !(0 == ~E_5~0); 127008#L1348-1 assume !(0 == ~E_6~0); 127405#L1353-1 assume !(0 == ~E_7~0); 126567#L1358-1 assume !(0 == ~E_8~0); 126568#L1363-1 assume !(0 == ~E_9~0); 126903#L1368-1 assume !(0 == ~E_10~0); 125489#L1373-1 assume !(0 == ~E_11~0); 125490#L1378-1 assume !(0 == ~E_12~0); 125779#L1383-1 assume !(0 == ~E_13~0); 125780#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126573#L607 assume !(1 == ~m_pc~0); 125852#L607-2 is_master_triggered_~__retres1~0#1 := 0; 125853#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127006#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 126487#L1560 assume !(0 != activate_threads_~tmp~1#1); 126488#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125672#L626 assume !(1 == ~t1_pc~0); 125673#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 125950#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125951#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126131#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 125572#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125573#L645 assume 1 == ~t2_pc~0; 125690#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 125646#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126361#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126362#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 126462#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126463#L664 assume 1 == ~t3_pc~0; 127399#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125411#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125412#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126091#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 126092#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127263#L683 assume !(1 == ~t4_pc~0); 126704#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126651#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126652#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126689#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126832#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126406#L702 assume 1 == ~t5_pc~0; 126407#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126327#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126827#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 127206#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 127126#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125461#L721 assume !(1 == ~t6_pc~0); 125434#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 125435#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125599#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 126101#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 126102#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 126761#L740 assume 1 == ~t7_pc~0; 125510#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125320#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125321#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125310#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 125311#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 126036#L759 assume !(1 == ~t8_pc~0); 126037#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 126066#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 126825#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 126826#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 126979#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 127365#L778 assume 1 == ~t9_pc~0; 127203#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 125488#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125426#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125354#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 125355#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125685#L797 assume !(1 == ~t10_pc~0); 125686#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 125808#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127071#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126214#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 126215#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 126530#L816 assume 1 == ~t11_pc~0; 125391#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 125392#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126173#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126108#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 126109#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 126678#L835 assume 1 == ~t12_pc~0; 126543#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125557#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125579#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125722#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 126277#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 126278#L854 assume !(1 == ~t13_pc~0); 125894#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 125895#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125946#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125597#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 125598#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127122#L1401 assume !(1 == ~M_E~0); 126095#L1401-2 assume !(1 == ~T1_E~0); 126096#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 127130#L1411-1 assume !(1 == ~T3_E~0); 135786#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 135785#L1421-1 assume !(1 == ~T5_E~0); 135784#L1426-1 assume !(1 == ~T6_E~0); 135783#L1431-1 assume !(1 == ~T7_E~0); 135782#L1436-1 assume !(1 == ~T8_E~0); 135779#L1441-1 assume !(1 == ~T9_E~0); 135777#L1446-1 assume !(1 == ~T10_E~0); 135775#L1451-1 assume !(1 == ~T11_E~0); 135773#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 135771#L1461-1 assume !(1 == ~T13_E~0); 135769#L1466-1 assume !(1 == ~E_1~0); 135766#L1471-1 assume !(1 == ~E_2~0); 126977#L1476-1 assume !(1 == ~E_3~0); 126978#L1481-1 assume !(1 == ~E_4~0); 127179#L1486-1 assume !(1 == ~E_5~0); 125727#L1491-1 assume !(1 == ~E_6~0); 125362#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 125363#L1501-1 assume !(1 == ~E_8~0); 126202#L1506-1 assume !(1 == ~E_9~0); 126203#L1511-1 assume !(1 == ~E_10~0); 126935#L1516-1 assume !(1 == ~E_11~0); 129278#L1521-1 assume !(1 == ~E_12~0); 129273#L1526-1 assume !(1 == ~E_13~0); 129234#L1531-1 assume { :end_inline_reset_delta_events } true; 129227#L1892-2 [2022-11-16 10:57:02,944 INFO L750 eck$LassoCheckResult]: Loop: 129227#L1892-2 assume !false; 129222#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129221#L1233 assume !false; 129220#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 129206#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 129205#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 129204#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 129202#L1046 assume !(0 != eval_~tmp~0#1); 129201#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 129200#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129199#L1258-3 assume !(0 == ~M_E~0); 129198#L1258-5 assume !(0 == ~T1_E~0); 129196#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 129197#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 138745#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 138741#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 138735#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 138731#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 138727#L1293-3 assume !(0 == ~T8_E~0); 138723#L1298-3 assume !(0 == ~T9_E~0); 138719#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 138715#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 138709#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 138705#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 138701#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 138697#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 138693#L1333-3 assume !(0 == ~E_3~0); 138689#L1338-3 assume !(0 == ~E_4~0); 138683#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 138679#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 138675#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 138671#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 138667#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 138663#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 138660#L1373-3 assume !(0 == ~E_11~0); 138658#L1378-3 assume !(0 == ~E_12~0); 138656#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 138654#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138652#L607-42 assume !(1 == ~m_pc~0); 138648#L607-44 is_master_triggered_~__retres1~0#1 := 0; 138645#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138642#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 138639#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 138636#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138633#L626-42 assume 1 == ~t1_pc~0; 138628#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 138624#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138621#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 138618#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 138615#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138612#L645-42 assume 1 == ~t2_pc~0; 138608#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 138604#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138601#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 138597#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 138594#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138591#L664-42 assume 1 == ~t3_pc~0; 138586#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 138584#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138582#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 138579#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 138576#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 138573#L683-42 assume !(1 == ~t4_pc~0); 138568#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 138565#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138562#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 138559#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 138556#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138553#L702-42 assume 1 == ~t5_pc~0; 138548#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 138545#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138542#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 138539#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 138536#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 138533#L721-42 assume 1 == ~t6_pc~0; 138528#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 138525#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138522#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 138519#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 138516#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 138513#L740-42 assume 1 == ~t7_pc~0; 138508#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 138505#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 138502#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 138499#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 138496#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 138493#L759-42 assume 1 == ~t8_pc~0; 138488#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 138485#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 138481#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 138478#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 138475#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 138472#L778-42 assume !(1 == ~t9_pc~0); 138467#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 138464#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 138461#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 138457#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 138454#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 138451#L797-42 assume 1 == ~t10_pc~0; 138446#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 138443#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 138440#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 138436#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 138433#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 138430#L816-42 assume 1 == ~t11_pc~0; 138426#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 138422#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 138419#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 138415#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 138412#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 138409#L835-42 assume 1 == ~t12_pc~0; 138404#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 138401#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 138398#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 138394#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 138391#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 138388#L854-42 assume 1 == ~t13_pc~0; 138384#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 138380#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 138377#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 138373#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 138368#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138363#L1401-3 assume !(1 == ~M_E~0); 138360#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 138357#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128855#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138351#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 138348#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 128679#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 128677#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 128678#L1436-3 assume !(1 == ~T8_E~0); 129864#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 129862#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 129440#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 129438#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 129436#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 129434#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 129432#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 129396#L1476-3 assume !(1 == ~E_3~0); 129375#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 129373#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 129371#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 129364#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 129356#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 129351#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 129346#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 129339#L1516-3 assume !(1 == ~E_11~0); 129335#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 129331#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 129327#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 129312#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 129305#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 129301#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 129298#L1911 assume !(0 == start_simulation_~tmp~3#1); 129295#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 129293#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 129267#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 129258#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 129251#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 129245#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129240#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 129233#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 129227#L1892-2 [2022-11-16 10:57:02,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:02,946 INFO L85 PathProgramCache]: Analyzing trace with hash -645040329, now seen corresponding path program 1 times [2022-11-16 10:57:02,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:02,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1976699677] [2022-11-16 10:57:02,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:02,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:02,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:03,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:03,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:03,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1976699677] [2022-11-16 10:57:03,032 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1976699677] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:03,032 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:03,032 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:03,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113423095] [2022-11-16 10:57:03,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:03,033 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:57:03,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:03,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1142774762, now seen corresponding path program 1 times [2022-11-16 10:57:03,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:03,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161541647] [2022-11-16 10:57:03,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:03,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:03,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:03,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:03,097 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:03,097 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161541647] [2022-11-16 10:57:03,098 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161541647] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:03,098 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:03,098 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:03,098 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23554005] [2022-11-16 10:57:03,098 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:03,099 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:57:03,099 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:57:03,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:57:03,100 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:57:03,100 INFO L87 Difference]: Start difference. First operand 25704 states and 37641 transitions. cyclomatic complexity: 11945 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:03,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:57:03,898 INFO L93 Difference]: Finished difference Result 74990 states and 108892 transitions. [2022-11-16 10:57:03,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74990 states and 108892 transitions. [2022-11-16 10:57:04,412 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 73032 [2022-11-16 10:57:04,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74990 states to 74990 states and 108892 transitions. [2022-11-16 10:57:04,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74990 [2022-11-16 10:57:04,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74990 [2022-11-16 10:57:04,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74990 states and 108892 transitions. [2022-11-16 10:57:04,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:57:04,966 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74990 states and 108892 transitions. [2022-11-16 10:57:05,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74990 states and 108892 transitions. [2022-11-16 10:57:06,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74990 to 72678. [2022-11-16 10:57:06,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72678 states, 72678 states have (on average 1.454140179971931) internal successors, (105684), 72677 states have internal predecessors, (105684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:06,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72678 states to 72678 states and 105684 transitions. [2022-11-16 10:57:06,670 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72678 states and 105684 transitions. [2022-11-16 10:57:06,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 10:57:06,671 INFO L428 stractBuchiCegarLoop]: Abstraction has 72678 states and 105684 transitions. [2022-11-16 10:57:06,671 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-16 10:57:06,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72678 states and 105684 transitions. [2022-11-16 10:57:07,269 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 72352 [2022-11-16 10:57:07,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:57:07,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:57:07,273 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:07,273 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:07,274 INFO L748 eck$LassoCheckResult]: Stem: 226858#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 226859#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 226675#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 226387#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 226388#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 227623#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 227624#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 226524#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 226525#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 226990#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 226818#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 226819#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 226594#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 226595#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 227002#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 227188#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 227347#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 227387#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 226605#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 226606#L1258 assume !(0 == ~M_E~0); 227879#L1258-2 assume !(0 == ~T1_E~0); 226905#L1263-1 assume !(0 == ~T2_E~0); 226906#L1268-1 assume !(0 == ~T3_E~0); 227222#L1273-1 assume !(0 == ~T4_E~0); 227858#L1278-1 assume !(0 == ~T5_E~0); 227685#L1283-1 assume !(0 == ~T6_E~0); 227686#L1288-1 assume !(0 == ~T7_E~0); 228001#L1293-1 assume !(0 == ~T8_E~0); 227978#L1298-1 assume !(0 == ~T9_E~0); 227872#L1303-1 assume !(0 == ~T10_E~0); 226416#L1308-1 assume !(0 == ~T11_E~0); 226358#L1313-1 assume !(0 == ~T12_E~0); 226359#L1318-1 assume !(0 == ~T13_E~0); 226365#L1323-1 assume !(0 == ~E_1~0); 226366#L1328-1 assume !(0 == ~E_2~0); 226534#L1333-1 assume !(0 == ~E_3~0); 227535#L1338-1 assume !(0 == ~E_4~0); 227536#L1343-1 assume !(0 == ~E_5~0); 227656#L1348-1 assume !(0 == ~E_6~0); 228039#L1353-1 assume !(0 == ~E_7~0); 227241#L1358-1 assume !(0 == ~E_8~0); 227242#L1363-1 assume !(0 == ~E_9~0); 227556#L1368-1 assume !(0 == ~E_10~0); 226191#L1373-1 assume !(0 == ~E_11~0); 226192#L1378-1 assume !(0 == ~E_12~0); 226483#L1383-1 assume !(0 == ~E_13~0); 226484#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227247#L607 assume !(1 == ~m_pc~0); 226553#L607-2 is_master_triggered_~__retres1~0#1 := 0; 226554#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227654#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 227166#L1560 assume !(0 != activate_threads_~tmp~1#1); 227167#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226378#L626 assume !(1 == ~t1_pc~0); 226379#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 226651#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 226652#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 226822#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 226277#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226278#L645 assume !(1 == ~t2_pc~0); 226351#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 226352#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227045#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 227046#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 227141#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 227142#L664 assume 1 == ~t3_pc~0; 228034#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 226114#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 226115#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 226784#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 226785#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227896#L683 assume !(1 == ~t4_pc~0); 227371#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 227320#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 227321#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 227356#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 227492#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227088#L702 assume 1 == ~t5_pc~0; 227089#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 227013#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227487#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 227842#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 227766#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226163#L721 assume !(1 == ~t6_pc~0); 226136#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 226137#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226304#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 226793#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 226794#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 227423#L740 assume 1 == ~t7_pc~0; 226213#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226024#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 226025#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 226014#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 226015#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 226728#L759 assume !(1 == ~t8_pc~0); 226729#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 226758#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 227485#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 227486#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 227636#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 228000#L778 assume 1 == ~t9_pc~0; 227839#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 226190#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 226129#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 226058#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 226059#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 226391#L797 assume !(1 == ~t10_pc~0); 226392#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 226511#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227714#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 226903#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 226904#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227206#L816 assume 1 == ~t11_pc~0; 226094#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 226095#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 226862#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 226800#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 226801#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 227346#L835 assume 1 == ~t12_pc~0; 227219#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 226262#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 226284#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 226426#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 226961#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 226962#L854 assume !(1 == ~t13_pc~0); 226596#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 226597#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 226647#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 226302#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 226303#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227760#L1401 assume !(1 == ~M_E~0); 226788#L1401-2 assume !(1 == ~T1_E~0); 226789#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 227411#L1411-1 assume !(1 == ~T3_E~0); 227412#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 227061#L1421-1 assume !(1 == ~T5_E~0); 226592#L1426-1 assume !(1 == ~T6_E~0); 226593#L1431-1 assume !(1 == ~T7_E~0); 226132#L1436-1 assume !(1 == ~T8_E~0); 226133#L1441-1 assume !(1 == ~T9_E~0); 226894#L1446-1 assume !(1 == ~T10_E~0); 226895#L1451-1 assume !(1 == ~T11_E~0); 227653#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 227267#L1461-1 assume !(1 == ~T13_E~0); 226812#L1466-1 assume !(1 == ~E_1~0); 226813#L1471-1 assume !(1 == ~E_2~0); 227634#L1476-1 assume !(1 == ~E_3~0); 227635#L1481-1 assume !(1 == ~E_4~0); 280576#L1486-1 assume !(1 == ~E_5~0); 226431#L1491-1 assume !(1 == ~E_6~0); 226066#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 226067#L1501-1 assume !(1 == ~E_8~0); 226892#L1506-1 assume !(1 == ~E_9~0); 226893#L1511-1 assume !(1 == ~E_10~0); 227594#L1516-1 assume !(1 == ~E_11~0); 276574#L1521-1 assume !(1 == ~E_12~0); 276572#L1526-1 assume !(1 == ~E_13~0); 276518#L1531-1 assume { :end_inline_reset_delta_events } true; 276505#L1892-2 [2022-11-16 10:57:07,274 INFO L750 eck$LassoCheckResult]: Loop: 276505#L1892-2 assume !false; 276495#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 276493#L1233 assume !false; 276492#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 276477#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 276462#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 276454#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 276440#L1046 assume !(0 != eval_~tmp~0#1); 276442#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 282930#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282928#L1258-3 assume !(0 == ~M_E~0); 282926#L1258-5 assume !(0 == ~T1_E~0); 282924#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 282922#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 282920#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 282918#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 282916#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 282914#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 282912#L1293-3 assume !(0 == ~T8_E~0); 282910#L1298-3 assume !(0 == ~T9_E~0); 282908#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 282906#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 282904#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 282902#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 282900#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 282898#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 282896#L1333-3 assume !(0 == ~E_3~0); 282894#L1338-3 assume !(0 == ~E_4~0); 282892#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 282890#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 282888#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 282886#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 282883#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 282881#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 282879#L1373-3 assume !(0 == ~E_11~0); 282877#L1378-3 assume !(0 == ~E_12~0); 277972#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 277969#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 277967#L607-42 assume !(1 == ~m_pc~0); 277965#L607-44 is_master_triggered_~__retres1~0#1 := 0; 277963#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 277961#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 277959#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 277956#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 277954#L626-42 assume !(1 == ~t1_pc~0); 277952#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 277949#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 277947#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 277945#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 277944#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 277941#L645-42 assume !(1 == ~t2_pc~0); 277939#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 277937#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 277935#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 277933#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 277931#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 277928#L664-42 assume 1 == ~t3_pc~0; 277925#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 277923#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 277921#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 277919#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 277917#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 277916#L683-42 assume !(1 == ~t4_pc~0); 277914#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 277911#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 277909#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 277907#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 277905#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 277903#L702-42 assume !(1 == ~t5_pc~0); 277900#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 277897#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 277894#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 277892#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 277890#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 277888#L721-42 assume 1 == ~t6_pc~0; 277885#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 277883#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 277882#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 277879#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 277877#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 277875#L740-42 assume 1 == ~t7_pc~0; 277872#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 277870#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 277868#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 277865#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 277863#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 277861#L759-42 assume 1 == ~t8_pc~0; 277858#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 277856#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 277854#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 277851#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 277849#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 277847#L778-42 assume !(1 == ~t9_pc~0); 277844#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 277842#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 277840#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 277837#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 277835#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 277833#L797-42 assume 1 == ~t10_pc~0; 277830#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 277828#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 277827#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 277826#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 277825#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 277824#L816-42 assume !(1 == ~t11_pc~0); 277821#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 277819#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 277817#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 277815#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 277812#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 277810#L835-42 assume !(1 == ~t12_pc~0); 277808#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 277805#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 277803#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 277801#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 277798#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 277796#L854-42 assume !(1 == ~t13_pc~0); 277793#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 277791#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 277789#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 277785#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 277783#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277773#L1401-3 assume !(1 == ~M_E~0); 277771#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 277769#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 255208#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 277764#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 277762#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 277760#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 277758#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 277755#L1436-3 assume !(1 == ~T8_E~0); 277753#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 277751#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 277749#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 277747#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 277743#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 277741#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 277739#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 277737#L1476-3 assume !(1 == ~E_3~0); 272547#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 277734#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 277732#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 277730#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 277728#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 277727#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 277725#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 276969#L1516-3 assume !(1 == ~E_11~0); 276967#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 276965#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 276963#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 276932#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 276928#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 276926#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 276923#L1911 assume !(0 == start_simulation_~tmp~3#1); 276920#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 276569#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 276555#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 276551#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 276549#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 276547#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 276546#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 276517#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 276505#L1892-2 [2022-11-16 10:57:07,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:07,276 INFO L85 PathProgramCache]: Analyzing trace with hash -1648097194, now seen corresponding path program 1 times [2022-11-16 10:57:07,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:07,276 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782587342] [2022-11-16 10:57:07,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:07,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:07,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:07,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:07,398 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:07,398 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782587342] [2022-11-16 10:57:07,399 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782587342] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:07,399 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:07,399 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:07,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985218285] [2022-11-16 10:57:07,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:07,400 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:57:07,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:07,401 INFO L85 PathProgramCache]: Analyzing trace with hash -1610079324, now seen corresponding path program 1 times [2022-11-16 10:57:07,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:07,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538773426] [2022-11-16 10:57:07,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:07,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:07,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:07,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:07,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:07,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538773426] [2022-11-16 10:57:07,477 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538773426] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:07,477 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:07,477 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:07,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841945419] [2022-11-16 10:57:07,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:07,478 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:57:07,479 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:57:07,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 10:57:07,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 10:57:07,479 INFO L87 Difference]: Start difference. First operand 72678 states and 105684 transitions. cyclomatic complexity: 33022 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:08,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:57:08,788 INFO L93 Difference]: Finished difference Result 210029 states and 303417 transitions. [2022-11-16 10:57:08,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 210029 states and 303417 transitions. [2022-11-16 10:57:09,990 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 206072 [2022-11-16 10:57:11,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 210029 states to 210029 states and 303417 transitions. [2022-11-16 10:57:11,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 210029 [2022-11-16 10:57:11,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 210029 [2022-11-16 10:57:11,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210029 states and 303417 transitions. [2022-11-16 10:57:11,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:57:11,494 INFO L218 hiAutomatonCegarLoop]: Abstraction has 210029 states and 303417 transitions. [2022-11-16 10:57:11,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210029 states and 303417 transitions. [2022-11-16 10:57:13,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210029 to 202813. [2022-11-16 10:57:14,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 202813 states, 202813 states have (on average 1.4468944298442408) internal successors, (293449), 202812 states have internal predecessors, (293449), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:14,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202813 states to 202813 states and 293449 transitions. [2022-11-16 10:57:14,733 INFO L240 hiAutomatonCegarLoop]: Abstraction has 202813 states and 293449 transitions. [2022-11-16 10:57:14,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 10:57:14,735 INFO L428 stractBuchiCegarLoop]: Abstraction has 202813 states and 293449 transitions. [2022-11-16 10:57:14,735 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-16 10:57:14,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 202813 states and 293449 transitions. [2022-11-16 10:57:15,748 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 202328 [2022-11-16 10:57:15,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:57:15,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:57:15,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:15,751 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:15,752 INFO L748 eck$LassoCheckResult]: Stem: 509589#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 509590#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 509395#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 509101#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 509102#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 510443#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 510444#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 509241#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 509242#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 509727#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 509547#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 509548#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 509309#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 509310#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 509738#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 509934#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 510110#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 510150#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 509320#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 509321#L1258 assume !(0 == ~M_E~0); 510753#L1258-2 assume !(0 == ~T1_E~0); 509636#L1263-1 assume !(0 == ~T2_E~0); 509637#L1268-1 assume !(0 == ~T3_E~0); 509971#L1273-1 assume !(0 == ~T4_E~0); 510722#L1278-1 assume !(0 == ~T5_E~0); 510512#L1283-1 assume !(0 == ~T6_E~0); 510513#L1288-1 assume !(0 == ~T7_E~0); 510899#L1293-1 assume !(0 == ~T8_E~0); 510873#L1298-1 assume !(0 == ~T9_E~0); 510743#L1303-1 assume !(0 == ~T10_E~0); 509129#L1308-1 assume !(0 == ~T11_E~0); 509072#L1313-1 assume !(0 == ~T12_E~0); 509073#L1318-1 assume !(0 == ~T13_E~0); 509079#L1323-1 assume !(0 == ~E_1~0); 509080#L1328-1 assume !(0 == ~E_2~0); 509251#L1333-1 assume !(0 == ~E_3~0); 510328#L1338-1 assume !(0 == ~E_4~0); 510329#L1343-1 assume !(0 == ~E_5~0); 510478#L1348-1 assume !(0 == ~E_6~0); 510953#L1353-1 assume !(0 == ~E_7~0); 509993#L1358-1 assume !(0 == ~E_8~0); 509994#L1363-1 assume !(0 == ~E_9~0); 510363#L1368-1 assume !(0 == ~E_10~0); 508908#L1373-1 assume !(0 == ~E_11~0); 508909#L1378-1 assume !(0 == ~E_12~0); 509196#L1383-1 assume !(0 == ~E_13~0); 509197#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 510001#L607 assume !(1 == ~m_pc~0); 509271#L607-2 is_master_triggered_~__retres1~0#1 := 0; 509272#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 510476#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 509911#L1560 assume !(0 != activate_threads_~tmp~1#1); 509912#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 509092#L626 assume !(1 == ~t1_pc~0); 509093#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 509369#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 509370#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 509551#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 508991#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508992#L645 assume !(1 == ~t2_pc~0); 509065#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 509066#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509782#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 509783#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 509886#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 509887#L664 assume !(1 == ~t3_pc~0); 510400#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 508830#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508831#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 509512#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 509513#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 510771#L683 assume !(1 == ~t4_pc~0); 510134#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 510079#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 510080#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 510121#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 510273#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 509829#L702 assume 1 == ~t5_pc~0; 509830#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 509748#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510268#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 510695#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 510596#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508878#L721 assume !(1 == ~t6_pc~0); 508852#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 508853#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 509018#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 509522#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 509523#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 510193#L740 assume 1 == ~t7_pc~0; 508929#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 508741#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 508742#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 508731#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 508732#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509451#L759 assume !(1 == ~t8_pc~0); 509452#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 509484#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 510264#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 510265#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 510457#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 510898#L778 assume 1 == ~t9_pc~0; 510693#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 508905#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 508845#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 508774#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 508775#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 509105#L797 assume !(1 == ~t10_pc~0); 509106#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 509228#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 510538#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 509634#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 509635#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 509953#L816 assume 1 == ~t11_pc~0; 508810#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 508811#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 509593#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 509529#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 509530#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 510109#L835 assume 1 == ~t12_pc~0; 509968#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 508976#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 508998#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 509139#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 509695#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 509696#L854 assume !(1 == ~t13_pc~0); 509311#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 509312#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 509364#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 509016#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 509017#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 510587#L1401 assume !(1 == ~M_E~0); 509516#L1401-2 assume !(1 == ~T1_E~0); 509517#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 510182#L1411-1 assume !(1 == ~T3_E~0); 510183#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 509798#L1421-1 assume !(1 == ~T5_E~0); 509307#L1426-1 assume !(1 == ~T6_E~0); 509308#L1431-1 assume !(1 == ~T7_E~0); 508848#L1436-1 assume !(1 == ~T8_E~0); 508849#L1441-1 assume !(1 == ~T9_E~0); 509625#L1446-1 assume !(1 == ~T10_E~0); 509626#L1451-1 assume !(1 == ~T11_E~0); 510475#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 510019#L1461-1 assume !(1 == ~T13_E~0); 509541#L1466-1 assume !(1 == ~E_1~0); 509542#L1471-1 assume !(1 == ~E_2~0); 510455#L1476-1 assume !(1 == ~E_3~0); 510456#L1481-1 assume !(1 == ~E_4~0); 647021#L1486-1 assume !(1 == ~E_5~0); 647019#L1491-1 assume !(1 == ~E_6~0); 647017#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 647015#L1501-1 assume !(1 == ~E_8~0); 647013#L1506-1 assume !(1 == ~E_9~0); 647011#L1511-1 assume !(1 == ~E_10~0); 647009#L1516-1 assume !(1 == ~E_11~0); 602235#L1521-1 assume !(1 == ~E_12~0); 646948#L1526-1 assume !(1 == ~E_13~0); 646922#L1531-1 assume { :end_inline_reset_delta_events } true; 646910#L1892-2 [2022-11-16 10:57:15,753 INFO L750 eck$LassoCheckResult]: Loop: 646910#L1892-2 assume !false; 646901#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 646896#L1233 assume !false; 646827#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 646791#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 646786#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 646778#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 646772#L1046 assume !(0 != eval_~tmp~0#1); 646773#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 664666#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 664661#L1258-3 assume !(0 == ~M_E~0); 664655#L1258-5 assume !(0 == ~T1_E~0); 664649#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 664642#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 664637#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 664631#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 664626#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 664620#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 664615#L1293-3 assume !(0 == ~T8_E~0); 664606#L1298-3 assume !(0 == ~T9_E~0); 664601#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 664595#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 664590#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 664584#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 664579#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 664570#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 664564#L1333-3 assume !(0 == ~E_3~0); 664559#L1338-3 assume !(0 == ~E_4~0); 664553#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 664546#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 664540#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 664533#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 664527#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 664520#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 664514#L1373-3 assume !(0 == ~E_11~0); 664507#L1378-3 assume !(0 == ~E_12~0); 664501#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 664492#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 664486#L607-42 assume !(1 == ~m_pc~0); 664479#L607-44 is_master_triggered_~__retres1~0#1 := 0; 664473#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 664466#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 664460#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 664451#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 664444#L626-42 assume 1 == ~t1_pc~0; 664435#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 664428#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 664420#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 664413#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 664403#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 664396#L645-42 assume !(1 == ~t2_pc~0); 664387#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 664380#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 664372#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 664364#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 664353#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 664346#L664-42 assume !(1 == ~t3_pc~0); 664339#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 664332#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 664324#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 664314#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 664303#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 664295#L683-42 assume !(1 == ~t4_pc~0); 664287#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 664278#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 664270#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 664265#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 664258#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 664048#L702-42 assume 1 == ~t5_pc~0; 664028#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 664023#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 664016#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 664011#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 648520#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 648505#L721-42 assume !(1 == ~t6_pc~0); 648501#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 648498#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 648495#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 648493#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 648489#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 648487#L740-42 assume !(1 == ~t7_pc~0); 648485#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 648482#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 648480#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 648478#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 648476#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 648474#L759-42 assume !(1 == ~t8_pc~0); 648473#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 648469#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 648467#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 648465#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 648463#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 648461#L778-42 assume 1 == ~t9_pc~0; 648459#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 648455#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 648453#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 648451#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 648449#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 648447#L797-42 assume !(1 == ~t10_pc~0); 648445#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 648441#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 648439#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 648437#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 648435#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 648433#L816-42 assume 1 == ~t11_pc~0; 648431#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 648427#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 648425#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 648423#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 648421#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 648419#L835-42 assume !(1 == ~t12_pc~0); 648417#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 648413#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 648411#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 648409#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 648407#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 648405#L854-42 assume 1 == ~t13_pc~0; 648403#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 648399#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 648397#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 648395#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 648393#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 648386#L1401-3 assume !(1 == ~M_E~0); 648384#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 648382#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 602586#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 648377#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 648375#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 648372#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 648370#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 648364#L1436-3 assume !(1 == ~T8_E~0); 648362#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 648360#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 648358#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 648356#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 648353#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 648268#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 648267#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 648262#L1476-3 assume !(1 == ~E_3~0); 648260#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 648258#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 648256#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 648253#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 648251#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 648224#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 648214#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 648204#L1516-3 assume !(1 == ~E_11~0); 602532#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 648187#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 647711#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 647645#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 647636#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 647629#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 647622#L1911 assume !(0 == start_simulation_~tmp~3#1); 647617#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 647006#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 646991#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 646989#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 646987#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 646985#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 646947#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 646921#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 646910#L1892-2 [2022-11-16 10:57:15,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:15,754 INFO L85 PathProgramCache]: Analyzing trace with hash -1375101771, now seen corresponding path program 1 times [2022-11-16 10:57:15,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:15,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446034728] [2022-11-16 10:57:15,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:15,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:15,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:15,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:15,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:15,839 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446034728] [2022-11-16 10:57:15,839 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446034728] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:15,839 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:15,839 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 10:57:15,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33820442] [2022-11-16 10:57:15,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:15,840 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:57:15,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:15,840 INFO L85 PathProgramCache]: Analyzing trace with hash 859800420, now seen corresponding path program 1 times [2022-11-16 10:57:15,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:15,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079650560] [2022-11-16 10:57:15,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:15,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:15,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:15,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:15,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:15,891 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079650560] [2022-11-16 10:57:15,891 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079650560] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:15,891 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:15,892 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:15,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589280417] [2022-11-16 10:57:15,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:15,892 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:57:15,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:57:15,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 10:57:15,893 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-16 10:57:15,893 INFO L87 Difference]: Start difference. First operand 202813 states and 293449 transitions. cyclomatic complexity: 90668 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:18,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:57:18,362 INFO L93 Difference]: Finished difference Result 547726 states and 795256 transitions. [2022-11-16 10:57:18,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 547726 states and 795256 transitions. [2022-11-16 10:57:21,286 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 546472 [2022-11-16 10:57:23,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 547726 states to 547726 states and 795256 transitions. [2022-11-16 10:57:23,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 547726 [2022-11-16 10:57:23,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 547726 [2022-11-16 10:57:23,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 547726 states and 795256 transitions. [2022-11-16 10:57:23,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:57:23,557 INFO L218 hiAutomatonCegarLoop]: Abstraction has 547726 states and 795256 transitions. [2022-11-16 10:57:23,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547726 states and 795256 transitions. [2022-11-16 10:57:27,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547726 to 207976. [2022-11-16 10:57:27,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207976 states, 207976 states have (on average 1.4358002846482287) internal successors, (298612), 207975 states have internal predecessors, (298612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:27,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207976 states to 207976 states and 298612 transitions. [2022-11-16 10:57:27,674 INFO L240 hiAutomatonCegarLoop]: Abstraction has 207976 states and 298612 transitions. [2022-11-16 10:57:27,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 10:57:27,675 INFO L428 stractBuchiCegarLoop]: Abstraction has 207976 states and 298612 transitions. [2022-11-16 10:57:27,675 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-16 10:57:27,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 207976 states and 298612 transitions. [2022-11-16 10:57:29,016 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 207488 [2022-11-16 10:57:29,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 10:57:29,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 10:57:29,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:29,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 10:57:29,049 INFO L748 eck$LassoCheckResult]: Stem: 1260121#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~T4_E~0 := 2;~t13_pc~0 := 0;~t6_st~0 := 0;~T2_E~0 := 2;~t11_i~0 := 0;~t3_pc~0 := 0;~T13_E~0 := 2;~T11_E~0 := 2;~T8_E~0 := 2;~T6_E~0 := 2;~t7_pc~0 := 0;~m_i~0 := 0;~t13_st~0 := 0;~t6_i~0 := 0;~t3_st~0 := 0;~t8_i~0 := 0;~t2_i~0 := 0;~t4_i~0 := 0;~t7_st~0 := 0;~t10_pc~0 := 0;~t4_pc~0 := 0;~t8_pc~0 := 0;~t10_st~0 := 0;~E_1~0 := 2;~m_pc~0 := 0;~E_3~0 := 2;~E_2~0 := 2;~E_5~0 := 2;~t4_st~0 := 0;~E_4~0 := 2;~E_7~0 := 2;~E_6~0 := 2;~E_9~0 := 2;~E_8~0 := 2;~T5_E~0 := 2;~m_st~0 := 0;~t8_st~0 := 0;~t11_pc~0 := 0;~T3_E~0 := 2;~t10_i~0 := 0;~T1_E~0 := 2;~t12_i~0 := 0;~T9_E~0 := 2;~t5_pc~0 := 0;~T12_E~0 := 2;~T7_E~0 := 2;~t1_pc~0 := 0;~T10_E~0 := 2;~t11_st~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~t9_pc~0 := 0;~t7_i~0 := 0;~t1_st~0 := 0;~t9_i~0 := 0;~t3_i~0 := 0;~t5_i~0 := 0;~t12_pc~0 := 0;~t5_st~0 := 0;~t9_st~0 := 0;~t6_pc~0 := 0;~t2_pc~0 := 0;~t12_st~0 := 0;~t2_st~0 := 0;~t13_i~0 := 0;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1260122#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1259936#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1259650#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1259651#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1260906#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260907#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1259786#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1259787#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1260258#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1260081#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1260082#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1259854#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1259855#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1260265#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1260446#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1260606#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1260649#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1259867#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1259868#L1258 assume !(0 == ~M_E~0); 1261169#L1258-2 assume !(0 == ~T1_E~0); 1260166#L1263-1 assume !(0 == ~T2_E~0); 1260167#L1268-1 assume !(0 == ~T3_E~0); 1260481#L1273-1 assume !(0 == ~T4_E~0); 1261146#L1278-1 assume !(0 == ~T5_E~0); 1260971#L1283-1 assume !(0 == ~T6_E~0); 1260972#L1288-1 assume !(0 == ~T7_E~0); 1261294#L1293-1 assume !(0 == ~T8_E~0); 1261273#L1298-1 assume !(0 == ~T9_E~0); 1261162#L1303-1 assume !(0 == ~T10_E~0); 1259678#L1308-1 assume !(0 == ~T11_E~0); 1259621#L1313-1 assume !(0 == ~T12_E~0); 1259622#L1318-1 assume !(0 == ~T13_E~0); 1259630#L1323-1 assume !(0 == ~E_1~0); 1259631#L1328-1 assume !(0 == ~E_2~0); 1259796#L1333-1 assume !(0 == ~E_3~0); 1260809#L1338-1 assume !(0 == ~E_4~0); 1260810#L1343-1 assume !(0 == ~E_5~0); 1260938#L1348-1 assume !(0 == ~E_6~0); 1261339#L1353-1 assume !(0 == ~E_7~0); 1260500#L1358-1 assume !(0 == ~E_8~0); 1260501#L1363-1 assume !(0 == ~E_9~0); 1260838#L1368-1 assume !(0 == ~E_10~0); 1259457#L1373-1 assume !(0 == ~E_11~0); 1259458#L1378-1 assume !(0 == ~E_12~0); 1259747#L1383-1 assume !(0 == ~E_13~0); 1259748#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1260506#L607 assume !(1 == ~m_pc~0); 1259816#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1259817#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1260936#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1260426#L1560 assume !(0 != activate_threads_~tmp~1#1); 1260427#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1259641#L626 assume !(1 == ~t1_pc~0); 1259642#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1259914#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1259915#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260087#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1259544#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259545#L645 assume !(1 == ~t2_pc~0); 1259614#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1259615#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1260309#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1260310#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1260402#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1260403#L664 assume !(1 == ~t3_pc~0); 1260868#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1259386#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1259387#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1260046#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1260047#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1261185#L683 assume !(1 == ~t4_pc~0); 1260631#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1260580#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1260581#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1261354#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1260762#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1260354#L702 assume 1 == ~t5_pc~0; 1260355#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1260275#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1260757#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1261129#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1261048#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1259429#L721 assume !(1 == ~t6_pc~0); 1259404#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1259405#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1259568#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1260055#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1260056#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1260688#L740 assume 1 == ~t7_pc~0; 1259478#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1259293#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1259294#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1259283#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1259284#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1259990#L759 assume !(1 == ~t8_pc~0); 1259991#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1260019#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1260755#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1260756#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1260920#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1261291#L778 assume 1 == ~t9_pc~0; 1261127#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1259456#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1259397#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1259326#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1259327#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1259655#L797 assume !(1 == ~t10_pc~0); 1259656#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1259773#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1260995#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1260164#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1260165#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1260465#L816 assume 1 == ~t11_pc~0; 1259362#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259363#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1260127#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1260062#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1260063#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1260605#L835 assume 1 == ~t12_pc~0; 1260478#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1259525#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1259548#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1259688#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1260225#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1260226#L854 assume !(1 == ~t13_pc~0); 1259856#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1259857#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1259909#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1259566#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1259567#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1261039#L1401 assume !(1 == ~M_E~0); 1260050#L1401-2 assume !(1 == ~T1_E~0); 1260051#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1261050#L1411-1 assume !(1 == ~T3_E~0); 1261318#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1261319#L1421-1 assume !(1 == ~T5_E~0); 1259852#L1426-1 assume !(1 == ~T6_E~0); 1259853#L1431-1 assume !(1 == ~T7_E~0); 1259400#L1436-1 assume !(1 == ~T8_E~0); 1259401#L1441-1 assume !(1 == ~T9_E~0); 1260157#L1446-1 assume !(1 == ~T10_E~0); 1260158#L1451-1 assume !(1 == ~T11_E~0); 1260934#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1260935#L1461-1 assume !(1 == ~T13_E~0); 1260075#L1466-1 assume !(1 == ~E_1~0); 1260076#L1471-1 assume !(1 == ~E_2~0); 1260918#L1476-1 assume !(1 == ~E_3~0); 1260919#L1481-1 assume !(1 == ~E_4~0); 1407310#L1486-1 assume !(1 == ~E_5~0); 1407295#L1491-1 assume !(1 == ~E_6~0); 1407293#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1407291#L1501-1 assume !(1 == ~E_8~0); 1407289#L1506-1 assume !(1 == ~E_9~0); 1407287#L1511-1 assume !(1 == ~E_10~0); 1407285#L1516-1 assume !(1 == ~E_11~0); 1336114#L1521-1 assume !(1 == ~E_12~0); 1407284#L1526-1 assume !(1 == ~E_13~0); 1407282#L1531-1 assume { :end_inline_reset_delta_events } true; 1407279#L1892-2 [2022-11-16 10:57:29,049 INFO L750 eck$LassoCheckResult]: Loop: 1407279#L1892-2 assume !false; 1403839#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1398477#L1233 assume !false; 1398474#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1396493#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1396484#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1396474#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1396466#L1046 assume !(0 != eval_~tmp~0#1); 1396467#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1407902#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1407900#L1258-3 assume !(0 == ~M_E~0); 1407898#L1258-5 assume !(0 == ~T1_E~0); 1407896#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1407894#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1407891#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1407889#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1407887#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1407885#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1407883#L1293-3 assume !(0 == ~T8_E~0); 1407882#L1298-3 assume !(0 == ~T9_E~0); 1407878#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1407876#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1407874#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1407873#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1407872#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1407868#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1407863#L1333-3 assume !(0 == ~E_3~0); 1407858#L1338-3 assume !(0 == ~E_4~0); 1407853#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1407852#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1407851#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1407850#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1407849#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1407848#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1407847#L1373-3 assume !(0 == ~E_11~0); 1407846#L1378-3 assume !(0 == ~E_12~0); 1407845#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1407844#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1407843#L607-42 assume !(1 == ~m_pc~0); 1407842#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1407841#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1407840#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1407839#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1407838#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1407837#L626-42 assume !(1 == ~t1_pc~0); 1407836#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1407834#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1407833#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1407832#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1407831#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1407830#L645-42 assume !(1 == ~t2_pc~0); 1407829#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1407828#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1407827#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1407826#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1407825#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1407824#L664-42 assume !(1 == ~t3_pc~0); 1407823#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1407822#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1407821#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1407820#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1407819#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1407818#L683-42 assume !(1 == ~t4_pc~0); 1407817#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1407815#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1407813#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1407811#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 1407808#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1407806#L702-42 assume !(1 == ~t5_pc~0); 1407804#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1407801#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1407798#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1407796#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 1407794#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1407792#L721-42 assume 1 == ~t6_pc~0; 1407789#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1407787#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1407784#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1407782#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1407780#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1407778#L740-42 assume !(1 == ~t7_pc~0); 1407776#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1407773#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1407770#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1407768#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1407766#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1407764#L759-42 assume 1 == ~t8_pc~0; 1407761#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1407760#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1407756#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1407754#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1407752#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1407751#L778-42 assume !(1 == ~t9_pc~0); 1407745#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1407740#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1407735#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1407730#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1407725#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1407719#L797-42 assume !(1 == ~t10_pc~0); 1407717#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1407714#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1407713#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1407712#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1407711#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1407710#L816-42 assume 1 == ~t11_pc~0; 1407709#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1407707#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1407706#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1407705#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1407704#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1407703#L835-42 assume 1 == ~t12_pc~0; 1407701#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1407700#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1407699#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1407698#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1407697#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1407682#L854-42 assume 1 == ~t13_pc~0; 1407680#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1407677#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1407674#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1407672#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1407670#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1407668#L1401-3 assume !(1 == ~M_E~0); 1403675#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1407665#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1372340#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1407660#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1407658#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1407656#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1407654#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1407455#L1436-3 assume !(1 == ~T8_E~0); 1407451#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1407449#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1407447#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1407445#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1407443#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1407441#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1407439#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1407435#L1476-3 assume !(1 == ~E_3~0); 1407434#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1407433#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1407432#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1407431#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1407430#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1407429#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1407428#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1407427#L1516-3 assume !(1 == ~E_11~0); 1389161#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1407426#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1407425#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1407319#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1407316#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1407314#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1407313#L1911 assume !(0 == start_simulation_~tmp~3#1); 1407311#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1407309#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1407294#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1407292#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1407290#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1407288#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1407286#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1407281#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1407279#L1892-2 [2022-11-16 10:57:29,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:29,062 INFO L85 PathProgramCache]: Analyzing trace with hash 1040734579, now seen corresponding path program 1 times [2022-11-16 10:57:29,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:29,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052259420] [2022-11-16 10:57:29,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:29,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:29,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:29,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:29,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:29,254 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052259420] [2022-11-16 10:57:29,254 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052259420] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:29,254 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:29,254 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 10:57:29,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833821315] [2022-11-16 10:57:29,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:29,256 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-16 10:57:29,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 10:57:29,256 INFO L85 PathProgramCache]: Analyzing trace with hash -474177694, now seen corresponding path program 1 times [2022-11-16 10:57:29,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 10:57:29,257 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815544020] [2022-11-16 10:57:29,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 10:57:29,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 10:57:29,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 10:57:29,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 10:57:29,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 10:57:29,314 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815544020] [2022-11-16 10:57:29,315 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815544020] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 10:57:29,315 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 10:57:29,315 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 10:57:29,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594158690] [2022-11-16 10:57:29,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 10:57:29,316 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 10:57:29,316 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 10:57:29,316 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 10:57:29,317 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 10:57:29,317 INFO L87 Difference]: Start difference. First operand 207976 states and 298612 transitions. cyclomatic complexity: 90668 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 10:57:31,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 10:57:31,494 INFO L93 Difference]: Finished difference Result 399423 states and 571771 transitions. [2022-11-16 10:57:31,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 399423 states and 571771 transitions. [2022-11-16 10:57:33,673 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 398408 [2022-11-16 10:57:34,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 399423 states to 399423 states and 571771 transitions. [2022-11-16 10:57:34,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 399423 [2022-11-16 10:57:34,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 399423 [2022-11-16 10:57:34,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 399423 states and 571771 transitions. [2022-11-16 10:57:35,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 10:57:35,014 INFO L218 hiAutomatonCegarLoop]: Abstraction has 399423 states and 571771 transitions. [2022-11-16 10:57:35,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399423 states and 571771 transitions.