./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 22b4144b7005899e18ff8135fa52f12863f7106dbe1ddb808d25d8593c5f8fc4 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 12:04:26,738 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 12:04:26,742 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 12:04:26,764 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 12:04:26,764 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 12:04:26,765 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 12:04:26,767 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 12:04:26,769 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 12:04:26,770 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 12:04:26,771 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 12:04:26,772 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 12:04:26,773 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 12:04:26,774 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 12:04:26,775 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 12:04:26,776 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 12:04:26,777 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 12:04:26,778 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 12:04:26,787 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 12:04:26,789 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 12:04:26,794 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 12:04:26,801 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 12:04:26,803 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 12:04:26,804 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 12:04:26,805 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 12:04:26,808 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 12:04:26,808 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 12:04:26,809 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 12:04:26,810 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 12:04:26,810 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 12:04:26,811 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 12:04:26,812 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 12:04:26,812 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 12:04:26,813 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 12:04:26,814 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 12:04:26,815 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 12:04:26,815 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 12:04:26,816 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 12:04:26,816 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 12:04:26,817 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 12:04:26,817 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 12:04:26,818 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 12:04:26,821 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 12:04:26,853 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 12:04:26,854 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 12:04:26,854 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 12:04:26,854 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 12:04:26,855 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 12:04:26,855 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 12:04:26,856 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 12:04:26,856 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 12:04:26,856 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 12:04:26,856 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 12:04:26,856 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 12:04:26,857 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 12:04:26,857 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 12:04:26,857 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 12:04:26,857 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 12:04:26,857 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 12:04:26,858 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 12:04:26,858 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 12:04:26,858 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 12:04:26,858 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 12:04:26,858 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 12:04:26,864 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 12:04:26,864 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 12:04:26,864 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 12:04:26,865 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 12:04:26,865 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 12:04:26,865 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 12:04:26,865 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 12:04:26,866 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 12:04:26,866 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 12:04:26,867 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 12:04:26,868 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 12:04:26,868 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 22b4144b7005899e18ff8135fa52f12863f7106dbe1ddb808d25d8593c5f8fc4 [2022-11-16 12:04:27,165 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 12:04:27,190 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 12:04:27,193 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 12:04:27,194 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 12:04:27,195 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 12:04:27,196 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i [2022-11-16 12:04:27,262 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/data/f5273df93/896af5aa24dc47fcbce8ebed1b43303e/FLAGbfc0eca14 [2022-11-16 12:04:27,950 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 12:04:27,955 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i [2022-11-16 12:04:27,989 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/data/f5273df93/896af5aa24dc47fcbce8ebed1b43303e/FLAGbfc0eca14 [2022-11-16 12:04:28,270 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/data/f5273df93/896af5aa24dc47fcbce8ebed1b43303e [2022-11-16 12:04:28,272 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 12:04:28,273 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 12:04:28,279 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 12:04:28,279 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 12:04:28,283 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 12:04:28,284 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:04:28" (1/1) ... [2022-11-16 12:04:28,285 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2c426a0b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:28, skipping insertion in model container [2022-11-16 12:04:28,285 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:04:28" (1/1) ... [2022-11-16 12:04:28,292 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 12:04:28,339 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 12:04:28,821 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i[33021,33034] [2022-11-16 12:04:28,948 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i[44124,44137] [2022-11-16 12:04:28,949 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i[44245,44258] [2022-11-16 12:04:28,955 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:04:28,964 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 12:04:28,989 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i[33021,33034] [2022-11-16 12:04:29,035 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i[44124,44137] [2022-11-16 12:04:29,036 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/sv-benchmarks/c/uthash-2.0.2/uthash_JEN_test7-1.i[44245,44258] [2022-11-16 12:04:29,039 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:04:29,071 INFO L208 MainTranslator]: Completed translation [2022-11-16 12:04:29,071 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29 WrapperNode [2022-11-16 12:04:29,071 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 12:04:29,072 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 12:04:29,072 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 12:04:29,073 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 12:04:29,080 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,105 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,153 INFO L138 Inliner]: procedures = 176, calls = 277, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 992 [2022-11-16 12:04:29,154 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 12:04:29,154 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 12:04:29,154 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 12:04:29,155 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 12:04:29,164 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,164 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,173 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,187 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,254 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,264 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,267 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,279 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,286 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 12:04:29,302 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 12:04:29,302 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 12:04:29,302 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 12:04:29,303 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (1/1) ... [2022-11-16 12:04:29,310 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 12:04:29,324 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:04:29,341 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 12:04:29,358 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 12:04:29,386 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-16 12:04:29,386 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-16 12:04:29,391 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-11-16 12:04:29,391 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-11-16 12:04:29,391 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-11-16 12:04:29,391 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 12:04:29,391 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-11-16 12:04:29,391 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-16 12:04:29,392 INFO L130 BoogieDeclarations]: Found specification of procedure memcmp [2022-11-16 12:04:29,392 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-11-16 12:04:29,392 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-16 12:04:29,392 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 12:04:29,392 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 12:04:29,392 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 12:04:29,652 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 12:04:29,654 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 12:04:29,660 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-11-16 12:04:31,398 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 12:04:31,410 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 12:04:31,410 INFO L300 CfgBuilder]: Removed 63 assume(true) statements. [2022-11-16 12:04:31,413 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:04:31 BoogieIcfgContainer [2022-11-16 12:04:31,413 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 12:04:31,415 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 12:04:31,415 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 12:04:31,420 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 12:04:31,420 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:04:31,421 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 12:04:28" (1/3) ... [2022-11-16 12:04:31,423 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1adbf955 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:04:31, skipping insertion in model container [2022-11-16 12:04:31,423 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:04:31,423 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:04:29" (2/3) ... [2022-11-16 12:04:31,424 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1adbf955 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:04:31, skipping insertion in model container [2022-11-16 12:04:31,424 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:04:31,424 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:04:31" (3/3) ... [2022-11-16 12:04:31,427 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_JEN_test7-1.i [2022-11-16 12:04:31,486 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 12:04:31,486 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 12:04:31,486 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 12:04:31,486 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 12:04:31,486 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 12:04:31,487 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 12:04:31,487 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 12:04:31,487 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 12:04:31,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 181 states, 176 states have (on average 1.6931818181818181) internal successors, (298), 176 states have internal predecessors, (298), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:04:31,523 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 169 [2022-11-16 12:04:31,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:04:31,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:04:31,530 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:04:31,531 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2022-11-16 12:04:31,531 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 12:04:31,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 181 states, 176 states have (on average 1.6931818181818181) internal successors, (298), 176 states have internal predecessors, (298), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:04:31,539 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 169 [2022-11-16 12:04:31,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:04:31,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:04:31,540 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:04:31,540 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2022-11-16 12:04:31,547 INFO L748 eck$LassoCheckResult]: Stem: 165#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 59#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~pre106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~post111#1, main_#t~mem115#1, main_#t~mem113#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem114#1, main_#t~mem116#1, main_#t~post117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~post94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~ite137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem145#1, main_#t~mem144#1, main_#t~mem146#1, main_#t~mem147#1, main_#t~mem149#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem151#1, main_#t~mem153#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem155#1, main_#t~switch156#1, main_#t~mem157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1, main_#t~mem179#1, main_#t~short180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~ret182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~short189#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem212#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1, main_#t~post216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1, main_#t~post227#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 138#L715-4true [2022-11-16 12:04:31,548 INFO L750 eck$LassoCheckResult]: Loop: 138#L715-4true call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 116#L715-1true assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 33#L717true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 141#L717-2true call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 151#L722-121true assume !true; 75#L715-3true call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 138#L715-4true [2022-11-16 12:04:31,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:04:31,554 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-11-16 12:04:31,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:04:31,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080920959] [2022-11-16 12:04:31,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:31,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:04:31,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:04:31,687 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:04:31,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:04:31,764 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:04:31,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:04:31,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1336134348, now seen corresponding path program 1 times [2022-11-16 12:04:31,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:04:31,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606399670] [2022-11-16 12:04:31,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:31,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:04:31,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:04:31,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:04:31,841 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606399670] [2022-11-16 12:04:31,842 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-11-16 12:04:31,843 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [762797785] [2022-11-16 12:04:31,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:31,855 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:04:31,855 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:04:31,863 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:04:31,893 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-16 12:04:32,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:04:32,008 INFO L263 TraceCheckSpWp]: Trace formula consists of 74 conjuncts, 1 conjunts are in the unsatisfiable core [2022-11-16 12:04:32,010 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:04:32,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:04:32,028 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:04:32,029 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [762797785] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:04:32,029 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:04:32,029 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:04:32,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017308320] [2022-11-16 12:04:32,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:04:32,034 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:04:32,035 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:04:32,066 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-16 12:04:32,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 12:04:32,069 INFO L87 Difference]: Start difference. First operand has 181 states, 176 states have (on average 1.6931818181818181) internal successors, (298), 176 states have internal predecessors, (298), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.0) internal successors, (6), 2 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:04:32,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:04:32,089 INFO L93 Difference]: Finished difference Result 180 states and 234 transitions. [2022-11-16 12:04:32,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 180 states and 234 transitions. [2022-11-16 12:04:32,094 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 167 [2022-11-16 12:04:32,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 180 states to 174 states and 228 transitions. [2022-11-16 12:04:32,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 174 [2022-11-16 12:04:32,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 174 [2022-11-16 12:04:32,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 174 states and 228 transitions. [2022-11-16 12:04:32,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:04:32,105 INFO L218 hiAutomatonCegarLoop]: Abstraction has 174 states and 228 transitions. [2022-11-16 12:04:32,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states and 228 transitions. [2022-11-16 12:04:32,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2022-11-16 12:04:32,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 174 states, 170 states have (on average 1.3058823529411765) internal successors, (222), 169 states have internal predecessors, (222), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:04:32,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 228 transitions. [2022-11-16 12:04:32,141 INFO L240 hiAutomatonCegarLoop]: Abstraction has 174 states and 228 transitions. [2022-11-16 12:04:32,142 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-16 12:04:32,145 INFO L428 stractBuchiCegarLoop]: Abstraction has 174 states and 228 transitions. [2022-11-16 12:04:32,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 12:04:32,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 174 states and 228 transitions. [2022-11-16 12:04:32,147 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 167 [2022-11-16 12:04:32,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:04:32,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:04:32,148 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:04:32,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:04:32,149 INFO L748 eck$LassoCheckResult]: Stem: 557#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 484#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~pre106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~post111#1, main_#t~mem115#1, main_#t~mem113#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem114#1, main_#t~mem116#1, main_#t~post117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~post94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~ite137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem145#1, main_#t~mem144#1, main_#t~mem146#1, main_#t~mem147#1, main_#t~mem149#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem151#1, main_#t~mem153#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem155#1, main_#t~switch156#1, main_#t~mem157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1, main_#t~mem179#1, main_#t~short180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~ret182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~short189#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem212#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1, main_#t~post216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1, main_#t~post227#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 485#L715-4 [2022-11-16 12:04:32,150 INFO L750 eck$LassoCheckResult]: Loop: 485#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 538#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 449#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 450#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 551#L722-121 havoc main_~_ha_hashv~0#1; 550#L722-49 goto; 482#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 431#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 432#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 493#L722-10 assume main_#t~switch22#1;call main_#t~mem23#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem23#1 % 256);havoc main_#t~mem23#1; 510#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 466#L722-13 assume main_#t~switch22#1;call main_#t~mem24#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem24#1 % 256);havoc main_#t~mem24#1; 467#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 501#L722-16 assume main_#t~switch22#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 531#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 425#L722-19 assume main_#t~switch22#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem26#1 % 256);havoc main_#t~mem26#1; 426#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 537#L722-22 assume !main_#t~switch22#1; 532#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 533#L722-25 assume main_#t~switch22#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 458#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 459#L722-28 assume main_#t~switch22#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem29#1 % 256;havoc main_#t~mem29#1; 544#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 545#L722-31 assume main_#t~switch22#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem30#1 % 256);havoc main_#t~mem30#1; 488#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 427#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 428#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 525#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 387#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 388#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 514#L722-42 havoc main_#t~switch22#1; 515#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 542#L722-44 goto; 408#L722-46 goto; 409#L722-48 goto; 497#L722-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 498#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 529#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 530#L722-66 goto; 476#L722-117 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 477#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem63#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem63#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1)));havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 483#L722-70 goto; 548#L722-115 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 412#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 413#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 505#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 384#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 385#L722-114 goto; 474#L722-116 goto; 547#L722-118 goto; 543#L722-120 goto; 504#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 485#L715-4 [2022-11-16 12:04:32,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:04:32,151 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-11-16 12:04:32,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:04:32,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026947113] [2022-11-16 12:04:32,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:32,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:04:32,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:04:32,167 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:04:32,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:04:32,188 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:04:32,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:04:32,191 INFO L85 PathProgramCache]: Analyzing trace with hash -1777661299, now seen corresponding path program 1 times [2022-11-16 12:04:32,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:04:32,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842130565] [2022-11-16 12:04:32,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:32,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:04:32,367 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:04:32,368 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1306898796] [2022-11-16 12:04:32,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:32,369 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:04:32,370 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:04:32,375 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:04:32,395 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-16 12:04:33,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:04:33,171 INFO L263 TraceCheckSpWp]: Trace formula consists of 1850 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 12:04:33,174 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:04:33,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:04:33,222 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:04:33,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:04:33,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842130565] [2022-11-16 12:04:33,223 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 12:04:33,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1306898796] [2022-11-16 12:04:33,223 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1306898796] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:04:33,223 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:04:33,224 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:04:33,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430763671] [2022-11-16 12:04:33,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:04:33,224 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:04:33,225 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:04:33,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:04:33,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:04:33,226 INFO L87 Difference]: Start difference. First operand 174 states and 228 transitions. cyclomatic complexity: 57 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:04:33,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:04:33,345 INFO L93 Difference]: Finished difference Result 195 states and 249 transitions. [2022-11-16 12:04:33,345 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 249 transitions. [2022-11-16 12:04:33,347 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 188 [2022-11-16 12:04:33,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 249 transitions. [2022-11-16 12:04:33,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2022-11-16 12:04:33,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2022-11-16 12:04:33,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 249 transitions. [2022-11-16 12:04:33,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:04:33,351 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 249 transitions. [2022-11-16 12:04:33,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 249 transitions. [2022-11-16 12:04:33,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 194. [2022-11-16 12:04:33,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 194 states, 190 states have (on average 1.2736842105263158) internal successors, (242), 189 states have internal predecessors, (242), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:04:33,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 248 transitions. [2022-11-16 12:04:33,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 194 states and 248 transitions. [2022-11-16 12:04:33,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:04:33,364 INFO L428 stractBuchiCegarLoop]: Abstraction has 194 states and 248 transitions. [2022-11-16 12:04:33,365 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 12:04:33,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 194 states and 248 transitions. [2022-11-16 12:04:33,366 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 187 [2022-11-16 12:04:33,366 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:04:33,366 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:04:33,367 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:04:33,367 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:04:33,368 INFO L748 eck$LassoCheckResult]: Stem: 1088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 1012#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~pre106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~post111#1, main_#t~mem115#1, main_#t~mem113#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem114#1, main_#t~mem116#1, main_#t~post117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~post94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~ite137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem145#1, main_#t~mem144#1, main_#t~mem146#1, main_#t~mem147#1, main_#t~mem149#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem151#1, main_#t~mem153#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem155#1, main_#t~switch156#1, main_#t~mem157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1, main_#t~mem179#1, main_#t~short180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~ret182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~short189#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem212#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1, main_#t~post216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1, main_#t~post227#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1013#L715-4 [2022-11-16 12:04:33,368 INFO L750 eck$LassoCheckResult]: Loop: 1013#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1069#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 977#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 978#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 1082#L722-121 havoc main_~_ha_hashv~0#1; 1081#L722-49 goto; 1008#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 955#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 956#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 1019#L722-10 assume !main_#t~switch22#1; 1068#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 1091#L722-13 assume !main_#t~switch22#1; 1092#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 1105#L722-16 assume !main_#t~switch22#1; 1104#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 1103#L722-19 assume main_#t~switch22#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem26#1 % 256);havoc main_#t~mem26#1; 947#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 1066#L722-22 assume main_#t~switch22#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 1062#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 1063#L722-25 assume main_#t~switch22#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 988#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 989#L722-28 assume main_#t~switch22#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem29#1 % 256;havoc main_#t~mem29#1; 1090#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 1089#L722-31 assume main_#t~switch22#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem30#1 % 256);havoc main_#t~mem30#1; 1016#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 958#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 959#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 1054#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 1055#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 1060#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 1044#L722-42 havoc main_#t~switch22#1; 1045#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1073#L722-44 goto; 936#L722-46 goto; 937#L722-48 goto; 1025#L722-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1026#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 1058#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 1059#L722-66 goto; 1006#L722-117 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 1007#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem63#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem63#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1)));havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 1011#L722-70 goto; 1079#L722-115 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 940#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 941#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 1033#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 912#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 913#L722-114 goto; 1003#L722-116 goto; 1078#L722-118 goto; 1074#L722-120 goto; 1032#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 1013#L715-4 [2022-11-16 12:04:33,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:04:33,369 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-11-16 12:04:33,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:04:33,369 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661725036] [2022-11-16 12:04:33,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:33,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:04:33,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:04:33,411 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:04:33,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:04:33,433 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:04:33,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:04:33,434 INFO L85 PathProgramCache]: Analyzing trace with hash 1042197777, now seen corresponding path program 1 times [2022-11-16 12:04:33,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:04:33,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903792501] [2022-11-16 12:04:33,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:33,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:04:33,592 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:04:33,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [796650587] [2022-11-16 12:04:33,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:33,593 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:04:33,593 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:04:33,621 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:04:33,627 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-16 12:04:34,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:04:34,500 INFO L263 TraceCheckSpWp]: Trace formula consists of 1838 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-16 12:04:34,503 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:04:34,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:04:34,549 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:04:34,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:04:34,550 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903792501] [2022-11-16 12:04:34,550 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 12:04:34,550 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [796650587] [2022-11-16 12:04:34,550 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [796650587] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:04:34,550 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:04:34,550 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 12:04:34,551 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937819672] [2022-11-16 12:04:34,551 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:04:34,551 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:04:34,551 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:04:34,552 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 12:04:34,552 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-16 12:04:34,552 INFO L87 Difference]: Start difference. First operand 194 states and 248 transitions. cyclomatic complexity: 57 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:04:34,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:04:34,689 INFO L93 Difference]: Finished difference Result 269 states and 344 transitions. [2022-11-16 12:04:34,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 269 states and 344 transitions. [2022-11-16 12:04:34,691 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 254 [2022-11-16 12:04:34,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 269 states to 269 states and 344 transitions. [2022-11-16 12:04:34,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 269 [2022-11-16 12:04:34,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 269 [2022-11-16 12:04:34,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 269 states and 344 transitions. [2022-11-16 12:04:34,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:04:34,695 INFO L218 hiAutomatonCegarLoop]: Abstraction has 269 states and 344 transitions. [2022-11-16 12:04:34,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states and 344 transitions. [2022-11-16 12:04:34,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 180. [2022-11-16 12:04:34,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 180 states, 176 states have (on average 1.2556818181818181) internal successors, (221), 175 states have internal predecessors, (221), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:04:34,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 227 transitions. [2022-11-16 12:04:34,704 INFO L240 hiAutomatonCegarLoop]: Abstraction has 180 states and 227 transitions. [2022-11-16 12:04:34,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:04:34,705 INFO L428 stractBuchiCegarLoop]: Abstraction has 180 states and 227 transitions. [2022-11-16 12:04:34,705 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 12:04:34,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 180 states and 227 transitions. [2022-11-16 12:04:34,706 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 173 [2022-11-16 12:04:34,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:04:34,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:04:34,707 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:04:34,708 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:04:34,708 INFO L748 eck$LassoCheckResult]: Stem: 1709#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2); 1636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~switch22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc34#1.base, main_#t~malloc34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~memset~res37#1.base, main_#t~memset~res37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~mem40#1.base, main_#t~mem40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~malloc43#1.base, main_#t~malloc43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~mem47#1.base, main_#t~mem47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~memset~res50#1.base, main_#t~memset~res50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~post61#1, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1, main_#t~post67#1, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem72#1, main_#t~mem71#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~short75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~malloc78#1.base, main_#t~malloc78#1.offset, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~memset~res83#1.base, main_#t~memset~res83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem88#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem92#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~pre106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~post111#1, main_#t~mem115#1, main_#t~mem113#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem114#1, main_#t~mem116#1, main_#t~post117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~post94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~ite137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem3#1, main_#t~post4#1, main_#t~mem5#1, main_#t~mem145#1, main_#t~mem144#1, main_#t~mem146#1, main_#t~mem147#1, main_#t~mem149#1, main_#t~mem148#1, main_#t~mem150#1, main_#t~mem151#1, main_#t~mem153#1, main_#t~mem152#1, main_#t~mem154#1, main_#t~mem155#1, main_#t~switch156#1, main_#t~mem157#1, main_#t~mem158#1, main_#t~mem159#1, main_#t~mem160#1, main_#t~mem161#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem166#1, main_#t~mem167#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1, main_#t~mem179#1, main_#t~short180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~ret182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1.base, main_#t~mem185#1.offset, main_#t~mem186#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~short189#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1.base, main_#t~mem191#1.offset, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1.base, main_#t~mem201#1.offset, main_#t~mem202#1, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem212#1, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1, main_#t~post216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1, main_#t~post227#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1637#L715-4 [2022-11-16 12:04:34,708 INFO L750 eck$LassoCheckResult]: Loop: 1637#L715-4 call main_#t~mem5#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1690#L715-1 assume !!(main_#t~mem5#1 < 1000);havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 1601#L717 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1602#L717-2 call main_#t~mem7#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1; 1703#L722-121 havoc main_~_ha_hashv~0#1; 1702#L722-49 goto; 1632#L722-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1579#L722-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1580#L722-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch22#1 := 11 == main_~_hj_k~0#1; 1643#L722-10 assume !main_#t~switch22#1; 1662#L722-12 main_#t~switch22#1 := main_#t~switch22#1 || 10 == main_~_hj_k~0#1; 1610#L722-13 assume !main_#t~switch22#1; 1611#L722-15 main_#t~switch22#1 := main_#t~switch22#1 || 9 == main_~_hj_k~0#1; 1653#L722-16 assume !main_#t~switch22#1; 1683#L722-18 main_#t~switch22#1 := main_#t~switch22#1 || 8 == main_~_hj_k~0#1; 1570#L722-19 assume !main_#t~switch22#1; 1571#L722-21 main_#t~switch22#1 := main_#t~switch22#1 || 7 == main_~_hj_k~0#1; 1688#L722-22 assume !main_#t~switch22#1; 1684#L722-24 main_#t~switch22#1 := main_#t~switch22#1 || 6 == main_~_hj_k~0#1; 1685#L722-25 assume !main_#t~switch22#1; 1612#L722-27 main_#t~switch22#1 := main_#t~switch22#1 || 5 == main_~_hj_k~0#1; 1613#L722-28 assume !main_#t~switch22#1; 1696#L722-30 main_#t~switch22#1 := main_#t~switch22#1 || 4 == main_~_hj_k~0#1; 1697#L722-31 assume main_#t~switch22#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem30#1 % 256);havoc main_#t~mem30#1; 1640#L722-33 main_#t~switch22#1 := main_#t~switch22#1 || 3 == main_~_hj_k~0#1; 1582#L722-34 assume main_#t~switch22#1;call main_#t~mem31#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem31#1 % 256);havoc main_#t~mem31#1; 1583#L722-36 main_#t~switch22#1 := main_#t~switch22#1 || 2 == main_~_hj_k~0#1; 1678#L722-37 assume main_#t~switch22#1;call main_#t~mem32#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem32#1 % 256);havoc main_#t~mem32#1; 1539#L722-39 main_#t~switch22#1 := main_#t~switch22#1 || 1 == main_~_hj_k~0#1; 1540#L722-40 assume main_#t~switch22#1;call main_#t~mem33#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem33#1 % 256;havoc main_#t~mem33#1; 1668#L722-42 havoc main_#t~switch22#1; 1669#L722-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1694#L722-44 goto; 1560#L722-46 goto; 1561#L722-48 goto; 1649#L722-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1650#L722-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem51#1.base, main_#t~mem51#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem51#1.base, main_#t~mem51#1.offset; 1681#L722-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem52#1.base, main_#t~mem52#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_#t~mem52#1.base, 16 + main_#t~mem52#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem55#1 := read~int(main_#t~mem54#1.base, 20 + main_#t~mem54#1.offset, 4);call write~$Pointer$(main_#t~mem53#1.base, main_#t~mem53#1.offset - main_#t~mem55#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem52#1.base, main_#t~mem52#1.offset;havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;havoc main_#t~mem55#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1.base, main_#t~mem57#1.offset := read~$Pointer$(main_#t~mem56#1.base, 16 + main_#t~mem56#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem57#1.base, 8 + main_#t~mem57#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1.base, main_#t~mem57#1.offset;call main_#t~mem58#1.base, main_#t~mem58#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem58#1.base, 16 + main_#t~mem58#1.offset, 4);havoc main_#t~mem58#1.base, main_#t~mem58#1.offset; 1682#L722-66 goto; 1630#L722-117 havoc main_~_ha_bkt~0#1;call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);main_#t~post61#1 := main_#t~mem60#1;call write~int(1 + main_#t~post61#1, main_#t~mem59#1.base, 12 + main_#t~mem59#1.offset, 4);havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1;havoc main_#t~post61#1; 1631#L722-71 call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem63#1 := read~int(main_#t~mem62#1.base, 4 + main_#t~mem62#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem63#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem63#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem63#1 - 1)));havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;havoc main_#t~mem63#1; 1635#L722-70 goto; 1700#L722-115 call main_#t~mem64#1.base, main_#t~mem64#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_#t~mem64#1.base, main_#t~mem64#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem65#1.base, main_#t~mem65#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem64#1.base, main_#t~mem64#1.offset;havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call main_#t~mem66#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post67#1 := main_#t~mem66#1;call write~int(1 + main_#t~post67#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem66#1;havoc main_#t~post67#1;call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem68#1.base, main_#t~mem68#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1564#L722-73 assume main_#t~mem69#1.base != 0 || main_#t~mem69#1.offset != 0;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem70#1.base, 12 + main_#t~mem70#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset; 1565#L722-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem72#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short75#1 := main_#t~mem72#1 % 4294967296 >= 10 * (1 + main_#t~mem71#1) % 4294967296; 1657#L722-76 assume main_#t~short75#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem74#1 := read~int(main_#t~mem73#1.base, 36 + main_#t~mem73#1.offset, 4);main_#t~short75#1 := 0 == main_#t~mem74#1 % 4294967296; 1536#L722-78 assume !main_#t~short75#1;havoc main_#t~mem72#1;havoc main_#t~mem71#1;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~short75#1; 1537#L722-114 goto; 1627#L722-116 goto; 1699#L722-118 goto; 1695#L722-120 goto; 1656#L715-3 call main_#t~mem3#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post4#1 := main_#t~mem3#1;call write~int(1 + main_#t~post4#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem3#1;havoc main_#t~post4#1; 1637#L715-4 [2022-11-16 12:04:34,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:04:34,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-11-16 12:04:34,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:04:34,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800687124] [2022-11-16 12:04:34,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:34,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:04:34,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:04:34,726 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:04:34,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:04:34,742 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:04:34,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:04:34,743 INFO L85 PathProgramCache]: Analyzing trace with hash 1486937113, now seen corresponding path program 1 times [2022-11-16 12:04:34,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:04:34,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941714810] [2022-11-16 12:04:34,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:34,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:04:34,867 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:04:34,868 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [525196471] [2022-11-16 12:04:34,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:04:34,868 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:04:34,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:04:34,875 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:04:34,896 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3c77efa0-c63f-49e9-8df2-41ad0f0f5210/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process