./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a74358cfc3b57ddf641c2843362a5594690e287c76148ee1838c9104dbe09de1 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 12:45:25,275 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 12:45:25,278 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 12:45:25,315 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 12:45:25,318 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 12:45:25,323 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 12:45:25,325 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 12:45:25,334 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 12:45:25,336 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 12:45:25,338 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 12:45:25,340 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 12:45:25,343 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 12:45:25,344 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 12:45:25,349 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 12:45:25,352 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 12:45:25,353 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 12:45:25,356 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 12:45:25,358 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 12:45:25,360 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 12:45:25,363 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 12:45:25,367 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 12:45:25,368 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 12:45:25,372 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 12:45:25,373 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 12:45:25,379 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 12:45:25,379 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 12:45:25,380 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 12:45:25,382 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 12:45:25,384 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 12:45:25,385 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 12:45:25,385 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 12:45:25,386 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 12:45:25,389 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 12:45:25,390 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 12:45:25,394 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 12:45:25,394 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 12:45:25,395 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 12:45:25,395 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 12:45:25,396 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 12:45:25,397 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 12:45:25,398 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 12:45:25,399 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 12:45:25,441 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 12:45:25,441 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 12:45:25,442 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 12:45:25,442 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 12:45:25,443 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 12:45:25,444 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 12:45:25,444 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 12:45:25,444 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 12:45:25,444 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 12:45:25,445 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 12:45:25,445 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 12:45:25,445 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 12:45:25,445 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 12:45:25,446 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 12:45:25,446 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 12:45:25,446 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 12:45:25,446 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 12:45:25,446 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 12:45:25,447 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 12:45:25,447 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 12:45:25,447 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 12:45:25,447 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 12:45:25,448 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 12:45:25,448 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 12:45:25,448 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 12:45:25,448 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 12:45:25,448 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 12:45:25,449 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 12:45:25,449 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 12:45:25,449 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 12:45:25,449 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 12:45:25,450 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 12:45:25,451 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a74358cfc3b57ddf641c2843362a5594690e287c76148ee1838c9104dbe09de1 [2022-11-16 12:45:25,776 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 12:45:25,799 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 12:45:25,802 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 12:45:25,804 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 12:45:25,805 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 12:45:25,806 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-1.i [2022-11-16 12:45:25,872 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/data/42a8a3fbd/684f221ffd6047319ec33eaa100f1433/FLAGe927afe9a [2022-11-16 12:45:26,505 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 12:45:26,506 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-1.i [2022-11-16 12:45:26,519 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/data/42a8a3fbd/684f221ffd6047319ec33eaa100f1433/FLAGe927afe9a [2022-11-16 12:45:26,704 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/data/42a8a3fbd/684f221ffd6047319ec33eaa100f1433 [2022-11-16 12:45:26,707 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 12:45:26,710 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 12:45:26,714 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 12:45:26,714 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 12:45:26,719 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 12:45:26,720 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:45:26" (1/1) ... [2022-11-16 12:45:26,721 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6cb1a9c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:26, skipping insertion in model container [2022-11-16 12:45:26,722 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:45:26" (1/1) ... [2022-11-16 12:45:26,730 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 12:45:26,805 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 12:45:27,240 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-1.i[33021,33034] [2022-11-16 12:45:27,326 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:45:27,345 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 12:45:27,399 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-1.i[33021,33034] [2022-11-16 12:45:27,486 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:45:27,530 INFO L208 MainTranslator]: Completed translation [2022-11-16 12:45:27,531 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27 WrapperNode [2022-11-16 12:45:27,531 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 12:45:27,532 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 12:45:27,533 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 12:45:27,533 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 12:45:27,546 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,604 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,675 INFO L138 Inliner]: procedures = 177, calls = 186, calls flagged for inlining = 13, calls inlined = 13, statements flattened = 648 [2022-11-16 12:45:27,675 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 12:45:27,676 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 12:45:27,677 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 12:45:27,677 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 12:45:27,687 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,688 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,711 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,717 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,769 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,795 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,798 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,802 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,815 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 12:45:27,816 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 12:45:27,825 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 12:45:27,825 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 12:45:27,826 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (1/1) ... [2022-11-16 12:45:27,836 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 12:45:27,849 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:45:27,871 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 12:45:27,897 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 12:45:27,933 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-16 12:45:27,933 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-16 12:45:27,933 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-11-16 12:45:27,934 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-11-16 12:45:27,934 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-11-16 12:45:27,934 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 12:45:27,934 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-16 12:45:27,935 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-11-16 12:45:27,935 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-11-16 12:45:27,935 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-16 12:45:27,935 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 12:45:27,935 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 12:45:27,936 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 12:45:28,187 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 12:45:28,190 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 12:45:28,195 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-11-16 12:45:29,523 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 12:45:29,531 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 12:45:29,531 INFO L300 CfgBuilder]: Removed 31 assume(true) statements. [2022-11-16 12:45:29,534 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:45:29 BoogieIcfgContainer [2022-11-16 12:45:29,535 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 12:45:29,536 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 12:45:29,536 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 12:45:29,541 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 12:45:29,542 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:45:29,542 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 12:45:26" (1/3) ... [2022-11-16 12:45:29,543 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7048c963 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:45:29, skipping insertion in model container [2022-11-16 12:45:29,544 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:45:29,544 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:45:27" (2/3) ... [2022-11-16 12:45:29,544 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7048c963 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:45:29, skipping insertion in model container [2022-11-16 12:45:29,544 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:45:29,545 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:45:29" (3/3) ... [2022-11-16 12:45:29,546 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_SAX_test1-1.i [2022-11-16 12:45:29,608 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 12:45:29,609 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 12:45:29,609 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 12:45:29,609 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 12:45:29,609 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 12:45:29,610 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 12:45:29,610 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 12:45:29,610 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 12:45:29,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 131 states, 126 states have (on average 1.6428571428571428) internal successors, (207), 126 states have internal predecessors, (207), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:45:29,668 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 120 [2022-11-16 12:45:29,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:45:29,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:45:29,677 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:45:29,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-16 12:45:29,677 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 12:45:29,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 131 states, 126 states have (on average 1.6428571428571428) internal successors, (207), 126 states have internal predecessors, (207), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:45:29,686 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 120 [2022-11-16 12:45:29,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:45:29,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:45:29,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:45:29,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-16 12:45:29,695 INFO L748 eck$LassoCheckResult]: Stem: 114#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 43#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 103#L750-3true [2022-11-16 12:45:29,696 INFO L750 eck$LassoCheckResult]: Loop: 103#L750-3true assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 68#L752true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 70#L752-2true call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 30#L757-121true assume !true; 50#L750-2true main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 103#L750-3true [2022-11-16 12:45:29,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:45:29,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-11-16 12:45:29,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:45:29,714 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849514831] [2022-11-16 12:45:29,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:29,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:45:29,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:45:29,804 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:45:29,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:45:29,840 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:45:29,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:45:29,844 INFO L85 PathProgramCache]: Analyzing trace with hash 46868248, now seen corresponding path program 1 times [2022-11-16 12:45:29,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:45:29,844 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514804311] [2022-11-16 12:45:29,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:29,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:45:29,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:45:29,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:45:29,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514804311] [2022-11-16 12:45:29,885 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-11-16 12:45:29,885 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1602303476] [2022-11-16 12:45:29,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:29,886 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:45:29,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:45:29,893 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:45:29,917 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-16 12:45:30,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:45:30,020 INFO L263 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 1 conjunts are in the unsatisfiable core [2022-11-16 12:45:30,022 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:45:30,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:45:30,046 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:45:30,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1602303476] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:45:30,047 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:45:30,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:45:30,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136496149] [2022-11-16 12:45:30,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:45:30,055 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:45:30,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:45:30,099 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-16 12:45:30,099 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 12:45:30,104 INFO L87 Difference]: Start difference. First operand has 131 states, 126 states have (on average 1.6428571428571428) internal successors, (207), 126 states have internal predecessors, (207), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:45:30,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:45:30,142 INFO L93 Difference]: Finished difference Result 131 states and 168 transitions. [2022-11-16 12:45:30,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 131 states and 168 transitions. [2022-11-16 12:45:30,154 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 120 [2022-11-16 12:45:30,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 131 states to 127 states and 164 transitions. [2022-11-16 12:45:30,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127 [2022-11-16 12:45:30,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127 [2022-11-16 12:45:30,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127 states and 164 transitions. [2022-11-16 12:45:30,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:45:30,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127 states and 164 transitions. [2022-11-16 12:45:30,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states and 164 transitions. [2022-11-16 12:45:30,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2022-11-16 12:45:30,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 127 states, 123 states have (on average 1.2845528455284554) internal successors, (158), 122 states have internal predecessors, (158), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:45:30,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 164 transitions. [2022-11-16 12:45:30,231 INFO L240 hiAutomatonCegarLoop]: Abstraction has 127 states and 164 transitions. [2022-11-16 12:45:30,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-16 12:45:30,236 INFO L428 stractBuchiCegarLoop]: Abstraction has 127 states and 164 transitions. [2022-11-16 12:45:30,236 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 12:45:30,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 127 states and 164 transitions. [2022-11-16 12:45:30,238 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 120 [2022-11-16 12:45:30,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:45:30,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:45:30,239 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:45:30,240 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:45:30,240 INFO L748 eck$LassoCheckResult]: Stem: 407#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 351#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 352#L750-3 [2022-11-16 12:45:30,241 INFO L750 eck$LassoCheckResult]: Loop: 352#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 381#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 382#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 334#L757-121 havoc main_~_ha_hashv~0#1; 335#L757-49 goto; 370#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 286#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 287#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 341#L757-10 assume main_#t~switch19#1;call main_#t~mem20#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem20#1 % 256);havoc main_#t~mem20#1; 405#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 327#L757-13 assume main_#t~switch19#1;call main_#t~mem21#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem21#1 % 256);havoc main_#t~mem21#1; 284#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 285#L757-16 assume main_#t~switch19#1;call main_#t~mem22#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem22#1 % 256);havoc main_#t~mem22#1; 397#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 385#L757-19 assume main_#t~switch19#1;call main_#t~mem23#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem23#1 % 256);havoc main_#t~mem23#1; 317#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 318#L757-22 assume !main_#t~switch19#1; 368#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 345#L757-25 assume main_#t~switch19#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 346#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 404#L757-28 assume main_#t~switch19#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem26#1 % 256;havoc main_#t~mem26#1; 402#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 401#L757-31 assume main_#t~switch19#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 293#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 294#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 367#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 353#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 354#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 319#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 302#L757-42 havoc main_#t~switch19#1; 303#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 350#L757-44 goto; 389#L757-46 goto; 390#L757-48 goto; 365#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 366#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 394#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 395#L757-66 goto; 320#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 325#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 369#L757-70 goto; 380#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 408#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 338#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 339#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 398#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 357#L757-114 goto; 358#L757-116 goto; 383#L757-118 goto; 384#L757-120 goto; 360#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 352#L750-3 [2022-11-16 12:45:30,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:45:30,243 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-11-16 12:45:30,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:45:30,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1913820872] [2022-11-16 12:45:30,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:30,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:45:30,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:45:30,254 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:45:30,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:45:30,267 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:45:30,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:45:30,269 INFO L85 PathProgramCache]: Analyzing trace with hash -51894535, now seen corresponding path program 1 times [2022-11-16 12:45:30,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:45:30,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558616796] [2022-11-16 12:45:30,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:30,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:45:30,484 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:45:30,485 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [712148577] [2022-11-16 12:45:30,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:30,485 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:45:30,486 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:45:30,489 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:45:30,509 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-16 12:45:31,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:45:31,375 INFO L263 TraceCheckSpWp]: Trace formula consists of 1823 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 12:45:31,379 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:45:31,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:45:31,417 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:45:31,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:45:31,418 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1558616796] [2022-11-16 12:45:31,418 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 12:45:31,418 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [712148577] [2022-11-16 12:45:31,419 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [712148577] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:45:31,419 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:45:31,419 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:45:31,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435072679] [2022-11-16 12:45:31,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:45:31,420 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:45:31,421 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:45:31,421 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:45:31,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:45:31,422 INFO L87 Difference]: Start difference. First operand 127 states and 164 transitions. cyclomatic complexity: 40 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:45:31,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:45:31,540 INFO L93 Difference]: Finished difference Result 148 states and 185 transitions. [2022-11-16 12:45:31,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 148 states and 185 transitions. [2022-11-16 12:45:31,542 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 141 [2022-11-16 12:45:31,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 148 states to 148 states and 185 transitions. [2022-11-16 12:45:31,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 148 [2022-11-16 12:45:31,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 148 [2022-11-16 12:45:31,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148 states and 185 transitions. [2022-11-16 12:45:31,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:45:31,546 INFO L218 hiAutomatonCegarLoop]: Abstraction has 148 states and 185 transitions. [2022-11-16 12:45:31,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states and 185 transitions. [2022-11-16 12:45:31,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 147. [2022-11-16 12:45:31,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 143 states have (on average 1.2447552447552448) internal successors, (178), 142 states have internal predecessors, (178), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:45:31,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 184 transitions. [2022-11-16 12:45:31,554 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147 states and 184 transitions. [2022-11-16 12:45:31,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:45:31,555 INFO L428 stractBuchiCegarLoop]: Abstraction has 147 states and 184 transitions. [2022-11-16 12:45:31,556 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 12:45:31,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147 states and 184 transitions. [2022-11-16 12:45:31,557 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 140 [2022-11-16 12:45:31,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:45:31,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:45:31,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:45:31,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:45:31,559 INFO L748 eck$LassoCheckResult]: Stem: 841#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 782#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 783#L750-3 [2022-11-16 12:45:31,559 INFO L750 eck$LassoCheckResult]: Loop: 783#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 812#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 813#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 763#L757-121 havoc main_~_ha_hashv~0#1; 764#L757-49 goto; 801#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 717#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 718#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 772#L757-10 assume main_#t~switch19#1;call main_#t~mem20#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem20#1 % 256);havoc main_#t~mem20#1; 836#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 758#L757-13 assume main_#t~switch19#1;call main_#t~mem21#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem21#1 % 256);havoc main_#t~mem21#1; 715#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 716#L757-16 assume main_#t~switch19#1;call main_#t~mem22#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem22#1 % 256);havoc main_#t~mem22#1; 828#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 816#L757-19 assume main_#t~switch19#1;call main_#t~mem23#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem23#1 % 256);havoc main_#t~mem23#1; 748#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 749#L757-22 assume main_#t~switch19#1;call main_#t~mem24#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem24#1 % 256);havoc main_#t~mem24#1; 799#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 776#L757-25 assume main_#t~switch19#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 777#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 835#L757-28 assume main_#t~switch19#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem26#1 % 256;havoc main_#t~mem26#1; 833#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 832#L757-31 assume main_#t~switch19#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 724#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 725#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 798#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 784#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 785#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 750#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 733#L757-42 havoc main_#t~switch19#1; 734#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 780#L757-44 goto; 820#L757-46 goto; 821#L757-48 goto; 796#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 797#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 825#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 826#L757-66 goto; 753#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 756#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 800#L757-70 goto; 811#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 842#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 769#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 770#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 829#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 788#L757-114 goto; 789#L757-116 goto; 814#L757-118 goto; 815#L757-120 goto; 792#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 783#L750-3 [2022-11-16 12:45:31,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:45:31,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-11-16 12:45:31,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:45:31,561 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785198079] [2022-11-16 12:45:31,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:31,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:45:31,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:45:31,574 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:45:31,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:45:31,590 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:45:31,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:45:31,591 INFO L85 PathProgramCache]: Analyzing trace with hash 792110967, now seen corresponding path program 1 times [2022-11-16 12:45:31,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:45:31,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327816951] [2022-11-16 12:45:31,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:31,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:45:31,750 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:45:31,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1091661349] [2022-11-16 12:45:31,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:31,751 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:45:31,751 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:45:31,780 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:45:31,797 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-16 12:45:32,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:45:32,764 INFO L263 TraceCheckSpWp]: Trace formula consists of 1829 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 12:45:32,767 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:45:32,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:45:32,798 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:45:32,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:45:32,801 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1327816951] [2022-11-16 12:45:32,801 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 12:45:32,801 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1091661349] [2022-11-16 12:45:32,802 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1091661349] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:45:32,802 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:45:32,802 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 12:45:32,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222511133] [2022-11-16 12:45:32,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:45:32,803 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:45:32,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:45:32,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:45:32,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:45:32,804 INFO L87 Difference]: Start difference. First operand 147 states and 184 transitions. cyclomatic complexity: 40 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 4 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:45:32,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:45:32,907 INFO L93 Difference]: Finished difference Result 175 states and 216 transitions. [2022-11-16 12:45:32,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175 states and 216 transitions. [2022-11-16 12:45:32,909 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 161 [2022-11-16 12:45:32,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175 states to 175 states and 216 transitions. [2022-11-16 12:45:32,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 175 [2022-11-16 12:45:32,912 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 175 [2022-11-16 12:45:32,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 175 states and 216 transitions. [2022-11-16 12:45:32,913 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:45:32,913 INFO L218 hiAutomatonCegarLoop]: Abstraction has 175 states and 216 transitions. [2022-11-16 12:45:32,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states and 216 transitions. [2022-11-16 12:45:32,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 133. [2022-11-16 12:45:32,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133 states, 129 states have (on average 1.2170542635658914) internal successors, (157), 128 states have internal predecessors, (157), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:45:32,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 163 transitions. [2022-11-16 12:45:32,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133 states and 163 transitions. [2022-11-16 12:45:32,920 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:45:32,921 INFO L428 stractBuchiCegarLoop]: Abstraction has 133 states and 163 transitions. [2022-11-16 12:45:32,921 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 12:45:32,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133 states and 163 transitions. [2022-11-16 12:45:32,922 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 126 [2022-11-16 12:45:32,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:45:32,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:45:32,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:45:32,923 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:45:32,924 INFO L748 eck$LassoCheckResult]: Stem: 1325#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 1263#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 1264#L750-3 [2022-11-16 12:45:32,924 INFO L750 eck$LassoCheckResult]: Loop: 1264#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 1294#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1295#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 1244#L757-121 havoc main_~_ha_hashv~0#1; 1245#L757-49 goto; 1283#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1198#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1199#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 1253#L757-10 assume !main_#t~switch19#1; 1319#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 1239#L757-13 assume !main_#t~switch19#1; 1196#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 1197#L757-16 assume !main_#t~switch19#1; 1310#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 1298#L757-19 assume !main_#t~switch19#1; 1229#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 1230#L757-22 assume !main_#t~switch19#1; 1281#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 1257#L757-25 assume !main_#t~switch19#1; 1258#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 1318#L757-28 assume !main_#t~switch19#1; 1316#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 1314#L757-31 assume main_#t~switch19#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 1315#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 1279#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 1280#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 1265#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 1266#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 1231#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 1214#L757-42 havoc main_#t~switch19#1; 1215#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1261#L757-44 goto; 1302#L757-46 goto; 1303#L757-48 goto; 1277#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1278#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 1307#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 1308#L757-66 goto; 1234#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 1237#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 1282#L757-70 goto; 1293#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1326#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 1250#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 1251#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 1311#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 1269#L757-114 goto; 1270#L757-116 goto; 1296#L757-118 goto; 1297#L757-120 goto; 1272#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1264#L750-3 [2022-11-16 12:45:32,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:45:32,925 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-11-16 12:45:32,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:45:32,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622100609] [2022-11-16 12:45:32,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:32,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:45:32,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:45:32,938 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:45:32,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:45:32,952 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:45:32,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:45:32,953 INFO L85 PathProgramCache]: Analyzing trace with hash -1082263419, now seen corresponding path program 1 times [2022-11-16 12:45:32,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:45:32,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776218153] [2022-11-16 12:45:32,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:32,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:45:33,168 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:45:33,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [671970742] [2022-11-16 12:45:33,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:45:33,174 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:45:33,174 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:45:33,187 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:45:33,194 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-16 12:46:59,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:46:59,507 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:47:03,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:47:03,657 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:47:03,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:47:03,658 INFO L85 PathProgramCache]: Analyzing trace with hash -1692418973, now seen corresponding path program 1 times [2022-11-16 12:47:03,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:47:03,658 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310163123] [2022-11-16 12:47:03,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:47:03,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:47:03,838 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:47:03,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1103532531] [2022-11-16 12:47:03,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:47:03,839 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:47:03,839 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:47:03,843 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:47:03,889 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b61bcdf0-148a-4efb-beda-6f7dc2754ae4/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-16 12:47:04,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:47:04,953 INFO L263 TraceCheckSpWp]: Trace formula consists of 1814 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-16 12:47:04,957 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:47:05,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:47:05,213 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:47:05,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:47:05,213 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310163123] [2022-11-16 12:47:05,214 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 12:47:05,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1103532531] [2022-11-16 12:47:05,214 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1103532531] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:47:05,214 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:47:05,214 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:47:05,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167526980] [2022-11-16 12:47:05,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton