./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-2.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7f552e336cb6eb3ea16ba25a84411e1d0c8dcfaa2b088c21df87ffefed1a84a7 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:22:32,817 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:22:32,819 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:22:32,844 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:22:32,845 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:22:32,846 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:22:32,847 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:22:32,849 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:22:32,851 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:22:32,852 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:22:32,853 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:22:32,854 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:22:32,854 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:22:32,855 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:22:32,857 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:22:32,858 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:22:32,859 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:22:32,860 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:22:32,861 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:22:32,863 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:22:32,865 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:22:32,866 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:22:32,867 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:22:32,868 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:22:32,872 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:22:32,872 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:22:32,873 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:22:32,874 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:22:32,874 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:22:32,875 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:22:32,875 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:22:32,876 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:22:32,877 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:22:32,878 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:22:32,879 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:22:32,879 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:22:32,880 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:22:32,880 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:22:32,881 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:22:32,882 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:22:32,883 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:22:32,888 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 11:22:32,924 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:22:32,924 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:22:32,924 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:22:32,925 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:22:32,926 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:22:32,926 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:22:32,926 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:22:32,926 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 11:22:32,927 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 11:22:32,927 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 11:22:32,927 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 11:22:32,927 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 11:22:32,927 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 11:22:32,928 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:22:32,928 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 11:22:32,928 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 11:22:32,928 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:22:32,928 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 11:22:32,928 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:22:32,929 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 11:22:32,929 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 11:22:32,929 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 11:22:32,929 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 11:22:32,929 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:22:32,930 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 11:22:32,930 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:22:32,930 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 11:22:32,935 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:22:32,936 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:22:32,936 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:22:32,937 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:22:32,938 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 11:22:32,938 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7f552e336cb6eb3ea16ba25a84411e1d0c8dcfaa2b088c21df87ffefed1a84a7 [2022-11-16 11:22:33,207 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:22:33,232 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:22:33,236 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:22:33,238 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:22:33,239 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:22:33,240 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-2.i [2022-11-16 11:22:33,326 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/data/4555395d3/1958f87e91124880b5bf6a8723b7d06d/FLAG4d0748398 [2022-11-16 11:22:33,989 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:22:33,990 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-2.i [2022-11-16 11:22:34,005 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/data/4555395d3/1958f87e91124880b5bf6a8723b7d06d/FLAG4d0748398 [2022-11-16 11:22:34,284 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/data/4555395d3/1958f87e91124880b5bf6a8723b7d06d [2022-11-16 11:22:34,287 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:22:34,288 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:22:34,290 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:22:34,291 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:22:34,297 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:22:34,298 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:22:34" (1/1) ... [2022-11-16 11:22:34,299 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7662e003 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:34, skipping insertion in model container [2022-11-16 11:22:34,299 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:22:34" (1/1) ... [2022-11-16 11:22:34,308 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:22:34,372 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:22:34,819 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-2.i[33021,33034] [2022-11-16 11:22:34,932 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:22:34,947 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:22:34,990 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test1-2.i[33021,33034] [2022-11-16 11:22:35,068 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:22:35,128 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:22:35,129 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35 WrapperNode [2022-11-16 11:22:35,130 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:22:35,131 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:22:35,131 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:22:35,131 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:22:35,139 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,162 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,216 INFO L138 Inliner]: procedures = 177, calls = 237, calls flagged for inlining = 13, calls inlined = 13, statements flattened = 803 [2022-11-16 11:22:35,217 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:22:35,218 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:22:35,218 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:22:35,218 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:22:35,228 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,228 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,244 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,252 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,291 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,302 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,305 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,309 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,316 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:22:35,317 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:22:35,317 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:22:35,317 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:22:35,319 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (1/1) ... [2022-11-16 11:22:35,326 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 11:22:35,338 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:22:35,353 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 11:22:35,382 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 11:22:35,401 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-16 11:22:35,401 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-16 11:22:35,401 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-11-16 11:22:35,401 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-11-16 11:22:35,402 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-11-16 11:22:35,402 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 11:22:35,402 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-16 11:22:35,402 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-11-16 11:22:35,404 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-11-16 11:22:35,404 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-16 11:22:35,404 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 11:22:35,404 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:22:35,404 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:22:35,687 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:22:35,698 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:22:35,702 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-11-16 11:22:37,372 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:22:37,389 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:22:37,389 INFO L300 CfgBuilder]: Removed 40 assume(true) statements. [2022-11-16 11:22:37,393 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:22:37 BoogieIcfgContainer [2022-11-16 11:22:37,393 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:22:37,395 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 11:22:37,395 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 11:22:37,400 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 11:22:37,400 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:22:37,401 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 11:22:34" (1/3) ... [2022-11-16 11:22:37,402 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5e896662 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:22:37, skipping insertion in model container [2022-11-16 11:22:37,402 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:22:37,402 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:22:35" (2/3) ... [2022-11-16 11:22:37,403 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5e896662 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 11:22:37, skipping insertion in model container [2022-11-16 11:22:37,403 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 11:22:37,403 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:22:37" (3/3) ... [2022-11-16 11:22:37,406 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_SAX_test1-2.i [2022-11-16 11:22:37,469 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 11:22:37,470 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 11:22:37,470 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 11:22:37,470 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 11:22:37,470 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 11:22:37,470 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 11:22:37,470 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 11:22:37,471 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 11:22:37,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 160 states, 155 states have (on average 1.6516129032258065) internal successors, (256), 155 states have internal predecessors, (256), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:22:37,508 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 146 [2022-11-16 11:22:37,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:22:37,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:22:37,515 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:22:37,515 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-16 11:22:37,515 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 11:22:37,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 160 states, 155 states have (on average 1.6516129032258065) internal successors, (256), 155 states have internal predecessors, (256), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:22:37,524 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 146 [2022-11-16 11:22:37,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:22:37,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:22:37,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:22:37,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-16 11:22:37,535 INFO L748 eck$LassoCheckResult]: Stem: 143#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 51#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 127#L750-3true [2022-11-16 11:22:37,535 INFO L750 eck$LassoCheckResult]: Loop: 127#L750-3true assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 86#L752true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 88#L752-2true call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 34#L757-121true assume !true; 62#L750-2true main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 127#L750-3true [2022-11-16 11:22:37,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:37,541 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-11-16 11:22:37,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:37,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625417755] [2022-11-16 11:22:37,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:37,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:37,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:37,659 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:22:37,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:37,727 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:22:37,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:37,730 INFO L85 PathProgramCache]: Analyzing trace with hash 46868248, now seen corresponding path program 1 times [2022-11-16 11:22:37,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:37,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259053623] [2022-11-16 11:22:37,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:37,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:37,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:22:37,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:22:37,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259053623] [2022-11-16 11:22:37,795 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-11-16 11:22:37,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [102676047] [2022-11-16 11:22:37,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:37,796 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:22:37,796 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:22:37,803 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:22:37,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-16 11:22:37,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:22:37,933 INFO L263 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 1 conjunts are in the unsatisfiable core [2022-11-16 11:22:37,934 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:22:37,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:22:37,953 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:22:37,954 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [102676047] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:22:37,954 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:22:37,954 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:22:37,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162589433] [2022-11-16 11:22:37,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:22:37,960 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:22:37,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:22:38,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-16 11:22:38,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 11:22:38,015 INFO L87 Difference]: Start difference. First operand has 160 states, 155 states have (on average 1.6516129032258065) internal successors, (256), 155 states have internal predecessors, (256), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:22:38,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:22:38,053 INFO L93 Difference]: Finished difference Result 160 states and 208 transitions. [2022-11-16 11:22:38,055 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 160 states and 208 transitions. [2022-11-16 11:22:38,066 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 146 [2022-11-16 11:22:38,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 160 states to 156 states and 204 transitions. [2022-11-16 11:22:38,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156 [2022-11-16 11:22:38,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156 [2022-11-16 11:22:38,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156 states and 204 transitions. [2022-11-16 11:22:38,087 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:22:38,088 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156 states and 204 transitions. [2022-11-16 11:22:38,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states and 204 transitions. [2022-11-16 11:22:38,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 156. [2022-11-16 11:22:38,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156 states, 152 states have (on average 1.3026315789473684) internal successors, (198), 151 states have internal predecessors, (198), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:22:38,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 204 transitions. [2022-11-16 11:22:38,131 INFO L240 hiAutomatonCegarLoop]: Abstraction has 156 states and 204 transitions. [2022-11-16 11:22:38,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-16 11:22:38,136 INFO L428 stractBuchiCegarLoop]: Abstraction has 156 states and 204 transitions. [2022-11-16 11:22:38,137 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 11:22:38,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states and 204 transitions. [2022-11-16 11:22:38,139 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 146 [2022-11-16 11:22:38,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:22:38,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:22:38,140 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:22:38,140 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:22:38,141 INFO L748 eck$LassoCheckResult]: Stem: 494#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 423#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 424#L750-3 [2022-11-16 11:22:38,142 INFO L750 eck$LassoCheckResult]: Loop: 424#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 465#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 466#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 404#L757-121 havoc main_~_ha_hashv~0#1; 405#L757-49 goto; 452#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 344#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 345#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 411#L757-10 assume main_#t~switch19#1;call main_#t~mem20#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem20#1 % 256);havoc main_#t~mem20#1; 492#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 393#L757-13 assume main_#t~switch19#1;call main_#t~mem21#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem21#1 % 256);havoc main_#t~mem21#1; 342#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 343#L757-16 assume main_#t~switch19#1;call main_#t~mem22#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem22#1 % 256);havoc main_#t~mem22#1; 485#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 469#L757-19 assume main_#t~switch19#1;call main_#t~mem23#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem23#1 % 256);havoc main_#t~mem23#1; 381#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 382#L757-22 assume !main_#t~switch19#1; 450#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 415#L757-25 assume main_#t~switch19#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 416#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 491#L757-28 assume main_#t~switch19#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem26#1 % 256;havoc main_#t~mem26#1; 489#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 488#L757-31 assume main_#t~switch19#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 357#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 358#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 448#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 427#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 428#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 385#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 366#L757-42 havoc main_#t~switch19#1; 367#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 421#L757-44 goto; 474#L757-46 goto; 475#L757-48 goto; 446#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 447#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 481#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 482#L757-66 goto; 386#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 390#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 451#L757-70 goto; 462#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 495#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 406#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 407#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 484#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 429#L757-114 goto; 430#L757-116 goto; 467#L757-118 goto; 468#L757-120 goto; 438#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 424#L750-3 [2022-11-16 11:22:38,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:38,143 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-11-16 11:22:38,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:38,144 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463849268] [2022-11-16 11:22:38,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:38,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:38,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:38,165 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:22:38,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:38,187 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:22:38,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:38,189 INFO L85 PathProgramCache]: Analyzing trace with hash -51894535, now seen corresponding path program 1 times [2022-11-16 11:22:38,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:38,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055182292] [2022-11-16 11:22:38,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:38,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:38,429 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:22:38,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [548150882] [2022-11-16 11:22:38,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:38,430 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:22:38,430 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:22:38,433 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:22:38,448 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-16 11:22:39,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:22:39,162 INFO L263 TraceCheckSpWp]: Trace formula consists of 1823 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 11:22:39,166 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:22:39,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:22:39,200 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:22:39,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:22:39,200 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055182292] [2022-11-16 11:22:39,200 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:22:39,201 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [548150882] [2022-11-16 11:22:39,201 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [548150882] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:22:39,201 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:22:39,201 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:22:39,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1939042466] [2022-11-16 11:22:39,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:22:39,202 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:22:39,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:22:39,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 11:22:39,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 11:22:39,203 INFO L87 Difference]: Start difference. First operand 156 states and 204 transitions. cyclomatic complexity: 52 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:22:39,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:22:39,323 INFO L93 Difference]: Finished difference Result 177 states and 225 transitions. [2022-11-16 11:22:39,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 177 states and 225 transitions. [2022-11-16 11:22:39,327 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 167 [2022-11-16 11:22:39,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 177 states to 177 states and 225 transitions. [2022-11-16 11:22:39,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 177 [2022-11-16 11:22:39,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 177 [2022-11-16 11:22:39,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 177 states and 225 transitions. [2022-11-16 11:22:39,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:22:39,344 INFO L218 hiAutomatonCegarLoop]: Abstraction has 177 states and 225 transitions. [2022-11-16 11:22:39,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states and 225 transitions. [2022-11-16 11:22:39,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 176. [2022-11-16 11:22:39,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 172 states have (on average 1.2674418604651163) internal successors, (218), 171 states have internal predecessors, (218), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:22:39,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 224 transitions. [2022-11-16 11:22:39,353 INFO L240 hiAutomatonCegarLoop]: Abstraction has 176 states and 224 transitions. [2022-11-16 11:22:39,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 11:22:39,354 INFO L428 stractBuchiCegarLoop]: Abstraction has 176 states and 224 transitions. [2022-11-16 11:22:39,355 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 11:22:39,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 224 transitions. [2022-11-16 11:22:39,356 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 166 [2022-11-16 11:22:39,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:22:39,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:22:39,358 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:22:39,358 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:22:39,358 INFO L748 eck$LassoCheckResult]: Stem: 988#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 912#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 913#L750-3 [2022-11-16 11:22:39,358 INFO L750 eck$LassoCheckResult]: Loop: 913#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 955#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 956#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 891#L757-121 havoc main_~_ha_hashv~0#1; 892#L757-49 goto; 942#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 833#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 834#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 900#L757-10 assume main_#t~switch19#1;call main_#t~mem20#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem20#1 % 256);havoc main_#t~mem20#1; 983#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 882#L757-13 assume main_#t~switch19#1;call main_#t~mem21#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem21#1 % 256);havoc main_#t~mem21#1; 831#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 832#L757-16 assume main_#t~switch19#1;call main_#t~mem22#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem22#1 % 256);havoc main_#t~mem22#1; 975#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 959#L757-19 assume main_#t~switch19#1;call main_#t~mem23#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem23#1 % 256);havoc main_#t~mem23#1; 870#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 871#L757-22 assume main_#t~switch19#1;call main_#t~mem24#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem24#1 % 256);havoc main_#t~mem24#1; 941#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 904#L757-25 assume main_#t~switch19#1;call main_#t~mem25#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem25#1 % 256);havoc main_#t~mem25#1; 905#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 982#L757-28 assume main_#t~switch19#1;call main_#t~mem26#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem26#1 % 256;havoc main_#t~mem26#1; 980#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 978#L757-31 assume main_#t~switch19#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 979#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 937#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 938#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 916#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 917#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 872#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 855#L757-42 havoc main_#t~switch19#1; 856#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 910#L757-44 goto; 964#L757-46 goto; 965#L757-48 goto; 935#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 936#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 971#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 972#L757-66 goto; 875#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 879#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 940#L757-70 goto; 952#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 991#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 895#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 896#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 974#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 918#L757-114 goto; 919#L757-116 goto; 957#L757-118 goto; 958#L757-120 goto; 927#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 913#L750-3 [2022-11-16 11:22:39,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:39,359 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-11-16 11:22:39,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:39,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313881059] [2022-11-16 11:22:39,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:39,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:39,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:39,373 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:22:39,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:39,386 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:22:39,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:39,387 INFO L85 PathProgramCache]: Analyzing trace with hash 792110967, now seen corresponding path program 1 times [2022-11-16 11:22:39,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:39,387 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533065945] [2022-11-16 11:22:39,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:39,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:39,575 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:22:39,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1237615821] [2022-11-16 11:22:39,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:39,576 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:22:39,576 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:22:39,613 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:22:39,631 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-16 11:22:40,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:22:40,420 INFO L263 TraceCheckSpWp]: Trace formula consists of 1829 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 11:22:40,423 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:22:40,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:22:40,455 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:22:40,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:22:40,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533065945] [2022-11-16 11:22:40,456 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:22:40,456 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1237615821] [2022-11-16 11:22:40,456 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1237615821] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:22:40,456 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:22:40,456 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 11:22:40,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047891345] [2022-11-16 11:22:40,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:22:40,457 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:22:40,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:22:40,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:22:40,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:22:40,458 INFO L87 Difference]: Start difference. First operand 176 states and 224 transitions. cyclomatic complexity: 52 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 4 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:22:40,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:22:40,559 INFO L93 Difference]: Finished difference Result 233 states and 296 transitions. [2022-11-16 11:22:40,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 233 states and 296 transitions. [2022-11-16 11:22:40,562 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 213 [2022-11-16 11:22:40,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 233 states to 233 states and 296 transitions. [2022-11-16 11:22:40,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 233 [2022-11-16 11:22:40,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 233 [2022-11-16 11:22:40,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 233 states and 296 transitions. [2022-11-16 11:22:40,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:22:40,565 INFO L218 hiAutomatonCegarLoop]: Abstraction has 233 states and 296 transitions. [2022-11-16 11:22:40,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states and 296 transitions. [2022-11-16 11:22:40,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 162. [2022-11-16 11:22:40,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162 states, 158 states have (on average 1.2468354430379747) internal successors, (197), 157 states have internal predecessors, (197), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:22:40,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 203 transitions. [2022-11-16 11:22:40,580 INFO L240 hiAutomatonCegarLoop]: Abstraction has 162 states and 203 transitions. [2022-11-16 11:22:40,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:22:40,581 INFO L428 stractBuchiCegarLoop]: Abstraction has 162 states and 203 transitions. [2022-11-16 11:22:40,581 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 11:22:40,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 162 states and 203 transitions. [2022-11-16 11:22:40,582 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 152 [2022-11-16 11:22:40,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:22:40,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:22:40,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:22:40,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:22:40,584 INFO L748 eck$LassoCheckResult]: Stem: 1553#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 1480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 1481#L750-3 [2022-11-16 11:22:40,584 INFO L750 eck$LassoCheckResult]: Loop: 1481#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 1523#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1524#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 1455#L757-121 havoc main_~_ha_hashv~0#1; 1456#L757-49 goto; 1510#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1401#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1402#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 1468#L757-10 assume !main_#t~switch19#1; 1551#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 1450#L757-13 assume !main_#t~switch19#1; 1399#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 1400#L757-16 assume !main_#t~switch19#1; 1542#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 1527#L757-19 assume !main_#t~switch19#1; 1438#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 1439#L757-22 assume !main_#t~switch19#1; 1508#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 1472#L757-25 assume !main_#t~switch19#1; 1473#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 1550#L757-28 assume !main_#t~switch19#1; 1548#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 1546#L757-31 assume !main_#t~switch19#1; 1414#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 1415#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 1506#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 1484#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 1485#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 1442#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 1423#L757-42 havoc main_#t~switch19#1; 1424#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1478#L757-44 goto; 1534#L757-46 goto; 1535#L757-48 goto; 1503#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1504#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 1539#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 1540#L757-66 goto; 1445#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 1448#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 1509#L757-70 goto; 1522#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1554#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 1465#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 1466#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 1543#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 1488#L757-114 goto; 1489#L757-116 goto; 1525#L757-118 goto; 1526#L757-120 goto; 1497#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1481#L750-3 [2022-11-16 11:22:40,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:40,585 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-11-16 11:22:40,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:40,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877728604] [2022-11-16 11:22:40,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:40,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:40,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:40,627 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:22:40,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:40,644 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:22:40,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:40,644 INFO L85 PathProgramCache]: Analyzing trace with hash 303939975, now seen corresponding path program 1 times [2022-11-16 11:22:40,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:40,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762085604] [2022-11-16 11:22:40,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:40,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:40,795 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:22:40,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [555493475] [2022-11-16 11:22:40,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:40,795 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:22:40,796 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:22:40,803 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:22:40,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-16 11:22:41,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:22:41,831 INFO L263 TraceCheckSpWp]: Trace formula consists of 1781 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-16 11:22:41,834 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:22:41,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:22:41,899 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:22:41,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:22:41,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762085604] [2022-11-16 11:22:41,900 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:22:41,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [555493475] [2022-11-16 11:22:41,900 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [555493475] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:22:41,901 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:22:41,901 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-16 11:22:41,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916750896] [2022-11-16 11:22:41,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:22:41,902 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:22:41,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:22:41,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-16 11:22:41,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:22:41,905 INFO L87 Difference]: Start difference. First operand 162 states and 203 transitions. cyclomatic complexity: 45 Second operand has 5 states, 5 states have (on average 10.2) internal successors, (51), 5 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:22:42,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:22:42,031 INFO L93 Difference]: Finished difference Result 319 states and 398 transitions. [2022-11-16 11:22:42,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319 states and 398 transitions. [2022-11-16 11:22:42,036 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 305 [2022-11-16 11:22:42,039 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319 states to 319 states and 398 transitions. [2022-11-16 11:22:42,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 319 [2022-11-16 11:22:42,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 319 [2022-11-16 11:22:42,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 319 states and 398 transitions. [2022-11-16 11:22:42,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:22:42,041 INFO L218 hiAutomatonCegarLoop]: Abstraction has 319 states and 398 transitions. [2022-11-16 11:22:42,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states and 398 transitions. [2022-11-16 11:22:42,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 185. [2022-11-16 11:22:42,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185 states, 181 states have (on average 1.2265193370165746) internal successors, (222), 180 states have internal predecessors, (222), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:22:42,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 228 transitions. [2022-11-16 11:22:42,066 INFO L240 hiAutomatonCegarLoop]: Abstraction has 185 states and 228 transitions. [2022-11-16 11:22:42,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-16 11:22:42,067 INFO L428 stractBuchiCegarLoop]: Abstraction has 185 states and 228 transitions. [2022-11-16 11:22:42,067 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-16 11:22:42,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185 states and 228 transitions. [2022-11-16 11:22:42,070 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 175 [2022-11-16 11:22:42,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:22:42,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:22:42,073 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:22:42,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:22:42,074 INFO L748 eck$LassoCheckResult]: Stem: 2204#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 2121#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 2122#L750-3 [2022-11-16 11:22:42,074 INFO L750 eck$LassoCheckResult]: Loop: 2122#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 2166#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 2167#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 2095#L757-121 havoc main_~_ha_hashv~0#1; 2096#L757-49 goto; 2153#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 2040#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 2041#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 2198#L757-10 assume !main_#t~switch19#1; 2199#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 2089#L757-13 assume !main_#t~switch19#1; 2090#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 2186#L757-16 assume !main_#t~switch19#1; 2187#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 2170#L757-19 assume !main_#t~switch19#1; 2171#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 2151#L757-22 assume !main_#t~switch19#1; 2152#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 2113#L757-25 assume !main_#t~switch19#1; 2114#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 2202#L757-28 assume !main_#t~switch19#1; 2203#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 2191#L757-31 assume !main_#t~switch19#1; 2192#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 2219#L757-34 assume !main_#t~switch19#1; 2217#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 2215#L757-37 assume !main_#t~switch19#1; 2213#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 2081#L757-40 assume !main_#t~switch19#1; 2062#L757-42 havoc main_#t~switch19#1; 2063#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 2119#L757-44 goto; 2178#L757-46 goto; 2179#L757-48 goto; 2144#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 2145#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 2183#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 2184#L757-66 goto; 2084#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 2087#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 2150#L757-70 goto; 2165#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 2207#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 2105#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 2106#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 2188#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 2129#L757-114 goto; 2130#L757-116 goto; 2168#L757-118 goto; 2169#L757-120 goto; 2138#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2122#L750-3 [2022-11-16 11:22:42,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:42,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 5 times [2022-11-16 11:22:42,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:42,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004510177] [2022-11-16 11:22:42,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:42,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:42,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:42,109 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:22:42,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:42,130 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:22:42,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:42,132 INFO L85 PathProgramCache]: Analyzing trace with hash 562278285, now seen corresponding path program 1 times [2022-11-16 11:22:42,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:42,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760087963] [2022-11-16 11:22:42,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:42,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:42,290 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:22:42,293 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1486751755] [2022-11-16 11:22:42,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:42,293 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:22:42,293 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:22:42,299 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:22:42,301 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-16 11:22:43,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:22:43,334 INFO L263 TraceCheckSpWp]: Trace formula consists of 1763 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-16 11:22:43,336 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:22:43,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:22:43,388 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:22:43,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:22:43,388 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760087963] [2022-11-16 11:22:43,389 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:22:43,389 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1486751755] [2022-11-16 11:22:43,389 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1486751755] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:22:43,389 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:22:43,389 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 11:22:43,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094347789] [2022-11-16 11:22:43,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:22:43,390 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 11:22:43,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:22:43,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:22:43,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:22:43,391 INFO L87 Difference]: Start difference. First operand 185 states and 228 transitions. cyclomatic complexity: 47 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 4 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 11:22:43,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:22:43,460 INFO L93 Difference]: Finished difference Result 223 states and 281 transitions. [2022-11-16 11:22:43,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 281 transitions. [2022-11-16 11:22:43,462 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 203 [2022-11-16 11:22:43,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 223 states and 281 transitions. [2022-11-16 11:22:43,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 223 [2022-11-16 11:22:43,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 223 [2022-11-16 11:22:43,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 281 transitions. [2022-11-16 11:22:43,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 11:22:43,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223 states and 281 transitions. [2022-11-16 11:22:43,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 281 transitions. [2022-11-16 11:22:43,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 153. [2022-11-16 11:22:43,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 153 states, 149 states have (on average 1.2281879194630871) internal successors, (183), 148 states have internal predecessors, (183), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:22:43,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 189 transitions. [2022-11-16 11:22:43,475 INFO L240 hiAutomatonCegarLoop]: Abstraction has 153 states and 189 transitions. [2022-11-16 11:22:43,475 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:22:43,478 INFO L428 stractBuchiCegarLoop]: Abstraction has 153 states and 189 transitions. [2022-11-16 11:22:43,478 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-16 11:22:43,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 153 states and 189 transitions. [2022-11-16 11:22:43,479 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 143 [2022-11-16 11:22:43,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 11:22:43,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 11:22:43,484 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 11:22:43,485 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:22:43,486 INFO L748 eck$LassoCheckResult]: Stem: 2754#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0; 2683#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~switch19#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~mem22#1, main_#t~mem23#1, main_#t~mem24#1, main_#t~mem25#1, main_#t~mem26#1, main_#t~mem27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc31#1.base, main_#t~malloc31#1.offset, main_#t~mem32#1.base, main_#t~mem32#1.offset, main_#t~mem33#1.base, main_#t~mem33#1.offset, main_#t~memset~res34#1.base, main_#t~memset~res34#1.offset, main_#t~mem35#1.base, main_#t~mem35#1.offset, main_#t~mem36#1.base, main_#t~mem36#1.offset, main_#t~mem37#1.base, main_#t~mem37#1.offset, main_#t~mem38#1.base, main_#t~mem38#1.offset, main_#t~mem39#1.base, main_#t~mem39#1.offset, main_#t~malloc40#1.base, main_#t~malloc40#1.offset, main_#t~mem41#1.base, main_#t~mem41#1.offset, main_#t~mem42#1.base, main_#t~mem42#1.offset, main_#t~mem43#1.base, main_#t~mem43#1.offset, main_#t~mem44#1.base, main_#t~mem44#1.offset, main_#t~mem45#1.base, main_#t~mem45#1.offset, main_#t~mem46#1.base, main_#t~mem46#1.offset, main_#t~memset~res47#1.base, main_#t~memset~res47#1.offset, main_#t~mem48#1.base, main_#t~mem48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1, main_#t~post58#1, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1, main_#t~post64#1, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem69#1, main_#t~mem68#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~short72#1, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~malloc75#1.base, main_#t~malloc75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~memset~res80#1.base, main_#t~memset~res80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem85#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem89#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem100#1, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~pre103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~post108#1, main_#t~mem112#1, main_#t~mem110#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem111#1, main_#t~mem113#1, main_#t~post114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~post91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~post124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem131#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~ite134#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post5#1, main_#t~mem139#1, main_#t~mem140#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~ite142#1.base, main_#t~ite142#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~short147#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem163#1.base, main_#t~mem163#1.offset, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1, main_#t~post174#1, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem184#1, main_#t~post185#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite144#1.base, main_#t~ite144#1.offset, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0; 2684#L750-3 [2022-11-16 11:22:43,489 INFO L750 eck$LassoCheckResult]: Loop: 2684#L750-3 assume !!(main_~i~0#1 < 10);call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset; 2725#L752 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 2726#L752-2 call write~int(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4); 2662#L757-121 havoc main_~_ha_hashv~0#1; 2663#L757-49 goto; 2712#L757-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 2605#L757-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 2606#L757-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch19#1 := 11 == main_~_hj_k~0#1; 2671#L757-10 assume !main_#t~switch19#1; 2752#L757-12 main_#t~switch19#1 := main_#t~switch19#1 || 10 == main_~_hj_k~0#1; 2653#L757-13 assume !main_#t~switch19#1; 2603#L757-15 main_#t~switch19#1 := main_#t~switch19#1 || 9 == main_~_hj_k~0#1; 2604#L757-16 assume !main_#t~switch19#1; 2744#L757-18 main_#t~switch19#1 := main_#t~switch19#1 || 8 == main_~_hj_k~0#1; 2729#L757-19 assume !main_#t~switch19#1; 2641#L757-21 main_#t~switch19#1 := main_#t~switch19#1 || 7 == main_~_hj_k~0#1; 2642#L757-22 assume !main_#t~switch19#1; 2710#L757-24 main_#t~switch19#1 := main_#t~switch19#1 || 6 == main_~_hj_k~0#1; 2675#L757-25 assume !main_#t~switch19#1; 2676#L757-27 main_#t~switch19#1 := main_#t~switch19#1 || 5 == main_~_hj_k~0#1; 2751#L757-28 assume !main_#t~switch19#1; 2749#L757-30 main_#t~switch19#1 := main_#t~switch19#1 || 4 == main_~_hj_k~0#1; 2748#L757-31 assume main_#t~switch19#1;call main_#t~mem27#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem27#1 % 256);havoc main_#t~mem27#1; 2617#L757-33 main_#t~switch19#1 := main_#t~switch19#1 || 3 == main_~_hj_k~0#1; 2618#L757-34 assume main_#t~switch19#1;call main_#t~mem28#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem28#1 % 256);havoc main_#t~mem28#1; 2708#L757-36 main_#t~switch19#1 := main_#t~switch19#1 || 2 == main_~_hj_k~0#1; 2687#L757-37 assume main_#t~switch19#1;call main_#t~mem29#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem29#1 % 256);havoc main_#t~mem29#1; 2688#L757-39 main_#t~switch19#1 := main_#t~switch19#1 || 1 == main_~_hj_k~0#1; 2645#L757-40 assume main_#t~switch19#1;call main_#t~mem30#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem30#1 % 256;havoc main_#t~mem30#1; 2626#L757-42 havoc main_#t~switch19#1; 2627#L757-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 2682#L757-44 goto; 2736#L757-46 goto; 2737#L757-48 goto; 2706#L757-119 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 2707#L757-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem48#1.base, main_#t~mem48#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem48#1.base, main_#t~mem48#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem48#1.base, main_#t~mem48#1.offset; 2741#L757-67 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem49#1.base, main_#t~mem49#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem50#1.base, main_#t~mem50#1.offset := read~$Pointer$(main_#t~mem49#1.base, 16 + main_#t~mem49#1.offset, 4);call main_#t~mem51#1.base, main_#t~mem51#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem52#1 := read~int(main_#t~mem51#1.base, 20 + main_#t~mem51#1.offset, 4);call write~$Pointer$(main_#t~mem50#1.base, main_#t~mem50#1.offset - main_#t~mem52#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem49#1.base, main_#t~mem49#1.offset;havoc main_#t~mem50#1.base, main_#t~mem50#1.offset;havoc main_#t~mem51#1.base, main_#t~mem51#1.offset;havoc main_#t~mem52#1;call main_#t~mem53#1.base, main_#t~mem53#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem54#1.base, main_#t~mem54#1.offset := read~$Pointer$(main_#t~mem53#1.base, 16 + main_#t~mem53#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem54#1.base, 8 + main_#t~mem54#1.offset, 4);havoc main_#t~mem53#1.base, main_#t~mem53#1.offset;havoc main_#t~mem54#1.base, main_#t~mem54#1.offset;call main_#t~mem55#1.base, main_#t~mem55#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem55#1.base, 16 + main_#t~mem55#1.offset, 4);havoc main_#t~mem55#1.base, main_#t~mem55#1.offset; 2742#L757-66 goto; 2648#L757-117 havoc main_~_ha_bkt~0#1;call main_#t~mem56#1.base, main_#t~mem56#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem57#1 := read~int(main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);main_#t~post58#1 := main_#t~mem57#1;call write~int(1 + main_#t~post58#1, main_#t~mem56#1.base, 12 + main_#t~mem56#1.offset, 4);havoc main_#t~mem56#1.base, main_#t~mem56#1.offset;havoc main_#t~mem57#1;havoc main_#t~post58#1; 2651#L757-71 call main_#t~mem59#1.base, main_#t~mem59#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem60#1 := read~int(main_#t~mem59#1.base, 4 + main_#t~mem59#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem60#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem60#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem60#1 - 1)));havoc main_#t~mem59#1.base, main_#t~mem59#1.offset;havoc main_#t~mem60#1; 2711#L757-70 goto; 2724#L757-115 call main_#t~mem61#1.base, main_#t~mem61#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem62#1.base, main_#t~mem62#1.offset := read~$Pointer$(main_#t~mem61#1.base, main_#t~mem61#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem62#1.base, main_#t~mem62#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem61#1.base, main_#t~mem61#1.offset;havoc main_#t~mem62#1.base, main_#t~mem62#1.offset;call main_#t~mem63#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post64#1 := main_#t~mem63#1;call write~int(1 + main_#t~post64#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem63#1;havoc main_#t~post64#1;call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 2755#L757-73 assume main_#t~mem66#1.base != 0 || main_#t~mem66#1.offset != 0;havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem67#1.base, 12 + main_#t~mem67#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset; 2668#L757-75 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem69#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem68#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short72#1 := main_#t~mem69#1 % 4294967296 >= 10 * (1 + main_#t~mem68#1) % 4294967296; 2669#L757-76 assume main_#t~short72#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem71#1 := read~int(main_#t~mem70#1.base, 36 + main_#t~mem70#1.offset, 4);main_#t~short72#1 := 0 == main_#t~mem71#1 % 4294967296; 2745#L757-78 assume !main_#t~short72#1;havoc main_#t~mem69#1;havoc main_#t~mem68#1;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;havoc main_#t~short72#1; 2691#L757-114 goto; 2692#L757-116 goto; 2727#L757-118 goto; 2728#L757-120 goto; 2700#L750-2 main_#t~post5#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2684#L750-3 [2022-11-16 11:22:43,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:43,490 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 6 times [2022-11-16 11:22:43,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:43,490 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965288434] [2022-11-16 11:22:43,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:43,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:43,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:43,526 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:22:43,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:22:43,556 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:22:43,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:22:43,557 INFO L85 PathProgramCache]: Analyzing trace with hash -1082263419, now seen corresponding path program 1 times [2022-11-16 11:22:43,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:22:43,558 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451475861] [2022-11-16 11:22:43,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:43,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:22:43,686 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:22:43,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1201870333] [2022-11-16 11:22:43,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:22:43,687 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:22:43,687 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:22:43,691 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:22:43,724 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-11-16 11:26:50,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:50,162 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:26:56,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:26:56,158 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:26:56,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:26:56,162 INFO L85 PathProgramCache]: Analyzing trace with hash -1692418973, now seen corresponding path program 1 times [2022-11-16 11:26:56,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:26:56,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885777894] [2022-11-16 11:26:56,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:56,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:26:56,360 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:26:56,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2140221884] [2022-11-16 11:26:56,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:26:56,361 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:26:56,361 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:26:56,365 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:26:56,387 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ef0d133d-7e61-43ae-a9bf-8297462f8c61/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-11-16 11:26:57,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:26:57,645 INFO L263 TraceCheckSpWp]: Trace formula consists of 1814 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-16 11:26:57,648 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:26:57,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 11:26:57,950 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:26:57,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:26:57,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1885777894] [2022-11-16 11:26:57,951 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:26:57,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2140221884] [2022-11-16 11:26:57,951 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2140221884] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:26:57,952 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:26:57,952 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:26:57,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707449812] [2022-11-16 11:26:57,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton