./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ff5be3465740cb655882704e7eef418c95d0bbd56a2060e741c7d3e996e58af7 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 12:39:56,269 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 12:39:56,271 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 12:39:56,295 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 12:39:56,295 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 12:39:56,296 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 12:39:56,298 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 12:39:56,300 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 12:39:56,301 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 12:39:56,302 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 12:39:56,303 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 12:39:56,305 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 12:39:56,305 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 12:39:56,306 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 12:39:56,308 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 12:39:56,309 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 12:39:56,310 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 12:39:56,311 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 12:39:56,313 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 12:39:56,315 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 12:39:56,316 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 12:39:56,318 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 12:39:56,319 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 12:39:56,320 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 12:39:56,324 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 12:39:56,325 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 12:39:56,325 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 12:39:56,326 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 12:39:56,326 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 12:39:56,327 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 12:39:56,328 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 12:39:56,329 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 12:39:56,329 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 12:39:56,330 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 12:39:56,331 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 12:39:56,332 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 12:39:56,333 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 12:39:56,333 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 12:39:56,333 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 12:39:56,334 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 12:39:56,335 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 12:39:56,336 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-16 12:39:56,361 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 12:39:56,361 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 12:39:56,362 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 12:39:56,362 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 12:39:56,363 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 12:39:56,364 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 12:39:56,364 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 12:39:56,364 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-16 12:39:56,364 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-16 12:39:56,365 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-16 12:39:56,365 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-16 12:39:56,365 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-16 12:39:56,366 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-16 12:39:56,366 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 12:39:56,366 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 12:39:56,366 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-16 12:39:56,367 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 12:39:56,367 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 12:39:56,367 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 12:39:56,367 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-16 12:39:56,368 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-16 12:39:56,368 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-16 12:39:56,368 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 12:39:56,368 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 12:39:56,369 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-16 12:39:56,369 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 12:39:56,369 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-16 12:39:56,370 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 12:39:56,370 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 12:39:56,370 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 12:39:56,370 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 12:39:56,371 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-16 12:39:56,372 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ff5be3465740cb655882704e7eef418c95d0bbd56a2060e741c7d3e996e58af7 [2022-11-16 12:39:56,621 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 12:39:56,648 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 12:39:56,652 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 12:39:56,655 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 12:39:56,656 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 12:39:56,657 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i [2022-11-16 12:39:56,763 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/data/2711cb21f/9aa95fd40cbf4a62b6bf39b52f34b50e/FLAG9d024898c [2022-11-16 12:39:57,446 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 12:39:57,447 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i [2022-11-16 12:39:57,469 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/data/2711cb21f/9aa95fd40cbf4a62b6bf39b52f34b50e/FLAG9d024898c [2022-11-16 12:39:57,638 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/data/2711cb21f/9aa95fd40cbf4a62b6bf39b52f34b50e [2022-11-16 12:39:57,644 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 12:39:57,647 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 12:39:57,649 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 12:39:57,650 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 12:39:57,655 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 12:39:57,656 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:39:57" (1/1) ... [2022-11-16 12:39:57,658 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@36430012 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:57, skipping insertion in model container [2022-11-16 12:39:57,661 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 12:39:57" (1/1) ... [2022-11-16 12:39:57,670 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 12:39:57,754 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 12:39:58,423 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[44118,44131] [2022-11-16 12:39:58,435 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[44660,44673] [2022-11-16 12:39:58,586 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[56247,56260] [2022-11-16 12:39:58,587 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[56368,56381] [2022-11-16 12:39:58,593 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:39:58,622 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 12:39:58,690 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[44118,44131] [2022-11-16 12:39:58,698 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[44660,44673] [2022-11-16 12:39:58,818 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[56247,56260] [2022-11-16 12:39:58,819 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i[56368,56381] [2022-11-16 12:39:58,833 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 12:39:58,887 INFO L208 MainTranslator]: Completed translation [2022-11-16 12:39:58,888 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58 WrapperNode [2022-11-16 12:39:58,888 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 12:39:58,890 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 12:39:58,890 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 12:39:58,890 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 12:39:58,898 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:58,932 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,016 INFO L138 Inliner]: procedures = 282, calls = 294, calls flagged for inlining = 19, calls inlined = 21, statements flattened = 1139 [2022-11-16 12:39:59,017 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 12:39:59,018 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 12:39:59,018 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 12:39:59,018 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 12:39:59,029 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,029 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,045 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,045 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,132 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,155 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,175 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,179 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,203 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 12:39:59,204 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 12:39:59,204 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 12:39:59,204 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 12:39:59,205 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (1/1) ... [2022-11-16 12:39:59,213 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-16 12:39:59,228 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:39:59,244 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-16 12:39:59,251 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-16 12:39:59,285 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-11-16 12:39:59,289 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-11-16 12:39:59,290 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-16 12:39:59,290 INFO L130 BoogieDeclarations]: Found specification of procedure memcmp [2022-11-16 12:39:59,290 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-11-16 12:39:59,290 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-16 12:39:59,291 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-16 12:39:59,291 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-16 12:39:59,291 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-11-16 12:39:59,291 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 12:39:59,291 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-11-16 12:39:59,292 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 12:39:59,293 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 12:39:59,293 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 12:39:59,611 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 12:39:59,613 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 12:39:59,618 WARN L816 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-11-16 12:40:01,794 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 12:40:01,813 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 12:40:01,813 INFO L300 CfgBuilder]: Removed 63 assume(true) statements. [2022-11-16 12:40:01,816 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:40:01 BoogieIcfgContainer [2022-11-16 12:40:01,817 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 12:40:01,820 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-16 12:40:01,820 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-16 12:40:01,825 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-16 12:40:01,826 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:40:01,827 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.11 12:39:57" (1/3) ... [2022-11-16 12:40:01,829 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5d113258 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:40:01, skipping insertion in model container [2022-11-16 12:40:01,829 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:40:01,830 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 12:39:58" (2/3) ... [2022-11-16 12:40:01,832 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5d113258 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.11 12:40:01, skipping insertion in model container [2022-11-16 12:40:01,832 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-16 12:40:01,832 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 12:40:01" (3/3) ... [2022-11-16 12:40:01,834 INFO L332 chiAutomizerObserver]: Analyzing ICFG uthash_SAX_test6-1.i [2022-11-16 12:40:01,925 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-16 12:40:01,925 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-16 12:40:01,925 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-16 12:40:01,925 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-16 12:40:01,925 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-16 12:40:01,926 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-16 12:40:01,926 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-16 12:40:01,926 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-16 12:40:01,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 220 states, 215 states have (on average 1.627906976744186) internal successors, (350), 215 states have internal predecessors, (350), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:40:01,988 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 202 [2022-11-16 12:40:01,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:40:01,992 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:40:02,002 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:40:02,003 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:40:02,003 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-16 12:40:02,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 220 states, 215 states have (on average 1.627906976744186) internal successors, (350), 215 states have internal predecessors, (350), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:40:02,017 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 202 [2022-11-16 12:40:02,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:40:02,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:40:02,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:40:02,019 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:40:02,030 INFO L748 eck$LassoCheckResult]: Stem: 213#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~alt_malloc_balance~0 := 0;~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 138#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~pre140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1, main_#t~post145#1, main_#t~mem149#1, main_#t~mem147#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem148#1, main_#t~mem150#1, main_#t~post151#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1, main_#t~post163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~ite173#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem181#1, main_#t~mem180#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem185#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem189#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~switch192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1, main_#t~mem214#1, main_#t~mem215#1, main_#t~short216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~ret218#1, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~short225#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem250#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem249#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem177#1, main_#t~post178#1, main_#t~mem179#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 9#L989-4true [2022-11-16 12:40:02,031 INFO L750 eck$LassoCheckResult]: Loop: 9#L989-4true call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 4#L989-1true assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 89#L979true main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 10#L991true assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false; 83#L991-2true call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 196#L996-115true assume !true; 200#L989-3true call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 9#L989-4true [2022-11-16 12:40:02,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:40:02,039 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 1 times [2022-11-16 12:40:02,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:40:02,051 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234616535] [2022-11-16 12:40:02,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:02,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:40:02,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:40:02,201 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:40:02,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:40:02,260 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:40:02,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:40:02,264 INFO L85 PathProgramCache]: Analyzing trace with hash -1530816298, now seen corresponding path program 1 times [2022-11-16 12:40:02,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:40:02,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909070737] [2022-11-16 12:40:02,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:02,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:40:02,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:40:02,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:40:02,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1909070737] [2022-11-16 12:40:02,329 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-11-16 12:40:02,329 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [842359178] [2022-11-16 12:40:02,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:02,330 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:40:02,330 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:40:02,351 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:40:02,383 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-16 12:40:02,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:40:02,555 INFO L263 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 1 conjunts are in the unsatisfiable core [2022-11-16 12:40:02,557 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:40:02,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:40:02,582 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:40:02,583 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [842359178] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:40:02,583 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:40:02,584 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 12:40:02,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198510762] [2022-11-16 12:40:02,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:40:02,591 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:40:02,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:40:02,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-16 12:40:02,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 12:40:02,650 INFO L87 Difference]: Start difference. First operand has 220 states, 215 states have (on average 1.627906976744186) internal successors, (350), 215 states have internal predecessors, (350), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:40:02,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:40:02,697 INFO L93 Difference]: Finished difference Result 216 states and 273 transitions. [2022-11-16 12:40:02,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 216 states and 273 transitions. [2022-11-16 12:40:02,719 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 197 [2022-11-16 12:40:02,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 216 states to 204 states and 261 transitions. [2022-11-16 12:40:02,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204 [2022-11-16 12:40:02,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204 [2022-11-16 12:40:02,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204 states and 261 transitions. [2022-11-16 12:40:02,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:40:02,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 204 states and 261 transitions. [2022-11-16 12:40:02,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states and 261 transitions. [2022-11-16 12:40:02,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 204. [2022-11-16 12:40:02,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 204 states, 200 states have (on average 1.275) internal successors, (255), 199 states have internal predecessors, (255), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:40:02,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 261 transitions. [2022-11-16 12:40:02,811 INFO L240 hiAutomatonCegarLoop]: Abstraction has 204 states and 261 transitions. [2022-11-16 12:40:02,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-16 12:40:02,825 INFO L428 stractBuchiCegarLoop]: Abstraction has 204 states and 261 transitions. [2022-11-16 12:40:02,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-16 12:40:02,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 261 transitions. [2022-11-16 12:40:02,831 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 197 [2022-11-16 12:40:02,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:40:02,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:40:02,836 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:40:02,837 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:40:02,837 INFO L748 eck$LassoCheckResult]: Stem: 665#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~alt_malloc_balance~0 := 0;~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 646#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~pre140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1, main_#t~post145#1, main_#t~mem149#1, main_#t~mem147#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem148#1, main_#t~mem150#1, main_#t~post151#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1, main_#t~post163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~ite173#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem181#1, main_#t~mem180#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem185#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem189#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~switch192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1, main_#t~mem214#1, main_#t~mem215#1, main_#t~short216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~ret218#1, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~short225#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem250#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem249#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem177#1, main_#t~post178#1, main_#t~mem179#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 475#L989-4 [2022-11-16 12:40:02,839 INFO L750 eck$LassoCheckResult]: Loop: 475#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 466#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 468#L979 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 476#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 477#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 592#L996-115 havoc main_~_ha_hashv~0#1; 635#L996-49 goto; 636#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 470#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 495#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 660#L996-10 assume main_#t~switch59#1;call main_#t~mem60#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem60#1 % 256);havoc main_#t~mem60#1; 664#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 567#L996-13 assume main_#t~switch59#1;call main_#t~mem61#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem61#1 % 256);havoc main_#t~mem61#1; 568#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 661#L996-16 assume main_#t~switch59#1;call main_#t~mem62#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem62#1 % 256);havoc main_#t~mem62#1; 662#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 653#L996-19 assume main_#t~switch59#1;call main_#t~mem63#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem63#1 % 256);havoc main_#t~mem63#1; 652#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 632#L996-22 assume main_#t~switch59#1;call main_#t~mem64#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem64#1 % 256);havoc main_#t~mem64#1; 633#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 649#L996-25 assume main_#t~switch59#1;call main_#t~mem65#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem65#1 % 256);havoc main_#t~mem65#1; 626#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 471#L996-28 assume !main_#t~switch59#1; 472#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 600#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 618#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 587#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 588#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 549#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 550#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 571#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 601#L996-42 havoc main_#t~switch59#1; 528#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 529#L996-44 goto; 613#L996-46 goto; 627#L996-48 goto; 515#L996-113 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 516#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 577#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 578#L996-62 goto; 531#L996-111 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 622#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem98#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1)));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 623#L996-66 goto; 656#L996-109 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 650#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 496#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 497#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 553#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 519#L996-108 goto; 513#L996-110 goto; 514#L996-112 goto; 565#L996-114 goto; 566#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 475#L989-4 [2022-11-16 12:40:02,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:40:02,840 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 2 times [2022-11-16 12:40:02,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:40:02,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [283382102] [2022-11-16 12:40:02,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:02,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:40:02,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:40:02,880 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:40:02,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:40:02,906 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:40:02,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:40:02,907 INFO L85 PathProgramCache]: Analyzing trace with hash 1735500791, now seen corresponding path program 1 times [2022-11-16 12:40:02,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:40:02,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215792893] [2022-11-16 12:40:02,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:02,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:40:03,146 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:40:03,147 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [951674854] [2022-11-16 12:40:03,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:03,147 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:40:03,147 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:40:03,152 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:40:03,179 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-16 12:40:04,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:40:04,164 INFO L263 TraceCheckSpWp]: Trace formula consists of 1858 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 12:40:04,168 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:40:04,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:40:04,240 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:40:04,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:40:04,241 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215792893] [2022-11-16 12:40:04,241 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 12:40:04,241 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [951674854] [2022-11-16 12:40:04,242 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [951674854] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:40:04,242 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:40:04,242 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:40:04,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242213652] [2022-11-16 12:40:04,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:40:04,243 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:40:04,243 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:40:04,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-16 12:40:04,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-16 12:40:04,245 INFO L87 Difference]: Start difference. First operand 204 states and 261 transitions. cyclomatic complexity: 60 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:40:04,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:40:04,491 INFO L93 Difference]: Finished difference Result 225 states and 282 transitions. [2022-11-16 12:40:04,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 225 states and 282 transitions. [2022-11-16 12:40:04,501 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 218 [2022-11-16 12:40:04,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 225 states to 225 states and 282 transitions. [2022-11-16 12:40:04,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2022-11-16 12:40:04,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2022-11-16 12:40:04,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 282 transitions. [2022-11-16 12:40:04,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:40:04,507 INFO L218 hiAutomatonCegarLoop]: Abstraction has 225 states and 282 transitions. [2022-11-16 12:40:04,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 282 transitions. [2022-11-16 12:40:04,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 224. [2022-11-16 12:40:04,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224 states, 220 states have (on average 1.25) internal successors, (275), 219 states have internal predecessors, (275), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:40:04,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 281 transitions. [2022-11-16 12:40:04,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224 states and 281 transitions. [2022-11-16 12:40:04,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-16 12:40:04,529 INFO L428 stractBuchiCegarLoop]: Abstraction has 224 states and 281 transitions. [2022-11-16 12:40:04,529 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-16 12:40:04,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224 states and 281 transitions. [2022-11-16 12:40:04,532 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 217 [2022-11-16 12:40:04,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:40:04,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:40:04,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:40:04,534 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:40:04,534 INFO L748 eck$LassoCheckResult]: Stem: 1261#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~alt_malloc_balance~0 := 0;~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 1238#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~pre140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1, main_#t~post145#1, main_#t~mem149#1, main_#t~mem147#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem148#1, main_#t~mem150#1, main_#t~post151#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1, main_#t~post163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~ite173#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem181#1, main_#t~mem180#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem185#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem189#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~switch192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1, main_#t~mem214#1, main_#t~mem215#1, main_#t~short216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~ret218#1, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~short225#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem250#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem249#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem177#1, main_#t~post178#1, main_#t~mem179#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1066#L989-4 [2022-11-16 12:40:04,535 INFO L750 eck$LassoCheckResult]: Loop: 1066#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1057#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 1059#L979 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 1067#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1068#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 1183#L996-115 havoc main_~_ha_hashv~0#1; 1227#L996-49 goto; 1228#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1061#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1088#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 1252#L996-10 assume main_#t~switch59#1;call main_#t~mem60#1 := read~int(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem60#1 % 256);havoc main_#t~mem60#1; 1257#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 1158#L996-13 assume main_#t~switch59#1;call main_#t~mem61#1 := read~int(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem61#1 % 256);havoc main_#t~mem61#1; 1159#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 1254#L996-16 assume main_#t~switch59#1;call main_#t~mem62#1 := read~int(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem62#1 % 256);havoc main_#t~mem62#1; 1255#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 1245#L996-19 assume main_#t~switch59#1;call main_#t~mem63#1 := read~int(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem63#1 % 256);havoc main_#t~mem63#1; 1244#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 1224#L996-22 assume main_#t~switch59#1;call main_#t~mem64#1 := read~int(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem64#1 % 256);havoc main_#t~mem64#1; 1225#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 1241#L996-25 assume main_#t~switch59#1;call main_#t~mem65#1 := read~int(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem65#1 % 256);havoc main_#t~mem65#1; 1218#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 1062#L996-28 assume main_#t~switch59#1;call main_#t~mem66#1 := read~int(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + main_#t~mem66#1 % 256;havoc main_#t~mem66#1; 1063#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 1253#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 1210#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 1178#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 1179#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 1140#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 1141#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 1162#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 1193#L996-42 havoc main_#t~switch59#1; 1119#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1120#L996-44 goto; 1205#L996-46 goto; 1219#L996-48 goto; 1106#L996-113 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1107#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 1169#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 1170#L996-62 goto; 1122#L996-111 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 1214#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem98#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1)));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 1215#L996-66 goto; 1249#L996-109 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1242#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 1089#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 1090#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 1144#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 1110#L996-108 goto; 1104#L996-110 goto; 1105#L996-112 goto; 1156#L996-114 goto; 1157#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 1066#L989-4 [2022-11-16 12:40:04,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:40:04,537 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 3 times [2022-11-16 12:40:04,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:40:04,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111702756] [2022-11-16 12:40:04,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:04,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:40:04,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:40:04,574 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:40:04,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:40:04,620 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:40:04,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:40:04,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1033900917, now seen corresponding path program 1 times [2022-11-16 12:40:04,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:40:04,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450017051] [2022-11-16 12:40:04,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:04,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:40:04,863 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:40:04,867 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1722468585] [2022-11-16 12:40:04,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:04,868 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:40:04,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:40:04,873 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:40:04,891 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-16 12:40:05,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:40:05,960 INFO L263 TraceCheckSpWp]: Trace formula consists of 1864 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 12:40:05,963 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:40:05,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:40:05,994 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:40:05,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:40:05,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450017051] [2022-11-16 12:40:05,995 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 12:40:05,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1722468585] [2022-11-16 12:40:05,995 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1722468585] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:40:05,996 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:40:05,996 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 12:40:05,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891610082] [2022-11-16 12:40:05,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 12:40:05,997 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-16 12:40:05,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 12:40:05,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 12:40:05,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 12:40:05,998 INFO L87 Difference]: Start difference. First operand 224 states and 281 transitions. cyclomatic complexity: 60 Second operand has 4 states, 4 states have (on average 13.25) internal successors, (53), 4 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-16 12:40:06,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 12:40:06,118 INFO L93 Difference]: Finished difference Result 308 states and 386 transitions. [2022-11-16 12:40:06,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 386 transitions. [2022-11-16 12:40:06,121 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 292 [2022-11-16 12:40:06,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 308 states and 386 transitions. [2022-11-16 12:40:06,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2022-11-16 12:40:06,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2022-11-16 12:40:06,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 386 transitions. [2022-11-16 12:40:06,127 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-16 12:40:06,127 INFO L218 hiAutomatonCegarLoop]: Abstraction has 308 states and 386 transitions. [2022-11-16 12:40:06,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 386 transitions. [2022-11-16 12:40:06,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 210. [2022-11-16 12:40:06,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 210 states, 206 states have (on average 1.233009708737864) internal successors, (254), 205 states have internal predecessors, (254), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 12:40:06,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 260 transitions. [2022-11-16 12:40:06,137 INFO L240 hiAutomatonCegarLoop]: Abstraction has 210 states and 260 transitions. [2022-11-16 12:40:06,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 12:40:06,139 INFO L428 stractBuchiCegarLoop]: Abstraction has 210 states and 260 transitions. [2022-11-16 12:40:06,139 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-16 12:40:06,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 210 states and 260 transitions. [2022-11-16 12:40:06,141 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 203 [2022-11-16 12:40:06,141 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-16 12:40:06,141 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-16 12:40:06,142 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-16 12:40:06,142 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 12:40:06,142 INFO L748 eck$LassoCheckResult]: Stem: 1956#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~alt_malloc_balance~0 := 0;~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call #Ultimate.allocInit(40, 3);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#alt_malloc_sizes~0.base);~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0; 1935#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset, main_#t~mem44#1, main_#t~mem45#1, main_#t~mem46#1, main_#t~mem48#1, main_#t~mem47#1, main_#t~mem49#1, main_#t~mem50#1, main_#t~mem52#1, main_#t~mem51#1, main_#t~mem53#1, main_#t~mem54#1, main_#t~mem56#1, main_#t~mem55#1, main_#t~mem57#1, main_#t~mem58#1, main_#t~switch59#1, main_#t~mem60#1, main_#t~mem61#1, main_#t~mem62#1, main_#t~mem63#1, main_#t~mem64#1, main_#t~mem65#1, main_#t~mem66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret71#1.base, main_#t~ret71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~ret79#1.base, main_#t~ret79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~post96#1, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~post102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem107#1, main_#t~mem106#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~short110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~ret113#1.base, main_#t~ret113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem122#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem126#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~pre140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1, main_#t~post145#1, main_#t~mem149#1, main_#t~mem147#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem148#1, main_#t~mem150#1, main_#t~post151#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~post128#1, main_#t~mem129#1.base, main_#t~mem129#1.offset, main_#t~mem130#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1, main_#t~post163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem170#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1, main_#t~ite173#1, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~#_he_new_buckets~0#1.base, main_~#_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem40#1, main_#t~post41#1, main_#t~mem42#1, main_#t~mem181#1, main_#t~mem180#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem185#1, main_#t~mem184#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem189#1, main_#t~mem188#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~switch192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~mem197#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem200#1, main_#t~mem201#1, main_#t~mem202#1, main_#t~mem203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1, main_#t~mem214#1, main_#t~mem215#1, main_#t~short216#1, main_#t~mem217#1.base, main_#t~mem217#1.offset, main_#t~ret218#1, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~short225#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem250#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem249#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem177#1, main_#t~post178#1, main_#t~mem179#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1763#L989-4 [2022-11-16 12:40:06,143 INFO L750 eck$LassoCheckResult]: Loop: 1763#L989-4 call main_#t~mem42#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4); 1754#L989-1 assume !!(main_#t~mem42#1 < 10);havoc main_#t~mem42#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; 1756#L979 main_#t~ret43#1.base, main_#t~ret43#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret43#1.base, main_#t~ret43#1.offset;havoc main_#t~ret43#1.base, main_#t~ret43#1.offset; 1764#L991 assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0); 1765#L991-2 call main_#t~mem44#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem44#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem44#1;call main_#t~mem45#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem46#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int(main_#t~mem45#1 * main_#t~mem46#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem45#1;havoc main_#t~mem46#1; 1881#L996-115 havoc main_~_ha_hashv~0#1; 1924#L996-49 goto; 1925#L996-47 havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4; 1758#L996-8 assume !(main_~_hj_k~0#1 % 4294967296 >= 12); 1787#L996-9 main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch59#1 := 11 == main_~_hj_k~0#1; 1950#L996-10 assume !main_#t~switch59#1; 1955#L996-12 main_#t~switch59#1 := main_#t~switch59#1 || 10 == main_~_hj_k~0#1; 1855#L996-13 assume !main_#t~switch59#1; 1856#L996-15 main_#t~switch59#1 := main_#t~switch59#1 || 9 == main_~_hj_k~0#1; 1952#L996-16 assume !main_#t~switch59#1; 1953#L996-18 main_#t~switch59#1 := main_#t~switch59#1 || 8 == main_~_hj_k~0#1; 1942#L996-19 assume !main_#t~switch59#1; 1941#L996-21 main_#t~switch59#1 := main_#t~switch59#1 || 7 == main_~_hj_k~0#1; 1921#L996-22 assume !main_#t~switch59#1; 1922#L996-24 main_#t~switch59#1 := main_#t~switch59#1 || 6 == main_~_hj_k~0#1; 1938#L996-25 assume !main_#t~switch59#1; 1915#L996-27 main_#t~switch59#1 := main_#t~switch59#1 || 5 == main_~_hj_k~0#1; 1759#L996-28 assume !main_#t~switch59#1; 1760#L996-30 main_#t~switch59#1 := main_#t~switch59#1 || 4 == main_~_hj_k~0#1; 1889#L996-31 assume main_#t~switch59#1;call main_#t~mem67#1 := read~int(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem67#1 % 256);havoc main_#t~mem67#1; 1907#L996-33 main_#t~switch59#1 := main_#t~switch59#1 || 3 == main_~_hj_k~0#1; 1876#L996-34 assume main_#t~switch59#1;call main_#t~mem68#1 := read~int(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem68#1 % 256);havoc main_#t~mem68#1; 1877#L996-36 main_#t~switch59#1 := main_#t~switch59#1 || 2 == main_~_hj_k~0#1; 1837#L996-37 assume main_#t~switch59#1;call main_#t~mem69#1 := read~int(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem69#1 % 256);havoc main_#t~mem69#1; 1838#L996-39 main_#t~switch59#1 := main_#t~switch59#1 || 1 == main_~_hj_k~0#1; 1944#L996-40 assume main_#t~switch59#1;call main_#t~mem70#1 := read~int(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + main_#t~mem70#1 % 256;havoc main_#t~mem70#1; 1890#L996-42 havoc main_#t~switch59#1; 1816#L996-45 main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8192 else (if 0 == main_~_ha_hashv~0#1 / 8192 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8192 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8192))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 256 * main_~_hj_i~0#1 else (if 0 == 256 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 256 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 256 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 8192 else (if 0 == main_~_hj_j~0#1 / 8192 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 8192 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 8192))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 4096 else (if 0 == main_~_ha_hashv~0#1 / 4096 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 4096 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 4096))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 65536 * main_~_hj_i~0#1 else (if 0 == 65536 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 65536 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 65536 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32 else (if 0 == main_~_hj_j~0#1 / 32 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32))));main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;main_~_hj_i~0#1 := (if 0 == main_~_hj_i~0#1 then main_~_ha_hashv~0#1 / 8 else (if 0 == main_~_ha_hashv~0#1 / 8 then main_~_hj_i~0#1 else (if main_~_hj_i~0#1 == main_~_ha_hashv~0#1 / 8 then 0 else ~bitwiseXor(main_~_hj_i~0#1, main_~_ha_hashv~0#1 / 8))));main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;main_~_hj_j~0#1 := (if 0 == main_~_hj_j~0#1 then 1024 * main_~_hj_i~0#1 else (if 0 == 1024 * main_~_hj_i~0#1 then main_~_hj_j~0#1 else (if main_~_hj_j~0#1 == 1024 * main_~_hj_i~0#1 then 0 else ~bitwiseXor(main_~_hj_j~0#1, 1024 * main_~_hj_i~0#1))));main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;main_~_ha_hashv~0#1 := (if 0 == main_~_ha_hashv~0#1 then main_~_hj_j~0#1 / 32768 else (if 0 == main_~_hj_j~0#1 / 32768 then main_~_ha_hashv~0#1 else (if main_~_ha_hashv~0#1 == main_~_hj_j~0#1 / 32768 then 0 else ~bitwiseXor(main_~_ha_hashv~0#1, main_~_hj_j~0#1 / 32768)))); 1817#L996-44 goto; 1904#L996-46 goto; 1916#L996-48 goto; 1803#L996-113 call write~int(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4); 1804#L996-51 assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_#t~mem86#1.base, main_#t~mem86#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset; 1867#L996-63 call write~$Pointer$(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$(main_#t~mem87#1.base, 16 + main_#t~mem87#1.offset, 4);call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem90#1 := read~int(main_#t~mem89#1.base, 20 + main_#t~mem89#1.offset, 4);call write~$Pointer$(main_#t~mem88#1.base, main_#t~mem88#1.offset - main_#t~mem90#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;call main_#t~mem91#1.base, main_#t~mem91#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$(main_#t~mem91#1.base, 16 + main_#t~mem91#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem92#1.base, 8 + main_#t~mem92#1.offset, 4);havoc main_#t~mem91#1.base, main_#t~mem91#1.offset;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;call main_#t~mem93#1.base, main_#t~mem93#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem93#1.base, 16 + main_#t~mem93#1.offset, 4);havoc main_#t~mem93#1.base, main_#t~mem93#1.offset; 1868#L996-62 goto; 1819#L996-111 havoc main_~_ha_bkt~0#1;call main_#t~mem94#1.base, main_#t~mem94#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem95#1 := read~int(main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);main_#t~post96#1 := main_#t~mem95#1;call write~int(1 + main_#t~post96#1, main_#t~mem94#1.base, 12 + main_#t~mem94#1.offset, 4);havoc main_#t~mem94#1.base, main_#t~mem94#1.offset;havoc main_#t~mem95#1;havoc main_#t~post96#1; 1911#L996-67 call main_#t~mem97#1.base, main_#t~mem97#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem98#1 := read~int(main_#t~mem97#1.base, 4 + main_#t~mem97#1.offset, 4);main_~_ha_bkt~0#1 := (if 0 == main_~_ha_hashv~0#1 || 0 == main_#t~mem98#1 - 1 then 0 else (if main_~_ha_hashv~0#1 == main_#t~mem98#1 - 1 then main_~_ha_hashv~0#1 else ~bitwiseAnd(main_~_ha_hashv~0#1, main_#t~mem98#1 - 1)));havoc main_#t~mem97#1.base, main_#t~mem97#1.offset;havoc main_#t~mem98#1; 1912#L996-66 goto; 1945#L996-109 call main_#t~mem99#1.base, main_#t~mem99#1.offset := read~$Pointer$(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem100#1.base, main_#t~mem100#1.offset := read~$Pointer$(main_#t~mem99#1.base, main_#t~mem99#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem100#1.base, main_#t~mem100#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem99#1.base, main_#t~mem99#1.offset;havoc main_#t~mem100#1.base, main_#t~mem100#1.offset;call main_#t~mem101#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post102#1 := main_#t~mem101#1;call write~int(1 + main_#t~post102#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem101#1;havoc main_#t~post102#1;call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_#t~mem103#1.base, main_#t~mem103#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;call write~$Pointer$(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4); 1939#L996-69 assume main_#t~mem104#1.base != 0 || main_#t~mem104#1.offset != 0;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem105#1.base, 12 + main_#t~mem105#1.offset, 4);havoc main_#t~mem105#1.base, main_#t~mem105#1.offset; 1782#L996-71 call write~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem107#1 := read~int(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem106#1 := read~int(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short110#1 := main_#t~mem107#1 % 4294967296 >= 10 * (1 + main_#t~mem106#1) % 4294967296; 1783#L996-72 assume main_#t~short110#1;call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem109#1 := read~int(main_#t~mem108#1.base, 36 + main_#t~mem108#1.offset, 4);main_#t~short110#1 := 0 == main_#t~mem109#1 % 4294967296; 1841#L996-74 assume !main_#t~short110#1;havoc main_#t~mem107#1;havoc main_#t~mem106#1;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;havoc main_#t~mem109#1;havoc main_#t~short110#1; 1805#L996-108 goto; 1801#L996-110 goto; 1802#L996-112 goto; 1851#L996-114 goto; 1852#L989-3 call main_#t~mem40#1 := read~int(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post41#1 := main_#t~mem40#1;call write~int(1 + main_#t~post41#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem40#1;havoc main_#t~post41#1; 1763#L989-4 [2022-11-16 12:40:06,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:40:06,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1251, now seen corresponding path program 4 times [2022-11-16 12:40:06,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:40:06,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060152463] [2022-11-16 12:40:06,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:06,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:40:06,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:40:06,166 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:40:06,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:40:06,187 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:40:06,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:40:06,188 INFO L85 PathProgramCache]: Analyzing trace with hash -840473469, now seen corresponding path program 1 times [2022-11-16 12:40:06,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:40:06,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745614067] [2022-11-16 12:40:06,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:06,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:40:06,347 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:40:06,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1852495571] [2022-11-16 12:40:06,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:40:06,350 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:40:06,350 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:40:06,354 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:40:06,376 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-16 12:45:51,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:45:51,508 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 12:46:08,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 12:46:08,593 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 12:46:08,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 12:46:08,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1210558689, now seen corresponding path program 1 times [2022-11-16 12:46:08,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 12:46:08,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144444304] [2022-11-16 12:46:08,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:46:08,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 12:46:08,815 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 12:46:08,821 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [120311717] [2022-11-16 12:46:08,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 12:46:08,821 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 12:46:08,822 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 12:46:08,827 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 12:46:08,857 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3f0a9251-6f58-44f5-80fe-4b9e529bedd1/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-16 12:46:10,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 12:46:10,171 INFO L263 TraceCheckSpWp]: Trace formula consists of 1889 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-16 12:46:10,175 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 12:46:10,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-16 12:46:10,427 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 12:46:10,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 12:46:10,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144444304] [2022-11-16 12:46:10,428 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 12:46:10,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [120311717] [2022-11-16 12:46:10,429 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [120311717] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 12:46:10,429 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 12:46:10,429 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 12:46:10,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191695261] [2022-11-16 12:46:10,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton