./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/aws-c-common/aws_priority_queue_clean_up_harness.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/config/AutomizerReach.xml -i ../../sv-benchmarks/c/aws-c-common/aws_priority_queue_clean_up_harness.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash efb3bc3d53d5de978717fadeb26804aec5f97721ade955fc2d1463ef24ff6010 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:39:00,288 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:39:00,291 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:39:00,317 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:39:00,318 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:39:00,319 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:39:00,321 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:39:00,323 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:39:00,326 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:39:00,327 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:39:00,328 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:39:00,330 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:39:00,330 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:39:00,332 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:39:00,333 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:39:00,335 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:39:00,336 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:39:00,337 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:39:00,339 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:39:00,342 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:39:00,344 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:39:00,346 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:39:00,347 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:39:00,349 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:39:00,354 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:39:00,354 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:39:00,355 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:39:00,356 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:39:00,356 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:39:00,358 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:39:00,358 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:39:00,359 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:39:00,360 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:39:00,362 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:39:00,363 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:39:00,363 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:39:00,364 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:39:00,365 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:39:00,365 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:39:00,366 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:39:00,367 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:39:00,369 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-11-16 11:39:00,399 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:39:00,400 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:39:00,400 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:39:00,401 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:39:00,401 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-16 11:39:00,402 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-16 11:39:00,403 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:39:00,403 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:39:00,403 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:39:00,404 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:39:00,404 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:39:00,404 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:39:00,405 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-16 11:39:00,405 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-16 11:39:00,405 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-16 11:39:00,406 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:39:00,406 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:39:00,406 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-16 11:39:00,407 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:39:00,407 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:39:00,407 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-16 11:39:00,408 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-16 11:39:00,408 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:39:00,412 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-16 11:39:00,412 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-16 11:39:00,412 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:39:00,413 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-16 11:39:00,413 INFO L138 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2022-11-16 11:39:00,413 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-11-16 11:39:00,413 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-16 11:39:00,414 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> efb3bc3d53d5de978717fadeb26804aec5f97721ade955fc2d1463ef24ff6010 [2022-11-16 11:39:00,818 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:39:00,854 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:39:00,858 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:39:00,862 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:39:00,863 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:39:00,864 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/aws-c-common/aws_priority_queue_clean_up_harness.i [2022-11-16 11:39:00,954 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/data/0bd1c1165/5f3e091dd825470d82293b30c029708d/FLAGd9dcfc62d [2022-11-16 11:39:01,987 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:39:01,987 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/sv-benchmarks/c/aws-c-common/aws_priority_queue_clean_up_harness.i [2022-11-16 11:39:02,025 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/data/0bd1c1165/5f3e091dd825470d82293b30c029708d/FLAGd9dcfc62d [2022-11-16 11:39:02,475 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/data/0bd1c1165/5f3e091dd825470d82293b30c029708d [2022-11-16 11:39:02,478 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:39:02,480 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:39:02,484 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:39:02,485 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:39:02,489 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:39:02,490 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:39:02" (1/1) ... [2022-11-16 11:39:02,492 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7a12c1b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:02, skipping insertion in model container [2022-11-16 11:39:02,492 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:39:02" (1/1) ... [2022-11-16 11:39:02,501 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:39:02,639 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:39:03,095 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/sv-benchmarks/c/aws-c-common/aws_priority_queue_clean_up_harness.i[4501,4514] [2022-11-16 11:39:03,106 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/sv-benchmarks/c/aws-c-common/aws_priority_queue_clean_up_harness.i[4561,4574] [2022-11-16 11:39:04,523 WARN L611 FunctionHandler]: implicit declaration of function __builtin_va_copy [2022-11-16 11:39:04,638 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:04,639 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:04,640 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:04,640 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:04,642 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:04,657 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:04,657 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:04,659 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:04,660 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,161 WARN L611 FunctionHandler]: implicit declaration of function __atomic_load_n [2022-11-16 11:39:05,162 WARN L611 FunctionHandler]: implicit declaration of function __atomic_store_n [2022-11-16 11:39:05,163 WARN L611 FunctionHandler]: implicit declaration of function __atomic_exchange_n [2022-11-16 11:39:05,183 WARN L611 FunctionHandler]: implicit declaration of function __atomic_compare_exchange_n [2022-11-16 11:39:05,185 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_add [2022-11-16 11:39:05,186 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_sub [2022-11-16 11:39:05,187 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_or [2022-11-16 11:39:05,190 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_and [2022-11-16 11:39:05,191 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_xor [2022-11-16 11:39:05,196 WARN L611 FunctionHandler]: implicit declaration of function __atomic_thread_fence [2022-11-16 11:39:05,411 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,412 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,493 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:39:05,572 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:39:05,600 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/sv-benchmarks/c/aws-c-common/aws_priority_queue_clean_up_harness.i[4501,4514] [2022-11-16 11:39:05,600 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/sv-benchmarks/c/aws-c-common/aws_priority_queue_clean_up_harness.i[4561,4574] [2022-11-16 11:39:05,670 WARN L611 FunctionHandler]: implicit declaration of function __builtin_va_copy [2022-11-16 11:39:05,704 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,705 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,705 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,706 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,713 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,729 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,732 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,733 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,734 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,807 WARN L611 FunctionHandler]: implicit declaration of function __atomic_load_n [2022-11-16 11:39:05,808 WARN L611 FunctionHandler]: implicit declaration of function __atomic_store_n [2022-11-16 11:39:05,809 WARN L611 FunctionHandler]: implicit declaration of function __atomic_exchange_n [2022-11-16 11:39:05,810 WARN L611 FunctionHandler]: implicit declaration of function __atomic_compare_exchange_n [2022-11-16 11:39:05,815 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_add [2022-11-16 11:39:05,815 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_sub [2022-11-16 11:39:05,816 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_or [2022-11-16 11:39:05,816 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_and [2022-11-16 11:39:05,817 WARN L611 FunctionHandler]: implicit declaration of function __atomic_fetch_xor [2022-11-16 11:39:05,818 WARN L611 FunctionHandler]: implicit declaration of function __atomic_thread_fence [2022-11-16 11:39:05,884 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,885 WARN L1554 CHandler]: Possible shadowing of function index [2022-11-16 11:39:05,941 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:39:06,289 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:39:06,290 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06 WrapperNode [2022-11-16 11:39:06,290 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:39:06,291 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:39:06,291 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:39:06,292 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:39:06,299 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,402 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,500 INFO L138 Inliner]: procedures = 689, calls = 1497, calls flagged for inlining = 55, calls inlined = 9, statements flattened = 598 [2022-11-16 11:39:06,500 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:39:06,501 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:39:06,501 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:39:06,502 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:39:06,513 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,514 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,528 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,529 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,560 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,566 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,572 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,576 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,585 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:39:06,586 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:39:06,586 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:39:06,587 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:39:06,588 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (1/1) ... [2022-11-16 11:39:06,596 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-16 11:39:06,610 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:06,625 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-16 11:39:06,660 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-16 11:39:06,686 INFO L130 BoogieDeclarations]: Found specification of procedure aws_is_mem_zeroed [2022-11-16 11:39:06,686 INFO L138 BoogieDeclarations]: Found implementation of procedure aws_is_mem_zeroed [2022-11-16 11:39:06,687 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-16 11:39:06,687 INFO L130 BoogieDeclarations]: Found specification of procedure aws_array_list_is_bounded [2022-11-16 11:39:06,687 INFO L138 BoogieDeclarations]: Found implementation of procedure aws_array_list_is_bounded [2022-11-16 11:39:06,687 INFO L130 BoogieDeclarations]: Found specification of procedure aws_array_list_is_valid [2022-11-16 11:39:06,688 INFO L138 BoogieDeclarations]: Found implementation of procedure aws_array_list_is_valid [2022-11-16 11:39:06,688 INFO L130 BoogieDeclarations]: Found specification of procedure nondet_bool [2022-11-16 11:39:06,689 INFO L138 BoogieDeclarations]: Found implementation of procedure nondet_bool [2022-11-16 11:39:06,689 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-16 11:39:06,690 INFO L130 BoogieDeclarations]: Found specification of procedure aws_raise_error [2022-11-16 11:39:06,691 INFO L138 BoogieDeclarations]: Found implementation of procedure aws_raise_error [2022-11-16 11:39:06,691 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-11-16 11:39:06,691 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-11-16 11:39:06,692 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-11-16 11:39:06,693 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 11:39:06,693 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-11-16 11:39:06,693 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:39:06,693 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:39:06,693 INFO L130 BoogieDeclarations]: Found specification of procedure aws_array_list_clean_up [2022-11-16 11:39:06,694 INFO L138 BoogieDeclarations]: Found implementation of procedure aws_array_list_clean_up [2022-11-16 11:39:06,694 INFO L130 BoogieDeclarations]: Found specification of procedure bounded_malloc [2022-11-16 11:39:06,695 INFO L138 BoogieDeclarations]: Found implementation of procedure bounded_malloc [2022-11-16 11:39:06,695 INFO L130 BoogieDeclarations]: Found specification of procedure aws_mul_size_checked [2022-11-16 11:39:06,696 INFO L138 BoogieDeclarations]: Found implementation of procedure aws_mul_size_checked [2022-11-16 11:39:06,696 INFO L130 BoogieDeclarations]: Found specification of procedure aws_priority_queue_is_valid [2022-11-16 11:39:06,696 INFO L138 BoogieDeclarations]: Found implementation of procedure aws_priority_queue_is_valid [2022-11-16 11:39:06,696 INFO L130 BoogieDeclarations]: Found specification of procedure aws_mem_release [2022-11-16 11:39:06,697 INFO L138 BoogieDeclarations]: Found implementation of procedure aws_mem_release [2022-11-16 11:39:06,697 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2022-11-16 11:39:06,697 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2022-11-16 11:39:06,698 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-16 11:39:06,698 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-11-16 11:39:06,699 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-11-16 11:39:06,699 INFO L130 BoogieDeclarations]: Found specification of procedure can_fail_allocator [2022-11-16 11:39:06,699 INFO L138 BoogieDeclarations]: Found implementation of procedure can_fail_allocator [2022-11-16 11:39:06,699 INFO L130 BoogieDeclarations]: Found specification of procedure __CPROVER_overflow_mult [2022-11-16 11:39:06,699 INFO L138 BoogieDeclarations]: Found implementation of procedure __CPROVER_overflow_mult [2022-11-16 11:39:06,700 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-16 11:39:06,700 INFO L130 BoogieDeclarations]: Found specification of procedure memset_impl [2022-11-16 11:39:06,700 INFO L138 BoogieDeclarations]: Found implementation of procedure memset_impl [2022-11-16 11:39:06,700 INFO L130 BoogieDeclarations]: Found specification of procedure my_memset [2022-11-16 11:39:06,701 INFO L138 BoogieDeclarations]: Found implementation of procedure my_memset [2022-11-16 11:39:06,701 INFO L130 BoogieDeclarations]: Found specification of procedure ensure_array_list_has_allocated_data_member [2022-11-16 11:39:06,701 INFO L138 BoogieDeclarations]: Found implementation of procedure ensure_array_list_has_allocated_data_member [2022-11-16 11:39:06,702 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 11:39:07,137 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:39:07,142 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:39:08,454 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:39:08,467 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:39:08,467 INFO L300 CfgBuilder]: Removed 4 assume(true) statements. [2022-11-16 11:39:08,471 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:39:08 BoogieIcfgContainer [2022-11-16 11:39:08,471 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:39:08,476 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-16 11:39:08,476 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-16 11:39:08,481 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-16 11:39:08,481 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 16.11 11:39:02" (1/3) ... [2022-11-16 11:39:08,482 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@cb78c87 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 11:39:08, skipping insertion in model container [2022-11-16 11:39:08,482 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:39:06" (2/3) ... [2022-11-16 11:39:08,484 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@cb78c87 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 11:39:08, skipping insertion in model container [2022-11-16 11:39:08,485 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:39:08" (3/3) ... [2022-11-16 11:39:08,486 INFO L112 eAbstractionObserver]: Analyzing ICFG aws_priority_queue_clean_up_harness.i [2022-11-16 11:39:08,510 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-16 11:39:08,510 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-16 11:39:08,605 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-16 11:39:08,613 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3ab7ef91, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-16 11:39:08,613 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-16 11:39:08,619 INFO L276 IsEmpty]: Start isEmpty. Operand has 165 states, 112 states have (on average 1.2678571428571428) internal successors, (142), 113 states have internal predecessors, (142), 35 states have call successors, (35), 17 states have call predecessors, (35), 17 states have return successors, (35), 35 states have call predecessors, (35), 35 states have call successors, (35) [2022-11-16 11:39:08,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2022-11-16 11:39:08,638 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:08,639 INFO L195 NwaCegarLoop]: trace histogram [5, 5, 5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:08,640 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:08,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:08,647 INFO L85 PathProgramCache]: Analyzing trace with hash 432166812, now seen corresponding path program 1 times [2022-11-16 11:39:08,659 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:08,659 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614692280] [2022-11-16 11:39:08,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:08,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:09,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,426 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-11-16 11:39:09,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,456 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 7 [2022-11-16 11:39:09,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,480 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 13 [2022-11-16 11:39:09,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,516 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-16 11:39:09,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,543 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-11-16 11:39:09,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,556 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 9 [2022-11-16 11:39:09,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,570 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2022-11-16 11:39:09,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,597 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-11-16 11:39:09,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,621 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 9 [2022-11-16 11:39:09,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,683 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 55 [2022-11-16 11:39:09,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,707 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 60 [2022-11-16 11:39:09,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,719 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 66 [2022-11-16 11:39:09,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,752 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-11-16 11:39:09,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,768 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 9 [2022-11-16 11:39:09,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,780 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 87 [2022-11-16 11:39:09,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,802 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 95 [2022-11-16 11:39:09,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:09,820 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2022-11-16 11:39:09,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:09,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614692280] [2022-11-16 11:39:09,822 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614692280] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:09,824 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:09,824 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 11:39:09,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474034922] [2022-11-16 11:39:09,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:09,835 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-16 11:39:09,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:09,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:39:09,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:39:09,878 INFO L87 Difference]: Start difference. First operand has 165 states, 112 states have (on average 1.2678571428571428) internal successors, (142), 113 states have internal predecessors, (142), 35 states have call successors, (35), 17 states have call predecessors, (35), 17 states have return successors, (35), 35 states have call predecessors, (35), 35 states have call successors, (35) Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 2 states have internal predecessors, (42), 2 states have call successors, (15), 4 states have call predecessors, (15), 2 states have return successors, (14), 2 states have call predecessors, (14), 2 states have call successors, (14) [2022-11-16 11:39:10,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:10,709 INFO L93 Difference]: Finished difference Result 361 states and 504 transitions. [2022-11-16 11:39:10,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:39:10,712 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 10.5) internal successors, (42), 2 states have internal predecessors, (42), 2 states have call successors, (15), 4 states have call predecessors, (15), 2 states have return successors, (14), 2 states have call predecessors, (14), 2 states have call successors, (14) Word has length 105 [2022-11-16 11:39:10,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:10,726 INFO L225 Difference]: With dead ends: 361 [2022-11-16 11:39:10,727 INFO L226 Difference]: Without dead ends: 202 [2022-11-16 11:39:10,732 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:39:10,736 INFO L413 NwaCegarLoop]: 151 mSDtfsCounter, 89 mSDsluCounter, 110 mSDsCounter, 0 mSdLazyCounter, 217 mSolverCounterSat, 45 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 98 SdHoareTripleChecker+Valid, 261 SdHoareTripleChecker+Invalid, 262 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 45 IncrementalHoareTripleChecker+Valid, 217 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:10,737 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [98 Valid, 261 Invalid, 262 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [45 Valid, 217 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-11-16 11:39:10,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states. [2022-11-16 11:39:10,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 160. [2022-11-16 11:39:10,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160 states, 107 states have (on average 1.233644859813084) internal successors, (132), 109 states have internal predecessors, (132), 35 states have call successors, (35), 17 states have call predecessors, (35), 17 states have return successors, (34), 34 states have call predecessors, (34), 34 states have call successors, (34) [2022-11-16 11:39:10,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 201 transitions. [2022-11-16 11:39:10,841 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 201 transitions. Word has length 105 [2022-11-16 11:39:10,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:10,842 INFO L495 AbstractCegarLoop]: Abstraction has 160 states and 201 transitions. [2022-11-16 11:39:10,843 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 10.5) internal successors, (42), 2 states have internal predecessors, (42), 2 states have call successors, (15), 4 states have call predecessors, (15), 2 states have return successors, (14), 2 states have call predecessors, (14), 2 states have call successors, (14) [2022-11-16 11:39:10,843 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 201 transitions. [2022-11-16 11:39:10,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2022-11-16 11:39:10,849 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:10,849 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:10,849 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-16 11:39:10,850 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:10,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:10,851 INFO L85 PathProgramCache]: Analyzing trace with hash 1130672400, now seen corresponding path program 1 times [2022-11-16 11:39:10,851 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:10,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802681800] [2022-11-16 11:39:10,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:10,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:10,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,492 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-11-16 11:39:11,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,546 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 7 [2022-11-16 11:39:11,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,568 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 13 [2022-11-16 11:39:11,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,598 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-16 11:39:11,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,630 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-11-16 11:39:11,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,641 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 9 [2022-11-16 11:39:11,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,650 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2022-11-16 11:39:11,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,684 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-11-16 11:39:11,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,695 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 9 [2022-11-16 11:39:11,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,725 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 55 [2022-11-16 11:39:11,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,775 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 60 [2022-11-16 11:39:11,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,787 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 66 [2022-11-16 11:39:11,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,818 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-11-16 11:39:11,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,829 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 9 [2022-11-16 11:39:11,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,854 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 17 [2022-11-16 11:39:11,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,868 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-11-16 11:39:11,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,883 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-11-16 11:39:11,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,895 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 104 [2022-11-16 11:39:11,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,908 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 112 [2022-11-16 11:39:11,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:11,922 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2022-11-16 11:39:11,922 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:11,923 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802681800] [2022-11-16 11:39:11,923 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802681800] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:11,923 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:11,923 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-16 11:39:11,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378244887] [2022-11-16 11:39:11,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:11,926 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-16 11:39:11,926 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:11,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-16 11:39:11,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2022-11-16 11:39:11,928 INFO L87 Difference]: Start difference. First operand 160 states and 201 transitions. Second operand has 8 states, 8 states have (on average 6.25) internal successors, (50), 5 states have internal predecessors, (50), 3 states have call successors, (18), 5 states have call predecessors, (18), 2 states have return successors, (17), 3 states have call predecessors, (17), 3 states have call successors, (17) [2022-11-16 11:39:13,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:13,097 INFO L93 Difference]: Finished difference Result 341 states and 448 transitions. [2022-11-16 11:39:13,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-16 11:39:13,098 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 6.25) internal successors, (50), 5 states have internal predecessors, (50), 3 states have call successors, (18), 5 states have call predecessors, (18), 2 states have return successors, (17), 3 states have call predecessors, (17), 3 states have call successors, (17) Word has length 122 [2022-11-16 11:39:13,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:13,101 INFO L225 Difference]: With dead ends: 341 [2022-11-16 11:39:13,101 INFO L226 Difference]: Without dead ends: 245 [2022-11-16 11:39:13,102 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=74, Unknown=0, NotChecked=0, Total=110 [2022-11-16 11:39:13,103 INFO L413 NwaCegarLoop]: 136 mSDtfsCounter, 282 mSDsluCounter, 422 mSDsCounter, 0 mSdLazyCounter, 622 mSolverCounterSat, 128 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 307 SdHoareTripleChecker+Valid, 558 SdHoareTripleChecker+Invalid, 750 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 128 IncrementalHoareTripleChecker+Valid, 622 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:13,104 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [307 Valid, 558 Invalid, 750 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [128 Valid, 622 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2022-11-16 11:39:13,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states. [2022-11-16 11:39:13,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 160. [2022-11-16 11:39:13,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160 states, 107 states have (on average 1.2242990654205608) internal successors, (131), 109 states have internal predecessors, (131), 35 states have call successors, (35), 17 states have call predecessors, (35), 17 states have return successors, (34), 34 states have call predecessors, (34), 34 states have call successors, (34) [2022-11-16 11:39:13,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 200 transitions. [2022-11-16 11:39:13,133 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 200 transitions. Word has length 122 [2022-11-16 11:39:13,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:13,134 INFO L495 AbstractCegarLoop]: Abstraction has 160 states and 200 transitions. [2022-11-16 11:39:13,134 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 6.25) internal successors, (50), 5 states have internal predecessors, (50), 3 states have call successors, (18), 5 states have call predecessors, (18), 2 states have return successors, (17), 3 states have call predecessors, (17), 3 states have call successors, (17) [2022-11-16 11:39:13,134 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 200 transitions. [2022-11-16 11:39:13,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2022-11-16 11:39:13,137 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:13,137 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:13,137 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-16 11:39:13,138 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:13,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:13,138 INFO L85 PathProgramCache]: Analyzing trace with hash -2103837312, now seen corresponding path program 1 times [2022-11-16 11:39:13,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:13,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820632915] [2022-11-16 11:39:13,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:13,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:13,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:13,731 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-11-16 11:39:13,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:13,781 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 7 [2022-11-16 11:39:13,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:13,807 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 13 [2022-11-16 11:39:13,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:13,840 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-16 11:39:13,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:13,890 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-11-16 11:39:13,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:13,902 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 9 [2022-11-16 11:39:13,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:13,912 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2022-11-16 11:39:13,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:13,966 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-11-16 11:39:13,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:13,986 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 9 [2022-11-16 11:39:13,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,025 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 55 [2022-11-16 11:39:14,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,121 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-11-16 11:39:14,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,227 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 68 [2022-11-16 11:39:14,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,240 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 74 [2022-11-16 11:39:14,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,275 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-11-16 11:39:14,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,292 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 9 [2022-11-16 11:39:14,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,325 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 17 [2022-11-16 11:39:14,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,348 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-11-16 11:39:14,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,366 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-11-16 11:39:14,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,383 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 112 [2022-11-16 11:39:14,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,398 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 120 [2022-11-16 11:39:14,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:14,414 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2022-11-16 11:39:14,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:14,415 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820632915] [2022-11-16 11:39:14,417 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [820632915] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:14,417 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:14,417 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2022-11-16 11:39:14,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987204758] [2022-11-16 11:39:14,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:14,420 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-16 11:39:14,421 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:14,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-16 11:39:14,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2022-11-16 11:39:14,423 INFO L87 Difference]: Start difference. First operand 160 states and 200 transitions. Second operand has 10 states, 10 states have (on average 5.6) internal successors, (56), 7 states have internal predecessors, (56), 4 states have call successors, (19), 5 states have call predecessors, (19), 3 states have return successors, (18), 4 states have call predecessors, (18), 4 states have call successors, (18) [2022-11-16 11:39:15,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:15,920 INFO L93 Difference]: Finished difference Result 371 states and 489 transitions. [2022-11-16 11:39:15,921 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-16 11:39:15,922 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 5.6) internal successors, (56), 7 states have internal predecessors, (56), 4 states have call successors, (19), 5 states have call predecessors, (19), 3 states have return successors, (18), 4 states have call predecessors, (18), 4 states have call successors, (18) Word has length 130 [2022-11-16 11:39:15,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:15,925 INFO L225 Difference]: With dead ends: 371 [2022-11-16 11:39:15,925 INFO L226 Difference]: Without dead ends: 226 [2022-11-16 11:39:15,926 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=73, Invalid=233, Unknown=0, NotChecked=0, Total=306 [2022-11-16 11:39:15,928 INFO L413 NwaCegarLoop]: 127 mSDtfsCounter, 243 mSDsluCounter, 672 mSDsCounter, 0 mSdLazyCounter, 995 mSolverCounterSat, 78 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 266 SdHoareTripleChecker+Valid, 799 SdHoareTripleChecker+Invalid, 1073 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 78 IncrementalHoareTripleChecker+Valid, 995 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:15,929 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [266 Valid, 799 Invalid, 1073 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [78 Valid, 995 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2022-11-16 11:39:15,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2022-11-16 11:39:15,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 162. [2022-11-16 11:39:15,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162 states, 108 states have (on average 1.2222222222222223) internal successors, (132), 111 states have internal predecessors, (132), 35 states have call successors, (35), 17 states have call predecessors, (35), 18 states have return successors, (36), 34 states have call predecessors, (36), 34 states have call successors, (36) [2022-11-16 11:39:15,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 203 transitions. [2022-11-16 11:39:15,954 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 203 transitions. Word has length 130 [2022-11-16 11:39:15,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:15,955 INFO L495 AbstractCegarLoop]: Abstraction has 162 states and 203 transitions. [2022-11-16 11:39:15,956 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 5.6) internal successors, (56), 7 states have internal predecessors, (56), 4 states have call successors, (19), 5 states have call predecessors, (19), 3 states have return successors, (18), 4 states have call predecessors, (18), 4 states have call successors, (18) [2022-11-16 11:39:15,956 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 203 transitions. [2022-11-16 11:39:15,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2022-11-16 11:39:15,959 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:15,960 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:15,960 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-11-16 11:39:15,960 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:15,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:15,961 INFO L85 PathProgramCache]: Analyzing trace with hash -209170488, now seen corresponding path program 1 times [2022-11-16 11:39:15,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:15,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591394837] [2022-11-16 11:39:15,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:15,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:16,075 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:16,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [456437846] [2022-11-16 11:39:16,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:16,076 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:16,076 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:16,080 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:16,107 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-16 11:39:16,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:16,794 INFO L263 TraceCheckSpWp]: Trace formula consists of 2428 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-16 11:39:16,807 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:17,030 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2022-11-16 11:39:17,035 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:17,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:17,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591394837] [2022-11-16 11:39:17,036 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:17,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [456437846] [2022-11-16 11:39:17,036 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [456437846] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:17,037 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:17,040 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-16 11:39:17,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503438076] [2022-11-16 11:39:17,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:17,042 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-16 11:39:17,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:17,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-16 11:39:17,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2022-11-16 11:39:17,045 INFO L87 Difference]: Start difference. First operand 162 states and 203 transitions. Second operand has 7 states, 7 states have (on average 10.0) internal successors, (70), 7 states have internal predecessors, (70), 4 states have call successors, (21), 2 states have call predecessors, (21), 3 states have return successors, (20), 4 states have call predecessors, (20), 4 states have call successors, (20) [2022-11-16 11:39:17,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:17,316 INFO L93 Difference]: Finished difference Result 261 states and 324 transitions. [2022-11-16 11:39:17,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 11:39:17,317 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 10.0) internal successors, (70), 7 states have internal predecessors, (70), 4 states have call successors, (21), 2 states have call predecessors, (21), 3 states have return successors, (20), 4 states have call predecessors, (20), 4 states have call successors, (20) Word has length 145 [2022-11-16 11:39:17,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:17,323 INFO L225 Difference]: With dead ends: 261 [2022-11-16 11:39:17,323 INFO L226 Difference]: Without dead ends: 162 [2022-11-16 11:39:17,324 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 139 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2022-11-16 11:39:17,328 INFO L413 NwaCegarLoop]: 169 mSDtfsCounter, 235 mSDsluCounter, 612 mSDsCounter, 0 mSdLazyCounter, 142 mSolverCounterSat, 30 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 235 SdHoareTripleChecker+Valid, 781 SdHoareTripleChecker+Invalid, 172 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 30 IncrementalHoareTripleChecker+Valid, 142 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:17,333 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [235 Valid, 781 Invalid, 172 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [30 Valid, 142 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-16 11:39:17,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2022-11-16 11:39:17,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2022-11-16 11:39:17,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162 states, 108 states have (on average 1.212962962962963) internal successors, (131), 111 states have internal predecessors, (131), 35 states have call successors, (35), 17 states have call predecessors, (35), 18 states have return successors, (36), 34 states have call predecessors, (36), 34 states have call successors, (36) [2022-11-16 11:39:17,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 202 transitions. [2022-11-16 11:39:17,379 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 202 transitions. Word has length 145 [2022-11-16 11:39:17,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:17,381 INFO L495 AbstractCegarLoop]: Abstraction has 162 states and 202 transitions. [2022-11-16 11:39:17,382 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 10.0) internal successors, (70), 7 states have internal predecessors, (70), 4 states have call successors, (21), 2 states have call predecessors, (21), 3 states have return successors, (20), 4 states have call predecessors, (20), 4 states have call successors, (20) [2022-11-16 11:39:17,382 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 202 transitions. [2022-11-16 11:39:17,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2022-11-16 11:39:17,391 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:17,391 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:17,409 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:17,602 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:17,603 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:17,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:17,604 INFO L85 PathProgramCache]: Analyzing trace with hash 1337604585, now seen corresponding path program 1 times [2022-11-16 11:39:17,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:17,604 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155380497] [2022-11-16 11:39:17,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:17,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:17,703 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:17,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1072497888] [2022-11-16 11:39:17,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:17,704 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:17,704 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:17,705 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:17,731 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-16 11:39:18,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:18,440 INFO L263 TraceCheckSpWp]: Trace formula consists of 2500 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-16 11:39:18,448 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:18,612 INFO L134 CoverageAnalysis]: Checked inductivity of 94 backedges. 39 proven. 0 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2022-11-16 11:39:18,613 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:18,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:18,613 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155380497] [2022-11-16 11:39:18,613 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:18,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1072497888] [2022-11-16 11:39:18,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1072497888] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:18,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:18,614 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2022-11-16 11:39:18,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856479078] [2022-11-16 11:39:18,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:18,615 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-11-16 11:39:18,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:18,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-11-16 11:39:18,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2022-11-16 11:39:18,617 INFO L87 Difference]: Start difference. First operand 162 states and 202 transitions. Second operand has 9 states, 9 states have (on average 9.333333333333334) internal successors, (84), 9 states have internal predecessors, (84), 5 states have call successors, (22), 2 states have call predecessors, (22), 4 states have return successors, (21), 5 states have call predecessors, (21), 5 states have call successors, (21) [2022-11-16 11:39:19,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:19,047 INFO L93 Difference]: Finished difference Result 274 states and 342 transitions. [2022-11-16 11:39:19,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-16 11:39:19,048 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 9.333333333333334) internal successors, (84), 9 states have internal predecessors, (84), 5 states have call successors, (22), 2 states have call predecessors, (22), 4 states have return successors, (21), 5 states have call predecessors, (21), 5 states have call successors, (21) Word has length 161 [2022-11-16 11:39:19,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:19,050 INFO L225 Difference]: With dead ends: 274 [2022-11-16 11:39:19,050 INFO L226 Difference]: Without dead ends: 162 [2022-11-16 11:39:19,051 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=163, Unknown=0, NotChecked=0, Total=210 [2022-11-16 11:39:19,052 INFO L413 NwaCegarLoop]: 161 mSDtfsCounter, 300 mSDsluCounter, 880 mSDsCounter, 0 mSdLazyCounter, 266 mSolverCounterSat, 41 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 302 SdHoareTripleChecker+Valid, 1041 SdHoareTripleChecker+Invalid, 307 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 41 IncrementalHoareTripleChecker+Valid, 266 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:19,052 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [302 Valid, 1041 Invalid, 307 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [41 Valid, 266 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-16 11:39:19,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2022-11-16 11:39:19,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2022-11-16 11:39:19,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162 states, 108 states have (on average 1.212962962962963) internal successors, (131), 111 states have internal predecessors, (131), 35 states have call successors, (35), 17 states have call predecessors, (35), 18 states have return successors, (35), 34 states have call predecessors, (35), 34 states have call successors, (35) [2022-11-16 11:39:19,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 201 transitions. [2022-11-16 11:39:19,072 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 201 transitions. Word has length 161 [2022-11-16 11:39:19,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:19,073 INFO L495 AbstractCegarLoop]: Abstraction has 162 states and 201 transitions. [2022-11-16 11:39:19,073 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 9.333333333333334) internal successors, (84), 9 states have internal predecessors, (84), 5 states have call successors, (22), 2 states have call predecessors, (22), 4 states have return successors, (21), 5 states have call predecessors, (21), 5 states have call successors, (21) [2022-11-16 11:39:19,073 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 201 transitions. [2022-11-16 11:39:19,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2022-11-16 11:39:19,076 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:19,077 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:19,094 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:19,288 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:19,289 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:19,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:19,289 INFO L85 PathProgramCache]: Analyzing trace with hash 996052163, now seen corresponding path program 1 times [2022-11-16 11:39:19,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:19,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847555415] [2022-11-16 11:39:19,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:19,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:19,415 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:19,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [941744555] [2022-11-16 11:39:19,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:19,416 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:19,417 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:19,418 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:19,424 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-16 11:39:20,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:20,167 INFO L263 TraceCheckSpWp]: Trace formula consists of 2641 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-16 11:39:20,205 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:20,385 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2022-11-16 11:39:20,386 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:20,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:20,386 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [847555415] [2022-11-16 11:39:20,386 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:20,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [941744555] [2022-11-16 11:39:20,387 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [941744555] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:20,387 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:20,387 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-16 11:39:20,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [892028307] [2022-11-16 11:39:20,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:20,388 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-16 11:39:20,389 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:20,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-16 11:39:20,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-11-16 11:39:20,390 INFO L87 Difference]: Start difference. First operand 162 states and 201 transitions. Second operand has 6 states, 6 states have (on average 13.5) internal successors, (81), 6 states have internal predecessors, (81), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:20,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:20,700 INFO L93 Difference]: Finished difference Result 286 states and 356 transitions. [2022-11-16 11:39:20,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-16 11:39:20,701 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 13.5) internal successors, (81), 6 states have internal predecessors, (81), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) Word has length 176 [2022-11-16 11:39:20,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:20,705 INFO L225 Difference]: With dead ends: 286 [2022-11-16 11:39:20,706 INFO L226 Difference]: Without dead ends: 180 [2022-11-16 11:39:20,707 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 178 GetRequests, 171 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2022-11-16 11:39:20,708 INFO L413 NwaCegarLoop]: 193 mSDtfsCounter, 23 mSDsluCounter, 700 mSDsCounter, 0 mSdLazyCounter, 111 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 24 SdHoareTripleChecker+Valid, 893 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 111 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:20,709 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [24 Valid, 893 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 111 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-16 11:39:20,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2022-11-16 11:39:20,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 166. [2022-11-16 11:39:20,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 166 states, 112 states have (on average 1.2142857142857142) internal successors, (136), 115 states have internal predecessors, (136), 35 states have call successors, (35), 17 states have call predecessors, (35), 18 states have return successors, (35), 34 states have call predecessors, (35), 34 states have call successors, (35) [2022-11-16 11:39:20,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 206 transitions. [2022-11-16 11:39:20,731 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 206 transitions. Word has length 176 [2022-11-16 11:39:20,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:20,736 INFO L495 AbstractCegarLoop]: Abstraction has 166 states and 206 transitions. [2022-11-16 11:39:20,736 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 13.5) internal successors, (81), 6 states have internal predecessors, (81), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:20,736 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 206 transitions. [2022-11-16 11:39:20,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2022-11-16 11:39:20,740 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:20,741 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:20,758 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:20,952 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable5 [2022-11-16 11:39:20,953 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:20,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:20,953 INFO L85 PathProgramCache]: Analyzing trace with hash 28701509, now seen corresponding path program 1 times [2022-11-16 11:39:20,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:20,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759316579] [2022-11-16 11:39:20,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:20,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:21,061 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:21,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1227346675] [2022-11-16 11:39:21,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:21,062 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:21,062 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:21,064 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:21,084 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-16 11:39:21,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:21,803 INFO L263 TraceCheckSpWp]: Trace formula consists of 2638 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 11:39:21,809 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:21,840 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2022-11-16 11:39:21,841 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:21,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:21,841 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759316579] [2022-11-16 11:39:21,841 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:21,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1227346675] [2022-11-16 11:39:21,842 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1227346675] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:21,842 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:21,842 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 11:39:21,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904432761] [2022-11-16 11:39:21,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:21,844 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-16 11:39:21,844 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:21,845 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:39:21,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:39:21,845 INFO L87 Difference]: Start difference. First operand 166 states and 206 transitions. Second operand has 4 states, 4 states have (on average 20.25) internal successors, (81), 4 states have internal predecessors, (81), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:21,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:21,908 INFO L93 Difference]: Finished difference Result 274 states and 339 transitions. [2022-11-16 11:39:21,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-16 11:39:21,909 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 20.25) internal successors, (81), 4 states have internal predecessors, (81), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) Word has length 176 [2022-11-16 11:39:21,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:21,911 INFO L225 Difference]: With dead ends: 274 [2022-11-16 11:39:21,912 INFO L226 Difference]: Without dead ends: 170 [2022-11-16 11:39:21,912 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 176 GetRequests, 173 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:39:21,913 INFO L413 NwaCegarLoop]: 196 mSDtfsCounter, 3 mSDsluCounter, 387 mSDsCounter, 0 mSdLazyCounter, 12 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 583 SdHoareTripleChecker+Invalid, 13 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 12 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:21,914 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 583 Invalid, 13 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 12 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-16 11:39:21,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2022-11-16 11:39:21,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 168. [2022-11-16 11:39:21,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 168 states, 114 states have (on average 1.2105263157894737) internal successors, (138), 117 states have internal predecessors, (138), 35 states have call successors, (35), 17 states have call predecessors, (35), 18 states have return successors, (35), 34 states have call predecessors, (35), 34 states have call successors, (35) [2022-11-16 11:39:21,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 208 transitions. [2022-11-16 11:39:21,933 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 208 transitions. Word has length 176 [2022-11-16 11:39:21,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:21,934 INFO L495 AbstractCegarLoop]: Abstraction has 168 states and 208 transitions. [2022-11-16 11:39:21,934 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 20.25) internal successors, (81), 4 states have internal predecessors, (81), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:21,935 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 208 transitions. [2022-11-16 11:39:21,937 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2022-11-16 11:39:21,938 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:21,938 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:21,955 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:22,150 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:22,150 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:22,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:22,151 INFO L85 PathProgramCache]: Analyzing trace with hash -463924665, now seen corresponding path program 1 times [2022-11-16 11:39:22,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:22,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492567158] [2022-11-16 11:39:22,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:22,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:22,278 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:22,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [67853255] [2022-11-16 11:39:22,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:22,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:22,279 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:22,280 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:22,303 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-16 11:39:23,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:23,141 INFO L263 TraceCheckSpWp]: Trace formula consists of 2633 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-16 11:39:23,148 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:23,218 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 105 trivial. 0 not checked. [2022-11-16 11:39:23,219 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:39:23,566 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 105 trivial. 0 not checked. [2022-11-16 11:39:23,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:23,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1492567158] [2022-11-16 11:39:23,567 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:23,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [67853255] [2022-11-16 11:39:23,568 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [67853255] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-16 11:39:23,568 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-16 11:39:23,568 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2022-11-16 11:39:23,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [741456835] [2022-11-16 11:39:23,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:23,569 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-16 11:39:23,570 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:23,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-16 11:39:23,570 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2022-11-16 11:39:23,571 INFO L87 Difference]: Start difference. First operand 168 states and 208 transitions. Second operand has 6 states, 5 states have (on average 16.0) internal successors, (80), 4 states have internal predecessors, (80), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 1 states have call successors, (21) [2022-11-16 11:39:23,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:23,649 INFO L93 Difference]: Finished difference Result 178 states and 222 transitions. [2022-11-16 11:39:23,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 11:39:23,650 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 16.0) internal successors, (80), 4 states have internal predecessors, (80), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 1 states have call successors, (21) Word has length 176 [2022-11-16 11:39:23,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:23,652 INFO L225 Difference]: With dead ends: 178 [2022-11-16 11:39:23,652 INFO L226 Difference]: Without dead ends: 176 [2022-11-16 11:39:23,653 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 351 GetRequests, 340 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2022-11-16 11:39:23,653 INFO L413 NwaCegarLoop]: 197 mSDtfsCounter, 6 mSDsluCounter, 773 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 970 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:23,654 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 970 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-16 11:39:23,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2022-11-16 11:39:23,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 175. [2022-11-16 11:39:23,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 175 states, 118 states have (on average 1.2033898305084745) internal successors, (142), 122 states have internal predecessors, (142), 36 states have call successors, (36), 18 states have call predecessors, (36), 20 states have return successors, (41), 35 states have call predecessors, (41), 35 states have call successors, (41) [2022-11-16 11:39:23,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 219 transitions. [2022-11-16 11:39:23,671 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 219 transitions. Word has length 176 [2022-11-16 11:39:23,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:23,672 INFO L495 AbstractCegarLoop]: Abstraction has 175 states and 219 transitions. [2022-11-16 11:39:23,672 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 16.0) internal successors, (80), 4 states have internal predecessors, (80), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 1 states have call successors, (21) [2022-11-16 11:39:23,673 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 219 transitions. [2022-11-16 11:39:23,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2022-11-16 11:39:23,676 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:23,676 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:23,693 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:23,888 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:23,888 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:23,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:23,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1104137534, now seen corresponding path program 1 times [2022-11-16 11:39:23,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:23,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033637976] [2022-11-16 11:39:23,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:23,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:23,980 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:23,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [622334676] [2022-11-16 11:39:23,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:23,981 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:23,981 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:23,983 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:24,012 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-11-16 11:39:24,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:24,758 INFO L263 TraceCheckSpWp]: Trace formula consists of 2636 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-16 11:39:24,765 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:24,834 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2022-11-16 11:39:24,835 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:24,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:24,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2033637976] [2022-11-16 11:39:24,835 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:24,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [622334676] [2022-11-16 11:39:24,836 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [622334676] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:24,836 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:24,836 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-16 11:39:24,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58939000] [2022-11-16 11:39:24,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:24,837 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-16 11:39:24,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:24,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-16 11:39:24,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-11-16 11:39:24,839 INFO L87 Difference]: Start difference. First operand 175 states and 219 transitions. Second operand has 6 states, 5 states have (on average 16.8) internal successors, (84), 6 states have internal predecessors, (84), 4 states have call successors, (22), 2 states have call predecessors, (22), 4 states have return successors, (21), 4 states have call predecessors, (21), 4 states have call successors, (21) [2022-11-16 11:39:24,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:24,923 INFO L93 Difference]: Finished difference Result 281 states and 350 transitions. [2022-11-16 11:39:24,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-16 11:39:24,924 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 16.8) internal successors, (84), 6 states have internal predecessors, (84), 4 states have call successors, (22), 2 states have call predecessors, (22), 4 states have return successors, (21), 4 states have call predecessors, (21), 4 states have call successors, (21) Word has length 176 [2022-11-16 11:39:24,924 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:24,926 INFO L225 Difference]: With dead ends: 281 [2022-11-16 11:39:24,926 INFO L226 Difference]: Without dead ends: 175 [2022-11-16 11:39:24,927 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 177 GetRequests, 171 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-16 11:39:24,928 INFO L413 NwaCegarLoop]: 193 mSDtfsCounter, 13 mSDsluCounter, 751 mSDsCounter, 0 mSdLazyCounter, 37 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 944 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 37 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:24,928 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 944 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 37 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-16 11:39:24,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2022-11-16 11:39:24,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 175. [2022-11-16 11:39:24,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 175 states, 118 states have (on average 1.194915254237288) internal successors, (141), 122 states have internal predecessors, (141), 36 states have call successors, (36), 18 states have call predecessors, (36), 20 states have return successors, (41), 35 states have call predecessors, (41), 35 states have call successors, (41) [2022-11-16 11:39:24,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 218 transitions. [2022-11-16 11:39:24,945 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 218 transitions. Word has length 176 [2022-11-16 11:39:24,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:24,946 INFO L495 AbstractCegarLoop]: Abstraction has 175 states and 218 transitions. [2022-11-16 11:39:24,946 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 16.8) internal successors, (84), 6 states have internal predecessors, (84), 4 states have call successors, (22), 2 states have call predecessors, (22), 4 states have return successors, (21), 4 states have call predecessors, (21), 4 states have call successors, (21) [2022-11-16 11:39:24,947 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 218 transitions. [2022-11-16 11:39:24,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 178 [2022-11-16 11:39:24,949 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:24,950 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:24,967 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:25,162 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable8 [2022-11-16 11:39:25,163 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:25,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:25,163 INFO L85 PathProgramCache]: Analyzing trace with hash -1406424536, now seen corresponding path program 1 times [2022-11-16 11:39:25,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:25,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927569830] [2022-11-16 11:39:25,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:25,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:25,255 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:25,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1448606248] [2022-11-16 11:39:25,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:25,256 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:25,256 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:25,257 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:25,277 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-11-16 11:39:25,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:26,000 INFO L263 TraceCheckSpWp]: Trace formula consists of 2643 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-16 11:39:26,006 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:26,105 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2022-11-16 11:39:26,105 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:26,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:26,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927569830] [2022-11-16 11:39:26,106 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:26,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1448606248] [2022-11-16 11:39:26,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1448606248] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:26,107 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:26,107 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-16 11:39:26,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804480378] [2022-11-16 11:39:26,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:26,111 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-16 11:39:26,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:26,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-16 11:39:26,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-11-16 11:39:26,112 INFO L87 Difference]: Start difference. First operand 175 states and 218 transitions. Second operand has 7 states, 6 states have (on average 14.166666666666666) internal successors, (85), 7 states have internal predecessors, (85), 4 states have call successors, (22), 2 states have call predecessors, (22), 4 states have return successors, (21), 4 states have call predecessors, (21), 4 states have call successors, (21) [2022-11-16 11:39:26,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:26,215 INFO L93 Difference]: Finished difference Result 283 states and 351 transitions. [2022-11-16 11:39:26,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 11:39:26,216 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 6 states have (on average 14.166666666666666) internal successors, (85), 7 states have internal predecessors, (85), 4 states have call successors, (22), 2 states have call predecessors, (22), 4 states have return successors, (21), 4 states have call predecessors, (21), 4 states have call successors, (21) Word has length 177 [2022-11-16 11:39:26,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:26,218 INFO L225 Difference]: With dead ends: 283 [2022-11-16 11:39:26,218 INFO L226 Difference]: Without dead ends: 177 [2022-11-16 11:39:26,219 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 178 GetRequests, 171 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2022-11-16 11:39:26,220 INFO L413 NwaCegarLoop]: 192 mSDtfsCounter, 19 mSDsluCounter, 750 mSDsCounter, 0 mSdLazyCounter, 43 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 21 SdHoareTripleChecker+Valid, 942 SdHoareTripleChecker+Invalid, 43 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 43 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:26,221 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [21 Valid, 942 Invalid, 43 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 43 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-16 11:39:26,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2022-11-16 11:39:26,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 176. [2022-11-16 11:39:26,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 119 states have (on average 1.1932773109243697) internal successors, (142), 123 states have internal predecessors, (142), 36 states have call successors, (36), 18 states have call predecessors, (36), 20 states have return successors, (41), 35 states have call predecessors, (41), 35 states have call successors, (41) [2022-11-16 11:39:26,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 219 transitions. [2022-11-16 11:39:26,244 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 219 transitions. Word has length 177 [2022-11-16 11:39:26,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:26,247 INFO L495 AbstractCegarLoop]: Abstraction has 176 states and 219 transitions. [2022-11-16 11:39:26,247 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 6 states have (on average 14.166666666666666) internal successors, (85), 7 states have internal predecessors, (85), 4 states have call successors, (22), 2 states have call predecessors, (22), 4 states have return successors, (21), 4 states have call predecessors, (21), 4 states have call successors, (21) [2022-11-16 11:39:26,247 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 219 transitions. [2022-11-16 11:39:26,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2022-11-16 11:39:26,251 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:26,251 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:26,267 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:26,462 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-11-16 11:39:26,463 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:26,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:26,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1080671750, now seen corresponding path program 1 times [2022-11-16 11:39:26,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:26,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836419704] [2022-11-16 11:39:26,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:26,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:26,580 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:26,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [257984015] [2022-11-16 11:39:26,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:26,581 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:26,581 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:26,582 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:26,589 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-11-16 11:39:27,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:27,321 INFO L263 TraceCheckSpWp]: Trace formula consists of 2662 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-16 11:39:27,326 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:27,363 INFO L134 CoverageAnalysis]: Checked inductivity of 108 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-16 11:39:27,364 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:27,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:27,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836419704] [2022-11-16 11:39:27,365 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:27,365 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [257984015] [2022-11-16 11:39:27,365 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [257984015] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:27,365 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:27,365 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 11:39:27,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [146917874] [2022-11-16 11:39:27,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:27,367 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-16 11:39:27,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:27,367 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:39:27,368 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:39:27,368 INFO L87 Difference]: Start difference. First operand 176 states and 219 transitions. Second operand has 4 states, 4 states have (on average 22.5) internal successors, (90), 4 states have internal predecessors, (90), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:27,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:27,447 INFO L93 Difference]: Finished difference Result 293 states and 372 transitions. [2022-11-16 11:39:27,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:39:27,449 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 22.5) internal successors, (90), 4 states have internal predecessors, (90), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) Word has length 179 [2022-11-16 11:39:27,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:27,450 INFO L225 Difference]: With dead ends: 293 [2022-11-16 11:39:27,451 INFO L226 Difference]: Without dead ends: 181 [2022-11-16 11:39:27,451 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:39:27,452 INFO L413 NwaCegarLoop]: 190 mSDtfsCounter, 7 mSDsluCounter, 369 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 559 SdHoareTripleChecker+Invalid, 38 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:27,452 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 559 Invalid, 38 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-16 11:39:27,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2022-11-16 11:39:27,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 177. [2022-11-16 11:39:27,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177 states, 120 states have (on average 1.1916666666666667) internal successors, (143), 124 states have internal predecessors, (143), 36 states have call successors, (36), 18 states have call predecessors, (36), 20 states have return successors, (41), 35 states have call predecessors, (41), 35 states have call successors, (41) [2022-11-16 11:39:27,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 220 transitions. [2022-11-16 11:39:27,469 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 220 transitions. Word has length 179 [2022-11-16 11:39:27,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:27,470 INFO L495 AbstractCegarLoop]: Abstraction has 177 states and 220 transitions. [2022-11-16 11:39:27,470 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 22.5) internal successors, (90), 4 states have internal predecessors, (90), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:27,471 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 220 transitions. [2022-11-16 11:39:27,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2022-11-16 11:39:27,474 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:27,474 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:27,486 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:27,686 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:27,686 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:27,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:27,687 INFO L85 PathProgramCache]: Analyzing trace with hash 712361510, now seen corresponding path program 1 times [2022-11-16 11:39:27,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:27,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783651041] [2022-11-16 11:39:27,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:27,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:27,870 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:27,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1350339195] [2022-11-16 11:39:27,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:27,871 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:27,871 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:27,873 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:27,895 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-16 11:39:28,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:28,683 INFO L263 TraceCheckSpWp]: Trace formula consists of 2668 conjuncts, 39 conjunts are in the unsatisfiable core [2022-11-16 11:39:28,690 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:28,941 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 5 [2022-11-16 11:39:28,978 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2022-11-16 11:39:28,978 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:28,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:28,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783651041] [2022-11-16 11:39:28,979 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:28,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1350339195] [2022-11-16 11:39:28,979 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1350339195] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:28,980 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:28,980 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2022-11-16 11:39:28,980 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136699452] [2022-11-16 11:39:28,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:28,981 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2022-11-16 11:39:28,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:28,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-16 11:39:28,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2022-11-16 11:39:28,983 INFO L87 Difference]: Start difference. First operand 177 states and 220 transitions. Second operand has 11 states, 11 states have (on average 8.363636363636363) internal successors, (92), 11 states have internal predecessors, (92), 6 states have call successors, (23), 2 states have call predecessors, (23), 3 states have return successors, (22), 6 states have call predecessors, (22), 6 states have call successors, (22) [2022-11-16 11:39:29,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:29,689 INFO L93 Difference]: Finished difference Result 326 states and 410 transitions. [2022-11-16 11:39:29,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-11-16 11:39:29,690 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 8.363636363636363) internal successors, (92), 11 states have internal predecessors, (92), 6 states have call successors, (23), 2 states have call predecessors, (23), 3 states have return successors, (22), 6 states have call predecessors, (22), 6 states have call successors, (22) Word has length 179 [2022-11-16 11:39:29,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:29,692 INFO L225 Difference]: With dead ends: 326 [2022-11-16 11:39:29,692 INFO L226 Difference]: Without dead ends: 205 [2022-11-16 11:39:29,693 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 189 GetRequests, 171 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=81, Invalid=299, Unknown=0, NotChecked=0, Total=380 [2022-11-16 11:39:29,694 INFO L413 NwaCegarLoop]: 179 mSDtfsCounter, 116 mSDsluCounter, 1438 mSDsCounter, 0 mSdLazyCounter, 348 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 125 SdHoareTripleChecker+Valid, 1617 SdHoareTripleChecker+Invalid, 359 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 348 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:29,694 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [125 Valid, 1617 Invalid, 359 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 348 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-11-16 11:39:29,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2022-11-16 11:39:29,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 186. [2022-11-16 11:39:29,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 128 states have (on average 1.1953125) internal successors, (153), 132 states have internal predecessors, (153), 36 states have call successors, (36), 18 states have call predecessors, (36), 21 states have return successors, (44), 36 states have call predecessors, (44), 35 states have call successors, (44) [2022-11-16 11:39:29,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 233 transitions. [2022-11-16 11:39:29,715 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 233 transitions. Word has length 179 [2022-11-16 11:39:29,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:29,715 INFO L495 AbstractCegarLoop]: Abstraction has 186 states and 233 transitions. [2022-11-16 11:39:29,716 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 8.363636363636363) internal successors, (92), 11 states have internal predecessors, (92), 6 states have call successors, (23), 2 states have call predecessors, (23), 3 states have return successors, (22), 6 states have call predecessors, (22), 6 states have call successors, (22) [2022-11-16 11:39:29,716 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 233 transitions. [2022-11-16 11:39:29,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2022-11-16 11:39:29,719 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:29,720 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:29,738 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:29,931 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable11 [2022-11-16 11:39:29,932 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:29,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:29,932 INFO L85 PathProgramCache]: Analyzing trace with hash 1965868264, now seen corresponding path program 1 times [2022-11-16 11:39:29,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:29,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58343146] [2022-11-16 11:39:29,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:29,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:30,026 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:30,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [470088290] [2022-11-16 11:39:30,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:30,027 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:30,027 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:30,028 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:30,033 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-16 11:39:30,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:30,896 INFO L263 TraceCheckSpWp]: Trace formula consists of 2671 conjuncts, 15 conjunts are in the unsatisfiable core [2022-11-16 11:39:30,903 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:31,076 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2022-11-16 11:39:31,076 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:31,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:31,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58343146] [2022-11-16 11:39:31,077 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:31,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [470088290] [2022-11-16 11:39:31,078 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [470088290] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:31,078 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:31,078 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-16 11:39:31,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379521143] [2022-11-16 11:39:31,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:31,079 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-16 11:39:31,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:31,080 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-16 11:39:31,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2022-11-16 11:39:31,080 INFO L87 Difference]: Start difference. First operand 186 states and 233 transitions. Second operand has 8 states, 8 states have (on average 11.0) internal successors, (88), 7 states have internal predecessors, (88), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 3 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:31,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:31,483 INFO L93 Difference]: Finished difference Result 304 states and 382 transitions. [2022-11-16 11:39:31,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-16 11:39:31,484 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 11.0) internal successors, (88), 7 states have internal predecessors, (88), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 3 states have call predecessors, (21), 2 states have call successors, (21) Word has length 179 [2022-11-16 11:39:31,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:31,487 INFO L225 Difference]: With dead ends: 304 [2022-11-16 11:39:31,487 INFO L226 Difference]: Without dead ends: 195 [2022-11-16 11:39:31,488 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 181 GetRequests, 172 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=28, Invalid=82, Unknown=0, NotChecked=0, Total=110 [2022-11-16 11:39:31,489 INFO L413 NwaCegarLoop]: 196 mSDtfsCounter, 8 mSDsluCounter, 1088 mSDsCounter, 0 mSdLazyCounter, 122 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 1284 SdHoareTripleChecker+Invalid, 125 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 122 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:31,489 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 1284 Invalid, 125 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 122 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-16 11:39:31,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2022-11-16 11:39:31,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 188. [2022-11-16 11:39:31,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188 states, 130 states have (on average 1.1923076923076923) internal successors, (155), 133 states have internal predecessors, (155), 36 states have call successors, (36), 18 states have call predecessors, (36), 21 states have return successors, (44), 37 states have call predecessors, (44), 35 states have call successors, (44) [2022-11-16 11:39:31,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 235 transitions. [2022-11-16 11:39:31,512 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 235 transitions. Word has length 179 [2022-11-16 11:39:31,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:31,513 INFO L495 AbstractCegarLoop]: Abstraction has 188 states and 235 transitions. [2022-11-16 11:39:31,514 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 11.0) internal successors, (88), 7 states have internal predecessors, (88), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 3 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:31,514 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 235 transitions. [2022-11-16 11:39:31,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2022-11-16 11:39:31,518 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:31,518 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:31,539 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:31,739 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12,11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:31,739 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:31,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:31,740 INFO L85 PathProgramCache]: Analyzing trace with hash 1941254556, now seen corresponding path program 1 times [2022-11-16 11:39:31,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:31,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843210139] [2022-11-16 11:39:31,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:31,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:31,866 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:31,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1355707100] [2022-11-16 11:39:31,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:31,867 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:31,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:31,869 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:31,899 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-16 11:39:32,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:32,752 INFO L263 TraceCheckSpWp]: Trace formula consists of 2675 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-16 11:39:32,759 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:32,926 INFO L134 CoverageAnalysis]: Checked inductivity of 113 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2022-11-16 11:39:32,927 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:32,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:32,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843210139] [2022-11-16 11:39:32,927 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:32,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1355707100] [2022-11-16 11:39:32,928 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1355707100] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:32,929 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:32,929 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-16 11:39:32,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2133907451] [2022-11-16 11:39:32,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:32,930 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-16 11:39:32,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:32,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-16 11:39:32,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-11-16 11:39:32,931 INFO L87 Difference]: Start difference. First operand 188 states and 235 transitions. Second operand has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 3 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:33,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:33,192 INFO L93 Difference]: Finished difference Result 219 states and 271 transitions. [2022-11-16 11:39:33,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-16 11:39:33,193 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 3 states have call predecessors, (21), 2 states have call successors, (21) Word has length 182 [2022-11-16 11:39:33,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:33,194 INFO L225 Difference]: With dead ends: 219 [2022-11-16 11:39:33,194 INFO L226 Difference]: Without dead ends: 192 [2022-11-16 11:39:33,195 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-16 11:39:33,196 INFO L413 NwaCegarLoop]: 193 mSDtfsCounter, 4 mSDsluCounter, 716 mSDsCounter, 0 mSdLazyCounter, 79 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 909 SdHoareTripleChecker+Invalid, 79 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 79 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:33,196 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 909 Invalid, 79 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 79 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-16 11:39:33,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192 states. [2022-11-16 11:39:33,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192 to 189. [2022-11-16 11:39:33,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 189 states, 131 states have (on average 1.1908396946564885) internal successors, (156), 133 states have internal predecessors, (156), 36 states have call successors, (36), 18 states have call predecessors, (36), 21 states have return successors, (44), 38 states have call predecessors, (44), 35 states have call successors, (44) [2022-11-16 11:39:33,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 236 transitions. [2022-11-16 11:39:33,231 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 236 transitions. Word has length 182 [2022-11-16 11:39:33,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:33,232 INFO L495 AbstractCegarLoop]: Abstraction has 189 states and 236 transitions. [2022-11-16 11:39:33,232 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 3 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:33,233 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 236 transitions. [2022-11-16 11:39:33,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2022-11-16 11:39:33,241 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:33,241 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:33,258 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:33,455 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:33,455 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:33,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:33,456 INFO L85 PathProgramCache]: Analyzing trace with hash -101731212, now seen corresponding path program 2 times [2022-11-16 11:39:33,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:33,456 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13462959] [2022-11-16 11:39:33,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:33,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:33,549 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:33,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1819775405] [2022-11-16 11:39:33,549 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:39:33,550 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:33,550 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:33,551 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:33,571 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-16 11:39:34,484 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:39:34,484 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:39:34,495 INFO L263 TraceCheckSpWp]: Trace formula consists of 2679 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-16 11:39:34,501 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:34,672 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2022-11-16 11:39:34,672 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:34,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:34,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [13462959] [2022-11-16 11:39:34,673 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:34,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1819775405] [2022-11-16 11:39:34,673 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1819775405] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:34,673 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:34,673 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-16 11:39:34,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441660376] [2022-11-16 11:39:34,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:34,674 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-16 11:39:34,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:34,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-16 11:39:34,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-11-16 11:39:34,676 INFO L87 Difference]: Start difference. First operand 189 states and 236 transitions. Second operand has 7 states, 7 states have (on average 12.571428571428571) internal successors, (88), 7 states have internal predecessors, (88), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:35,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:35,004 INFO L93 Difference]: Finished difference Result 324 states and 402 transitions. [2022-11-16 11:39:35,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-16 11:39:35,005 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 12.571428571428571) internal successors, (88), 7 states have internal predecessors, (88), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) Word has length 185 [2022-11-16 11:39:35,005 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:35,007 INFO L225 Difference]: With dead ends: 324 [2022-11-16 11:39:35,007 INFO L226 Difference]: Without dead ends: 205 [2022-11-16 11:39:35,008 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 187 GetRequests, 179 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2022-11-16 11:39:35,009 INFO L413 NwaCegarLoop]: 198 mSDtfsCounter, 13 mSDsluCounter, 907 mSDsCounter, 0 mSdLazyCounter, 110 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 1105 SdHoareTripleChecker+Invalid, 113 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 110 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:35,009 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 1105 Invalid, 113 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 110 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-16 11:39:35,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2022-11-16 11:39:35,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 199. [2022-11-16 11:39:35,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 199 states, 141 states have (on average 1.1914893617021276) internal successors, (168), 143 states have internal predecessors, (168), 36 states have call successors, (36), 18 states have call predecessors, (36), 21 states have return successors, (44), 38 states have call predecessors, (44), 35 states have call successors, (44) [2022-11-16 11:39:35,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 248 transitions. [2022-11-16 11:39:35,029 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 248 transitions. Word has length 185 [2022-11-16 11:39:35,030 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:35,030 INFO L495 AbstractCegarLoop]: Abstraction has 199 states and 248 transitions. [2022-11-16 11:39:35,031 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 12.571428571428571) internal successors, (88), 7 states have internal predecessors, (88), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:35,031 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 248 transitions. [2022-11-16 11:39:35,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2022-11-16 11:39:35,033 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:35,033 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:35,048 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:35,247 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2022-11-16 11:39:35,247 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:35,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:35,248 INFO L85 PathProgramCache]: Analyzing trace with hash -1980862158, now seen corresponding path program 1 times [2022-11-16 11:39:35,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:35,248 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237650982] [2022-11-16 11:39:35,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:35,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:35,344 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:35,345 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [567795201] [2022-11-16 11:39:35,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:35,345 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:35,345 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:35,346 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:35,369 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-16 11:39:36,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:36,153 INFO L263 TraceCheckSpWp]: Trace formula consists of 2676 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-16 11:39:36,160 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:36,323 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 38 proven. 0 refuted. 0 times theorem prover too weak. 81 trivial. 0 not checked. [2022-11-16 11:39:36,323 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:36,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:36,323 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237650982] [2022-11-16 11:39:36,324 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:36,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [567795201] [2022-11-16 11:39:36,324 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [567795201] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:36,324 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:36,324 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-16 11:39:36,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699157209] [2022-11-16 11:39:36,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:36,325 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-16 11:39:36,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:36,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-16 11:39:36,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2022-11-16 11:39:36,327 INFO L87 Difference]: Start difference. First operand 199 states and 248 transitions. Second operand has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 3 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:36,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:36,423 INFO L93 Difference]: Finished difference Result 328 states and 406 transitions. [2022-11-16 11:39:36,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-16 11:39:36,424 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 3 states have call predecessors, (21), 2 states have call successors, (21) Word has length 185 [2022-11-16 11:39:36,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:36,426 INFO L225 Difference]: With dead ends: 328 [2022-11-16 11:39:36,427 INFO L226 Difference]: Without dead ends: 209 [2022-11-16 11:39:36,427 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 179 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2022-11-16 11:39:36,428 INFO L413 NwaCegarLoop]: 195 mSDtfsCounter, 15 mSDsluCounter, 949 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 1144 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:36,428 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 1144 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 33 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-16 11:39:36,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2022-11-16 11:39:36,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 193. [2022-11-16 11:39:36,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193 states, 135 states have (on average 1.1851851851851851) internal successors, (160), 137 states have internal predecessors, (160), 36 states have call successors, (36), 18 states have call predecessors, (36), 21 states have return successors, (44), 38 states have call predecessors, (44), 35 states have call successors, (44) [2022-11-16 11:39:36,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 240 transitions. [2022-11-16 11:39:36,450 INFO L78 Accepts]: Start accepts. Automaton has 193 states and 240 transitions. Word has length 185 [2022-11-16 11:39:36,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:36,452 INFO L495 AbstractCegarLoop]: Abstraction has 193 states and 240 transitions. [2022-11-16 11:39:36,452 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 2 states have call successors, (22), 2 states have call predecessors, (22), 3 states have return successors, (21), 3 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:36,452 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 240 transitions. [2022-11-16 11:39:36,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2022-11-16 11:39:36,454 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:36,456 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:36,477 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:36,671 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2022-11-16 11:39:36,671 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:36,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:36,672 INFO L85 PathProgramCache]: Analyzing trace with hash 382427316, now seen corresponding path program 1 times [2022-11-16 11:39:36,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:36,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189515437] [2022-11-16 11:39:36,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:36,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:36,829 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:36,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [266711380] [2022-11-16 11:39:36,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:36,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:36,830 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:36,836 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:36,845 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-11-16 11:39:37,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:37,624 INFO L263 TraceCheckSpWp]: Trace formula consists of 2671 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 11:39:37,629 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:37,648 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 78 trivial. 0 not checked. [2022-11-16 11:39:37,648 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:39:37,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:37,649 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189515437] [2022-11-16 11:39:37,649 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:37,649 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [266711380] [2022-11-16 11:39:37,649 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [266711380] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:39:37,649 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:39:37,650 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-16 11:39:37,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856980935] [2022-11-16 11:39:37,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:39:37,651 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-16 11:39:37,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:37,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:39:37,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:39:37,652 INFO L87 Difference]: Start difference. First operand 193 states and 240 transitions. Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 4 states have internal predecessors, (93), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:37,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:37,694 INFO L93 Difference]: Finished difference Result 339 states and 427 transitions. [2022-11-16 11:39:37,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-16 11:39:37,696 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 23.25) internal successors, (93), 4 states have internal predecessors, (93), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) Word has length 185 [2022-11-16 11:39:37,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:37,698 INFO L225 Difference]: With dead ends: 339 [2022-11-16 11:39:37,698 INFO L226 Difference]: Without dead ends: 193 [2022-11-16 11:39:37,699 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 183 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-16 11:39:37,699 INFO L413 NwaCegarLoop]: 202 mSDtfsCounter, 7 mSDsluCounter, 384 mSDsCounter, 0 mSdLazyCounter, 13 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 586 SdHoareTripleChecker+Invalid, 14 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 13 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:37,700 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 586 Invalid, 14 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 13 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-16 11:39:37,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2022-11-16 11:39:37,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 193. [2022-11-16 11:39:37,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193 states, 135 states have (on average 1.1777777777777778) internal successors, (159), 137 states have internal predecessors, (159), 36 states have call successors, (36), 18 states have call predecessors, (36), 21 states have return successors, (44), 38 states have call predecessors, (44), 35 states have call successors, (44) [2022-11-16 11:39:37,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 239 transitions. [2022-11-16 11:39:37,717 INFO L78 Accepts]: Start accepts. Automaton has 193 states and 239 transitions. Word has length 185 [2022-11-16 11:39:37,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:37,717 INFO L495 AbstractCegarLoop]: Abstraction has 193 states and 239 transitions. [2022-11-16 11:39:37,718 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 23.25) internal successors, (93), 4 states have internal predecessors, (93), 2 states have call successors, (22), 2 states have call predecessors, (22), 2 states have return successors, (21), 2 states have call predecessors, (21), 2 states have call successors, (21) [2022-11-16 11:39:37,718 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 239 transitions. [2022-11-16 11:39:37,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 188 [2022-11-16 11:39:37,720 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:37,720 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:37,733 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:37,932 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable16 [2022-11-16 11:39:37,932 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:37,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:37,932 INFO L85 PathProgramCache]: Analyzing trace with hash -908019048, now seen corresponding path program 1 times [2022-11-16 11:39:37,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:37,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211678660] [2022-11-16 11:39:37,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:37,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:38,041 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:38,043 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1937428392] [2022-11-16 11:39:38,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:38,044 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:38,044 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:38,045 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:38,067 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-16 11:39:38,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:38,858 INFO L263 TraceCheckSpWp]: Trace formula consists of 2681 conjuncts, 125 conjunts are in the unsatisfiable core [2022-11-16 11:39:38,869 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:38,880 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2022-11-16 11:39:39,476 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-16 11:39:41,592 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:39:41,594 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-16 11:39:44,685 WARN L855 $PredicateComparison]: unable to prove that (exists ((v_ArrVal_1772 (Array Int Int))) (= (store |c_old(#memory_int)| |c_aws_mul_size_checked_#in~r#1.base| v_ArrVal_1772) |c_#memory_int|)) is different from true [2022-11-16 11:39:45,908 INFO L321 Elim1Store]: treesize reduction 48, result has 2.0 percent of original size [2022-11-16 11:39:45,909 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 125 treesize of output 1 [2022-11-16 11:39:45,914 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 19 refuted. 3 times theorem prover too weak. 43 trivial. 3 not checked. [2022-11-16 11:39:45,914 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:39:46,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:39:46,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211678660] [2022-11-16 11:39:46,861 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:39:46,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1937428392] [2022-11-16 11:39:46,861 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1937428392] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:39:46,862 INFO L184 FreeRefinementEngine]: Found 0 perfect and 1 imperfect interpolant sequences. [2022-11-16 11:39:46,862 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2022-11-16 11:39:46,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44013982] [2022-11-16 11:39:46,862 INFO L85 oduleStraightlineAll]: Using 1 imperfect interpolants to construct interpolant automaton [2022-11-16 11:39:46,863 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-11-16 11:39:46,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:39:46,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-16 11:39:46,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=848, Unknown=44, NotChecked=60, Total=1056 [2022-11-16 11:39:46,865 INFO L87 Difference]: Start difference. First operand 193 states and 239 transitions. Second operand has 32 states, 28 states have (on average 4.178571428571429) internal successors, (117), 28 states have internal predecessors, (117), 12 states have call successors, (26), 7 states have call predecessors, (26), 12 states have return successors, (25), 12 states have call predecessors, (25), 12 states have call successors, (25) [2022-11-16 11:39:47,677 WARN L855 $PredicateComparison]: unable to prove that (and (exists ((v_ArrVal_1772 (Array Int Int))) (= (store |c_old(#memory_int)| |c_aws_mul_size_checked_#in~r#1.base| v_ArrVal_1772) |c_#memory_int|)) (exists ((|v___CPROVER_overflow_mult_~#c~1.base_84| Int) (v_ArrVal_1769 Int)) (and (= |c_#valid| (store |c_old(#valid)| |v___CPROVER_overflow_mult_~#c~1.base_84| v_ArrVal_1769)) (= (select |c_old(#valid)| |v___CPROVER_overflow_mult_~#c~1.base_84|) 0))) (exists ((v_ArrVal_1770 (Array Int Int))) (= |c_#memory_int| (store |c_old(#memory_int)| |c_aws_mul_size_checked_#in~r#1.base| v_ArrVal_1770)))) is different from true [2022-11-16 11:39:48,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:39:48,354 INFO L93 Difference]: Finished difference Result 399 states and 504 transitions. [2022-11-16 11:39:48,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-16 11:39:48,355 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 28 states have (on average 4.178571428571429) internal successors, (117), 28 states have internal predecessors, (117), 12 states have call successors, (26), 7 states have call predecessors, (26), 12 states have return successors, (25), 12 states have call predecessors, (25), 12 states have call successors, (25) Word has length 187 [2022-11-16 11:39:48,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:39:48,358 INFO L225 Difference]: With dead ends: 399 [2022-11-16 11:39:48,358 INFO L226 Difference]: Without dead ends: 282 [2022-11-16 11:39:48,359 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 219 SyntacticMatches, 9 SemanticMatches, 37 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 418 ImplicationChecksByTransitivity, 6.0s TimeCoverageRelationStatistics Valid=139, Invalid=1151, Unknown=50, NotChecked=142, Total=1482 [2022-11-16 11:39:48,360 INFO L413 NwaCegarLoop]: 149 mSDtfsCounter, 90 mSDsluCounter, 1380 mSDsCounter, 0 mSdLazyCounter, 860 mSolverCounterSat, 54 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 96 SdHoareTripleChecker+Valid, 1529 SdHoareTripleChecker+Invalid, 2364 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 54 IncrementalHoareTripleChecker+Valid, 860 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 1450 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:39:48,361 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [96 Valid, 1529 Invalid, 2364 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [54 Valid, 860 Invalid, 0 Unknown, 1450 Unchecked, 1.0s Time] [2022-11-16 11:39:48,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2022-11-16 11:39:48,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 255. [2022-11-16 11:39:48,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 255 states, 183 states have (on average 1.174863387978142) internal successors, (215), 188 states have internal predecessors, (215), 41 states have call successors, (41), 23 states have call predecessors, (41), 30 states have return successors, (64), 44 states have call predecessors, (64), 40 states have call successors, (64) [2022-11-16 11:39:48,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 255 states to 255 states and 320 transitions. [2022-11-16 11:39:48,389 INFO L78 Accepts]: Start accepts. Automaton has 255 states and 320 transitions. Word has length 187 [2022-11-16 11:39:48,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:39:48,389 INFO L495 AbstractCegarLoop]: Abstraction has 255 states and 320 transitions. [2022-11-16 11:39:48,390 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 28 states have (on average 4.178571428571429) internal successors, (117), 28 states have internal predecessors, (117), 12 states have call successors, (26), 7 states have call predecessors, (26), 12 states have return successors, (25), 12 states have call predecessors, (25), 12 states have call successors, (25) [2022-11-16 11:39:48,390 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 320 transitions. [2022-11-16 11:39:48,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 194 [2022-11-16 11:39:48,392 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:39:48,392 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:39:48,411 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2022-11-16 11:39:48,605 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable17 [2022-11-16 11:39:48,606 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:39:48,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:39:48,606 INFO L85 PathProgramCache]: Analyzing trace with hash 1752761233, now seen corresponding path program 1 times [2022-11-16 11:39:48,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:39:48,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3667039] [2022-11-16 11:39:48,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:48,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:39:48,714 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:39:48,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [89451348] [2022-11-16 11:39:48,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:39:48,715 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:39:48,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:39:48,717 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:39:48,731 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-16 11:39:49,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:39:49,629 INFO L263 TraceCheckSpWp]: Trace formula consists of 2720 conjuncts, 135 conjunts are in the unsatisfiable core [2022-11-16 11:39:49,642 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:39:49,648 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2022-11-16 11:39:50,304 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-16 11:39:50,324 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2022-11-16 11:39:50,482 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-16 11:39:50,584 INFO L321 Elim1Store]: treesize reduction 18, result has 35.7 percent of original size [2022-11-16 11:39:50,584 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 17 treesize of output 21 [2022-11-16 11:39:54,676 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-16 11:39:54,677 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-16 11:39:59,981 WARN L855 $PredicateComparison]: unable to prove that (exists ((v_ArrVal_1967 (Array Int Int))) (= (store |c_old(#memory_int)| |c_aws_mul_size_checked_#in~r#1.base| v_ArrVal_1967) |c_#memory_int|)) is different from true [2022-11-16 11:40:01,026 INFO L321 Elim1Store]: treesize reduction 72, result has 1.4 percent of original size [2022-11-16 11:40:01,027 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 1 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 9 case distinctions, treesize of input 236 treesize of output 1 [2022-11-16 11:40:01,032 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 43 proven. 21 refuted. 3 times theorem prover too weak. 42 trivial. 3 not checked. [2022-11-16 11:40:01,032 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:02,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:02,010 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3667039] [2022-11-16 11:40:02,010 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:02,010 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [89451348] [2022-11-16 11:40:02,011 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [89451348] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-16 11:40:02,011 INFO L184 FreeRefinementEngine]: Found 0 perfect and 1 imperfect interpolant sequences. [2022-11-16 11:40:02,011 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2022-11-16 11:40:02,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623423209] [2022-11-16 11:40:02,011 INFO L85 oduleStraightlineAll]: Using 1 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:02,012 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-11-16 11:40:02,012 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:02,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-11-16 11:40:02,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=1086, Unknown=51, NotChecked=68, Total=1332 [2022-11-16 11:40:02,013 INFO L87 Difference]: Start difference. First operand 255 states and 320 transitions. Second operand has 36 states, 32 states have (on average 3.8125) internal successors, (122), 31 states have internal predecessors, (122), 14 states have call successors, (27), 9 states have call predecessors, (27), 14 states have return successors, (26), 13 states have call predecessors, (26), 14 states have call successors, (26) [2022-11-16 11:40:02,820 WARN L855 $PredicateComparison]: unable to prove that (and (exists ((v_ArrVal_1967 (Array Int Int))) (= (store |c_old(#memory_int)| |c_aws_mul_size_checked_#in~r#1.base| v_ArrVal_1967) |c_#memory_int|)) (exists ((v_ArrVal_1965 (Array Int Int))) (= |c_#memory_int| (store |c_old(#memory_int)| |c_aws_mul_size_checked_#in~r#1.base| v_ArrVal_1965))) (exists ((|v___CPROVER_overflow_mult_~#c~1.base_107| Int) (v_ArrVal_1964 Int)) (and (= (select |c_old(#valid)| |v___CPROVER_overflow_mult_~#c~1.base_107|) 0) (= |c_#valid| (store |c_old(#valid)| |v___CPROVER_overflow_mult_~#c~1.base_107| v_ArrVal_1964))))) is different from true [2022-11-16 11:40:07,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:07,736 INFO L93 Difference]: Finished difference Result 476 states and 601 transitions. [2022-11-16 11:40:07,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2022-11-16 11:40:07,737 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 32 states have (on average 3.8125) internal successors, (122), 31 states have internal predecessors, (122), 14 states have call successors, (27), 9 states have call predecessors, (27), 14 states have return successors, (26), 13 states have call predecessors, (26), 14 states have call successors, (26) Word has length 193 [2022-11-16 11:40:07,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:07,743 INFO L225 Difference]: With dead ends: 476 [2022-11-16 11:40:07,743 INFO L226 Difference]: Without dead ends: 339 [2022-11-16 11:40:07,745 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 276 GetRequests, 225 SyntacticMatches, 7 SemanticMatches, 44 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 632 ImplicationChecksByTransitivity, 14.6s TimeCoverageRelationStatistics Valid=177, Invalid=1659, Unknown=64, NotChecked=170, Total=2070 [2022-11-16 11:40:07,746 INFO L413 NwaCegarLoop]: 152 mSDtfsCounter, 143 mSDsluCounter, 2029 mSDsCounter, 0 mSdLazyCounter, 824 mSolverCounterSat, 95 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 150 SdHoareTripleChecker+Valid, 2181 SdHoareTripleChecker+Invalid, 3151 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 95 IncrementalHoareTripleChecker+Valid, 824 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 2232 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:07,747 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [150 Valid, 2181 Invalid, 3151 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [95 Valid, 824 Invalid, 0 Unknown, 2232 Unchecked, 1.0s Time] [2022-11-16 11:40:07,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 339 states. [2022-11-16 11:40:07,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 339 to 309. [2022-11-16 11:40:07,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 309 states, 225 states have (on average 1.1777777777777778) internal successors, (265), 233 states have internal predecessors, (265), 45 states have call successors, (45), 26 states have call predecessors, (45), 38 states have return successors, (79), 50 states have call predecessors, (79), 44 states have call successors, (79) [2022-11-16 11:40:07,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 309 states to 309 states and 389 transitions. [2022-11-16 11:40:07,781 INFO L78 Accepts]: Start accepts. Automaton has 309 states and 389 transitions. Word has length 193 [2022-11-16 11:40:07,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:07,782 INFO L495 AbstractCegarLoop]: Abstraction has 309 states and 389 transitions. [2022-11-16 11:40:07,782 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 32 states have (on average 3.8125) internal successors, (122), 31 states have internal predecessors, (122), 14 states have call successors, (27), 9 states have call predecessors, (27), 14 states have return successors, (26), 13 states have call predecessors, (26), 14 states have call successors, (26) [2022-11-16 11:40:07,783 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 389 transitions. [2022-11-16 11:40:07,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 194 [2022-11-16 11:40:07,786 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:07,786 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:07,804 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:07,999 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:07,999 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:08,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:08,000 INFO L85 PathProgramCache]: Analyzing trace with hash -16710381, now seen corresponding path program 1 times [2022-11-16 11:40:08,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:08,000 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315600319] [2022-11-16 11:40:08,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:08,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:08,094 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:08,095 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1142256267] [2022-11-16 11:40:08,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:08,095 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:08,095 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:08,096 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:08,109 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-16 11:40:10,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:10,170 INFO L263 TraceCheckSpWp]: Trace formula consists of 2717 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-16 11:40:10,175 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:10,273 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 20 proven. 3 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2022-11-16 11:40:10,273 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:10,700 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2022-11-16 11:40:10,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:10,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1315600319] [2022-11-16 11:40:10,701 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:10,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1142256267] [2022-11-16 11:40:10,701 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1142256267] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:10,701 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:10,702 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5] total 10 [2022-11-16 11:40:10,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753498655] [2022-11-16 11:40:10,702 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:10,703 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-16 11:40:10,703 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:10,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-16 11:40:10,704 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2022-11-16 11:40:10,704 INFO L87 Difference]: Start difference. First operand 309 states and 389 transitions. Second operand has 10 states, 9 states have (on average 13.555555555555555) internal successors, (122), 10 states have internal predecessors, (122), 3 states have call successors, (27), 2 states have call predecessors, (27), 4 states have return successors, (27), 2 states have call predecessors, (27), 3 states have call successors, (27) [2022-11-16 11:40:11,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:11,008 INFO L93 Difference]: Finished difference Result 476 states and 615 transitions. [2022-11-16 11:40:11,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-16 11:40:11,009 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 9 states have (on average 13.555555555555555) internal successors, (122), 10 states have internal predecessors, (122), 3 states have call successors, (27), 2 states have call predecessors, (27), 4 states have return successors, (27), 2 states have call predecessors, (27), 3 states have call successors, (27) Word has length 193 [2022-11-16 11:40:11,009 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:11,012 INFO L225 Difference]: With dead ends: 476 [2022-11-16 11:40:11,012 INFO L226 Difference]: Without dead ends: 324 [2022-11-16 11:40:11,014 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 386 GetRequests, 376 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2022-11-16 11:40:11,016 INFO L413 NwaCegarLoop]: 192 mSDtfsCounter, 37 mSDsluCounter, 1114 mSDsCounter, 0 mSdLazyCounter, 142 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 38 SdHoareTripleChecker+Valid, 1306 SdHoareTripleChecker+Invalid, 155 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 142 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:11,018 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [38 Valid, 1306 Invalid, 155 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 142 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-16 11:40:11,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 324 states. [2022-11-16 11:40:11,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 324 to 318. [2022-11-16 11:40:11,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 234 states have (on average 1.1837606837606838) internal successors, (277), 242 states have internal predecessors, (277), 45 states have call successors, (45), 26 states have call predecessors, (45), 38 states have return successors, (79), 50 states have call predecessors, (79), 44 states have call successors, (79) [2022-11-16 11:40:11,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 401 transitions. [2022-11-16 11:40:11,063 INFO L78 Accepts]: Start accepts. Automaton has 318 states and 401 transitions. Word has length 193 [2022-11-16 11:40:11,064 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:11,064 INFO L495 AbstractCegarLoop]: Abstraction has 318 states and 401 transitions. [2022-11-16 11:40:11,064 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 9 states have (on average 13.555555555555555) internal successors, (122), 10 states have internal predecessors, (122), 3 states have call successors, (27), 2 states have call predecessors, (27), 4 states have return successors, (27), 2 states have call predecessors, (27), 3 states have call successors, (27) [2022-11-16 11:40:11,064 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 401 transitions. [2022-11-16 11:40:11,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 206 [2022-11-16 11:40:11,067 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:11,067 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:11,093 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:11,293 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:11,294 INFO L420 AbstractCegarLoop]: === Iteration 21 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:11,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:11,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1529453249, now seen corresponding path program 1 times [2022-11-16 11:40:11,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:11,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47803799] [2022-11-16 11:40:11,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:11,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:11,396 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:11,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1765099820] [2022-11-16 11:40:11,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:11,399 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:11,399 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:11,400 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:11,437 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-16 11:40:12,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:12,280 INFO L263 TraceCheckSpWp]: Trace formula consists of 2768 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-16 11:40:12,284 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:12,404 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 124 trivial. 0 not checked. [2022-11-16 11:40:12,404 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:40:12,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:12,405 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [47803799] [2022-11-16 11:40:12,405 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:12,405 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1765099820] [2022-11-16 11:40:12,407 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1765099820] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:40:12,407 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:40:12,408 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2022-11-16 11:40:12,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377149699] [2022-11-16 11:40:12,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:40:12,409 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-11-16 11:40:12,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:12,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-11-16 11:40:12,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2022-11-16 11:40:12,410 INFO L87 Difference]: Start difference. First operand 318 states and 401 transitions. Second operand has 9 states, 8 states have (on average 13.375) internal successors, (107), 9 states have internal predecessors, (107), 6 states have call successors, (26), 2 states have call predecessors, (26), 4 states have return successors, (25), 5 states have call predecessors, (25), 6 states have call successors, (25) [2022-11-16 11:40:12,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:12,857 INFO L93 Difference]: Finished difference Result 477 states and 596 transitions. [2022-11-16 11:40:12,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-16 11:40:12,858 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 8 states have (on average 13.375) internal successors, (107), 9 states have internal predecessors, (107), 6 states have call successors, (26), 2 states have call predecessors, (26), 4 states have return successors, (25), 5 states have call predecessors, (25), 6 states have call successors, (25) Word has length 205 [2022-11-16 11:40:12,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:12,861 INFO L225 Difference]: With dead ends: 477 [2022-11-16 11:40:12,861 INFO L226 Difference]: Without dead ends: 316 [2022-11-16 11:40:12,863 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 212 GetRequests, 199 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=165, Unknown=0, NotChecked=0, Total=210 [2022-11-16 11:40:12,863 INFO L413 NwaCegarLoop]: 162 mSDtfsCounter, 233 mSDsluCounter, 881 mSDsCounter, 0 mSdLazyCounter, 287 mSolverCounterSat, 50 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 235 SdHoareTripleChecker+Valid, 1043 SdHoareTripleChecker+Invalid, 337 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 50 IncrementalHoareTripleChecker+Valid, 287 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:12,864 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [235 Valid, 1043 Invalid, 337 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [50 Valid, 287 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-16 11:40:12,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 316 states. [2022-11-16 11:40:12,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 316 to 316. [2022-11-16 11:40:12,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 316 states, 233 states have (on average 1.1802575107296138) internal successors, (275), 240 states have internal predecessors, (275), 45 states have call successors, (45), 26 states have call predecessors, (45), 37 states have return successors, (78), 50 states have call predecessors, (78), 44 states have call successors, (78) [2022-11-16 11:40:12,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 398 transitions. [2022-11-16 11:40:12,898 INFO L78 Accepts]: Start accepts. Automaton has 316 states and 398 transitions. Word has length 205 [2022-11-16 11:40:12,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:12,899 INFO L495 AbstractCegarLoop]: Abstraction has 316 states and 398 transitions. [2022-11-16 11:40:12,899 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 8 states have (on average 13.375) internal successors, (107), 9 states have internal predecessors, (107), 6 states have call successors, (26), 2 states have call predecessors, (26), 4 states have return successors, (25), 5 states have call predecessors, (25), 6 states have call successors, (25) [2022-11-16 11:40:12,899 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 398 transitions. [2022-11-16 11:40:12,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2022-11-16 11:40:12,902 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:12,903 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:12,917 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:13,115 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20,19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:13,115 INFO L420 AbstractCegarLoop]: === Iteration 22 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:13,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:13,116 INFO L85 PathProgramCache]: Analyzing trace with hash 957801786, now seen corresponding path program 1 times [2022-11-16 11:40:13,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:13,116 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428956752] [2022-11-16 11:40:13,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:13,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:13,197 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:13,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [157802944] [2022-11-16 11:40:13,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:13,198 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:13,198 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:13,199 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:13,210 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-16 11:40:14,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:14,047 INFO L263 TraceCheckSpWp]: Trace formula consists of 2881 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-16 11:40:14,053 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:14,138 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 17 proven. 1 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2022-11-16 11:40:14,138 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:14,760 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 189 trivial. 0 not checked. [2022-11-16 11:40:14,760 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:14,760 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428956752] [2022-11-16 11:40:14,761 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:14,761 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [157802944] [2022-11-16 11:40:14,761 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [157802944] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:14,761 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:14,761 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 13 [2022-11-16 11:40:14,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380309137] [2022-11-16 11:40:14,761 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:14,762 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2022-11-16 11:40:14,762 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:14,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-11-16 11:40:14,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2022-11-16 11:40:14,763 INFO L87 Difference]: Start difference. First operand 316 states and 398 transitions. Second operand has 13 states, 11 states have (on average 10.090909090909092) internal successors, (111), 13 states have internal predecessors, (111), 6 states have call successors, (28), 2 states have call predecessors, (28), 5 states have return successors, (28), 6 states have call predecessors, (28), 6 states have call successors, (28) [2022-11-16 11:40:14,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:14,954 INFO L93 Difference]: Finished difference Result 470 states and 584 transitions. [2022-11-16 11:40:14,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-16 11:40:14,958 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 11 states have (on average 10.090909090909092) internal successors, (111), 13 states have internal predecessors, (111), 6 states have call successors, (28), 2 states have call predecessors, (28), 5 states have return successors, (28), 6 states have call predecessors, (28), 6 states have call successors, (28) Word has length 226 [2022-11-16 11:40:14,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:14,961 INFO L225 Difference]: With dead ends: 470 [2022-11-16 11:40:14,962 INFO L226 Difference]: Without dead ends: 319 [2022-11-16 11:40:14,963 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 453 GetRequests, 438 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=60, Invalid=180, Unknown=0, NotChecked=0, Total=240 [2022-11-16 11:40:14,964 INFO L413 NwaCegarLoop]: 191 mSDtfsCounter, 33 mSDsluCounter, 1122 mSDsCounter, 0 mSdLazyCounter, 77 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 35 SdHoareTripleChecker+Valid, 1313 SdHoareTripleChecker+Invalid, 80 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 77 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:14,964 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [35 Valid, 1313 Invalid, 80 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 77 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-16 11:40:14,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2022-11-16 11:40:14,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 318. [2022-11-16 11:40:14,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 235 states have (on average 1.1787234042553192) internal successors, (277), 242 states have internal predecessors, (277), 45 states have call successors, (45), 26 states have call predecessors, (45), 37 states have return successors, (78), 50 states have call predecessors, (78), 44 states have call successors, (78) [2022-11-16 11:40:14,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 400 transitions. [2022-11-16 11:40:14,997 INFO L78 Accepts]: Start accepts. Automaton has 318 states and 400 transitions. Word has length 226 [2022-11-16 11:40:14,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:14,998 INFO L495 AbstractCegarLoop]: Abstraction has 318 states and 400 transitions. [2022-11-16 11:40:14,998 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 11 states have (on average 10.090909090909092) internal successors, (111), 13 states have internal predecessors, (111), 6 states have call successors, (28), 2 states have call predecessors, (28), 5 states have return successors, (28), 6 states have call predecessors, (28), 6 states have call successors, (28) [2022-11-16 11:40:14,999 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 400 transitions. [2022-11-16 11:40:15,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2022-11-16 11:40:15,002 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:15,002 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:15,020 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:15,215 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:15,215 INFO L420 AbstractCegarLoop]: === Iteration 23 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:15,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:15,215 INFO L85 PathProgramCache]: Analyzing trace with hash -2088645763, now seen corresponding path program 1 times [2022-11-16 11:40:15,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:15,216 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769426650] [2022-11-16 11:40:15,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:15,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:15,305 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:15,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1921207626] [2022-11-16 11:40:15,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:15,306 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:15,306 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:15,307 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:15,319 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-16 11:40:16,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:16,248 INFO L263 TraceCheckSpWp]: Trace formula consists of 2936 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-16 11:40:16,252 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:16,377 INFO L134 CoverageAnalysis]: Checked inductivity of 186 backedges. 17 proven. 4 refuted. 0 times theorem prover too weak. 165 trivial. 0 not checked. [2022-11-16 11:40:16,377 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:17,004 INFO L134 CoverageAnalysis]: Checked inductivity of 186 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2022-11-16 11:40:17,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:17,005 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769426650] [2022-11-16 11:40:17,005 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:17,005 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1921207626] [2022-11-16 11:40:17,006 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1921207626] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:17,006 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:17,006 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 16 [2022-11-16 11:40:17,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1429675947] [2022-11-16 11:40:17,010 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:17,011 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-11-16 11:40:17,011 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:17,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-11-16 11:40:17,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=190, Unknown=0, NotChecked=0, Total=240 [2022-11-16 11:40:17,012 INFO L87 Difference]: Start difference. First operand 318 states and 400 transitions. Second operand has 16 states, 13 states have (on average 9.692307692307692) internal successors, (126), 16 states have internal predecessors, (126), 7 states have call successors, (32), 2 states have call predecessors, (32), 5 states have return successors, (32), 6 states have call predecessors, (32), 7 states have call successors, (32) [2022-11-16 11:40:17,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:17,281 INFO L93 Difference]: Finished difference Result 474 states and 588 transitions. [2022-11-16 11:40:17,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-16 11:40:17,282 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 13 states have (on average 9.692307692307692) internal successors, (126), 16 states have internal predecessors, (126), 7 states have call successors, (32), 2 states have call predecessors, (32), 5 states have return successors, (32), 6 states have call predecessors, (32), 7 states have call successors, (32) Word has length 234 [2022-11-16 11:40:17,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:17,285 INFO L225 Difference]: With dead ends: 474 [2022-11-16 11:40:17,285 INFO L226 Difference]: Without dead ends: 321 [2022-11-16 11:40:17,286 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 451 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=74, Invalid=268, Unknown=0, NotChecked=0, Total=342 [2022-11-16 11:40:17,287 INFO L413 NwaCegarLoop]: 191 mSDtfsCounter, 47 mSDsluCounter, 1833 mSDsCounter, 0 mSdLazyCounter, 131 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 62 SdHoareTripleChecker+Valid, 2024 SdHoareTripleChecker+Invalid, 136 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 131 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:17,288 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [62 Valid, 2024 Invalid, 136 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 131 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-16 11:40:17,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2022-11-16 11:40:17,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 320. [2022-11-16 11:40:17,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 320 states, 237 states have (on average 1.1772151898734178) internal successors, (279), 244 states have internal predecessors, (279), 45 states have call successors, (45), 26 states have call predecessors, (45), 37 states have return successors, (78), 50 states have call predecessors, (78), 44 states have call successors, (78) [2022-11-16 11:40:17,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 320 states to 320 states and 402 transitions. [2022-11-16 11:40:17,352 INFO L78 Accepts]: Start accepts. Automaton has 320 states and 402 transitions. Word has length 234 [2022-11-16 11:40:17,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:17,353 INFO L495 AbstractCegarLoop]: Abstraction has 320 states and 402 transitions. [2022-11-16 11:40:17,353 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 13 states have (on average 9.692307692307692) internal successors, (126), 16 states have internal predecessors, (126), 7 states have call successors, (32), 2 states have call predecessors, (32), 5 states have return successors, (32), 6 states have call predecessors, (32), 7 states have call successors, (32) [2022-11-16 11:40:17,353 INFO L276 IsEmpty]: Start isEmpty. Operand 320 states and 402 transitions. [2022-11-16 11:40:17,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 225 [2022-11-16 11:40:17,358 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:17,359 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:17,381 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:17,571 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22,21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:17,572 INFO L420 AbstractCegarLoop]: === Iteration 24 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:17,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:17,573 INFO L85 PathProgramCache]: Analyzing trace with hash 441693325, now seen corresponding path program 1 times [2022-11-16 11:40:17,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:17,573 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889766636] [2022-11-16 11:40:17,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:17,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:17,674 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:17,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1817674382] [2022-11-16 11:40:17,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:17,675 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:17,675 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:17,676 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:17,699 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-11-16 11:40:18,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:18,628 INFO L263 TraceCheckSpWp]: Trace formula consists of 2947 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-16 11:40:18,632 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:18,754 INFO L134 CoverageAnalysis]: Checked inductivity of 185 backedges. 17 proven. 9 refuted. 0 times theorem prover too weak. 159 trivial. 0 not checked. [2022-11-16 11:40:18,754 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:19,440 INFO L134 CoverageAnalysis]: Checked inductivity of 185 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 176 trivial. 0 not checked. [2022-11-16 11:40:19,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:19,440 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889766636] [2022-11-16 11:40:19,441 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:19,441 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1817674382] [2022-11-16 11:40:19,441 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1817674382] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:19,441 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:19,441 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 17 [2022-11-16 11:40:19,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1522539148] [2022-11-16 11:40:19,442 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:19,443 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-11-16 11:40:19,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:19,443 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-16 11:40:19,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=213, Unknown=0, NotChecked=0, Total=272 [2022-11-16 11:40:19,444 INFO L87 Difference]: Start difference. First operand 320 states and 402 transitions. Second operand has 17 states, 15 states have (on average 8.266666666666667) internal successors, (124), 17 states have internal predecessors, (124), 6 states have call successors, (30), 2 states have call predecessors, (30), 5 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2022-11-16 11:40:19,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:19,720 INFO L93 Difference]: Finished difference Result 478 states and 592 transitions. [2022-11-16 11:40:19,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-16 11:40:19,725 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 15 states have (on average 8.266666666666667) internal successors, (124), 17 states have internal predecessors, (124), 6 states have call successors, (30), 2 states have call predecessors, (30), 5 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) Word has length 224 [2022-11-16 11:40:19,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:19,728 INFO L225 Difference]: With dead ends: 478 [2022-11-16 11:40:19,728 INFO L226 Difference]: Without dead ends: 323 [2022-11-16 11:40:19,729 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 449 GetRequests, 430 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=85, Invalid=295, Unknown=0, NotChecked=0, Total=380 [2022-11-16 11:40:19,730 INFO L413 NwaCegarLoop]: 191 mSDtfsCounter, 43 mSDsluCounter, 2055 mSDsCounter, 0 mSdLazyCounter, 154 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 45 SdHoareTripleChecker+Valid, 2246 SdHoareTripleChecker+Invalid, 161 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 154 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:19,730 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [45 Valid, 2246 Invalid, 161 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 154 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-16 11:40:19,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states. [2022-11-16 11:40:19,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 322. [2022-11-16 11:40:19,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 239 states have (on average 1.1757322175732217) internal successors, (281), 246 states have internal predecessors, (281), 45 states have call successors, (45), 26 states have call predecessors, (45), 37 states have return successors, (78), 50 states have call predecessors, (78), 44 states have call successors, (78) [2022-11-16 11:40:19,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 404 transitions. [2022-11-16 11:40:19,763 INFO L78 Accepts]: Start accepts. Automaton has 322 states and 404 transitions. Word has length 224 [2022-11-16 11:40:19,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:19,764 INFO L495 AbstractCegarLoop]: Abstraction has 322 states and 404 transitions. [2022-11-16 11:40:19,764 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 15 states have (on average 8.266666666666667) internal successors, (124), 17 states have internal predecessors, (124), 6 states have call successors, (30), 2 states have call predecessors, (30), 5 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2022-11-16 11:40:19,764 INFO L276 IsEmpty]: Start isEmpty. Operand 322 states and 404 transitions. [2022-11-16 11:40:19,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2022-11-16 11:40:19,767 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:19,768 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:19,787 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:19,981 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable23 [2022-11-16 11:40:19,982 INFO L420 AbstractCegarLoop]: === Iteration 25 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:19,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:19,982 INFO L85 PathProgramCache]: Analyzing trace with hash 720148011, now seen corresponding path program 2 times [2022-11-16 11:40:19,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:19,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323164702] [2022-11-16 11:40:19,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:19,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:20,080 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:20,080 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1742046731] [2022-11-16 11:40:20,080 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:40:20,080 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:20,081 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:20,082 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:20,097 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-16 11:40:22,704 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:40:22,704 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:40:22,719 INFO L263 TraceCheckSpWp]: Trace formula consists of 2966 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-16 11:40:22,723 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:22,869 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 17 proven. 16 refuted. 0 times theorem prover too weak. 159 trivial. 0 not checked. [2022-11-16 11:40:22,869 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:23,589 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 176 trivial. 0 not checked. [2022-11-16 11:40:23,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:23,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323164702] [2022-11-16 11:40:23,590 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:23,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1742046731] [2022-11-16 11:40:23,590 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1742046731] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:23,590 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:23,590 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 19 [2022-11-16 11:40:23,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1935514308] [2022-11-16 11:40:23,590 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:23,594 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-11-16 11:40:23,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:23,595 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-16 11:40:23,595 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=271, Unknown=0, NotChecked=0, Total=342 [2022-11-16 11:40:23,596 INFO L87 Difference]: Start difference. First operand 322 states and 404 transitions. Second operand has 19 states, 17 states have (on average 7.529411764705882) internal successors, (128), 19 states have internal predecessors, (128), 6 states have call successors, (30), 2 states have call predecessors, (30), 5 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2022-11-16 11:40:23,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:23,947 INFO L93 Difference]: Finished difference Result 482 states and 596 transitions. [2022-11-16 11:40:23,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-16 11:40:23,948 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 17 states have (on average 7.529411764705882) internal successors, (128), 19 states have internal predecessors, (128), 6 states have call successors, (30), 2 states have call predecessors, (30), 5 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) Word has length 226 [2022-11-16 11:40:23,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:23,951 INFO L225 Difference]: With dead ends: 482 [2022-11-16 11:40:23,951 INFO L226 Difference]: Without dead ends: 325 [2022-11-16 11:40:23,953 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 453 GetRequests, 432 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=99, Invalid=363, Unknown=0, NotChecked=0, Total=462 [2022-11-16 11:40:23,954 INFO L413 NwaCegarLoop]: 191 mSDtfsCounter, 66 mSDsluCounter, 2059 mSDsCounter, 0 mSdLazyCounter, 178 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 68 SdHoareTripleChecker+Valid, 2250 SdHoareTripleChecker+Invalid, 189 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 178 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:23,955 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [68 Valid, 2250 Invalid, 189 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 178 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-16 11:40:23,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2022-11-16 11:40:23,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 324. [2022-11-16 11:40:24,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 324 states, 241 states have (on average 1.1742738589211619) internal successors, (283), 248 states have internal predecessors, (283), 45 states have call successors, (45), 26 states have call predecessors, (45), 37 states have return successors, (78), 50 states have call predecessors, (78), 44 states have call successors, (78) [2022-11-16 11:40:24,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 406 transitions. [2022-11-16 11:40:24,008 INFO L78 Accepts]: Start accepts. Automaton has 324 states and 406 transitions. Word has length 226 [2022-11-16 11:40:24,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:24,009 INFO L495 AbstractCegarLoop]: Abstraction has 324 states and 406 transitions. [2022-11-16 11:40:24,010 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 17 states have (on average 7.529411764705882) internal successors, (128), 19 states have internal predecessors, (128), 6 states have call successors, (30), 2 states have call predecessors, (30), 5 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2022-11-16 11:40:24,010 INFO L276 IsEmpty]: Start isEmpty. Operand 324 states and 406 transitions. [2022-11-16 11:40:24,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2022-11-16 11:40:24,013 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:24,014 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:24,033 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:24,227 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2022-11-16 11:40:24,227 INFO L420 AbstractCegarLoop]: === Iteration 26 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:24,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:24,228 INFO L85 PathProgramCache]: Analyzing trace with hash -631418446, now seen corresponding path program 2 times [2022-11-16 11:40:24,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:24,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160475835] [2022-11-16 11:40:24,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:24,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:24,339 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:24,340 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2090074839] [2022-11-16 11:40:24,340 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:40:24,340 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:24,340 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:24,341 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:24,375 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-16 11:40:25,332 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:40:25,332 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:40:25,345 INFO L263 TraceCheckSpWp]: Trace formula consists of 2957 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-16 11:40:25,349 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:25,694 INFO L134 CoverageAnalysis]: Checked inductivity of 214 backedges. 28 proven. 47 refuted. 0 times theorem prover too weak. 139 trivial. 0 not checked. [2022-11-16 11:40:25,694 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:26,635 INFO L134 CoverageAnalysis]: Checked inductivity of 214 backedges. 11 proven. 33 refuted. 0 times theorem prover too weak. 170 trivial. 0 not checked. [2022-11-16 11:40:26,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:26,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160475835] [2022-11-16 11:40:26,635 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:26,636 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2090074839] [2022-11-16 11:40:26,636 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2090074839] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:26,636 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:26,636 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 8] total 23 [2022-11-16 11:40:26,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288881621] [2022-11-16 11:40:26,637 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:26,638 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-11-16 11:40:26,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:26,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-16 11:40:26,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=422, Unknown=0, NotChecked=0, Total=506 [2022-11-16 11:40:26,639 INFO L87 Difference]: Start difference. First operand 324 states and 406 transitions. Second operand has 23 states, 22 states have (on average 6.590909090909091) internal successors, (145), 23 states have internal predecessors, (145), 4 states have call successors, (27), 2 states have call predecessors, (27), 6 states have return successors, (28), 4 states have call predecessors, (28), 4 states have call successors, (28) [2022-11-16 11:40:28,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:28,953 INFO L93 Difference]: Finished difference Result 528 states and 701 transitions. [2022-11-16 11:40:28,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-16 11:40:28,954 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 22 states have (on average 6.590909090909091) internal successors, (145), 23 states have internal predecessors, (145), 4 states have call successors, (27), 2 states have call predecessors, (27), 6 states have return successors, (28), 4 states have call predecessors, (28), 4 states have call successors, (28) Word has length 234 [2022-11-16 11:40:28,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:28,957 INFO L225 Difference]: With dead ends: 528 [2022-11-16 11:40:28,957 INFO L226 Difference]: Without dead ends: 361 [2022-11-16 11:40:28,958 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 483 GetRequests, 450 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=192, Invalid=998, Unknown=0, NotChecked=0, Total=1190 [2022-11-16 11:40:28,960 INFO L413 NwaCegarLoop]: 193 mSDtfsCounter, 130 mSDsluCounter, 2456 mSDsCounter, 0 mSdLazyCounter, 796 mSolverCounterSat, 32 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 130 SdHoareTripleChecker+Valid, 2649 SdHoareTripleChecker+Invalid, 828 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 32 IncrementalHoareTripleChecker+Valid, 796 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:28,964 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [130 Valid, 2649 Invalid, 828 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [32 Valid, 796 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-11-16 11:40:28,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 361 states. [2022-11-16 11:40:29,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 361 to 342. [2022-11-16 11:40:29,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 342 states, 259 states have (on average 1.1853281853281854) internal successors, (307), 266 states have internal predecessors, (307), 45 states have call successors, (45), 26 states have call predecessors, (45), 37 states have return successors, (78), 50 states have call predecessors, (78), 44 states have call successors, (78) [2022-11-16 11:40:29,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342 states to 342 states and 430 transitions. [2022-11-16 11:40:29,008 INFO L78 Accepts]: Start accepts. Automaton has 342 states and 430 transitions. Word has length 234 [2022-11-16 11:40:29,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:29,009 INFO L495 AbstractCegarLoop]: Abstraction has 342 states and 430 transitions. [2022-11-16 11:40:29,009 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 22 states have (on average 6.590909090909091) internal successors, (145), 23 states have internal predecessors, (145), 4 states have call successors, (27), 2 states have call predecessors, (27), 6 states have return successors, (28), 4 states have call predecessors, (28), 4 states have call successors, (28) [2022-11-16 11:40:29,010 INFO L276 IsEmpty]: Start isEmpty. Operand 342 states and 430 transitions. [2022-11-16 11:40:29,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 296 [2022-11-16 11:40:29,013 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:29,013 INFO L195 NwaCegarLoop]: trace histogram [13, 10, 10, 10, 10, 8, 8, 8, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:29,031 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2022-11-16 11:40:29,226 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable25 [2022-11-16 11:40:29,226 INFO L420 AbstractCegarLoop]: === Iteration 27 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:29,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:29,227 INFO L85 PathProgramCache]: Analyzing trace with hash -1281085344, now seen corresponding path program 1 times [2022-11-16 11:40:29,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:29,227 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002093269] [2022-11-16 11:40:29,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:29,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:29,322 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:29,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [396700771] [2022-11-16 11:40:29,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:29,323 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:29,323 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:29,324 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:29,343 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-11-16 11:40:30,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:30,268 INFO L263 TraceCheckSpWp]: Trace formula consists of 3286 conjuncts, 38 conjunts are in the unsatisfiable core [2022-11-16 11:40:30,274 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:30,424 INFO L134 CoverageAnalysis]: Checked inductivity of 544 backedges. 163 proven. 25 refuted. 0 times theorem prover too weak. 356 trivial. 0 not checked. [2022-11-16 11:40:30,424 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:31,175 INFO L134 CoverageAnalysis]: Checked inductivity of 544 backedges. 0 proven. 99 refuted. 0 times theorem prover too weak. 445 trivial. 0 not checked. [2022-11-16 11:40:31,176 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:31,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002093269] [2022-11-16 11:40:31,176 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:31,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [396700771] [2022-11-16 11:40:31,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [396700771] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:31,176 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:31,177 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 21 [2022-11-16 11:40:31,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1534861014] [2022-11-16 11:40:31,177 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:31,178 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 21 states [2022-11-16 11:40:31,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:31,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2022-11-16 11:40:31,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=336, Unknown=0, NotChecked=0, Total=420 [2022-11-16 11:40:31,179 INFO L87 Difference]: Start difference. First operand 342 states and 430 transitions. Second operand has 21 states, 19 states have (on average 8.68421052631579) internal successors, (165), 21 states have internal predecessors, (165), 6 states have call successors, (39), 2 states have call predecessors, (39), 5 states have return successors, (40), 6 states have call predecessors, (40), 6 states have call successors, (40) [2022-11-16 11:40:31,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:31,603 INFO L93 Difference]: Finished difference Result 522 states and 648 transitions. [2022-11-16 11:40:31,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-16 11:40:31,604 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 19 states have (on average 8.68421052631579) internal successors, (165), 21 states have internal predecessors, (165), 6 states have call successors, (39), 2 states have call predecessors, (39), 5 states have return successors, (40), 6 states have call predecessors, (40), 6 states have call successors, (40) Word has length 295 [2022-11-16 11:40:31,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:31,612 INFO L225 Difference]: With dead ends: 522 [2022-11-16 11:40:31,612 INFO L226 Difference]: Without dead ends: 345 [2022-11-16 11:40:31,614 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 591 GetRequests, 568 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 118 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=114, Invalid=438, Unknown=0, NotChecked=0, Total=552 [2022-11-16 11:40:31,615 INFO L413 NwaCegarLoop]: 191 mSDtfsCounter, 69 mSDsluCounter, 2061 mSDsCounter, 0 mSdLazyCounter, 199 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 71 SdHoareTripleChecker+Valid, 2252 SdHoareTripleChecker+Invalid, 212 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 199 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:31,616 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [71 Valid, 2252 Invalid, 212 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 199 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-16 11:40:31,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 345 states. [2022-11-16 11:40:31,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 345 to 344. [2022-11-16 11:40:31,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 344 states, 261 states have (on average 1.1839080459770115) internal successors, (309), 268 states have internal predecessors, (309), 45 states have call successors, (45), 26 states have call predecessors, (45), 37 states have return successors, (78), 50 states have call predecessors, (78), 44 states have call successors, (78) [2022-11-16 11:40:31,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 344 states to 344 states and 432 transitions. [2022-11-16 11:40:31,655 INFO L78 Accepts]: Start accepts. Automaton has 344 states and 432 transitions. Word has length 295 [2022-11-16 11:40:31,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:31,656 INFO L495 AbstractCegarLoop]: Abstraction has 344 states and 432 transitions. [2022-11-16 11:40:31,656 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 21 states, 19 states have (on average 8.68421052631579) internal successors, (165), 21 states have internal predecessors, (165), 6 states have call successors, (39), 2 states have call predecessors, (39), 5 states have return successors, (40), 6 states have call predecessors, (40), 6 states have call successors, (40) [2022-11-16 11:40:31,656 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 432 transitions. [2022-11-16 11:40:31,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 306 [2022-11-16 11:40:31,659 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:31,660 INFO L195 NwaCegarLoop]: trace histogram [13, 12, 12, 10, 10, 8, 8, 8, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:31,674 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:31,874 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2022-11-16 11:40:31,874 INFO L420 AbstractCegarLoop]: === Iteration 28 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:31,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:31,875 INFO L85 PathProgramCache]: Analyzing trace with hash 711140571, now seen corresponding path program 1 times [2022-11-16 11:40:31,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:31,875 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013171955] [2022-11-16 11:40:31,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:31,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:31,976 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:31,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1636730330] [2022-11-16 11:40:31,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:31,977 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:31,977 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:31,979 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:31,999 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-16 11:40:32,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:32,960 INFO L263 TraceCheckSpWp]: Trace formula consists of 3296 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-16 11:40:32,968 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:33,154 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 187 proven. 36 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2022-11-16 11:40:33,155 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:34,181 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 469 trivial. 0 not checked. [2022-11-16 11:40:34,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:34,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013171955] [2022-11-16 11:40:34,182 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:34,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1636730330] [2022-11-16 11:40:34,182 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1636730330] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:34,182 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:34,182 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 23 [2022-11-16 11:40:34,182 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19596170] [2022-11-16 11:40:34,183 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:34,184 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-11-16 11:40:34,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:34,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-16 11:40:34,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=408, Unknown=0, NotChecked=0, Total=506 [2022-11-16 11:40:34,185 INFO L87 Difference]: Start difference. First operand 344 states and 432 transitions. Second operand has 23 states, 21 states have (on average 7.809523809523809) internal successors, (164), 23 states have internal predecessors, (164), 6 states have call successors, (37), 2 states have call predecessors, (37), 5 states have return successors, (38), 6 states have call predecessors, (38), 6 states have call successors, (38) [2022-11-16 11:40:34,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:34,615 INFO L93 Difference]: Finished difference Result 526 states and 652 transitions. [2022-11-16 11:40:34,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-11-16 11:40:34,616 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 21 states have (on average 7.809523809523809) internal successors, (164), 23 states have internal predecessors, (164), 6 states have call successors, (37), 2 states have call predecessors, (37), 5 states have return successors, (38), 6 states have call predecessors, (38), 6 states have call successors, (38) Word has length 305 [2022-11-16 11:40:34,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:34,619 INFO L225 Difference]: With dead ends: 526 [2022-11-16 11:40:34,619 INFO L226 Difference]: Without dead ends: 347 [2022-11-16 11:40:34,620 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 611 GetRequests, 586 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 147 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=130, Invalid=520, Unknown=0, NotChecked=0, Total=650 [2022-11-16 11:40:34,621 INFO L413 NwaCegarLoop]: 191 mSDtfsCounter, 57 mSDsluCounter, 1880 mSDsCounter, 0 mSdLazyCounter, 204 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 59 SdHoareTripleChecker+Valid, 2071 SdHoareTripleChecker+Invalid, 219 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 204 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:34,622 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [59 Valid, 2071 Invalid, 219 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 204 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-16 11:40:34,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 347 states. [2022-11-16 11:40:34,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 347 to 346. [2022-11-16 11:40:34,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 346 states, 263 states have (on average 1.182509505703422) internal successors, (311), 270 states have internal predecessors, (311), 45 states have call successors, (45), 26 states have call predecessors, (45), 37 states have return successors, (78), 50 states have call predecessors, (78), 44 states have call successors, (78) [2022-11-16 11:40:34,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 434 transitions. [2022-11-16 11:40:34,656 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 434 transitions. Word has length 305 [2022-11-16 11:40:34,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:34,656 INFO L495 AbstractCegarLoop]: Abstraction has 346 states and 434 transitions. [2022-11-16 11:40:34,657 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 21 states have (on average 7.809523809523809) internal successors, (164), 23 states have internal predecessors, (164), 6 states have call successors, (37), 2 states have call predecessors, (37), 5 states have return successors, (38), 6 states have call predecessors, (38), 6 states have call successors, (38) [2022-11-16 11:40:34,657 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 434 transitions. [2022-11-16 11:40:34,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 304 [2022-11-16 11:40:34,660 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:34,661 INFO L195 NwaCegarLoop]: trace histogram [14, 14, 13, 10, 10, 8, 8, 8, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:34,682 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:34,881 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2022-11-16 11:40:34,882 INFO L420 AbstractCegarLoop]: === Iteration 29 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:34,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:34,882 INFO L85 PathProgramCache]: Analyzing trace with hash 1955674728, now seen corresponding path program 2 times [2022-11-16 11:40:34,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:34,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769791093] [2022-11-16 11:40:34,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:34,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:34,977 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:34,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [667772345] [2022-11-16 11:40:34,978 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:40:34,978 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:34,978 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:34,980 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:35,011 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2022-11-16 11:40:36,381 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:40:36,381 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:40:36,397 INFO L263 TraceCheckSpWp]: Trace formula consists of 3362 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-16 11:40:36,402 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:36,599 INFO L134 CoverageAnalysis]: Checked inductivity of 644 backedges. 215 proven. 49 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2022-11-16 11:40:36,599 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:37,558 INFO L134 CoverageAnalysis]: Checked inductivity of 644 backedges. 0 proven. 175 refuted. 0 times theorem prover too weak. 469 trivial. 0 not checked. [2022-11-16 11:40:37,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:37,558 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [769791093] [2022-11-16 11:40:37,559 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:37,559 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [667772345] [2022-11-16 11:40:37,559 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [667772345] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:37,559 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:37,559 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 25 [2022-11-16 11:40:37,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998623475] [2022-11-16 11:40:37,560 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:37,560 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2022-11-16 11:40:37,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:37,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-11-16 11:40:37,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=113, Invalid=487, Unknown=0, NotChecked=0, Total=600 [2022-11-16 11:40:37,562 INFO L87 Difference]: Start difference. First operand 346 states and 434 transitions. Second operand has 25 states, 23 states have (on average 7.521739130434782) internal successors, (173), 25 states have internal predecessors, (173), 6 states have call successors, (39), 2 states have call predecessors, (39), 5 states have return successors, (40), 6 states have call predecessors, (40), 6 states have call successors, (40) [2022-11-16 11:40:38,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:38,030 INFO L93 Difference]: Finished difference Result 530 states and 656 transitions. [2022-11-16 11:40:38,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-16 11:40:38,031 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 23 states have (on average 7.521739130434782) internal successors, (173), 25 states have internal predecessors, (173), 6 states have call successors, (39), 2 states have call predecessors, (39), 5 states have return successors, (40), 6 states have call predecessors, (40), 6 states have call successors, (40) Word has length 303 [2022-11-16 11:40:38,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:38,034 INFO L225 Difference]: With dead ends: 530 [2022-11-16 11:40:38,034 INFO L226 Difference]: Without dead ends: 349 [2022-11-16 11:40:38,035 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 607 GetRequests, 580 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 179 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=147, Invalid=609, Unknown=0, NotChecked=0, Total=756 [2022-11-16 11:40:38,036 INFO L413 NwaCegarLoop]: 191 mSDtfsCounter, 75 mSDsluCounter, 2441 mSDsCounter, 0 mSdLazyCounter, 267 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 77 SdHoareTripleChecker+Valid, 2632 SdHoareTripleChecker+Invalid, 284 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 267 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:38,036 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [77 Valid, 2632 Invalid, 284 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [17 Valid, 267 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-16 11:40:38,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 349 states. [2022-11-16 11:40:38,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 349 to 348. [2022-11-16 11:40:38,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 348 states, 265 states have (on average 1.181132075471698) internal successors, (313), 272 states have internal predecessors, (313), 45 states have call successors, (45), 26 states have call predecessors, (45), 37 states have return successors, (78), 50 states have call predecessors, (78), 44 states have call successors, (78) [2022-11-16 11:40:38,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 348 states to 348 states and 436 transitions. [2022-11-16 11:40:38,068 INFO L78 Accepts]: Start accepts. Automaton has 348 states and 436 transitions. Word has length 303 [2022-11-16 11:40:38,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:38,069 INFO L495 AbstractCegarLoop]: Abstraction has 348 states and 436 transitions. [2022-11-16 11:40:38,070 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 23 states have (on average 7.521739130434782) internal successors, (173), 25 states have internal predecessors, (173), 6 states have call successors, (39), 2 states have call predecessors, (39), 5 states have return successors, (40), 6 states have call predecessors, (40), 6 states have call successors, (40) [2022-11-16 11:40:38,070 INFO L276 IsEmpty]: Start isEmpty. Operand 348 states and 436 transitions. [2022-11-16 11:40:38,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 308 [2022-11-16 11:40:38,073 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:38,073 INFO L195 NwaCegarLoop]: trace histogram [16, 16, 13, 10, 10, 8, 8, 8, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:38,092 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:38,286 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2022-11-16 11:40:38,287 INFO L420 AbstractCegarLoop]: === Iteration 30 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:38,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:38,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1011762284, now seen corresponding path program 3 times [2022-11-16 11:40:38,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:38,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466572317] [2022-11-16 11:40:38,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:38,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:38,395 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:38,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [159866372] [2022-11-16 11:40:38,395 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:40:38,396 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:38,396 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:38,397 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:38,419 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2022-11-16 11:40:41,069 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-11-16 11:40:41,069 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:40:41,080 INFO L263 TraceCheckSpWp]: Trace formula consists of 2311 conjuncts, 81 conjunts are in the unsatisfiable core [2022-11-16 11:40:41,086 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:41,463 INFO L134 CoverageAnalysis]: Checked inductivity of 706 backedges. 77 proven. 40 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2022-11-16 11:40:41,463 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:40:42,609 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:40:42,610 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 58 treesize of output 69 [2022-11-16 11:40:43,067 INFO L134 CoverageAnalysis]: Checked inductivity of 706 backedges. 59 proven. 50 refuted. 0 times theorem prover too weak. 597 trivial. 0 not checked. [2022-11-16 11:40:43,068 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:43,068 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466572317] [2022-11-16 11:40:43,068 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:43,068 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [159866372] [2022-11-16 11:40:43,069 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [159866372] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:40:43,069 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:40:43,069 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12] total 19 [2022-11-16 11:40:43,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113522699] [2022-11-16 11:40:43,069 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:40:43,070 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-11-16 11:40:43,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:43,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-16 11:40:43,072 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=290, Unknown=0, NotChecked=0, Total=342 [2022-11-16 11:40:43,072 INFO L87 Difference]: Start difference. First operand 348 states and 436 transitions. Second operand has 19 states, 16 states have (on average 8.4375) internal successors, (135), 17 states have internal predecessors, (135), 9 states have call successors, (37), 4 states have call predecessors, (37), 5 states have return successors, (35), 6 states have call predecessors, (35), 9 states have call successors, (35) [2022-11-16 11:40:45,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:45,412 INFO L93 Difference]: Finished difference Result 473 states and 623 transitions. [2022-11-16 11:40:45,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-16 11:40:45,414 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 16 states have (on average 8.4375) internal successors, (135), 17 states have internal predecessors, (135), 9 states have call successors, (37), 4 states have call predecessors, (37), 5 states have return successors, (35), 6 states have call predecessors, (35), 9 states have call successors, (35) Word has length 307 [2022-11-16 11:40:45,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:45,419 INFO L225 Difference]: With dead ends: 473 [2022-11-16 11:40:45,419 INFO L226 Difference]: Without dead ends: 419 [2022-11-16 11:40:45,420 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 622 GetRequests, 595 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=116, Invalid=586, Unknown=0, NotChecked=0, Total=702 [2022-11-16 11:40:45,421 INFO L413 NwaCegarLoop]: 183 mSDtfsCounter, 252 mSDsluCounter, 1709 mSDsCounter, 0 mSdLazyCounter, 1850 mSolverCounterSat, 103 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 268 SdHoareTripleChecker+Valid, 1892 SdHoareTripleChecker+Invalid, 1953 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 103 IncrementalHoareTripleChecker+Valid, 1850 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:45,421 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [268 Valid, 1892 Invalid, 1953 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [103 Valid, 1850 Invalid, 0 Unknown, 0 Unchecked, 2.1s Time] [2022-11-16 11:40:45,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 419 states. [2022-11-16 11:40:45,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 419 to 367. [2022-11-16 11:40:45,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 367 states, 277 states have (on average 1.1805054151624548) internal successors, (327), 285 states have internal predecessors, (327), 50 states have call successors, (50), 26 states have call predecessors, (50), 39 states have return successors, (95), 56 states have call predecessors, (95), 49 states have call successors, (95) [2022-11-16 11:40:45,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 367 states to 367 states and 472 transitions. [2022-11-16 11:40:45,461 INFO L78 Accepts]: Start accepts. Automaton has 367 states and 472 transitions. Word has length 307 [2022-11-16 11:40:45,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:45,462 INFO L495 AbstractCegarLoop]: Abstraction has 367 states and 472 transitions. [2022-11-16 11:40:45,462 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 16 states have (on average 8.4375) internal successors, (135), 17 states have internal predecessors, (135), 9 states have call successors, (37), 4 states have call predecessors, (37), 5 states have return successors, (35), 6 states have call predecessors, (35), 9 states have call successors, (35) [2022-11-16 11:40:45,463 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 472 transitions. [2022-11-16 11:40:45,466 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2022-11-16 11:40:45,466 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:45,466 INFO L195 NwaCegarLoop]: trace histogram [16, 16, 8, 8, 8, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:45,483 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:45,679 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:45,679 INFO L420 AbstractCegarLoop]: === Iteration 31 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:45,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:45,680 INFO L85 PathProgramCache]: Analyzing trace with hash -501768153, now seen corresponding path program 1 times [2022-11-16 11:40:45,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:45,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102937768] [2022-11-16 11:40:45,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:45,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:45,819 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:45,819 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [133237635] [2022-11-16 11:40:45,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:45,820 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:45,820 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:45,821 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:45,831 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-11-16 11:40:46,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:46,925 INFO L263 TraceCheckSpWp]: Trace formula consists of 3491 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-16 11:40:46,931 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:47,057 INFO L134 CoverageAnalysis]: Checked inductivity of 596 backedges. 158 proven. 0 refuted. 0 times theorem prover too weak. 438 trivial. 0 not checked. [2022-11-16 11:40:47,058 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:40:47,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:47,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102937768] [2022-11-16 11:40:47,058 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:47,059 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [133237635] [2022-11-16 11:40:47,059 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [133237635] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:40:47,059 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:40:47,059 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2022-11-16 11:40:47,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651063086] [2022-11-16 11:40:47,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:40:47,062 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2022-11-16 11:40:47,062 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:47,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-16 11:40:47,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2022-11-16 11:40:47,064 INFO L87 Difference]: Start difference. First operand 367 states and 472 transitions. Second operand has 11 states, 11 states have (on average 10.909090909090908) internal successors, (120), 8 states have internal predecessors, (120), 2 states have call successors, (28), 2 states have call predecessors, (28), 5 states have return successors, (28), 5 states have call predecessors, (28), 2 states have call successors, (28) [2022-11-16 11:40:47,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:47,252 INFO L93 Difference]: Finished difference Result 605 states and 779 transitions. [2022-11-16 11:40:47,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-16 11:40:47,253 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 10.909090909090908) internal successors, (120), 8 states have internal predecessors, (120), 2 states have call successors, (28), 2 states have call predecessors, (28), 5 states have return successors, (28), 5 states have call predecessors, (28), 2 states have call successors, (28) Word has length 313 [2022-11-16 11:40:47,253 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:47,255 INFO L225 Difference]: With dead ends: 605 [2022-11-16 11:40:47,256 INFO L226 Difference]: Without dead ends: 382 [2022-11-16 11:40:47,257 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 315 GetRequests, 303 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2022-11-16 11:40:47,258 INFO L413 NwaCegarLoop]: 213 mSDtfsCounter, 13 mSDsluCounter, 1870 mSDsCounter, 0 mSdLazyCounter, 93 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 2083 SdHoareTripleChecker+Invalid, 94 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 93 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:47,258 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [13 Valid, 2083 Invalid, 94 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 93 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-16 11:40:47,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 382 states. [2022-11-16 11:40:47,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 382 to 369. [2022-11-16 11:40:47,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 369 states, 279 states have (on average 1.17921146953405) internal successors, (329), 286 states have internal predecessors, (329), 50 states have call successors, (50), 26 states have call predecessors, (50), 39 states have return successors, (95), 57 states have call predecessors, (95), 49 states have call successors, (95) [2022-11-16 11:40:47,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 474 transitions. [2022-11-16 11:40:47,302 INFO L78 Accepts]: Start accepts. Automaton has 369 states and 474 transitions. Word has length 313 [2022-11-16 11:40:47,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:47,303 INFO L495 AbstractCegarLoop]: Abstraction has 369 states and 474 transitions. [2022-11-16 11:40:47,303 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 10.909090909090908) internal successors, (120), 8 states have internal predecessors, (120), 2 states have call successors, (28), 2 states have call predecessors, (28), 5 states have return successors, (28), 5 states have call predecessors, (28), 2 states have call successors, (28) [2022-11-16 11:40:47,304 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 474 transitions. [2022-11-16 11:40:47,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 311 [2022-11-16 11:40:47,307 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:47,307 INFO L195 NwaCegarLoop]: trace histogram [16, 16, 8, 8, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:47,328 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:47,527 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable30 [2022-11-16 11:40:47,528 INFO L420 AbstractCegarLoop]: === Iteration 32 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:47,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:47,528 INFO L85 PathProgramCache]: Analyzing trace with hash 937325064, now seen corresponding path program 1 times [2022-11-16 11:40:47,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:47,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371224383] [2022-11-16 11:40:47,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:47,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:47,637 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:47,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [611618237] [2022-11-16 11:40:47,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:47,638 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:47,638 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:47,639 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:47,659 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2022-11-16 11:40:48,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:48,749 INFO L263 TraceCheckSpWp]: Trace formula consists of 3516 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-16 11:40:48,753 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:49,015 INFO L134 CoverageAnalysis]: Checked inductivity of 569 backedges. 177 proven. 0 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2022-11-16 11:40:49,015 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:40:49,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:40:49,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371224383] [2022-11-16 11:40:49,016 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:40:49,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [611618237] [2022-11-16 11:40:49,016 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [611618237] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:40:49,017 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:40:49,017 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2022-11-16 11:40:49,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272782020] [2022-11-16 11:40:49,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:40:49,018 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2022-11-16 11:40:49,018 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:40:49,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-11-16 11:40:49,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=183, Unknown=0, NotChecked=0, Total=210 [2022-11-16 11:40:49,020 INFO L87 Difference]: Start difference. First operand 369 states and 474 transitions. Second operand has 15 states, 15 states have (on average 9.4) internal successors, (141), 11 states have internal predecessors, (141), 3 states have call successors, (34), 2 states have call predecessors, (34), 7 states have return successors, (34), 6 states have call predecessors, (34), 3 states have call successors, (34) [2022-11-16 11:40:49,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:40:49,410 INFO L93 Difference]: Finished difference Result 574 states and 743 transitions. [2022-11-16 11:40:49,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-16 11:40:49,411 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 9.4) internal successors, (141), 11 states have internal predecessors, (141), 3 states have call successors, (34), 2 states have call predecessors, (34), 7 states have return successors, (34), 6 states have call predecessors, (34), 3 states have call successors, (34) Word has length 310 [2022-11-16 11:40:49,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:40:49,414 INFO L225 Difference]: With dead ends: 574 [2022-11-16 11:40:49,414 INFO L226 Difference]: Without dead ends: 373 [2022-11-16 11:40:49,416 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 316 GetRequests, 297 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=54, Invalid=366, Unknown=0, NotChecked=0, Total=420 [2022-11-16 11:40:49,417 INFO L413 NwaCegarLoop]: 202 mSDtfsCounter, 17 mSDsluCounter, 2541 mSDsCounter, 0 mSdLazyCounter, 283 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 2743 SdHoareTripleChecker+Invalid, 286 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 283 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-16 11:40:49,418 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 2743 Invalid, 286 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 283 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-16 11:40:49,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 373 states. [2022-11-16 11:40:49,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 373 to 369. [2022-11-16 11:40:49,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 369 states, 279 states have (on average 1.17921146953405) internal successors, (329), 286 states have internal predecessors, (329), 50 states have call successors, (50), 26 states have call predecessors, (50), 39 states have return successors, (93), 57 states have call predecessors, (93), 49 states have call successors, (93) [2022-11-16 11:40:49,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 472 transitions. [2022-11-16 11:40:49,456 INFO L78 Accepts]: Start accepts. Automaton has 369 states and 472 transitions. Word has length 310 [2022-11-16 11:40:49,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:40:49,457 INFO L495 AbstractCegarLoop]: Abstraction has 369 states and 472 transitions. [2022-11-16 11:40:49,458 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 9.4) internal successors, (141), 11 states have internal predecessors, (141), 3 states have call successors, (34), 2 states have call predecessors, (34), 7 states have return successors, (34), 6 states have call predecessors, (34), 3 states have call successors, (34) [2022-11-16 11:40:49,458 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 472 transitions. [2022-11-16 11:40:49,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 299 [2022-11-16 11:40:49,461 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:40:49,462 INFO L195 NwaCegarLoop]: trace histogram [16, 16, 8, 8, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:40:49,484 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Forceful destruction successful, exit code 0 [2022-11-16 11:40:49,677 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31,30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:49,678 INFO L420 AbstractCegarLoop]: === Iteration 33 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:40:49,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:40:49,678 INFO L85 PathProgramCache]: Analyzing trace with hash 1517392424, now seen corresponding path program 1 times [2022-11-16 11:40:49,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:40:49,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790456082] [2022-11-16 11:40:49,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:49,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:40:49,783 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:40:49,784 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [55200788] [2022-11-16 11:40:49,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:40:49,784 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:40:49,784 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:40:49,785 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:40:49,823 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_18d2a477-51df-4b43-96da-c985615ea9e3/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2022-11-16 11:40:53,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:40:53,380 INFO L263 TraceCheckSpWp]: Trace formula consists of 3508 conjuncts, 378 conjunts are in the unsatisfiable core [2022-11-16 11:40:53,397 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:40:53,401 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2022-11-16 11:40:53,627 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2022-11-16 11:40:53,674 INFO L321 Elim1Store]: treesize reduction 18, result has 35.7 percent of original size [2022-11-16 11:40:53,675 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 17 treesize of output 21 [2022-11-16 11:40:53,692 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-16 11:40:54,621 WARN L855 $PredicateComparison]: unable to prove that (exists ((v_ArrVal_5728 (Array Int Int))) (= (store |c_old(#memory_int)| |c_aws_mul_size_checked_#in~r#1.base| v_ArrVal_5728) |c_#memory_int|)) is different from true [2022-11-16 11:40:55,989 INFO L321 Elim1Store]: treesize reduction 30, result has 38.8 percent of original size [2022-11-16 11:40:55,990 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 231 treesize of output 239 [2022-11-16 11:40:56,045 INFO L321 Elim1Store]: treesize reduction 10, result has 64.3 percent of original size [2022-11-16 11:40:56,045 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 39 treesize of output 48 [2022-11-16 11:40:56,123 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-16 11:40:56,123 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 24 [2022-11-16 11:41:23,836 WARN L855 $PredicateComparison]: unable to prove that (exists ((v_ArrVal_5729 (Array Int Int))) (= (store |c_old(#memory_int)| |c_aws_mul_size_checked_#in~r#1.base| v_ArrVal_5729) |c_#memory_int|)) is different from true [2022-11-16 11:41:28,278 INFO L321 Elim1Store]: treesize reduction 10, result has 64.3 percent of original size [2022-11-16 11:41:28,278 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 24 treesize of output 36 [2022-11-16 11:42:45,372 WARN L233 SmtUtils]: Spent 10.89s on a formula simplification. DAG size of input: 151 DAG size of output: 125 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-16 11:42:49,510 WARN L833 $PredicateComparison]: unable to prove that (and (= c_memset_impl_~sp~0.base |c_memset_impl_#in~s.base|) (= |c_memset_impl_#in~s.offset| c_memset_impl_~sp~0.offset) (let ((.cse6 (mod c_memset_impl_~c 256))) (let ((.cse3 (select |c_old(#memory_int)| c_memset_impl_~sp~0.base)) (.cse4 (+ c_memset_impl_~sp~0.offset 1)) (.cse5 (+ 2 c_memset_impl_~sp~0.offset)) (.cse0 (<= .cse6 127))) (or (and (not .cse0) (let ((.cse2 (+ .cse6 (- 256)))) (let ((.cse1 (store (store (store .cse3 c_memset_impl_~sp~0.offset .cse2) .cse4 .cse2) .cse5 .cse2))) (or (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse1 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse2) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse1 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse2) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_14 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse2) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2))) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse1 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse2) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (= |c_#memory_int| (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse1 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse2) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2))) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))))))))) (and (let ((.cse7 (store (store (store .cse3 c_memset_impl_~sp~0.offset .cse6) .cse4 .cse6) .cse5 .cse6))) (or (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_1 18446744073709551616)) .cse6)) |c_#memory_int|))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (<= 0 v_subst_6) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse7 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_6 18446744073709551616)) .cse6)) |c_#memory_int|))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_4 Int)) (and (<= 0 v_subst_4) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse7 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse6) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_4 18446744073709551616)) .cse6)) |c_#memory_int|) (<= v_subst_4 9223372036854775807))))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_3 Int)) (and (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse7 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse6) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_3 18446744073709551616)) .cse6)) |c_#memory_int|) (< 9223372036854775807 v_subst_3) (< v_subst_3 18446744073709551616))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_2 18446744073709551616)) .cse6)) |c_#memory_int|) (<= v_subst_2 9223372036854775807))))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store .cse7 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_5 18446744073709551616)) .cse6)) |c_#memory_int|) (< v_subst_5 18446744073709551616))))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))))) .cse0)))) (= |c_memset_impl_#in~c| c_memset_impl_~c)) is different from false [2022-11-16 11:42:58,826 WARN L833 $PredicateComparison]: unable to prove that (and (= c_memset_impl_~sp~0.base |c_memset_impl_#in~s.base|) (= |c_memset_impl_#in~s.offset| c_memset_impl_~sp~0.offset) (let ((.cse6 (mod c_memset_impl_~c 256))) (let ((.cse0 (<= .cse6 127)) (.cse3 (select |c_old(#memory_int)| c_memset_impl_~sp~0.base)) (.cse4 (+ c_memset_impl_~sp~0.offset 1)) (.cse5 (+ 2 c_memset_impl_~sp~0.offset))) (or (and (not .cse0) (let ((.cse2 (+ .cse6 (- 256)))) (let ((.cse1 (store (store (store .cse3 c_memset_impl_~sp~0.offset .cse2) .cse4 .cse2) .cse5 .cse2))) (or (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int)) (and (exists ((v_subst_53 Int)) (and (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse2) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (mod v_subst_53 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2)) |c_#memory_int|) (<= 0 v_subst_53) (<= v_subst_53 9223372036854775807))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (exists ((v_subst_45 Int)) (and (<= 0 v_subst_45) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (mod v_subst_45 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2)) |c_#memory_int|) (<= v_subst_45 9223372036854775807))))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (exists ((v_aux_mod_memset_impl_~i~6_43_7 Int)) (and (exists ((v_subst_33 Int)) (and (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse2) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (mod v_subst_33 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2)) |c_#memory_int|) (<= 0 v_subst_33) (<= v_subst_33 9223372036854775807))) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_7 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (exists ((v_subst_41 Int)) (and (<= v_subst_41 9223372036854775807) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse2) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_subst_41 18446744073709551616)) .cse2)) |c_#memory_int|) (<= 0 v_subst_41))) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807))))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_7 Int)) (and (exists ((v_subst_34 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse2) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (- 18446744073709551616) (mod v_subst_34 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2))) (< v_subst_34 18446744073709551616) (< 9223372036854775807 v_subst_34))) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (exists ((v_aux_mod_memset_impl_~i~6_43_14 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (exists ((v_subst_49 Int)) (and (<= 0 v_subst_49) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse2) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_subst_49 18446744073709551616)) .cse2)) |c_#memory_int|) (<= v_subst_49 9223372036854775807))))) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (exists ((v_subst_37 Int)) (and (<= v_subst_37 9223372036854775807) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse2) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_subst_37 18446744073709551616)) .cse2)) |c_#memory_int|) (<= 0 v_subst_37))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_14 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (exists ((v_subst_50 Int)) (and (< v_subst_50 18446744073709551616) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse2) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (- 18446744073709551616) (mod v_subst_50 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_subst_50))))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (exists ((v_subst_38 Int)) (and (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse2) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_38 18446744073709551616)) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_subst_38) (< v_subst_38 18446744073709551616))))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int)) (and (exists ((v_subst_54 Int)) (and (< v_subst_54 18446744073709551616) (< 9223372036854775807 v_subst_54) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse2) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_54 18446744073709551616)) .cse2)) |c_#memory_int|))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_7 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (exists ((v_subst_42 Int)) (and (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse2) (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse2) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_42 18446744073709551616)) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_subst_42) (< v_subst_42 18446744073709551616))))) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (exists ((v_subst_46 Int)) (and (< v_subst_46 18446744073709551616) (< 9223372036854775807 v_subst_46) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse2) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_46 18446744073709551616)) .cse2)) |c_#memory_int|))) (<= 0 v_aux_mod_memset_impl_~i~6_43_11))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))))))) (and .cse0 (let ((.cse7 (store (store (store .cse3 c_memset_impl_~sp~0.offset .cse6) .cse4 .cse6) .cse5 .cse6))) (or (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_6 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_11 Int)) (and (< v_subst_11 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_6 18446744073709551616)) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_11 18446744073709551616)) .cse6))) (< 9223372036854775807 v_subst_11))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= v_subst_6 9223372036854775807) (<= 0 v_subst_6))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_5 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_5 18446744073709551616)) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_28 18446744073709551616)) .cse6)) |c_#memory_int|) (<= 0 v_subst_28))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (< 9223372036854775807 v_subst_5) (< v_subst_5 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_19 Int)) (and (< 9223372036854775807 v_subst_19) (< v_subst_19 18446744073709551616) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse6) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_3 18446744073709551616)) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_19 18446744073709551616)) .cse6)) |c_#memory_int|))) (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_subst_3 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_27 Int)) (and (< 9223372036854775807 v_subst_27) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_5 18446744073709551616)) .cse6) (+ (mod v_subst_27 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6)) |c_#memory_int|) (< v_subst_27 18446744073709551616))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (< v_subst_5 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_2 18446744073709551616)) .cse6) (+ (mod v_subst_23 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6)) |c_#memory_int|) (< v_subst_23 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_1 18446744073709551616)) .cse6) (+ (mod v_subst_16 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6)) |c_#memory_int|))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_24 Int)) (and (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_2 18446744073709551616)) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_24 18446744073709551616)) .cse6)) |c_#memory_int|))) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_12 Int)) (and (<= v_subst_12 9223372036854775807) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_6 18446744073709551616)) .cse6) (+ (mod v_subst_12 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6)) |c_#memory_int|) (<= 0 v_subst_12))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (<= 0 v_subst_8) (<= v_subst_8 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse6) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_4 18446744073709551616)) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_8 18446744073709551616)) .cse6))))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse6) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_3 18446744073709551616)) .cse6) (+ (mod v_subst_20 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6)) |c_#memory_int|) (<= 0 v_subst_20))))) (< v_subst_3 18446744073709551616))))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_1 18446744073709551616)) .cse6) (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_subst_15 18446744073709551616)) .cse6)) |c_#memory_int|) (< v_subst_15 18446744073709551616))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (< 9223372036854775807 v_subst_1))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (= (store |c_old(#memory_int)| c_memset_impl_~sp~0.base (store (store (store (store .cse7 (+ (- 18446744073709551616) c_memset_impl_~sp~0.offset (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse6) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6) (+ c_memset_impl_~sp~0.offset (mod v_subst_4 18446744073709551616)) .cse6) (+ (mod v_subst_7 18446744073709551616) (- 18446744073709551616) c_memset_impl_~sp~0.offset) .cse6)) |c_#memory_int|) (< v_subst_7 18446744073709551616))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616))))))))) (= |c_memset_impl_#in~c| c_memset_impl_~c)) is different from false [2022-11-16 11:43:27,814 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse2 (mod |c_memset_impl_#in~c| 256))) (let ((.cse3 (select |c_old(#memory_int)| |c_memset_impl_#in~s.base|)) (.cse4 (+ |c_memset_impl_#in~s.offset| 1)) (.cse5 (+ |c_memset_impl_#in~s.offset| 2)) (.cse0 (<= .cse2 127))) (or (and .cse0 (let ((.cse1 (store (store (store .cse3 |c_memset_impl_#in~s.offset| .cse2) .cse4 .cse2) .cse5 .cse2))) (or (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (exists ((v_subst_74 Int)) (and (< 9223372036854775807 v_subst_74) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_2 18446744073709551616)) .cse2) (+ (mod v_subst_23 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_74 18446744073709551616)) .cse2))) (< v_subst_74 18446744073709551616))) (< v_subst_23 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_64 Int)) (and (< 9223372036854775807 v_subst_64) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_5 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_28 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_64 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_64 18446744073709551616))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_24 Int)) (and (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807) (exists ((v_subst_76 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_2 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_24 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_76 18446744073709551616)) .cse2))) (< v_subst_76 18446744073709551616) (< 9223372036854775807 v_subst_76))))) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_19 Int)) (and (< 9223372036854775807 v_subst_19) (exists ((v_subst_70 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_3 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_19 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_70 18446744073709551616) (- 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_70 18446744073709551616) (< 9223372036854775807 v_subst_70))) (< v_subst_19 18446744073709551616))))) (< 9223372036854775807 v_subst_3) (< v_subst_3 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_24 Int)) (and (exists ((v_subst_75 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_2 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_24 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_75 18446744073709551616)) .cse2))) (<= 0 v_subst_75) (<= v_subst_75 9223372036854775807))) (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (exists ((v_subst_62 Int)) (and (< 9223372036854775807 v_subst_62) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_15 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_62 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_62 18446744073709551616))) (< v_subst_15 18446744073709551616))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_27 Int)) (and (< 9223372036854775807 v_subst_27) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_71 Int)) (and (<= v_subst_71 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_5 18446744073709551616)) .cse2) (+ (mod v_subst_27 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_71 18446744073709551616)) .cse2))) (<= 0 v_subst_71))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (< v_subst_27 18446744073709551616))) (< v_subst_5 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_67 Int)) (and (<= 0 v_subst_67) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_7 18446744073709551616) (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_67 18446744073709551616)) .cse2)) |c_#memory_int|) (<= v_subst_67 9223372036854775807))) (< v_subst_7 18446744073709551616))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_subst_12 Int)) (and (<= v_subst_12 9223372036854775807) (<= 0 v_subst_12) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_56 Int)) (and (< 9223372036854775807 v_subst_56) (< v_subst_56 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse2) (+ (mod v_subst_12 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_56 18446744073709551616)) .cse2))))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))))) (<= 0 v_subst_6))))) (exists ((v_subst_11 Int)) (and (< v_subst_11 18446744073709551616) (< 9223372036854775807 v_subst_11) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (<= 0 v_subst_6) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_65 Int)) (and (<= v_subst_65 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_11 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_65 18446744073709551616)) .cse2))) (<= 0 v_subst_65))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))))) (<= 0 aux_mod_memset_impl_~i~6_43))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_58 Int)) (and (< v_subst_58 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_3 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_20 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_58 18446744073709551616) (- 18446744073709551616)) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_subst_58))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (< v_subst_15 18446744073709551616) (exists ((v_subst_61 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_15 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_61 18446744073709551616)) .cse2)) |c_#memory_int|) (<= v_subst_61 9223372036854775807) (<= 0 v_subst_61))))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (< v_subst_23 18446744073709551616) (exists ((v_subst_73 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_2 18446744073709551616)) .cse2) (+ (mod v_subst_23 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_73 18446744073709551616)) .cse2))) (<= 0 v_subst_73) (<= v_subst_73 9223372036854775807))))) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (exists ((v_subst_77 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_8 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_77 18446744073709551616)) .cse2))) (<= 0 v_subst_77) (<= v_subst_77 9223372036854775807))) (<= 0 v_subst_8) (<= v_subst_8 9223372036854775807))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_27 Int)) (and (< 9223372036854775807 v_subst_27) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_72 Int)) (and (< v_subst_72 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_5 18446744073709551616)) .cse2) (+ (mod v_subst_27 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_72 18446744073709551616)) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_subst_72))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (< v_subst_27 18446744073709551616))) (< v_subst_5 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_63 Int)) (and (<= v_subst_63 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_5 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_28 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_63 18446744073709551616)) .cse2)) |c_#memory_int|) (<= 0 v_subst_63))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_4 Int)) (and (<= 0 v_subst_4) (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_68 Int)) (and (< v_subst_68 18446744073709551616) (< 9223372036854775807 v_subst_68) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_7 18446744073709551616) (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_68 18446744073709551616)) .cse2)) |c_#memory_int|))) (< v_subst_7 18446744073709551616))) (<= v_subst_4 9223372036854775807))))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (<= 0 v_subst_8) (<= v_subst_8 9223372036854775807) (exists ((v_subst_78 Int)) (and (< 9223372036854775807 v_subst_78) (< v_subst_78 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_8 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_78 18446744073709551616)) .cse2)) |c_#memory_int|))))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_6 Int)) (and (exists ((v_subst_12 Int)) (and (<= v_subst_12 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807) (exists ((v_subst_55 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse2) (+ (mod v_subst_12 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_55 18446744073709551616)) .cse2)) |c_#memory_int|) (<= v_subst_55 9223372036854775807) (<= 0 v_subst_55))))) (<= 0 v_subst_12))) (<= v_subst_6 9223372036854775807) (<= 0 v_subst_6))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (exists ((v_subst_60 Int)) (and (< 9223372036854775807 v_subst_60) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_1 18446744073709551616)) .cse2) (+ (mod v_subst_16 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_60 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_60 18446744073709551616))))) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (< 9223372036854775807 v_subst_1))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (exists ((v_subst_59 Int)) (and (<= 0 v_subst_59) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_1 18446744073709551616)) .cse2) (+ (mod v_subst_16 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_59 18446744073709551616)) .cse2)) |c_#memory_int|) (<= v_subst_59 9223372036854775807))))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (< 9223372036854775807 v_subst_1))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_57 Int)) (and (<= 0 v_subst_57) (<= v_subst_57 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_3 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_20 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_57 18446744073709551616)) .cse2)) |c_#memory_int|))))) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_19 Int)) (and (< 9223372036854775807 v_subst_19) (exists ((v_subst_69 Int)) (and (<= v_subst_69 9223372036854775807) (<= 0 v_subst_69) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_3 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_19 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_69 18446744073709551616)) .cse2))))) (< v_subst_19 18446744073709551616))))) (< v_subst_3 18446744073709551616))))) (exists ((v_subst_11 Int)) (and (< v_subst_11 18446744073709551616) (< 9223372036854775807 v_subst_11) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_66 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_11 18446744073709551616)) .cse2) (+ (mod v_subst_66 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_66 18446744073709551616) (< 9223372036854775807 v_subst_66))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_6)))))))))) (and (let ((.cse7 (+ (- 256) .cse2))) (let ((.cse6 (store (store (store .cse3 |c_memset_impl_#in~s.offset| .cse7) .cse4 .cse7) .cse5 .cse7))) (or (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int) (v_subst_45 Int) (v_aux_mod_memset_impl_~i~6_43_29 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_29) (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_29 18446744073709551616) (<= 0 v_subst_45) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_29 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_45 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_45 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_37 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_42 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (< 9223372036854775807 v_subst_42) (<= 0 v_aux_mod_memset_impl_~i~6_43_37) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_37 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_42 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_37 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< v_subst_42 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_17 Int) (v_subst_41 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_17 9223372036854775807) (<= v_subst_41 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_17 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_41 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= 0 v_aux_mod_memset_impl_~i~6_43_17) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_subst_41) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_37 Int) (v_aux_mod_memset_impl_~i~6_43_16 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (<= v_subst_37 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_16) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_16 18446744073709551616) (<= 0 v_subst_37) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_16 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_37 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_34 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_53 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_34 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_53 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))) (<= v_aux_mod_memset_impl_~i~6_43_34 9223372036854775807) (<= 0 v_subst_53) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (<= 0 v_aux_mod_memset_impl_~i~6_43_34) (<= v_subst_53 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_46 Int) (v_aux_mod_memset_impl_~i~6_43_11 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int) (v_aux_mod_memset_impl_~i~6_43_30 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_30 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_46 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_30 18446744073709551616) (< v_subst_46 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_46) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_30) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_33 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_54 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_33 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_33 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_54 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< v_subst_54 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< 9223372036854775807 v_subst_54) (<= 0 v_aux_mod_memset_impl_~i~6_43_33) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_34 Int) (v_aux_mod_memset_impl_~i~6_43_25 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_25 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_34 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_25 18446744073709551616) (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< v_subst_34 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_25) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< 9223372036854775807 v_subst_34))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_21 Int) (v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_54 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< v_subst_54 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< 9223372036854775807 v_subst_54) (<= 0 v_aux_mod_memset_impl_~i~6_43_21) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_21 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_54 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_21 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_15 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int) (v_subst_33 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_15 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_33 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_15) (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< v_aux_mod_memset_impl_~i~6_43_15 18446744073709551616) (<= 0 v_subst_33) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_subst_33 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_32 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_49 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_32) (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_32 9223372036854775807) (<= 0 v_subst_49) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_49 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_32 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_49 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_46 Int) (v_aux_mod_memset_impl_~i~6_43_11 Int) (v_aux_mod_memset_impl_~i~6_43_18 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_18 18446744073709551616) (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_46 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_18) (< v_subst_46 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_18 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_46) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_27 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_41 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= 0 v_aux_mod_memset_impl_~i~6_43_27) (<= v_subst_41 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_27 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_41 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_27 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_subst_41) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_20 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_50 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< v_subst_50 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_20 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_50 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_aux_mod_memset_impl_~i~6_43_20 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_20) (< 9223372036854775807 v_subst_50) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int) (v_subst_45 Int) (v_aux_mod_memset_impl_~i~6_43_24 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_subst_45) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< v_aux_mod_memset_impl_~i~6_43_24 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_24 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_45 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_subst_45 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_24) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_38 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_aux_mod_memset_impl_~i~6_43_19 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_19 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_38 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< 9223372036854775807 v_subst_38) (< v_subst_38 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_19) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< v_aux_mod_memset_impl_~i~6_43_19 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_22 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_49 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_subst_49) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_22 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_49 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= 0 v_aux_mod_memset_impl_~i~6_43_22) (<= v_subst_49 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_22 9223372036854775807))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_23 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_53 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_23 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_23) (<= 0 v_subst_53) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_23 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_53 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_subst_53 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_aux_mod_memset_impl_~i~6_43_35 Int) (v_subst_38 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_35 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_38 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< 9223372036854775807 v_subst_38) (< v_subst_38 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_35 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_35) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_36 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int) (v_subst_33 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_36) (< v_aux_mod_memset_impl_~i~6_43_36 18446744073709551616) (<= 0 v_subst_33) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_36 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_33 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_subst_33 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_34 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_28 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_28) (< v_subst_34 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_28 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_28 18446744073709551616) (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_34 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< 9223372036854775807 v_subst_34))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_37 Int) (v_aux_mod_memset_impl_~i~6_43_31 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (<= v_subst_37 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_31 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_31) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_31 18446744073709551616) (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_37 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= 0 v_subst_37) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_26 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_42 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_26 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_26 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_42 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (< 9223372036854775807 v_subst_42) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_26) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< v_subst_42 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_14 Int) (v_aux_mod_memset_impl_~i~6_43_38 Int) (v_subst_50 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_38) (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_38 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< v_subst_50 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_50) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_38 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_50 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)))))))))) (not .cse0))))) is different from false [2022-11-16 11:43:27,876 WARN L855 $PredicateComparison]: unable to prove that (let ((.cse2 (mod |c_memset_impl_#in~c| 256))) (let ((.cse3 (select |c_old(#memory_int)| |c_memset_impl_#in~s.base|)) (.cse4 (+ |c_memset_impl_#in~s.offset| 1)) (.cse5 (+ |c_memset_impl_#in~s.offset| 2)) (.cse0 (<= .cse2 127))) (or (and .cse0 (let ((.cse1 (store (store (store .cse3 |c_memset_impl_#in~s.offset| .cse2) .cse4 .cse2) .cse5 .cse2))) (or (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (exists ((v_subst_74 Int)) (and (< 9223372036854775807 v_subst_74) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_2 18446744073709551616)) .cse2) (+ (mod v_subst_23 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_74 18446744073709551616)) .cse2))) (< v_subst_74 18446744073709551616))) (< v_subst_23 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_64 Int)) (and (< 9223372036854775807 v_subst_64) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_5 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_28 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_64 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_64 18446744073709551616))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_24 Int)) (and (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807) (exists ((v_subst_76 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_2 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_24 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_76 18446744073709551616)) .cse2))) (< v_subst_76 18446744073709551616) (< 9223372036854775807 v_subst_76))))) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_19 Int)) (and (< 9223372036854775807 v_subst_19) (exists ((v_subst_70 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_3 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_19 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_70 18446744073709551616) (- 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_70 18446744073709551616) (< 9223372036854775807 v_subst_70))) (< v_subst_19 18446744073709551616))))) (< 9223372036854775807 v_subst_3) (< v_subst_3 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_24 Int)) (and (exists ((v_subst_75 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_2 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_24 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_75 18446744073709551616)) .cse2))) (<= 0 v_subst_75) (<= v_subst_75 9223372036854775807))) (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (exists ((v_subst_62 Int)) (and (< 9223372036854775807 v_subst_62) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_15 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_62 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_62 18446744073709551616))) (< v_subst_15 18446744073709551616))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_27 Int)) (and (< 9223372036854775807 v_subst_27) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_71 Int)) (and (<= v_subst_71 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_5 18446744073709551616)) .cse2) (+ (mod v_subst_27 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_71 18446744073709551616)) .cse2))) (<= 0 v_subst_71))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (< v_subst_27 18446744073709551616))) (< v_subst_5 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_67 Int)) (and (<= 0 v_subst_67) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_7 18446744073709551616) (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_67 18446744073709551616)) .cse2)) |c_#memory_int|) (<= v_subst_67 9223372036854775807))) (< v_subst_7 18446744073709551616))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_subst_12 Int)) (and (<= v_subst_12 9223372036854775807) (<= 0 v_subst_12) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_56 Int)) (and (< 9223372036854775807 v_subst_56) (< v_subst_56 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse2) (+ (mod v_subst_12 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_56 18446744073709551616)) .cse2))))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))))) (<= 0 v_subst_6))))) (exists ((v_subst_11 Int)) (and (< v_subst_11 18446744073709551616) (< 9223372036854775807 v_subst_11) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (<= 0 v_subst_6) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_65 Int)) (and (<= v_subst_65 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_11 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_65 18446744073709551616)) .cse2))) (<= 0 v_subst_65))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))))) (<= 0 aux_mod_memset_impl_~i~6_43))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_58 Int)) (and (< v_subst_58 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_3 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_20 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_58 18446744073709551616) (- 18446744073709551616)) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_subst_58))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (< v_subst_15 18446744073709551616) (exists ((v_subst_61 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_15 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_61 18446744073709551616)) .cse2)) |c_#memory_int|) (<= v_subst_61 9223372036854775807) (<= 0 v_subst_61))))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (< v_subst_23 18446744073709551616) (exists ((v_subst_73 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_2 18446744073709551616)) .cse2) (+ (mod v_subst_23 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_73 18446744073709551616)) .cse2))) (<= 0 v_subst_73) (<= v_subst_73 9223372036854775807))))) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (exists ((v_subst_77 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_8 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_77 18446744073709551616)) .cse2))) (<= 0 v_subst_77) (<= v_subst_77 9223372036854775807))) (<= 0 v_subst_8) (<= v_subst_8 9223372036854775807))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_27 Int)) (and (< 9223372036854775807 v_subst_27) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_72 Int)) (and (< v_subst_72 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_5 18446744073709551616)) .cse2) (+ (mod v_subst_27 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_72 18446744073709551616)) .cse2)) |c_#memory_int|) (< 9223372036854775807 v_subst_72))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (< v_subst_27 18446744073709551616))) (< v_subst_5 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_63 Int)) (and (<= v_subst_63 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_5 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_28 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_63 18446744073709551616)) .cse2)) |c_#memory_int|) (<= 0 v_subst_63))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_4 Int)) (and (<= 0 v_subst_4) (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_68 Int)) (and (< v_subst_68 18446744073709551616) (< 9223372036854775807 v_subst_68) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_7 18446744073709551616) (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_68 18446744073709551616)) .cse2)) |c_#memory_int|))) (< v_subst_7 18446744073709551616))) (<= v_subst_4 9223372036854775807))))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (<= 0 v_subst_8) (<= v_subst_8 9223372036854775807) (exists ((v_subst_78 Int)) (and (< 9223372036854775807 v_subst_78) (< v_subst_78 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_8 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_78 18446744073709551616)) .cse2)) |c_#memory_int|))))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_6 Int)) (and (exists ((v_subst_12 Int)) (and (<= v_subst_12 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807) (exists ((v_subst_55 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse2) (+ (mod v_subst_12 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_55 18446744073709551616)) .cse2)) |c_#memory_int|) (<= v_subst_55 9223372036854775807) (<= 0 v_subst_55))))) (<= 0 v_subst_12))) (<= v_subst_6 9223372036854775807) (<= 0 v_subst_6))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (exists ((v_subst_60 Int)) (and (< 9223372036854775807 v_subst_60) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_1 18446744073709551616)) .cse2) (+ (mod v_subst_16 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_60 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_60 18446744073709551616))))) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (< 9223372036854775807 v_subst_1))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (exists ((v_subst_59 Int)) (and (<= 0 v_subst_59) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_1 18446744073709551616)) .cse2) (+ (mod v_subst_16 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_59 18446744073709551616)) .cse2)) |c_#memory_int|) (<= v_subst_59 9223372036854775807))))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (< 9223372036854775807 v_subst_1))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_57 Int)) (and (<= 0 v_subst_57) (<= v_subst_57 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_3 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_20 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_57 18446744073709551616)) .cse2)) |c_#memory_int|))))) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_19 Int)) (and (< 9223372036854775807 v_subst_19) (exists ((v_subst_69 Int)) (and (<= v_subst_69 9223372036854775807) (<= 0 v_subst_69) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_3 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_19 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_69 18446744073709551616)) .cse2))))) (< v_subst_19 18446744073709551616))))) (< v_subst_3 18446744073709551616))))) (exists ((v_subst_11 Int)) (and (< v_subst_11 18446744073709551616) (< 9223372036854775807 v_subst_11) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_66 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse1 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse2) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_11 18446744073709551616)) .cse2) (+ (mod v_subst_66 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse2)) |c_#memory_int|) (< v_subst_66 18446744073709551616) (< 9223372036854775807 v_subst_66))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_6)))))))))) (and (let ((.cse7 (+ (- 256) .cse2))) (let ((.cse6 (store (store (store .cse3 |c_memset_impl_#in~s.offset| .cse7) .cse4 .cse7) .cse5 .cse7))) (or (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int) (v_subst_45 Int) (v_aux_mod_memset_impl_~i~6_43_29 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_29) (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_29 18446744073709551616) (<= 0 v_subst_45) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_29 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_45 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_45 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_37 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_42 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (< 9223372036854775807 v_subst_42) (<= 0 v_aux_mod_memset_impl_~i~6_43_37) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_37 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_42 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_37 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< v_subst_42 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_17 Int) (v_subst_41 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_17 9223372036854775807) (<= v_subst_41 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_17 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_41 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= 0 v_aux_mod_memset_impl_~i~6_43_17) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_subst_41) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_37 Int) (v_aux_mod_memset_impl_~i~6_43_16 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (<= v_subst_37 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_16) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_16 18446744073709551616) (<= 0 v_subst_37) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_16 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_37 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_34 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_53 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_34 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_53 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))) (<= v_aux_mod_memset_impl_~i~6_43_34 9223372036854775807) (<= 0 v_subst_53) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (<= 0 v_aux_mod_memset_impl_~i~6_43_34) (<= v_subst_53 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_46 Int) (v_aux_mod_memset_impl_~i~6_43_11 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int) (v_aux_mod_memset_impl_~i~6_43_30 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_30 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_46 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_30 18446744073709551616) (< v_subst_46 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_46) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_30) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_33 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_54 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_33 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_33 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_54 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< v_subst_54 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< 9223372036854775807 v_subst_54) (<= 0 v_aux_mod_memset_impl_~i~6_43_33) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_34 Int) (v_aux_mod_memset_impl_~i~6_43_25 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_25 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_34 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_25 18446744073709551616) (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< v_subst_34 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_25) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< 9223372036854775807 v_subst_34))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_21 Int) (v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_54 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< v_subst_54 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< 9223372036854775807 v_subst_54) (<= 0 v_aux_mod_memset_impl_~i~6_43_21) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_21 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_54 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_21 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_15 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int) (v_subst_33 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_15 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_33 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_15) (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< v_aux_mod_memset_impl_~i~6_43_15 18446744073709551616) (<= 0 v_subst_33) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_subst_33 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_32 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_49 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_32) (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_32 9223372036854775807) (<= 0 v_subst_49) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_49 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_32 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_49 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_46 Int) (v_aux_mod_memset_impl_~i~6_43_11 Int) (v_aux_mod_memset_impl_~i~6_43_18 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_18 18446744073709551616) (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_46 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_18) (< v_subst_46 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_18 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_46) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_27 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_41 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= 0 v_aux_mod_memset_impl_~i~6_43_27) (<= v_subst_41 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_27 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_41 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_27 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_subst_41) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_20 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_50 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< v_subst_50 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_20 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_50 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_aux_mod_memset_impl_~i~6_43_20 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_20) (< 9223372036854775807 v_subst_50) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int) (v_subst_45 Int) (v_aux_mod_memset_impl_~i~6_43_24 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_subst_45) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< v_aux_mod_memset_impl_~i~6_43_24 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_24 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_45 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_subst_45 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_24) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_38 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_aux_mod_memset_impl_~i~6_43_19 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_19 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_38 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< 9223372036854775807 v_subst_38) (< v_subst_38 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_19) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< v_aux_mod_memset_impl_~i~6_43_19 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_22 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_49 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_subst_49) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_22 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_49 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= 0 v_aux_mod_memset_impl_~i~6_43_22) (<= v_subst_49 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_22 9223372036854775807))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_23 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_53 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_23 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_23) (<= 0 v_subst_53) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_23 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_53 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_subst_53 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_aux_mod_memset_impl_~i~6_43_35 Int) (v_subst_38 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_35 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_38 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< 9223372036854775807 v_subst_38) (< v_subst_38 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_35 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_35) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_36 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int) (v_subst_33 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_36) (< v_aux_mod_memset_impl_~i~6_43_36 18446744073709551616) (<= 0 v_subst_33) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_36 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_33 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7))) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_subst_33 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_34 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_28 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_28) (< v_subst_34 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_28 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_28 18446744073709551616) (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_34 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< 9223372036854775807 v_subst_34))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_37 Int) (v_aux_mod_memset_impl_~i~6_43_31 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (<= v_subst_37 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_31 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_31) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_31 18446744073709551616) (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_subst_37 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= 0 v_subst_37) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_26 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_42 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_26 9223372036854775807) (= (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_26 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_42 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (< 9223372036854775807 v_subst_42) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_26) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< v_subst_42 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_14 Int) (v_aux_mod_memset_impl_~i~6_43_38 Int) (v_subst_50 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_38) (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_38 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< v_subst_50 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_50) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_memset_impl_#in~s.base| (store (store (store (store (store .cse6 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) |c_memset_impl_#in~s.offset| (- 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse7) (+ (mod v_aux_mod_memset_impl_~i~6_43_38 18446744073709551616) |c_memset_impl_#in~s.offset|) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod v_subst_50 18446744073709551616)) .cse7) (+ |c_memset_impl_#in~s.offset| (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616)) .cse7)))))))))) (not .cse0))))) is different from true [2022-11-16 11:44:26,775 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse5 (mod |c_my_memset_#in~c| 256))) (let ((.cse2 (select |c_old(#memory_int)| |c_my_memset_#in~s.base|)) (.cse3 (+ |c_my_memset_#in~s.offset| 1)) (.cse4 (+ 2 |c_my_memset_#in~s.offset|)) (.cse6 (<= .cse5 127))) (or (and (let ((.cse1 (+ (- 256) .cse5))) (let ((.cse0 (store (store (store .cse2 |c_my_memset_#in~s.offset| .cse1) .cse3 .cse1) .cse4 .cse1))) (or (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_37 Int) (v_aux_mod_memset_impl_~i~6_43_31 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (<= v_subst_37 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_31 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_31) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_31 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_37 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (<= 0 v_subst_37) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_32 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_49 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_32) (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_32 9223372036854775807) (<= 0 v_subst_49) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_49 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_32 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_subst_49 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_17 Int) (v_subst_41 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_17 9223372036854775807) (<= v_subst_41 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_17) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_17 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_subst_41 18446744073709551616)) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (<= 0 v_subst_41) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_14 Int) (v_aux_mod_memset_impl_~i~6_43_38 Int) (v_subst_50 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_38) (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_38 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< v_subst_50 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_38 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_50 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_50) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_46 Int) (v_aux_mod_memset_impl_~i~6_43_11 Int) (v_aux_mod_memset_impl_~i~6_43_18 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_18) (< v_subst_46 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_18 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_46) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_18 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_46 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_34 Int) (v_aux_mod_memset_impl_~i~6_43_25 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_25 18446744073709551616) (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< v_subst_34 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_25 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_34 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_25) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< 9223372036854775807 v_subst_34))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_aux_mod_memset_impl_~i~6_43_35 Int) (v_subst_38 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_35 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_38 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< 9223372036854775807 v_subst_38) (< v_subst_38 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_35 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_35) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_34 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_53 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_34 9223372036854775807) (<= 0 v_subst_53) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_34 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_53 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (<= 0 v_aux_mod_memset_impl_~i~6_43_34) (<= v_subst_53 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_37 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_42 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (< 9223372036854775807 v_subst_42) (<= 0 v_aux_mod_memset_impl_~i~6_43_37) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_37 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_42 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (<= v_aux_mod_memset_impl_~i~6_43_37 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< v_subst_42 18446744073709551616))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_26 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_42 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_26 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (< 9223372036854775807 v_subst_42) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_26 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_42 18446744073709551616)) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_26) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< v_subst_42 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int) (v_subst_45 Int) (v_aux_mod_memset_impl_~i~6_43_29 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_29) (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_29 18446744073709551616) (<= 0 v_subst_45) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_29 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_45 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_45 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_23 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_53 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_23 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_23) (<= 0 v_subst_53) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_23 18446744073709551616)) .cse1) (+ (mod v_subst_53 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (<= v_subst_53 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_37 Int) (v_aux_mod_memset_impl_~i~6_43_16 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (<= v_subst_37 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_16) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_16 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_16 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_37 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (<= 0 v_subst_37) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_34 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_28 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_28) (< v_subst_34 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_28 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_28 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_34 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< 9223372036854775807 v_subst_34))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_38 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_aux_mod_memset_impl_~i~6_43_19 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_19 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_38 18446744073709551616)) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< 9223372036854775807 v_subst_38) (< v_subst_38 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_19) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< v_aux_mod_memset_impl_~i~6_43_19 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_27 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_41 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= 0 v_aux_mod_memset_impl_~i~6_43_27) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_27 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_subst_41 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (<= v_subst_41 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_27 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_subst_41) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_15 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int) (v_subst_33 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_15 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_33 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_15) (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< v_aux_mod_memset_impl_~i~6_43_15 18446744073709551616) (<= 0 v_subst_33) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_subst_33 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_22 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_49 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_subst_49) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= 0 v_aux_mod_memset_impl_~i~6_43_22) (<= v_subst_49 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_22 18446744073709551616)) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_subst_49 18446744073709551616)) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_22 9223372036854775807))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_46 Int) (v_aux_mod_memset_impl_~i~6_43_11 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int) (v_aux_mod_memset_impl_~i~6_43_30 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< v_aux_mod_memset_impl_~i~6_43_30 18446744073709551616) (< v_subst_46 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_30 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_subst_46 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_46) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_30) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_21 Int) (v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_54 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_21 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_subst_54 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_subst_54 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< 9223372036854775807 v_subst_54) (<= 0 v_aux_mod_memset_impl_~i~6_43_21) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_21 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_33 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_54 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_33 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_54 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_33 9223372036854775807) (< v_subst_54 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< 9223372036854775807 v_subst_54) (<= 0 v_aux_mod_memset_impl_~i~6_43_33) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int) (v_subst_45 Int) (v_aux_mod_memset_impl_~i~6_43_24 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_subst_45) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< v_aux_mod_memset_impl_~i~6_43_24 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_45 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_24) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_24 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_45 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_20 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_50 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< v_subst_50 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_20 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_50 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_aux_mod_memset_impl_~i~6_43_20 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_20) (< 9223372036854775807 v_subst_50) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_36 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int) (v_subst_33 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_36) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_36 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_33 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_36 18446744073709551616) (<= 0 v_subst_33) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_subst_33 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7)))))))) (not .cse6)) (and (let ((.cse7 (store (store (store .cse2 |c_my_memset_#in~s.offset| .cse5) .cse3 .cse5) .cse4 .cse5))) (or (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_4 Int)) (and (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807) (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_68 Int)) (and (< v_subst_68 18446744073709551616) (< 9223372036854775807 v_subst_68) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse5) (+ (mod v_subst_7 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_68 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5))))) (< v_subst_7 18446744073709551616))))) (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (exists ((v_subst_78 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_8 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_78 18446744073709551616)) .cse5)) |c_#memory_int|) (< 9223372036854775807 v_subst_78) (< v_subst_78 18446744073709551616))) (<= 0 v_subst_8) (<= v_subst_8 9223372036854775807))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_4 Int)) (and (<= 0 v_subst_4) (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_67 Int)) (and (<= 0 v_subst_67) (<= v_subst_67 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse5) (+ (mod v_subst_7 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_67 18446744073709551616)) .cse5)) |c_#memory_int|))) (< v_subst_7 18446744073709551616))) (<= v_subst_4 9223372036854775807))))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (exists ((v_subst_74 Int)) (and (< 9223372036854775807 v_subst_74) (< v_subst_74 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_2 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_23 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_74 18446744073709551616)) .cse5)) |c_#memory_int|))) (< v_subst_23 18446744073709551616))))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_5 Int)) (and (exists ((v_subst_27 Int)) (and (< 9223372036854775807 v_subst_27) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807) (exists ((v_subst_72 Int)) (and (< v_subst_72 18446744073709551616) (< 9223372036854775807 v_subst_72) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_27 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_72 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|))))) (< v_subst_27 18446744073709551616))) (< 9223372036854775807 v_subst_5) (< v_subst_5 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (exists ((v_subst_59 Int)) (and (<= 0 v_subst_59) (<= v_subst_59 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_16 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_59 18446744073709551616)) .cse5))))))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_57 Int)) (and (<= 0 v_subst_57) (<= v_subst_57 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_20 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_57 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|))))) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_24 Int)) (and (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807) (exists ((v_subst_75 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_2 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_24 18446744073709551616)) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_75 18446744073709551616)) .cse5)) |c_#memory_int|) (<= 0 v_subst_75) (<= v_subst_75 9223372036854775807))))))) (<= v_subst_2 9223372036854775807))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_58 Int)) (and (< v_subst_58 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_20 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_58 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (< 9223372036854775807 v_subst_58))))) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_subst_12 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_55 Int)) (and (<= v_subst_55 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse5) (+ (mod v_subst_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_55 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (<= 0 v_subst_55))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= v_subst_12 9223372036854775807) (<= 0 v_subst_12))) (<= 0 v_subst_6))))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (exists ((v_subst_62 Int)) (and (< 9223372036854775807 v_subst_62) (< v_subst_62 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_15 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_62 18446744073709551616)) .cse5))))) (< v_subst_15 18446744073709551616))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (exists ((v_subst_77 Int)) (and (<= 0 v_subst_77) (<= v_subst_77 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_8 18446744073709551616)) .cse5) (+ (mod v_subst_77 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|))) (<= 0 v_subst_8) (<= v_subst_8 9223372036854775807))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))))) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (exists ((v_subst_73 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_2 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_23 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_73 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (<= 0 v_subst_73) (<= v_subst_73 9223372036854775807))) (< v_subst_23 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_19 Int)) (and (exists ((v_subst_70 Int)) (and (< v_subst_70 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_19 18446744073709551616)) .cse5) (+ (mod v_subst_70 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (< 9223372036854775807 v_subst_70))) (< 9223372036854775807 v_subst_19) (< v_subst_19 18446744073709551616))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_subst_3 18446744073709551616))))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (exists ((v_subst_61 Int)) (and (<= v_subst_61 9223372036854775807) (<= 0 v_subst_61) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_15 18446744073709551616)) .cse5) (+ (mod v_subst_61 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5))))) (< v_subst_15 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_5 Int)) (and (exists ((v_subst_27 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_71 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_27 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_71 18446744073709551616)) .cse5))) (<= v_subst_71 9223372036854775807) (<= 0 v_subst_71))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (< 9223372036854775807 v_subst_27) (< v_subst_27 18446744073709551616))) (< 9223372036854775807 v_subst_5) (< v_subst_5 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_63 Int)) (and (<= v_subst_63 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_28 18446744073709551616)) .cse5) (+ (mod v_subst_63 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (<= 0 v_subst_63))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_subst_12 Int)) (and (<= v_subst_12 9223372036854775807) (<= 0 v_subst_12) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_56 Int)) (and (< 9223372036854775807 v_subst_56) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse5) (+ (mod v_subst_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_56 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (< v_subst_56 18446744073709551616))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))))) (<= 0 v_subst_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_24 Int)) (and (exists ((v_subst_76 Int)) (and (< v_subst_76 18446744073709551616) (< 9223372036854775807 v_subst_76) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_2 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_24 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_76 18446744073709551616)) .cse5)) |c_#memory_int|))) (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807))))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_subst_11 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_66 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_11 18446744073709551616)) .cse5) (+ (mod v_subst_66 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5))) (< v_subst_66 18446744073709551616) (< 9223372036854775807 v_subst_66))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_6))))) (< v_subst_11 18446744073709551616) (< 9223372036854775807 v_subst_11))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807) (exists ((v_subst_64 Int)) (and (< 9223372036854775807 v_subst_64) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_28 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_64 18446744073709551616)) .cse5)) |c_#memory_int|) (< v_subst_64 18446744073709551616))))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_19 Int)) (and (< 9223372036854775807 v_subst_19) (exists ((v_subst_69 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_19 18446744073709551616)) .cse5) (+ (mod v_subst_69 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (<= v_subst_69 9223372036854775807) (<= 0 v_subst_69))) (< v_subst_19 18446744073709551616))))) (< 9223372036854775807 v_subst_3) (< v_subst_3 18446744073709551616))))) (exists ((v_subst_11 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807) (exists ((v_subst_65 Int)) (and (<= v_subst_65 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_11 18446744073709551616)) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_65 18446744073709551616)) .cse5))) (<= 0 v_subst_65))))) (<= v_subst_6 9223372036854775807) (<= 0 v_subst_6))))) (< v_subst_11 18446744073709551616) (< 9223372036854775807 v_subst_11))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (exists ((v_subst_60 Int)) (and (< 9223372036854775807 v_subst_60) (< v_subst_60 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_16 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_60 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|))))) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))))) .cse6)))) is different from false [2022-11-16 11:44:26,834 WARN L855 $PredicateComparison]: unable to prove that (let ((.cse5 (mod |c_my_memset_#in~c| 256))) (let ((.cse2 (select |c_old(#memory_int)| |c_my_memset_#in~s.base|)) (.cse3 (+ |c_my_memset_#in~s.offset| 1)) (.cse4 (+ 2 |c_my_memset_#in~s.offset|)) (.cse6 (<= .cse5 127))) (or (and (let ((.cse1 (+ (- 256) .cse5))) (let ((.cse0 (store (store (store .cse2 |c_my_memset_#in~s.offset| .cse1) .cse3 .cse1) .cse4 .cse1))) (or (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_37 Int) (v_aux_mod_memset_impl_~i~6_43_31 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (<= v_subst_37 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_31 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_31) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_31 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_37 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (<= 0 v_subst_37) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_32 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_49 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_32) (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_32 9223372036854775807) (<= 0 v_subst_49) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_49 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_32 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_subst_49 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_17 Int) (v_subst_41 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_17 9223372036854775807) (<= v_subst_41 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_17) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_17 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_subst_41 18446744073709551616)) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (<= 0 v_subst_41) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_14 Int) (v_aux_mod_memset_impl_~i~6_43_38 Int) (v_subst_50 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_38) (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_38 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< v_subst_50 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_38 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_50 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_50) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_46 Int) (v_aux_mod_memset_impl_~i~6_43_11 Int) (v_aux_mod_memset_impl_~i~6_43_18 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_18) (< v_subst_46 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_18 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_46) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_18 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_46 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_34 Int) (v_aux_mod_memset_impl_~i~6_43_25 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_25 18446744073709551616) (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< v_subst_34 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_25 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_34 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_25) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< 9223372036854775807 v_subst_34))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_aux_mod_memset_impl_~i~6_43_35 Int) (v_subst_38 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_35 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_38 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< 9223372036854775807 v_subst_38) (< v_subst_38 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_35 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_35) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_34 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_53 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_34 9223372036854775807) (<= 0 v_subst_53) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_34 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_53 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (<= 0 v_aux_mod_memset_impl_~i~6_43_34) (<= v_subst_53 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_37 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_42 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (< 9223372036854775807 v_subst_42) (<= 0 v_aux_mod_memset_impl_~i~6_43_37) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_37 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_42 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (<= v_aux_mod_memset_impl_~i~6_43_37 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< v_subst_42 18446744073709551616))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_26 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_42 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= v_aux_mod_memset_impl_~i~6_43_26 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (< 9223372036854775807 v_subst_42) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_26 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_42 18446744073709551616)) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_26) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< v_subst_42 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int) (v_subst_45 Int) (v_aux_mod_memset_impl_~i~6_43_29 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_29) (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_29 18446744073709551616) (<= 0 v_subst_45) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_29 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_45 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_45 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_23 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_53 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_23 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_23) (<= 0 v_subst_53) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_23 18446744073709551616)) .cse1) (+ (mod v_subst_53 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (<= v_subst_53 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_37 Int) (v_aux_mod_memset_impl_~i~6_43_16 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int)) (and (<= v_subst_37 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_16) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_16 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_16 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_37 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (<= 0 v_subst_37) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_34 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_28 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_28) (< v_subst_34 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (< v_aux_mod_memset_impl_~i~6_43_28 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_28 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_34 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (<= 0 v_aux_mod_memset_impl_~i~6_43_7) (< 9223372036854775807 v_subst_34))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_10 Int) (v_subst_38 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_aux_mod_memset_impl_~i~6_43_19 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_19 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_38 18446744073709551616)) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (< v_aux_mod_memset_impl_~i~6_43_10 18446744073709551616) (< 9223372036854775807 v_subst_38) (< v_subst_38 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_19) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_10) (< v_aux_mod_memset_impl_~i~6_43_19 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_13 Int) (v_aux_mod_memset_impl_~i~6_43_27 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_subst_41 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_13) (<= 0 v_aux_mod_memset_impl_~i~6_43_27) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_13 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_27 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_subst_41 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (<= v_subst_41 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_13 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_27 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= 0 v_subst_41) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_15 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int) (v_subst_33 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_15 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_33 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_15) (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< v_aux_mod_memset_impl_~i~6_43_15 18446744073709551616) (<= 0 v_subst_33) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_subst_33 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_22 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_49 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_subst_49) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= 0 v_aux_mod_memset_impl_~i~6_43_22) (<= v_subst_49 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_22 18446744073709551616)) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_subst_49 18446744073709551616)) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_22 9223372036854775807))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_46 Int) (v_aux_mod_memset_impl_~i~6_43_11 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int) (v_aux_mod_memset_impl_~i~6_43_30 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< v_aux_mod_memset_impl_~i~6_43_30 18446744073709551616) (< v_subst_46 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_30 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_subst_46 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (< 9223372036854775807 v_subst_46) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_30) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_21 Int) (v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_54 Int)) (and (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_21 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_subst_54 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_subst_54 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< 9223372036854775807 v_subst_54) (<= 0 v_aux_mod_memset_impl_~i~6_43_21) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_21 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_12 Int) (v_aux_mod_memset_impl_~i~6_43_33 Int) (v_aux_mod_memset_impl_~i~6_43_6 Int) (v_subst_54 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_33 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_54 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_6 18446744073709551616) (<= v_aux_mod_memset_impl_~i~6_43_33 9223372036854775807) (< v_subst_54 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_12) (< 9223372036854775807 v_subst_54) (<= 0 v_aux_mod_memset_impl_~i~6_43_33) (< v_aux_mod_memset_impl_~i~6_43_12 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_6))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_11 Int) (v_subst_45 Int) (v_aux_mod_memset_impl_~i~6_43_24 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_11 9223372036854775807) (<= 0 v_subst_45) (<= 0 v_aux_mod_memset_impl_~i~6_43_11) (< v_aux_mod_memset_impl_~i~6_43_24 18446744073709551616) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_subst_45 9223372036854775807) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_24) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_11 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_24 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_45 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_aux_mod_memset_impl_~i~6_43_20 Int) (v_aux_mod_memset_impl_~i~6_43_14 Int) (v_subst_50 Int) (v_aux_mod_memset_impl_~i~6_43_8 Int)) (and (<= v_aux_mod_memset_impl_~i~6_43_14 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_14) (< v_subst_50 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_14 18446744073709551616)) .cse1) (+ (mod v_aux_mod_memset_impl_~i~6_43_20 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod v_subst_50 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_8) (<= v_aux_mod_memset_impl_~i~6_43_20 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_20) (< 9223372036854775807 v_subst_50) (< v_aux_mod_memset_impl_~i~6_43_8 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_36 Int) (v_aux_mod_memset_impl_~i~6_43_7 Int) (v_aux_mod_memset_impl_~i~6_43_9 Int) (v_subst_33 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_9) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_36) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse0 (+ (mod v_aux_mod_memset_impl_~i~6_43_7 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_9 18446744073709551616)) .cse1) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_36 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (mod v_subst_33 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse1)) |c_#memory_int|) (< v_aux_mod_memset_impl_~i~6_43_36 18446744073709551616) (<= 0 v_subst_33) (<= v_aux_mod_memset_impl_~i~6_43_7 9223372036854775807) (<= v_subst_33 9223372036854775807) (<= v_aux_mod_memset_impl_~i~6_43_9 9223372036854775807) (<= 0 v_aux_mod_memset_impl_~i~6_43_7)))))))) (not .cse6)) (and (let ((.cse7 (store (store (store .cse2 |c_my_memset_#in~s.offset| .cse5) .cse3 .cse5) .cse4 .cse5))) (or (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_4 Int)) (and (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807) (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_68 Int)) (and (< v_subst_68 18446744073709551616) (< 9223372036854775807 v_subst_68) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse5) (+ (mod v_subst_7 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_68 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5))))) (< v_subst_7 18446744073709551616))))) (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (exists ((v_subst_78 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_8 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_78 18446744073709551616)) .cse5)) |c_#memory_int|) (< 9223372036854775807 v_subst_78) (< v_subst_78 18446744073709551616))) (<= 0 v_subst_8) (<= v_subst_8 9223372036854775807))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_4 Int)) (and (<= 0 v_subst_4) (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_67 Int)) (and (<= 0 v_subst_67) (<= v_subst_67 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse5) (+ (mod v_subst_7 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_67 18446744073709551616)) .cse5)) |c_#memory_int|))) (< v_subst_7 18446744073709551616))) (<= v_subst_4 9223372036854775807))))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (exists ((v_subst_74 Int)) (and (< 9223372036854775807 v_subst_74) (< v_subst_74 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_2 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_23 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_74 18446744073709551616)) .cse5)) |c_#memory_int|))) (< v_subst_23 18446744073709551616))))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_5 Int)) (and (exists ((v_subst_27 Int)) (and (< 9223372036854775807 v_subst_27) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807) (exists ((v_subst_72 Int)) (and (< v_subst_72 18446744073709551616) (< 9223372036854775807 v_subst_72) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_27 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_72 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|))))) (< v_subst_27 18446744073709551616))) (< 9223372036854775807 v_subst_5) (< v_subst_5 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (exists ((v_subst_59 Int)) (and (<= 0 v_subst_59) (<= v_subst_59 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_16 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_59 18446744073709551616)) .cse5))))))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_57 Int)) (and (<= 0 v_subst_57) (<= v_subst_57 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_20 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_57 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|))))) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_24 Int)) (and (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807) (exists ((v_subst_75 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_2 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_24 18446744073709551616)) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_75 18446744073709551616)) .cse5)) |c_#memory_int|) (<= 0 v_subst_75) (<= v_subst_75 9223372036854775807))))))) (<= v_subst_2 9223372036854775807))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_58 Int)) (and (< v_subst_58 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_20 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_58 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (< 9223372036854775807 v_subst_58))))) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_subst_12 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_55 Int)) (and (<= v_subst_55 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse5) (+ (mod v_subst_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_55 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (<= 0 v_subst_55))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= v_subst_12 9223372036854775807) (<= 0 v_subst_12))) (<= 0 v_subst_6))))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (exists ((v_subst_62 Int)) (and (< 9223372036854775807 v_subst_62) (< v_subst_62 18446744073709551616) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_15 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_62 18446744073709551616)) .cse5))))) (< v_subst_15 18446744073709551616))))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (exists ((v_subst_77 Int)) (and (<= 0 v_subst_77) (<= v_subst_77 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_4 18446744073709551616)) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_8 18446744073709551616)) .cse5) (+ (mod v_subst_77 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|))) (<= 0 v_subst_8) (<= v_subst_8 9223372036854775807))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))))) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (exists ((v_subst_73 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_2 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_23 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_73 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (<= 0 v_subst_73) (<= v_subst_73 9223372036854775807))) (< v_subst_23 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_19 Int)) (and (exists ((v_subst_70 Int)) (and (< v_subst_70 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_19 18446744073709551616)) .cse5) (+ (mod v_subst_70 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (< 9223372036854775807 v_subst_70))) (< 9223372036854775807 v_subst_19) (< v_subst_19 18446744073709551616))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_subst_3 18446744073709551616))))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (exists ((v_subst_61 Int)) (and (<= v_subst_61 9223372036854775807) (<= 0 v_subst_61) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_15 18446744073709551616)) .cse5) (+ (mod v_subst_61 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5))))) (< v_subst_15 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_5 Int)) (and (exists ((v_subst_27 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_71 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_27 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_71 18446744073709551616)) .cse5))) (<= v_subst_71 9223372036854775807) (<= 0 v_subst_71))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (< 9223372036854775807 v_subst_27) (< v_subst_27 18446744073709551616))) (< 9223372036854775807 v_subst_5) (< v_subst_5 18446744073709551616))))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_63 Int)) (and (<= v_subst_63 9223372036854775807) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_28 18446744073709551616)) .cse5) (+ (mod v_subst_63 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (<= 0 v_subst_63))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_subst_12 Int)) (and (<= v_subst_12 9223372036854775807) (<= 0 v_subst_12) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_56 Int)) (and (< 9223372036854775807 v_subst_56) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse5) (+ (mod v_subst_12 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_56 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (< v_subst_56 18446744073709551616))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))))) (<= 0 v_subst_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_24 Int)) (and (exists ((v_subst_76 Int)) (and (< v_subst_76 18446744073709551616) (< 9223372036854775807 v_subst_76) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_2 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_24 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_76 18446744073709551616)) .cse5)) |c_#memory_int|))) (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807))))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (exists ((v_subst_11 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_66 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_11 18446744073709551616)) .cse5) (+ (mod v_subst_66 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5))) (< v_subst_66 18446744073709551616) (< 9223372036854775807 v_subst_66))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_6))))) (< v_subst_11 18446744073709551616) (< 9223372036854775807 v_subst_11))) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807) (exists ((v_subst_64 Int)) (and (< 9223372036854775807 v_subst_64) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_28 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_64 18446744073709551616)) .cse5)) |c_#memory_int|) (< v_subst_64 18446744073709551616))))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (exists ((v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_19 Int)) (and (< 9223372036854775807 v_subst_19) (exists ((v_subst_69 Int)) (and (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616)) .cse5) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_19 18446744073709551616)) .cse5) (+ (mod v_subst_69 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|) (<= v_subst_69 9223372036854775807) (<= 0 v_subst_69))) (< v_subst_19 18446744073709551616))))) (< 9223372036854775807 v_subst_3) (< v_subst_3 18446744073709551616))))) (exists ((v_subst_11 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807) (exists ((v_subst_65 Int)) (and (<= v_subst_65 9223372036854775807) (= |c_#memory_int| (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ |c_my_memset_#in~s.offset| (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616)) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_6 18446744073709551616)) .cse5) (+ (- 18446744073709551616) |c_my_memset_#in~s.offset| (mod v_subst_11 18446744073709551616)) .cse5) (+ |c_my_memset_#in~s.offset| (mod v_subst_65 18446744073709551616)) .cse5))) (<= 0 v_subst_65))))) (<= v_subst_6 9223372036854775807) (<= 0 v_subst_6))))) (< v_subst_11 18446744073709551616) (< 9223372036854775807 v_subst_11))) (exists ((v_subst_1 Int)) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (exists ((v_subst_60 Int)) (and (< 9223372036854775807 v_subst_60) (< v_subst_60 18446744073709551616) (= (store |c_old(#memory_int)| |c_my_memset_#in~s.base| (store (store (store (store (store .cse7 (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (mod v_subst_16 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5) (+ (- 18446744073709551616) (mod v_subst_60 18446744073709551616) |c_my_memset_#in~s.offset|) .cse5)) |c_#memory_int|))))) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))))) .cse6)))) is different from true [2022-11-16 11:45:02,115 WARN L833 $PredicateComparison]: unable to prove that (and (not (= (mod (select (select |c_old(#memory_int)| |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset|) 256) 0)) (let ((.cse1 (+ |c_aws_array_list_clean_up_#in~list.offset| 1)) (.cse2 (+ 2 |c_aws_array_list_clean_up_#in~list.offset|))) (or (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_subst_1 Int) (v_ArrVal_5729 (Array Int Int))) (and (< v_subst_1 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (exists ((v_subst_60 Int)) (and (< 9223372036854775807 v_subst_60) (< v_subst_60 18446744073709551616) (= (let ((.cse0 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse0 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse0 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_16 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_60 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|))) (<= v_subst_16 9223372036854775807))) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (< 9223372036854775807 v_subst_1))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int) (v_ArrVal_5729 (Array Int Int))) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (exists ((v_subst_73 Int)) (and (<= 0 v_subst_73) (<= v_subst_73 9223372036854775807) (= (let ((.cse3 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse3 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse3 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_2 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_23 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_73 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|))) (< v_subst_23 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int) (v_ArrVal_5729 (Array Int Int))) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_24 Int)) (and (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807) (exists ((v_subst_76 Int)) (and (= |c_#memory_int| (let ((.cse4 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse4 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse4 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_2 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_24 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_76 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0)))) (< v_subst_76 18446744073709551616) (< 9223372036854775807 v_subst_76))))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_subst_1 Int) (v_ArrVal_5729 (Array Int Int))) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (exists ((v_subst_62 Int)) (and (< 9223372036854775807 v_subst_62) (= |c_#memory_int| (let ((.cse5 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse5 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse5 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_15 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_62 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0)))) (< v_subst_62 18446744073709551616))) (< v_subst_15 18446744073709551616))) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int) (v_ArrVal_5729 (Array Int Int))) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_23 Int)) (and (< 9223372036854775807 v_subst_23) (exists ((v_subst_74 Int)) (and (< 9223372036854775807 v_subst_74) (= |c_#memory_int| (let ((.cse6 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse6 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse6 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_2 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_23 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_74 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0)))) (< v_subst_74 18446744073709551616))) (< v_subst_23 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((v_ArrVal_5729 (Array Int Int)) (v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_3 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_19 Int)) (and (< 9223372036854775807 v_subst_19) (< v_subst_19 18446744073709551616) (exists ((v_subst_70 Int)) (and (< v_subst_70 18446744073709551616) (= (let ((.cse7 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse7 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse7 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_19 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_70 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (< 9223372036854775807 v_subst_70))))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< 9223372036854775807 v_subst_3) (< v_subst_3 18446744073709551616))))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_subst_1 Int) (v_ArrVal_5729 (Array Int Int))) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_15 Int)) (and (< 9223372036854775807 v_subst_15) (exists ((v_subst_61 Int)) (and (<= v_subst_61 9223372036854775807) (<= 0 v_subst_61) (= (let ((.cse8 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse8 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse8 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_15 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_61 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|))) (< v_subst_15 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_ArrVal_5729 (Array Int Int)) (v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_68 Int)) (and (< v_subst_68 18446744073709551616) (< 9223372036854775807 v_subst_68) (= |c_#memory_int| (let ((.cse9 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse9 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse9 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_7 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_68 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0)))))) (< v_subst_7 18446744073709551616))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int) (v_ArrVal_5729 (Array Int Int))) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((v_subst_2 Int)) (and (<= 0 v_subst_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_24 Int)) (and (exists ((v_subst_75 Int)) (and (= |c_#memory_int| (let ((.cse10 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse10 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse10 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_2 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_24 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_75 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0)))) (<= 0 v_subst_75) (<= v_subst_75 9223372036854775807))) (<= 0 v_subst_24) (<= v_subst_24 9223372036854775807))))) (<= v_subst_2 9223372036854775807))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_ArrVal_5729 (Array Int Int)) (v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_57 Int)) (and (<= 0 v_subst_57) (<= v_subst_57 9223372036854775807) (= |c_#memory_int| (let ((.cse11 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse11 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse11 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_20 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_57 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0)))))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< 9223372036854775807 v_subst_3) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((aux_mod_memset_impl_~i~6_43 Int) (v_ArrVal_5729 (Array Int Int))) (and (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_subst_12 Int)) (and (<= v_subst_12 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_56 Int)) (and (< 9223372036854775807 v_subst_56) (= (let ((.cse12 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse12 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse12 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_6 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_12 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_56 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (< v_subst_56 18446744073709551616))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_12))) (<= 0 v_subst_6))))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((v_ArrVal_5729 (Array Int Int)) (v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (<= 0 v_subst_8) (exists ((v_subst_78 Int)) (and (= (let ((.cse13 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse13 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse13 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ |c_aws_array_list_clean_up_#in~list.offset| (mod v_subst_8 18446744073709551616)) 0) (+ (- 18446744073709551616) (mod v_subst_78 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (< 9223372036854775807 v_subst_78) (< v_subst_78 18446744073709551616))) (<= v_subst_8 9223372036854775807))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))))))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_subst_11 Int) (v_ArrVal_5729 (Array Int Int))) (and (< v_subst_11 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_66 Int)) (and (< v_subst_66 18446744073709551616) (= (let ((.cse14 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse14 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse14 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_6 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_11 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_66 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (< 9223372036854775807 v_subst_66))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (< 9223372036854775807 v_subst_11))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_subst_11 Int) (v_ArrVal_5729 (Array Int Int))) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (<= 0 v_subst_6) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_65 Int)) (and (= (let ((.cse15 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse15 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse15 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_6 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_11 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_65 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (<= v_subst_65 9223372036854775807) (<= 0 v_subst_65))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_subst_11 18446744073709551616) (< 9223372036854775807 v_subst_11))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_subst_1 Int) (v_ArrVal_5729 (Array Int Int))) (and (< v_subst_1 18446744073709551616) (< 9223372036854775807 v_subst_1) (exists ((v_aux_mod_memset_impl_~i~6_43_2 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_2) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (exists ((v_subst_16 Int)) (and (<= 0 v_subst_16) (<= v_subst_16 9223372036854775807) (exists ((v_subst_59 Int)) (and (<= 0 v_subst_59) (= (let ((.cse16 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse16 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse16 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_16 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ |c_aws_array_list_clean_up_#in~list.offset| (mod v_subst_59 18446744073709551616)) 0))) |c_#memory_int|) (<= v_subst_59 9223372036854775807))))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (< v_aux_mod_memset_impl_~i~6_43_2 18446744073709551616))))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((aux_mod_memset_impl_~i~6_43 Int) (v_ArrVal_5729 (Array Int Int))) (and (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_27 Int)) (and (< 9223372036854775807 v_subst_27) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_72 Int)) (and (< v_subst_72 18446744073709551616) (= (let ((.cse17 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse17 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse17 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_27 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_72 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (< 9223372036854775807 v_subst_72))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (< v_subst_27 18446744073709551616))) (< v_subst_5 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((v_ArrVal_5729 (Array Int Int)) (v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_4 Int)) (and (exists ((v_subst_8 Int)) (and (<= 0 v_subst_8) (exists ((v_subst_77 Int)) (and (<= 0 v_subst_77) (<= v_subst_77 9223372036854775807) (= |c_#memory_int| (let ((.cse18 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse18 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse18 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ |c_aws_array_list_clean_up_#in~list.offset| (mod v_subst_8 18446744073709551616)) 0) (+ (mod v_subst_77 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0)))))) (<= v_subst_8 9223372036854775807))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((aux_mod_memset_impl_~i~6_43 Int) (v_ArrVal_5729 (Array Int Int))) (and (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_64 Int)) (and (< 9223372036854775807 v_subst_64) (< v_subst_64 18446744073709551616) (= (let ((.cse19 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse19 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse19 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_28 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_64 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int) (v_ArrVal_5729 (Array Int Int))) (and (exists ((v_subst_6 Int)) (and (<= v_subst_6 9223372036854775807) (exists ((v_subst_12 Int)) (and (<= v_subst_12 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_55 Int)) (and (<= v_subst_55 9223372036854775807) (<= 0 v_subst_55) (= (let ((.cse20 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse20 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse20 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_6 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_12 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_55 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_12))) (<= 0 v_subst_6))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((v_ArrVal_5729 (Array Int Int)) (v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((v_subst_20 Int)) (and (<= v_subst_20 9223372036854775807) (exists ((v_subst_3 Int)) (and (< 9223372036854775807 v_subst_3) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_58 Int)) (and (< v_subst_58 18446744073709551616) (= (let ((.cse21 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse21 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse21 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_20 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_58 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (< 9223372036854775807 v_subst_58))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< v_subst_3 18446744073709551616))) (<= 0 v_subst_20))))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int) (v_ArrVal_5729 (Array Int Int))) (and (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_27 Int)) (and (< 9223372036854775807 v_subst_27) (< v_subst_27 18446744073709551616) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (exists ((v_subst_71 Int)) (and (<= v_subst_71 9223372036854775807) (= (let ((.cse22 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse22 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse22 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_27 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_71 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (<= 0 v_subst_71))) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))))) (< v_subst_5 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))) (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((v_ArrVal_5729 (Array Int Int)) (v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (exists ((v_subst_3 Int)) (and (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (exists ((v_subst_19 Int)) (and (< 9223372036854775807 v_subst_19) (< v_subst_19 18446744073709551616) (exists ((v_subst_69 Int)) (and (= (let ((.cse23 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse23 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse23 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_3 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_19 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_69 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (<= v_subst_69 9223372036854775807) (<= 0 v_subst_69))))) (< aux_mod_memset_impl_~i~6_43 18446744073709551616))) (< 9223372036854775807 v_subst_3) (< v_subst_3 18446744073709551616))) (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((aux_mod_memset_impl_~i~6_43 Int) (v_ArrVal_5729 (Array Int Int))) (and (exists ((v_subst_5 Int)) (and (< 9223372036854775807 v_subst_5) (exists ((v_subst_28 Int)) (and (<= v_subst_28 9223372036854775807) (exists ((v_aux_mod_memset_impl_~i~6_43_1 Int)) (and (exists ((v_subst_63 Int)) (and (<= v_subst_63 9223372036854775807) (= (let ((.cse24 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse24 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse24 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (mod v_aux_mod_memset_impl_~i~6_43_1 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod v_subst_5 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_28 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_63 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0))) |c_#memory_int|) (<= 0 v_subst_63))) (<= 0 v_aux_mod_memset_impl_~i~6_43_1) (<= v_aux_mod_memset_impl_~i~6_43_1 9223372036854775807))) (<= 0 v_subst_28))) (< v_subst_5 18446744073709551616))) (<= aux_mod_memset_impl_~i~6_43 9223372036854775807) (<= 0 aux_mod_memset_impl_~i~6_43))))) (exists ((|aws_array_list_is_valid_~#required_size~0.base| Int)) (and (= (select (select |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base|) 0) 0) (exists ((v_ArrVal_5729 (Array Int Int)) (v_aux_mod_memset_impl_~i~6_43_4 Int)) (and (< 9223372036854775807 v_aux_mod_memset_impl_~i~6_43_4) (< v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) (exists ((aux_mod_memset_impl_~i~6_43 Int)) (and (< 9223372036854775807 aux_mod_memset_impl_~i~6_43) (< aux_mod_memset_impl_~i~6_43 18446744073709551616) (exists ((v_subst_4 Int)) (and (exists ((v_subst_7 Int)) (and (< 9223372036854775807 v_subst_7) (exists ((v_subst_67 Int)) (and (<= 0 v_subst_67) (<= v_subst_67 9223372036854775807) (= |c_#memory_int| (let ((.cse25 (store |c_old(#memory_int)| |aws_array_list_is_valid_~#required_size~0.base| v_ArrVal_5729))) (store .cse25 |c_aws_array_list_clean_up_#in~list.base| (store (store (store (store (store (store (store (store (select .cse25 |c_aws_array_list_clean_up_#in~list.base|) |c_aws_array_list_clean_up_#in~list.offset| 0) .cse1 0) .cse2 0) (+ (- 18446744073709551616) (mod v_aux_mod_memset_impl_~i~6_43_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (- 18446744073709551616) (mod aux_mod_memset_impl_~i~6_43 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_4 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_7 18446744073709551616) (- 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0) (+ (mod v_subst_67 18446744073709551616) |c_aws_array_list_clean_up_#in~list.offset|) 0)))))) (< v_subst_7 18446744073709551616))) (<= 0 v_subst_4) (<= v_subst_4 9223372036854775807)))))))))))) is different from false