./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version e04fb08f Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/config/AutomizerReach.xml -i ../../sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0bd5c2784fe43830be309c722c3fa9fc4d3ef116c17a8343acb2a2dfbcf830c0 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-e04fb08 [2022-11-16 11:31:41,766 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-16 11:31:41,769 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-16 11:31:41,816 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-16 11:31:41,818 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-16 11:31:41,824 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-16 11:31:41,827 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-16 11:31:41,832 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-16 11:31:41,836 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-16 11:31:41,843 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-16 11:31:41,845 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-16 11:31:41,847 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-16 11:31:41,848 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-16 11:31:41,851 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-16 11:31:41,853 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-16 11:31:41,856 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-16 11:31:41,859 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-16 11:31:41,860 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-16 11:31:41,866 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-16 11:31:41,870 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-16 11:31:41,875 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-16 11:31:41,877 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-16 11:31:41,880 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-16 11:31:41,882 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-16 11:31:41,889 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-16 11:31:41,890 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-16 11:31:41,895 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-16 11:31:41,896 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-16 11:31:41,898 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-16 11:31:41,899 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-16 11:31:41,900 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-16 11:31:41,901 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-16 11:31:41,904 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-16 11:31:41,905 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-16 11:31:41,908 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-16 11:31:41,909 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-16 11:31:41,910 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-16 11:31:41,910 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-16 11:31:41,910 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-16 11:31:41,911 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-16 11:31:41,912 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-16 11:31:41,913 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/config/svcomp-Reach-32bit-Automizer_Default.epf [2022-11-16 11:31:41,968 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-16 11:31:41,969 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-16 11:31:41,969 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-16 11:31:41,970 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-16 11:31:41,971 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-16 11:31:41,971 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-16 11:31:41,972 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-16 11:31:41,973 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-16 11:31:41,973 INFO L138 SettingsManager]: * Use SBE=true [2022-11-16 11:31:41,973 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-16 11:31:41,975 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-16 11:31:41,975 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-16 11:31:41,975 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-16 11:31:41,976 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-16 11:31:41,976 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-16 11:31:41,976 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-16 11:31:41,976 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-16 11:31:41,977 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-16 11:31:41,977 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-16 11:31:41,977 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-16 11:31:41,977 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-16 11:31:41,978 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-16 11:31:41,978 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-16 11:31:41,978 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-16 11:31:41,979 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-16 11:31:41,979 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-16 11:31:41,982 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-16 11:31:41,982 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-16 11:31:41,982 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-16 11:31:41,983 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-16 11:31:41,983 INFO L138 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2022-11-16 11:31:41,983 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-11-16 11:31:41,984 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-16 11:31:41,984 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0bd5c2784fe43830be309c722c3fa9fc4d3ef116c17a8343acb2a2dfbcf830c0 [2022-11-16 11:31:42,354 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-16 11:31:42,389 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-16 11:31:42,392 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-16 11:31:42,393 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-16 11:31:42,394 INFO L275 PluginConnector]: CDTParser initialized [2022-11-16 11:31:42,395 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/../../sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c [2022-11-16 11:31:42,494 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/data/899841e70/74fa0b55d073487493cbefc4bd33a06d/FLAG32978086f [2022-11-16 11:31:43,022 INFO L306 CDTParser]: Found 1 translation units. [2022-11-16 11:31:43,023 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c [2022-11-16 11:31:43,031 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/data/899841e70/74fa0b55d073487493cbefc4bd33a06d/FLAG32978086f [2022-11-16 11:31:43,431 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/data/899841e70/74fa0b55d073487493cbefc4bd33a06d [2022-11-16 11:31:43,436 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-16 11:31:43,438 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-16 11:31:43,440 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-16 11:31:43,440 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-16 11:31:43,445 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-16 11:31:43,445 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,447 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@58792438 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43, skipping insertion in model container [2022-11-16 11:31:43,447 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,456 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-16 11:31:43,477 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-16 11:31:43,664 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c[573,586] [2022-11-16 11:31:43,680 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:31:43,689 INFO L203 MainTranslator]: Completed pre-run [2022-11-16 11:31:43,704 WARN L229 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c[573,586] [2022-11-16 11:31:43,709 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-16 11:31:43,727 INFO L208 MainTranslator]: Completed translation [2022-11-16 11:31:43,728 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43 WrapperNode [2022-11-16 11:31:43,728 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-16 11:31:43,729 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-16 11:31:43,729 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-16 11:31:43,730 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-16 11:31:43,739 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,746 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,762 INFO L138 Inliner]: procedures = 14, calls = 11, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 47 [2022-11-16 11:31:43,763 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-16 11:31:43,764 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-16 11:31:43,764 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-16 11:31:43,764 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-16 11:31:43,772 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,772 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,774 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,774 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,777 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,782 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,784 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,785 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,786 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-16 11:31:43,787 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-16 11:31:43,788 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-16 11:31:43,788 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-16 11:31:43,789 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (1/1) ... [2022-11-16 11:31:43,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-16 11:31:43,810 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:43,822 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-16 11:31:43,824 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-16 11:31:43,861 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-16 11:31:43,861 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2022-11-16 11:31:43,862 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2022-11-16 11:31:43,862 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-16 11:31:43,862 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-16 11:31:43,862 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-16 11:31:43,862 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-11-16 11:31:43,862 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-11-16 11:31:43,926 INFO L235 CfgBuilder]: Building ICFG [2022-11-16 11:31:43,928 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-16 11:31:44,078 INFO L276 CfgBuilder]: Performing block encoding [2022-11-16 11:31:44,086 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-16 11:31:44,087 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-16 11:31:44,089 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:31:44 BoogieIcfgContainer [2022-11-16 11:31:44,089 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-16 11:31:44,112 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-16 11:31:44,112 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-16 11:31:44,117 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-16 11:31:44,118 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 16.11 11:31:43" (1/3) ... [2022-11-16 11:31:44,119 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32404d77 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 11:31:44, skipping insertion in model container [2022-11-16 11:31:44,119 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.11 11:31:43" (2/3) ... [2022-11-16 11:31:44,120 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32404d77 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.11 11:31:44, skipping insertion in model container [2022-11-16 11:31:44,120 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:31:44" (3/3) ... [2022-11-16 11:31:44,122 INFO L112 eAbstractionObserver]: Analyzing ICFG mannadiv_unwindbound100.c [2022-11-16 11:31:44,146 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-16 11:31:44,146 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-16 11:31:44,209 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-16 11:31:44,218 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@63ca9bf, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-16 11:31:44,218 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-16 11:31:44,224 INFO L276 IsEmpty]: Start isEmpty. Operand has 25 states, 17 states have (on average 1.411764705882353) internal successors, (24), 18 states have internal predecessors, (24), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2022-11-16 11:31:44,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-11-16 11:31:44,234 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:31:44,235 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:44,236 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:31:44,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:44,242 INFO L85 PathProgramCache]: Analyzing trace with hash 1086166160, now seen corresponding path program 1 times [2022-11-16 11:31:44,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:44,255 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831851241] [2022-11-16 11:31:44,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:44,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:44,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:44,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:44,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831851241] [2022-11-16 11:31:44,491 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-11-16 11:31:44,492 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [365135867] [2022-11-16 11:31:44,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:44,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:44,493 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:44,499 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:44,528 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-16 11:31:44,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:44,635 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 1 conjunts are in the unsatisfiable core [2022-11-16 11:31:44,640 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:44,687 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-16 11:31:44,688 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:31:44,690 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [365135867] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:44,692 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:44,693 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-16 11:31:44,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127062894] [2022-11-16 11:31:44,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:44,708 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2022-11-16 11:31:44,708 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:44,762 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-16 11:31:44,764 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 11:31:44,766 INFO L87 Difference]: Start difference. First operand has 25 states, 17 states have (on average 1.411764705882353) internal successors, (24), 18 states have internal predecessors, (24), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) Second operand has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-16 11:31:44,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:44,807 INFO L93 Difference]: Finished difference Result 47 states and 64 transitions. [2022-11-16 11:31:44,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-16 11:31:44,829 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 18 [2022-11-16 11:31:44,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:31:44,839 INFO L225 Difference]: With dead ends: 47 [2022-11-16 11:31:44,842 INFO L226 Difference]: Without dead ends: 21 [2022-11-16 11:31:44,846 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-16 11:31:44,850 INFO L413 NwaCegarLoop]: 29 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 29 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:31:44,852 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-16 11:31:44,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2022-11-16 11:31:44,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-11-16 11:31:44,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:31:44,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2022-11-16 11:31:44,911 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 18 [2022-11-16 11:31:44,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:31:44,912 INFO L495 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2022-11-16 11:31:44,913 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-16 11:31:44,913 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2022-11-16 11:31:44,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-11-16 11:31:44,916 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:31:44,916 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:44,937 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-11-16 11:31:45,123 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:45,124 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:31:45,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:45,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1345709874, now seen corresponding path program 1 times [2022-11-16 11:31:45,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:45,134 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019578921] [2022-11-16 11:31:45,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:45,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:45,179 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:31:45,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1320272879] [2022-11-16 11:31:45,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:45,180 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:45,181 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:45,182 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:45,187 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-16 11:31:45,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:45,279 INFO L263 TraceCheckSpWp]: Trace formula consists of 69 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-16 11:31:45,281 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:45,402 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-16 11:31:45,403 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:31:45,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:45,407 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019578921] [2022-11-16 11:31:45,407 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:31:45,407 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1320272879] [2022-11-16 11:31:45,409 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1320272879] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:45,409 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:45,410 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-16 11:31:45,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83699790] [2022-11-16 11:31:45,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:45,416 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-16 11:31:45,417 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:45,417 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-16 11:31:45,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:31:45,419 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-16 11:31:45,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:45,461 INFO L93 Difference]: Finished difference Result 30 states and 34 transitions. [2022-11-16 11:31:45,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-16 11:31:45,467 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 19 [2022-11-16 11:31:45,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:31:45,468 INFO L225 Difference]: With dead ends: 30 [2022-11-16 11:31:45,468 INFO L226 Difference]: Without dead ends: 23 [2022-11-16 11:31:45,469 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-16 11:31:45,470 INFO L413 NwaCegarLoop]: 23 mSDtfsCounter, 0 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 57 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:31:45,471 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 57 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-16 11:31:45,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2022-11-16 11:31:45,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2022-11-16 11:31:45,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 16 states have (on average 1.25) internal successors, (20), 17 states have internal predecessors, (20), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:31:45,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 27 transitions. [2022-11-16 11:31:45,478 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 27 transitions. Word has length 19 [2022-11-16 11:31:45,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:31:45,481 INFO L495 AbstractCegarLoop]: Abstraction has 23 states and 27 transitions. [2022-11-16 11:31:45,481 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-16 11:31:45,481 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 27 transitions. [2022-11-16 11:31:45,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-11-16 11:31:45,482 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:31:45,482 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:45,488 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-11-16 11:31:45,687 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable1 [2022-11-16 11:31:45,688 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:31:45,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:45,689 INFO L85 PathProgramCache]: Analyzing trace with hash 1347497334, now seen corresponding path program 1 times [2022-11-16 11:31:45,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:45,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223966847] [2022-11-16 11:31:45,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:45,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:45,716 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:31:45,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1923895142] [2022-11-16 11:31:45,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:45,725 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:45,725 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:45,744 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:45,778 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-16 11:31:45,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:45,846 INFO L263 TraceCheckSpWp]: Trace formula consists of 69 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-16 11:31:45,849 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:46,060 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:31:46,060 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-16 11:31:46,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:46,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223966847] [2022-11-16 11:31:46,061 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:31:46,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1923895142] [2022-11-16 11:31:46,061 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1923895142] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-16 11:31:46,061 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-16 11:31:46,061 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-16 11:31:46,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1857886952] [2022-11-16 11:31:46,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-16 11:31:46,062 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-16 11:31:46,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:46,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-16 11:31:46,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2022-11-16 11:31:46,064 INFO L87 Difference]: Start difference. First operand 23 states and 27 transitions. Second operand has 8 states, 8 states have (on average 1.75) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 2 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-16 11:31:46,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:46,231 INFO L93 Difference]: Finished difference Result 33 states and 39 transitions. [2022-11-16 11:31:46,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-16 11:31:46,233 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 1.75) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 2 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 1 states have call successors, (2) Word has length 19 [2022-11-16 11:31:46,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:31:46,235 INFO L225 Difference]: With dead ends: 33 [2022-11-16 11:31:46,236 INFO L226 Difference]: Without dead ends: 31 [2022-11-16 11:31:46,236 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2022-11-16 11:31:46,238 INFO L413 NwaCegarLoop]: 16 mSDtfsCounter, 21 mSDsluCounter, 64 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 23 SdHoareTripleChecker+Valid, 80 SdHoareTripleChecker+Invalid, 84 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:31:46,239 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [23 Valid, 80 Invalid, 84 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 84 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-16 11:31:46,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2022-11-16 11:31:46,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 28. [2022-11-16 11:31:46,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 19 states have (on average 1.2105263157894737) internal successors, (23), 21 states have internal predecessors, (23), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-11-16 11:31:46,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 32 transitions. [2022-11-16 11:31:46,249 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 32 transitions. Word has length 19 [2022-11-16 11:31:46,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:31:46,249 INFO L495 AbstractCegarLoop]: Abstraction has 28 states and 32 transitions. [2022-11-16 11:31:46,250 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 1.75) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 2 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-16 11:31:46,250 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2022-11-16 11:31:46,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-11-16 11:31:46,251 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:31:46,251 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:46,259 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-11-16 11:31:46,457 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:46,457 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:31:46,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:46,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1636478750, now seen corresponding path program 1 times [2022-11-16 11:31:46,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:46,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380500378] [2022-11-16 11:31:46,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:46,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:46,487 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:31:46,493 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1163137167] [2022-11-16 11:31:46,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:46,494 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:46,494 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:46,496 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:46,513 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-16 11:31:46,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:46,572 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-16 11:31:46,576 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:46,809 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-16 11:31:46,810 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:47,041 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-16 11:31:47,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:47,042 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380500378] [2022-11-16 11:31:47,042 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:31:47,042 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1163137167] [2022-11-16 11:31:47,042 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1163137167] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:47,042 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:31:47,043 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 7] total 16 [2022-11-16 11:31:47,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351768533] [2022-11-16 11:31:47,043 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:47,044 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-11-16 11:31:47,044 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:47,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-11-16 11:31:47,045 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=198, Unknown=0, NotChecked=0, Total=240 [2022-11-16 11:31:47,045 INFO L87 Difference]: Start difference. First operand 28 states and 32 transitions. Second operand has 16 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 12 states have internal predecessors, (26), 5 states have call successors, (7), 3 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 3 states have call successors, (6) [2022-11-16 11:31:47,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:47,266 INFO L93 Difference]: Finished difference Result 35 states and 38 transitions. [2022-11-16 11:31:47,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-16 11:31:47,267 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 12 states have internal predecessors, (26), 5 states have call successors, (7), 3 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 3 states have call successors, (6) Word has length 25 [2022-11-16 11:31:47,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:31:47,270 INFO L225 Difference]: With dead ends: 35 [2022-11-16 11:31:47,270 INFO L226 Difference]: Without dead ends: 30 [2022-11-16 11:31:47,271 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=69, Invalid=311, Unknown=0, NotChecked=0, Total=380 [2022-11-16 11:31:47,272 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 28 mSDsluCounter, 79 mSDsCounter, 0 mSdLazyCounter, 136 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 92 SdHoareTripleChecker+Invalid, 146 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 136 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:31:47,272 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 92 Invalid, 146 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 136 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-16 11:31:47,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2022-11-16 11:31:47,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 25. [2022-11-16 11:31:47,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 18 states have (on average 1.1111111111111112) internal successors, (20), 18 states have internal predecessors, (20), 4 states have call successors, (4), 3 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-16 11:31:47,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 27 transitions. [2022-11-16 11:31:47,300 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 27 transitions. Word has length 25 [2022-11-16 11:31:47,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:31:47,300 INFO L495 AbstractCegarLoop]: Abstraction has 25 states and 27 transitions. [2022-11-16 11:31:47,300 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 12 states have internal predecessors, (26), 5 states have call successors, (7), 3 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 3 states have call successors, (6) [2022-11-16 11:31:47,301 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 27 transitions. [2022-11-16 11:31:47,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2022-11-16 11:31:47,301 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:31:47,302 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:47,311 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-11-16 11:31:47,507 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:47,508 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:31:47,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:47,508 INFO L85 PathProgramCache]: Analyzing trace with hash -126969667, now seen corresponding path program 1 times [2022-11-16 11:31:47,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:47,509 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102099826] [2022-11-16 11:31:47,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:47,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:47,524 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:31:47,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [110290313] [2022-11-16 11:31:47,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:47,524 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:47,525 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:47,526 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:47,547 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-16 11:31:47,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-16 11:31:47,591 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-16 11:31:47,595 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:47,654 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-16 11:31:47,654 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:47,711 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-16 11:31:47,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:47,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102099826] [2022-11-16 11:31:47,712 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:31:47,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [110290313] [2022-11-16 11:31:47,712 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [110290313] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:47,712 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:31:47,712 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 8 [2022-11-16 11:31:47,712 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017675964] [2022-11-16 11:31:47,712 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:47,713 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-16 11:31:47,713 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:47,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-16 11:31:47,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2022-11-16 11:31:47,714 INFO L87 Difference]: Start difference. First operand 25 states and 27 transitions. Second operand has 8 states, 8 states have (on average 4.125) internal successors, (33), 8 states have internal predecessors, (33), 5 states have call successors, (7), 4 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 4 states have call successors, (6) [2022-11-16 11:31:47,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:47,799 INFO L93 Difference]: Finished difference Result 57 states and 64 transitions. [2022-11-16 11:31:47,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-16 11:31:47,800 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 4.125) internal successors, (33), 8 states have internal predecessors, (33), 5 states have call successors, (7), 4 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 4 states have call successors, (6) Word has length 28 [2022-11-16 11:31:47,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:31:47,803 INFO L225 Difference]: With dead ends: 57 [2022-11-16 11:31:47,803 INFO L226 Difference]: Without dead ends: 52 [2022-11-16 11:31:47,803 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 48 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2022-11-16 11:31:47,805 INFO L413 NwaCegarLoop]: 25 mSDtfsCounter, 30 mSDsluCounter, 81 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 30 SdHoareTripleChecker+Valid, 106 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-16 11:31:47,810 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [30 Valid, 106 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-16 11:31:47,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2022-11-16 11:31:47,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2022-11-16 11:31:47,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 39 states have (on average 1.1282051282051282) internal successors, (44), 39 states have internal predecessors, (44), 7 states have call successors, (7), 6 states have call predecessors, (7), 5 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-11-16 11:31:47,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 57 transitions. [2022-11-16 11:31:47,829 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 57 transitions. Word has length 28 [2022-11-16 11:31:47,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:31:47,830 INFO L495 AbstractCegarLoop]: Abstraction has 52 states and 57 transitions. [2022-11-16 11:31:47,830 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 4.125) internal successors, (33), 8 states have internal predecessors, (33), 5 states have call successors, (7), 4 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 4 states have call successors, (6) [2022-11-16 11:31:47,830 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 57 transitions. [2022-11-16 11:31:47,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2022-11-16 11:31:47,835 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:31:47,835 INFO L195 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:47,842 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-11-16 11:31:48,042 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:48,042 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:31:48,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:48,043 INFO L85 PathProgramCache]: Analyzing trace with hash 972990450, now seen corresponding path program 2 times [2022-11-16 11:31:48,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:48,043 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743046119] [2022-11-16 11:31:48,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:48,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:48,059 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:31:48,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [245898807] [2022-11-16 11:31:48,061 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-16 11:31:48,061 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:48,062 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:48,063 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:48,067 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-11-16 11:31:48,137 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-16 11:31:48,137 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:31:48,139 INFO L263 TraceCheckSpWp]: Trace formula consists of 161 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-16 11:31:48,141 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:48,267 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 8 proven. 62 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-16 11:31:48,268 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:48,396 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 8 proven. 38 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2022-11-16 11:31:48,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:48,396 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743046119] [2022-11-16 11:31:48,396 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:31:48,397 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [245898807] [2022-11-16 11:31:48,397 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [245898807] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:48,397 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:31:48,397 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 14 [2022-11-16 11:31:48,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881942210] [2022-11-16 11:31:48,398 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:48,398 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-16 11:31:48,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:48,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-16 11:31:48,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=111, Unknown=0, NotChecked=0, Total=182 [2022-11-16 11:31:48,399 INFO L87 Difference]: Start difference. First operand 52 states and 57 transitions. Second operand has 14 states, 14 states have (on average 4.714285714285714) internal successors, (66), 14 states have internal predecessors, (66), 11 states have call successors, (13), 7 states have call predecessors, (13), 6 states have return successors, (12), 10 states have call predecessors, (12), 10 states have call successors, (12) [2022-11-16 11:31:48,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:48,640 INFO L93 Difference]: Finished difference Result 111 states and 127 transitions. [2022-11-16 11:31:48,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-16 11:31:48,641 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 4.714285714285714) internal successors, (66), 14 states have internal predecessors, (66), 11 states have call successors, (13), 7 states have call predecessors, (13), 6 states have return successors, (12), 10 states have call predecessors, (12), 10 states have call successors, (12) Word has length 55 [2022-11-16 11:31:48,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:31:48,645 INFO L225 Difference]: With dead ends: 111 [2022-11-16 11:31:48,646 INFO L226 Difference]: Without dead ends: 106 [2022-11-16 11:31:48,647 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 96 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 55 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=184, Invalid=322, Unknown=0, NotChecked=0, Total=506 [2022-11-16 11:31:48,650 INFO L413 NwaCegarLoop]: 31 mSDtfsCounter, 120 mSDsluCounter, 100 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 41 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 120 SdHoareTripleChecker+Valid, 131 SdHoareTripleChecker+Invalid, 95 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 41 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:31:48,650 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [120 Valid, 131 Invalid, 95 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [41 Valid, 54 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-16 11:31:48,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2022-11-16 11:31:48,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2022-11-16 11:31:48,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106 states, 81 states have (on average 1.1358024691358024) internal successors, (92), 81 states have internal predecessors, (92), 13 states have call successors, (13), 12 states have call predecessors, (13), 11 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2022-11-16 11:31:48,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 117 transitions. [2022-11-16 11:31:48,696 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 117 transitions. Word has length 55 [2022-11-16 11:31:48,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:31:48,700 INFO L495 AbstractCegarLoop]: Abstraction has 106 states and 117 transitions. [2022-11-16 11:31:48,704 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 4.714285714285714) internal successors, (66), 14 states have internal predecessors, (66), 11 states have call successors, (13), 7 states have call predecessors, (13), 6 states have return successors, (12), 10 states have call predecessors, (12), 10 states have call successors, (12) [2022-11-16 11:31:48,704 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 117 transitions. [2022-11-16 11:31:48,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2022-11-16 11:31:48,709 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:31:48,709 INFO L195 NwaCegarLoop]: trace histogram [11, 11, 10, 10, 10, 10, 10, 10, 10, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:48,720 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-11-16 11:31:48,909 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable5 [2022-11-16 11:31:48,910 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:31:48,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:48,910 INFO L85 PathProgramCache]: Analyzing trace with hash -1909967598, now seen corresponding path program 3 times [2022-11-16 11:31:48,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:48,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475574812] [2022-11-16 11:31:48,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:48,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:48,933 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:31:48,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1333547274] [2022-11-16 11:31:48,959 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-16 11:31:48,959 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:48,959 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:48,962 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:48,983 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-11-16 11:31:49,092 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-16 11:31:49,092 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:31:49,095 INFO L263 TraceCheckSpWp]: Trace formula consists of 299 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-16 11:31:49,101 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:49,441 INFO L134 CoverageAnalysis]: Checked inductivity of 449 backedges. 20 proven. 425 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-16 11:31:49,441 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:49,949 INFO L134 CoverageAnalysis]: Checked inductivity of 449 backedges. 20 proven. 245 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2022-11-16 11:31:49,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:49,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475574812] [2022-11-16 11:31:49,950 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:31:49,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1333547274] [2022-11-16 11:31:49,950 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1333547274] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:49,951 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:31:49,951 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14] total 26 [2022-11-16 11:31:49,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870270678] [2022-11-16 11:31:49,951 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:49,953 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-11-16 11:31:49,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:49,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-16 11:31:49,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=281, Invalid=369, Unknown=0, NotChecked=0, Total=650 [2022-11-16 11:31:49,955 INFO L87 Difference]: Start difference. First operand 106 states and 117 transitions. Second operand has 26 states, 26 states have (on average 5.076923076923077) internal successors, (132), 26 states have internal predecessors, (132), 23 states have call successors, (25), 13 states have call predecessors, (25), 12 states have return successors, (24), 22 states have call predecessors, (24), 22 states have call successors, (24) [2022-11-16 11:31:50,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:50,708 INFO L93 Difference]: Finished difference Result 219 states and 253 transitions. [2022-11-16 11:31:50,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-16 11:31:50,709 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 5.076923076923077) internal successors, (132), 26 states have internal predecessors, (132), 23 states have call successors, (25), 13 states have call predecessors, (25), 12 states have return successors, (24), 22 states have call predecessors, (24), 22 states have call successors, (24) Word has length 109 [2022-11-16 11:31:50,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:31:50,712 INFO L225 Difference]: With dead ends: 219 [2022-11-16 11:31:50,712 INFO L226 Difference]: Without dead ends: 214 [2022-11-16 11:31:50,713 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 237 GetRequests, 192 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 286 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=796, Invalid=1366, Unknown=0, NotChecked=0, Total=2162 [2022-11-16 11:31:50,714 INFO L413 NwaCegarLoop]: 43 mSDtfsCounter, 262 mSDsluCounter, 189 mSDsCounter, 0 mSdLazyCounter, 119 mSolverCounterSat, 76 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 262 SdHoareTripleChecker+Valid, 232 SdHoareTripleChecker+Invalid, 195 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 76 IncrementalHoareTripleChecker+Valid, 119 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-16 11:31:50,715 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [262 Valid, 232 Invalid, 195 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [76 Valid, 119 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-16 11:31:50,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2022-11-16 11:31:50,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 214. [2022-11-16 11:31:50,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 214 states, 165 states have (on average 1.1393939393939394) internal successors, (188), 165 states have internal predecessors, (188), 25 states have call successors, (25), 24 states have call predecessors, (25), 23 states have return successors, (24), 24 states have call predecessors, (24), 24 states have call successors, (24) [2022-11-16 11:31:50,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 237 transitions. [2022-11-16 11:31:50,752 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 237 transitions. Word has length 109 [2022-11-16 11:31:50,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:31:50,753 INFO L495 AbstractCegarLoop]: Abstraction has 214 states and 237 transitions. [2022-11-16 11:31:50,754 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 5.076923076923077) internal successors, (132), 26 states have internal predecessors, (132), 23 states have call successors, (25), 13 states have call predecessors, (25), 12 states have return successors, (24), 22 states have call predecessors, (24), 22 states have call successors, (24) [2022-11-16 11:31:50,754 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 237 transitions. [2022-11-16 11:31:50,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2022-11-16 11:31:50,757 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:31:50,757 INFO L195 NwaCegarLoop]: trace histogram [23, 23, 22, 22, 22, 22, 22, 22, 22, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:50,769 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-11-16 11:31:50,964 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:50,964 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:31:50,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:50,965 INFO L85 PathProgramCache]: Analyzing trace with hash -1216739502, now seen corresponding path program 4 times [2022-11-16 11:31:50,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:50,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034186955] [2022-11-16 11:31:50,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:50,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:51,010 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:31:51,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1967760034] [2022-11-16 11:31:51,014 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-16 11:31:51,014 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:51,014 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:51,016 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:51,043 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-11-16 11:31:51,199 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-16 11:31:51,199 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:31:51,204 INFO L263 TraceCheckSpWp]: Trace formula consists of 575 conjuncts, 47 conjunts are in the unsatisfiable core [2022-11-16 11:31:51,211 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:52,038 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 44 proven. 2123 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-16 11:31:52,038 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:31:53,390 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 44 proven. 1199 refuted. 0 times theorem prover too weak. 928 trivial. 0 not checked. [2022-11-16 11:31:53,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:31:53,391 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2034186955] [2022-11-16 11:31:53,391 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:31:53,391 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1967760034] [2022-11-16 11:31:53,391 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1967760034] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:31:53,391 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:31:53,391 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26] total 50 [2022-11-16 11:31:53,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444417540] [2022-11-16 11:31:53,392 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:31:53,393 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2022-11-16 11:31:53,393 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:31:53,394 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-11-16 11:31:53,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1133, Invalid=1317, Unknown=0, NotChecked=0, Total=2450 [2022-11-16 11:31:53,396 INFO L87 Difference]: Start difference. First operand 214 states and 237 transitions. Second operand has 50 states, 50 states have (on average 5.28) internal successors, (264), 50 states have internal predecessors, (264), 47 states have call successors, (49), 25 states have call predecessors, (49), 24 states have return successors, (48), 46 states have call predecessors, (48), 46 states have call successors, (48) [2022-11-16 11:31:55,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:31:55,488 INFO L93 Difference]: Finished difference Result 435 states and 505 transitions. [2022-11-16 11:31:55,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2022-11-16 11:31:55,489 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 5.28) internal successors, (264), 50 states have internal predecessors, (264), 47 states have call successors, (49), 25 states have call predecessors, (49), 24 states have return successors, (48), 46 states have call predecessors, (48), 46 states have call successors, (48) Word has length 217 [2022-11-16 11:31:55,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:31:55,493 INFO L225 Difference]: With dead ends: 435 [2022-11-16 11:31:55,493 INFO L226 Difference]: Without dead ends: 430 [2022-11-16 11:31:55,497 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 477 GetRequests, 384 SyntacticMatches, 0 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1288 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=3316, Invalid=5614, Unknown=0, NotChecked=0, Total=8930 [2022-11-16 11:31:55,498 INFO L413 NwaCegarLoop]: 67 mSDtfsCounter, 715 mSDsluCounter, 427 mSDsCounter, 0 mSdLazyCounter, 292 mSolverCounterSat, 197 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 715 SdHoareTripleChecker+Valid, 494 SdHoareTripleChecker+Invalid, 489 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 197 IncrementalHoareTripleChecker+Valid, 292 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-16 11:31:55,499 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [715 Valid, 494 Invalid, 489 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [197 Valid, 292 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-11-16 11:31:55,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states. [2022-11-16 11:31:55,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2022-11-16 11:31:55,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 333 states have (on average 1.1411411411411412) internal successors, (380), 333 states have internal predecessors, (380), 49 states have call successors, (49), 48 states have call predecessors, (49), 47 states have return successors, (48), 48 states have call predecessors, (48), 48 states have call successors, (48) [2022-11-16 11:31:55,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 477 transitions. [2022-11-16 11:31:55,562 INFO L78 Accepts]: Start accepts. Automaton has 430 states and 477 transitions. Word has length 217 [2022-11-16 11:31:55,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:31:55,564 INFO L495 AbstractCegarLoop]: Abstraction has 430 states and 477 transitions. [2022-11-16 11:31:55,564 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 5.28) internal successors, (264), 50 states have internal predecessors, (264), 47 states have call successors, (49), 25 states have call predecessors, (49), 24 states have return successors, (48), 46 states have call predecessors, (48), 46 states have call successors, (48) [2022-11-16 11:31:55,565 INFO L276 IsEmpty]: Start isEmpty. Operand 430 states and 477 transitions. [2022-11-16 11:31:55,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 434 [2022-11-16 11:31:55,580 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:31:55,581 INFO L195 NwaCegarLoop]: trace histogram [47, 47, 46, 46, 46, 46, 46, 46, 46, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:31:55,594 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-11-16 11:31:55,788 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:55,789 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:31:55,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:31:55,790 INFO L85 PathProgramCache]: Analyzing trace with hash -623866926, now seen corresponding path program 5 times [2022-11-16 11:31:55,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:31:55,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3495572] [2022-11-16 11:31:55,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:31:55,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:31:55,823 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:31:55,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [508754865] [2022-11-16 11:31:55,824 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-16 11:31:55,824 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:31:55,824 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:31:55,825 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:31:55,831 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-16 11:31:56,344 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-11-16 11:31:56,345 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:31:56,354 INFO L263 TraceCheckSpWp]: Trace formula consists of 1127 conjuncts, 95 conjunts are in the unsatisfiable core [2022-11-16 11:31:56,365 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:31:58,464 INFO L134 CoverageAnalysis]: Checked inductivity of 9503 backedges. 92 proven. 9407 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-16 11:31:58,464 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:32:02,274 INFO L134 CoverageAnalysis]: Checked inductivity of 9503 backedges. 92 proven. 5267 refuted. 0 times theorem prover too weak. 4144 trivial. 0 not checked. [2022-11-16 11:32:02,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:32:02,274 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3495572] [2022-11-16 11:32:02,274 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:32:02,274 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [508754865] [2022-11-16 11:32:02,274 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [508754865] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:32:02,275 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:32:02,275 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 50] total 98 [2022-11-16 11:32:02,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148163010] [2022-11-16 11:32:02,275 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:32:02,277 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 98 states [2022-11-16 11:32:02,278 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:32:02,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-11-16 11:32:02,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4565, Invalid=4941, Unknown=0, NotChecked=0, Total=9506 [2022-11-16 11:32:02,290 INFO L87 Difference]: Start difference. First operand 430 states and 477 transitions. Second operand has 98 states, 98 states have (on average 5.387755102040816) internal successors, (528), 98 states have internal predecessors, (528), 95 states have call successors, (97), 49 states have call predecessors, (97), 48 states have return successors, (96), 94 states have call predecessors, (96), 94 states have call successors, (96) [2022-11-16 11:32:09,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:32:09,486 INFO L93 Difference]: Finished difference Result 867 states and 1009 transitions. [2022-11-16 11:32:09,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2022-11-16 11:32:09,488 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 5.387755102040816) internal successors, (528), 98 states have internal predecessors, (528), 95 states have call successors, (97), 49 states have call predecessors, (97), 48 states have return successors, (96), 94 states have call predecessors, (96), 94 states have call successors, (96) Word has length 433 [2022-11-16 11:32:09,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:32:09,494 INFO L225 Difference]: With dead ends: 867 [2022-11-16 11:32:09,494 INFO L226 Difference]: Without dead ends: 862 [2022-11-16 11:32:09,503 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 957 GetRequests, 768 SyntacticMatches, 0 SemanticMatches, 189 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5452 ImplicationChecksByTransitivity, 8.5s TimeCoverageRelationStatistics Valid=13540, Invalid=22750, Unknown=0, NotChecked=0, Total=36290 [2022-11-16 11:32:09,505 INFO L413 NwaCegarLoop]: 115 mSDtfsCounter, 1668 mSDsluCounter, 816 mSDsCounter, 0 mSdLazyCounter, 869 mSolverCounterSat, 412 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1668 SdHoareTripleChecker+Valid, 931 SdHoareTripleChecker+Invalid, 1281 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 412 IncrementalHoareTripleChecker+Valid, 869 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-11-16 11:32:09,506 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1668 Valid, 931 Invalid, 1281 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [412 Valid, 869 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2022-11-16 11:32:09,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 862 states. [2022-11-16 11:32:09,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 862 to 862. [2022-11-16 11:32:09,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 862 states, 669 states have (on average 1.1420029895366217) internal successors, (764), 669 states have internal predecessors, (764), 97 states have call successors, (97), 96 states have call predecessors, (97), 95 states have return successors, (96), 96 states have call predecessors, (96), 96 states have call successors, (96) [2022-11-16 11:32:09,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 862 states to 862 states and 957 transitions. [2022-11-16 11:32:09,601 INFO L78 Accepts]: Start accepts. Automaton has 862 states and 957 transitions. Word has length 433 [2022-11-16 11:32:09,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:32:09,602 INFO L495 AbstractCegarLoop]: Abstraction has 862 states and 957 transitions. [2022-11-16 11:32:09,603 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 98 states, 98 states have (on average 5.387755102040816) internal successors, (528), 98 states have internal predecessors, (528), 95 states have call successors, (97), 49 states have call predecessors, (97), 48 states have return successors, (96), 94 states have call predecessors, (96), 94 states have call successors, (96) [2022-11-16 11:32:09,603 INFO L276 IsEmpty]: Start isEmpty. Operand 862 states and 957 transitions. [2022-11-16 11:32:09,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 866 [2022-11-16 11:32:09,638 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:32:09,638 INFO L195 NwaCegarLoop]: trace histogram [95, 95, 94, 94, 94, 94, 94, 94, 94, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:32:09,647 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-11-16 11:32:09,847 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:32:09,847 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:32:09,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:32:09,848 INFO L85 PathProgramCache]: Analyzing trace with hash -1106701102, now seen corresponding path program 6 times [2022-11-16 11:32:09,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:32:09,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912656352] [2022-11-16 11:32:09,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:32:09,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:32:09,933 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:32:09,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1662656811] [2022-11-16 11:32:09,933 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-16 11:32:09,933 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:32:09,934 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:32:09,935 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:32:09,959 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-16 11:32:11,425 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2022-11-16 11:32:11,425 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-16 11:32:11,444 INFO L263 TraceCheckSpWp]: Trace formula consists of 2231 conjuncts, 191 conjunts are in the unsatisfiable core [2022-11-16 11:32:11,466 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-16 11:32:17,183 INFO L134 CoverageAnalysis]: Checked inductivity of 39719 backedges. 188 proven. 39527 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-16 11:32:17,183 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-16 11:32:22,897 INFO L134 CoverageAnalysis]: Checked inductivity of 39719 backedges. 188 proven. 22043 refuted. 0 times theorem prover too weak. 17488 trivial. 0 not checked. [2022-11-16 11:32:22,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-16 11:32:22,897 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912656352] [2022-11-16 11:32:22,897 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-16 11:32:22,897 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1662656811] [2022-11-16 11:32:22,898 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1662656811] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-16 11:32:22,898 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-16 11:32:22,898 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [97, 98] total 104 [2022-11-16 11:32:22,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447122056] [2022-11-16 11:32:22,900 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-16 11:32:22,906 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 104 states [2022-11-16 11:32:22,906 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-16 11:32:22,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 104 interpolants. [2022-11-16 11:32:22,910 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5156, Invalid=5556, Unknown=0, NotChecked=0, Total=10712 [2022-11-16 11:32:22,911 INFO L87 Difference]: Start difference. First operand 862 states and 957 transitions. Second operand has 104 states, 104 states have (on average 6.730769230769231) internal successors, (700), 104 states have internal predecessors, (700), 101 states have call successors, (193), 97 states have call predecessors, (193), 96 states have return successors, (192), 100 states have call predecessors, (192), 100 states have call successors, (192) [2022-11-16 11:32:29,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-16 11:32:29,341 INFO L93 Difference]: Finished difference Result 921 states and 1027 transitions. [2022-11-16 11:32:29,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2022-11-16 11:32:29,343 INFO L78 Accepts]: Start accepts. Automaton has has 104 states, 104 states have (on average 6.730769230769231) internal successors, (700), 104 states have internal predecessors, (700), 101 states have call successors, (193), 97 states have call predecessors, (193), 96 states have return successors, (192), 100 states have call predecessors, (192), 100 states have call successors, (192) Word has length 865 [2022-11-16 11:32:29,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-16 11:32:29,349 INFO L225 Difference]: With dead ends: 921 [2022-11-16 11:32:29,349 INFO L226 Difference]: Without dead ends: 916 [2022-11-16 11:32:29,356 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1827 GetRequests, 1536 SyntacticMatches, 90 SemanticMatches, 201 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9505 ImplicationChecksByTransitivity, 13.4s TimeCoverageRelationStatistics Valid=15349, Invalid=25657, Unknown=0, NotChecked=0, Total=41006 [2022-11-16 11:32:29,357 INFO L413 NwaCegarLoop]: 121 mSDtfsCounter, 995 mSDsluCounter, 879 mSDsCounter, 0 mSdLazyCounter, 718 mSolverCounterSat, 214 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 995 SdHoareTripleChecker+Valid, 1000 SdHoareTripleChecker+Invalid, 932 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 214 IncrementalHoareTripleChecker+Valid, 718 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-11-16 11:32:29,357 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [995 Valid, 1000 Invalid, 932 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [214 Valid, 718 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-11-16 11:32:29,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 916 states. [2022-11-16 11:32:29,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 916 to 916. [2022-11-16 11:32:29,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 916 states, 711 states have (on average 1.1420534458509142) internal successors, (812), 711 states have internal predecessors, (812), 103 states have call successors, (103), 102 states have call predecessors, (103), 101 states have return successors, (102), 102 states have call predecessors, (102), 102 states have call successors, (102) [2022-11-16 11:32:29,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 916 states to 916 states and 1017 transitions. [2022-11-16 11:32:29,441 INFO L78 Accepts]: Start accepts. Automaton has 916 states and 1017 transitions. Word has length 865 [2022-11-16 11:32:29,442 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-16 11:32:29,443 INFO L495 AbstractCegarLoop]: Abstraction has 916 states and 1017 transitions. [2022-11-16 11:32:29,444 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 104 states, 104 states have (on average 6.730769230769231) internal successors, (700), 104 states have internal predecessors, (700), 101 states have call successors, (193), 97 states have call predecessors, (193), 96 states have return successors, (192), 100 states have call predecessors, (192), 100 states have call successors, (192) [2022-11-16 11:32:29,444 INFO L276 IsEmpty]: Start isEmpty. Operand 916 states and 1017 transitions. [2022-11-16 11:32:29,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 920 [2022-11-16 11:32:29,482 INFO L187 NwaCegarLoop]: Found error trace [2022-11-16 11:32:29,483 INFO L195 NwaCegarLoop]: trace histogram [101, 101, 100, 100, 100, 100, 100, 100, 100, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-16 11:32:29,498 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-16 11:32:29,693 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:32:29,694 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-16 11:32:29,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-16 11:32:29,694 INFO L85 PathProgramCache]: Analyzing trace with hash 611596786, now seen corresponding path program 7 times [2022-11-16 11:32:29,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-16 11:32:29,695 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978288244] [2022-11-16 11:32:29,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-16 11:32:29,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-16 11:32:29,759 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-16 11:32:29,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1746303841] [2022-11-16 11:32:29,761 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-16 11:32:29,761 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-16 11:32:29,761 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 [2022-11-16 11:32:29,762 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-16 11:32:29,778 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-16 11:32:30,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:32:30,263 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-16 11:32:30,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-16 11:32:31,128 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-16 11:32:31,128 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-16 11:32:31,129 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-16 11:32:31,143 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-11-16 11:32:31,343 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable10 [2022-11-16 11:32:31,347 INFO L444 BasicCegarLoop]: Path program histogram: [7, 1, 1, 1, 1] [2022-11-16 11:32:31,353 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-16 11:32:31,708 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 16.11 11:32:31 BoogieIcfgContainer [2022-11-16 11:32:31,709 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-16 11:32:31,709 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-16 11:32:31,709 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-16 11:32:31,710 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-16 11:32:31,710 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.11 11:31:44" (3/4) ... [2022-11-16 11:32:31,712 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-11-16 11:32:31,981 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/witness.graphml [2022-11-16 11:32:31,981 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-16 11:32:31,982 INFO L158 Benchmark]: Toolchain (without parser) took 48543.67ms. Allocated memory was 121.6MB in the beginning and 371.2MB in the end (delta: 249.6MB). Free memory was 81.8MB in the beginning and 287.9MB in the end (delta: -206.1MB). Peak memory consumption was 42.9MB. Max. memory is 16.1GB. [2022-11-16 11:32:31,982 INFO L158 Benchmark]: CDTParser took 0.23ms. Allocated memory is still 121.6MB. Free memory is still 98.5MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-16 11:32:31,983 INFO L158 Benchmark]: CACSL2BoogieTranslator took 288.54ms. Allocated memory is still 121.6MB. Free memory was 81.7MB in the beginning and 97.4MB in the end (delta: -15.7MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-16 11:32:31,983 INFO L158 Benchmark]: Boogie Procedure Inliner took 33.71ms. Allocated memory is still 121.6MB. Free memory was 97.4MB in the beginning and 95.9MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-16 11:32:31,983 INFO L158 Benchmark]: Boogie Preprocessor took 22.95ms. Allocated memory is still 121.6MB. Free memory was 95.9MB in the beginning and 94.8MB in the end (delta: 1.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-16 11:32:31,984 INFO L158 Benchmark]: RCFGBuilder took 301.96ms. Allocated memory is still 121.6MB. Free memory was 94.4MB in the beginning and 84.4MB in the end (delta: 10.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-16 11:32:31,985 INFO L158 Benchmark]: TraceAbstraction took 47596.89ms. Allocated memory was 121.6MB in the beginning and 371.2MB in the end (delta: 249.6MB). Free memory was 83.4MB in the beginning and 320.5MB in the end (delta: -237.0MB). Peak memory consumption was 213.2MB. Max. memory is 16.1GB. [2022-11-16 11:32:31,985 INFO L158 Benchmark]: Witness Printer took 271.79ms. Allocated memory is still 371.2MB. Free memory was 320.5MB in the beginning and 287.9MB in the end (delta: 32.5MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2022-11-16 11:32:31,987 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23ms. Allocated memory is still 121.6MB. Free memory is still 98.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 288.54ms. Allocated memory is still 121.6MB. Free memory was 81.7MB in the beginning and 97.4MB in the end (delta: -15.7MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 33.71ms. Allocated memory is still 121.6MB. Free memory was 97.4MB in the beginning and 95.9MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 22.95ms. Allocated memory is still 121.6MB. Free memory was 95.9MB in the beginning and 94.8MB in the end (delta: 1.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 301.96ms. Allocated memory is still 121.6MB. Free memory was 94.4MB in the beginning and 84.4MB in the end (delta: 10.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * TraceAbstraction took 47596.89ms. Allocated memory was 121.6MB in the beginning and 371.2MB in the end (delta: 249.6MB). Free memory was 83.4MB in the beginning and 320.5MB in the end (delta: -237.0MB). Peak memory consumption was 213.2MB. Max. memory is 16.1GB. * Witness Printer took 271.79ms. Allocated memory is still 371.2MB. Free memory was 320.5MB in the beginning and 287.9MB in the end (delta: 32.5MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 18]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L22] int counter = 0; VAL [counter=0] [L24] int x1, x2; [L25] int y1, y2, y3; [L26] x1 = __VERIFIER_nondet_int() [L27] x2 = __VERIFIER_nondet_int() [L29] CALL assume_abort_if_not(x1 >= 0) VAL [\old(cond)=1, counter=0] [L13] COND FALSE !(!cond) VAL [\old(cond)=1, cond=1, counter=0] [L29] RET assume_abort_if_not(x1 >= 0) VAL [counter=0, x1=101, x2=1] [L30] CALL assume_abort_if_not(x2 != 0) VAL [\old(cond)=1, counter=0] [L13] COND FALSE !(!cond) VAL [\old(cond)=1, cond=1, counter=0] [L30] RET assume_abort_if_not(x2 != 0) VAL [counter=0, x1=101, x2=1] [L32] y1 = 0 [L33] y2 = 0 [L34] y3 = x1 VAL [counter=0, x1=101, x2=1, y1=0, y2=0, y3=101] [L36] EXPR counter++ VAL [counter=1, counter++=0, x1=101, x2=1, y1=0, y2=0, y3=101] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=1] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=1] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=1, x1=101, x2=1, y1=0, y2=0, y3=101] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=1, x1=101, x2=1, y1=0, y2=0, y3=101] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=1, x1=101, x2=1, y1=1, y2=0, y3=100] [L36] EXPR counter++ VAL [counter=2, counter++=1, x1=101, x2=1, y1=1, y2=0, y3=100] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=2] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=2] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=2, x1=101, x2=1, y1=1, y2=0, y3=100] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=2, x1=101, x2=1, y1=1, y2=0, y3=100] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=2, x1=101, x2=1, y1=2, y2=0, y3=99] [L36] EXPR counter++ VAL [counter=3, counter++=2, x1=101, x2=1, y1=2, y2=0, y3=99] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=3] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=3] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=3, x1=101, x2=1, y1=2, y2=0, y3=99] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=3, x1=101, x2=1, y1=2, y2=0, y3=99] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=3, x1=101, x2=1, y1=3, y2=0, y3=98] [L36] EXPR counter++ VAL [counter=4, counter++=3, x1=101, x2=1, y1=3, y2=0, y3=98] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=4] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=4] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=4, x1=101, x2=1, y1=3, y2=0, y3=98] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=4, x1=101, x2=1, y1=3, y2=0, y3=98] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=4, x1=101, x2=1, y1=4, y2=0, y3=97] [L36] EXPR counter++ VAL [counter=5, counter++=4, x1=101, x2=1, y1=4, y2=0, y3=97] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=5] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=5] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=5, x1=101, x2=1, y1=4, y2=0, y3=97] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=5, x1=101, x2=1, y1=4, y2=0, y3=97] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=5, x1=101, x2=1, y1=5, y2=0, y3=96] [L36] EXPR counter++ VAL [counter=6, counter++=5, x1=101, x2=1, y1=5, y2=0, y3=96] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=6] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=6] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=6, x1=101, x2=1, y1=5, y2=0, y3=96] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=6, x1=101, x2=1, y1=5, y2=0, y3=96] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=6, x1=101, x2=1, y1=6, y2=0, y3=95] [L36] EXPR counter++ VAL [counter=7, counter++=6, x1=101, x2=1, y1=6, y2=0, y3=95] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=7] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=7] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=7, x1=101, x2=1, y1=6, y2=0, y3=95] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=7, x1=101, x2=1, y1=6, y2=0, y3=95] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=7, x1=101, x2=1, y1=7, y2=0, y3=94] [L36] EXPR counter++ VAL [counter=8, counter++=7, x1=101, x2=1, y1=7, y2=0, y3=94] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=8] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=8] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=8, x1=101, x2=1, y1=7, y2=0, y3=94] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=8, x1=101, x2=1, y1=7, y2=0, y3=94] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=8, x1=101, x2=1, y1=8, y2=0, y3=93] [L36] EXPR counter++ VAL [counter=9, counter++=8, x1=101, x2=1, y1=8, y2=0, y3=93] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=9] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=9] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=9, x1=101, x2=1, y1=8, y2=0, y3=93] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=9, x1=101, x2=1, y1=8, y2=0, y3=93] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=9, x1=101, x2=1, y1=9, y2=0, y3=92] [L36] EXPR counter++ VAL [counter=10, counter++=9, x1=101, x2=1, y1=9, y2=0, y3=92] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=10] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=10] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=10, x1=101, x2=1, y1=9, y2=0, y3=92] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=10, x1=101, x2=1, y1=9, y2=0, y3=92] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=10, x1=101, x2=1, y1=10, y2=0, y3=91] [L36] EXPR counter++ VAL [counter=11, counter++=10, x1=101, x2=1, y1=10, y2=0, y3=91] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=11] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=11] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=11, x1=101, x2=1, y1=10, y2=0, y3=91] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=11, x1=101, x2=1, y1=10, y2=0, y3=91] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=11, x1=101, x2=1, y1=11, y2=0, y3=90] [L36] EXPR counter++ VAL [counter=12, counter++=11, x1=101, x2=1, y1=11, y2=0, y3=90] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=12] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=12] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=12, x1=101, x2=1, y1=11, y2=0, y3=90] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=12, x1=101, x2=1, y1=11, y2=0, y3=90] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=12, x1=101, x2=1, y1=12, y2=0, y3=89] [L36] EXPR counter++ VAL [counter=13, counter++=12, x1=101, x2=1, y1=12, y2=0, y3=89] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=13] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=13] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=13, x1=101, x2=1, y1=12, y2=0, y3=89] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=13, x1=101, x2=1, y1=12, y2=0, y3=89] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=13, x1=101, x2=1, y1=13, y2=0, y3=88] [L36] EXPR counter++ VAL [counter=14, counter++=13, x1=101, x2=1, y1=13, y2=0, y3=88] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=14] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=14] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=14, x1=101, x2=1, y1=13, y2=0, y3=88] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=14, x1=101, x2=1, y1=13, y2=0, y3=88] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=14, x1=101, x2=1, y1=14, y2=0, y3=87] [L36] EXPR counter++ VAL [counter=15, counter++=14, x1=101, x2=1, y1=14, y2=0, y3=87] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=15] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=15] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=15, x1=101, x2=1, y1=14, y2=0, y3=87] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=15, x1=101, x2=1, y1=14, y2=0, y3=87] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=15, x1=101, x2=1, y1=15, y2=0, y3=86] [L36] EXPR counter++ VAL [counter=16, counter++=15, x1=101, x2=1, y1=15, y2=0, y3=86] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=16] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=16] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=16, x1=101, x2=1, y1=15, y2=0, y3=86] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=16, x1=101, x2=1, y1=15, y2=0, y3=86] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=16, x1=101, x2=1, y1=16, y2=0, y3=85] [L36] EXPR counter++ VAL [counter=17, counter++=16, x1=101, x2=1, y1=16, y2=0, y3=85] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=17] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=17] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=17, x1=101, x2=1, y1=16, y2=0, y3=85] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=17, x1=101, x2=1, y1=16, y2=0, y3=85] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=17, x1=101, x2=1, y1=17, y2=0, y3=84] [L36] EXPR counter++ VAL [counter=18, counter++=17, x1=101, x2=1, y1=17, y2=0, y3=84] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=18] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=18] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=18, x1=101, x2=1, y1=17, y2=0, y3=84] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=18, x1=101, x2=1, y1=17, y2=0, y3=84] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=18, x1=101, x2=1, y1=18, y2=0, y3=83] [L36] EXPR counter++ VAL [counter=19, counter++=18, x1=101, x2=1, y1=18, y2=0, y3=83] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=19] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=19] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=19, x1=101, x2=1, y1=18, y2=0, y3=83] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=19, x1=101, x2=1, y1=18, y2=0, y3=83] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=19, x1=101, x2=1, y1=19, y2=0, y3=82] [L36] EXPR counter++ VAL [counter=20, counter++=19, x1=101, x2=1, y1=19, y2=0, y3=82] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=20] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=20] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=20, x1=101, x2=1, y1=19, y2=0, y3=82] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=20, x1=101, x2=1, y1=19, y2=0, y3=82] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=20, x1=101, x2=1, y1=20, y2=0, y3=81] [L36] EXPR counter++ VAL [counter=21, counter++=20, x1=101, x2=1, y1=20, y2=0, y3=81] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=21] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=21] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=21, x1=101, x2=1, y1=20, y2=0, y3=81] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=21, x1=101, x2=1, y1=20, y2=0, y3=81] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=21, x1=101, x2=1, y1=21, y2=0, y3=80] [L36] EXPR counter++ VAL [counter=22, counter++=21, x1=101, x2=1, y1=21, y2=0, y3=80] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=22] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=22] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=22, x1=101, x2=1, y1=21, y2=0, y3=80] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=22, x1=101, x2=1, y1=21, y2=0, y3=80] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=22, x1=101, x2=1, y1=22, y2=0, y3=79] [L36] EXPR counter++ VAL [counter=23, counter++=22, x1=101, x2=1, y1=22, y2=0, y3=79] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=23] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=23] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=23, x1=101, x2=1, y1=22, y2=0, y3=79] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=23, x1=101, x2=1, y1=22, y2=0, y3=79] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=23, x1=101, x2=1, y1=23, y2=0, y3=78] [L36] EXPR counter++ VAL [counter=24, counter++=23, x1=101, x2=1, y1=23, y2=0, y3=78] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=24] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=24] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=24, x1=101, x2=1, y1=23, y2=0, y3=78] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=24, x1=101, x2=1, y1=23, y2=0, y3=78] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=24, x1=101, x2=1, y1=24, y2=0, y3=77] [L36] EXPR counter++ VAL [counter=25, counter++=24, x1=101, x2=1, y1=24, y2=0, y3=77] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=25] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=25] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=25, x1=101, x2=1, y1=24, y2=0, y3=77] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=25, x1=101, x2=1, y1=24, y2=0, y3=77] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=25, x1=101, x2=1, y1=25, y2=0, y3=76] [L36] EXPR counter++ VAL [counter=26, counter++=25, x1=101, x2=1, y1=25, y2=0, y3=76] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=26] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=26] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=26, x1=101, x2=1, y1=25, y2=0, y3=76] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=26, x1=101, x2=1, y1=25, y2=0, y3=76] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=26, x1=101, x2=1, y1=26, y2=0, y3=75] [L36] EXPR counter++ VAL [counter=27, counter++=26, x1=101, x2=1, y1=26, y2=0, y3=75] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=27] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=27] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=27, x1=101, x2=1, y1=26, y2=0, y3=75] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=27, x1=101, x2=1, y1=26, y2=0, y3=75] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=27, x1=101, x2=1, y1=27, y2=0, y3=74] [L36] EXPR counter++ VAL [counter=28, counter++=27, x1=101, x2=1, y1=27, y2=0, y3=74] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=28] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=28] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=28, x1=101, x2=1, y1=27, y2=0, y3=74] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=28, x1=101, x2=1, y1=27, y2=0, y3=74] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=28, x1=101, x2=1, y1=28, y2=0, y3=73] [L36] EXPR counter++ VAL [counter=29, counter++=28, x1=101, x2=1, y1=28, y2=0, y3=73] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=29] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=29] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=29, x1=101, x2=1, y1=28, y2=0, y3=73] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=29, x1=101, x2=1, y1=28, y2=0, y3=73] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=29, x1=101, x2=1, y1=29, y2=0, y3=72] [L36] EXPR counter++ VAL [counter=30, counter++=29, x1=101, x2=1, y1=29, y2=0, y3=72] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=30] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=30] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=30, x1=101, x2=1, y1=29, y2=0, y3=72] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=30, x1=101, x2=1, y1=29, y2=0, y3=72] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=30, x1=101, x2=1, y1=30, y2=0, y3=71] [L36] EXPR counter++ VAL [counter=31, counter++=30, x1=101, x2=1, y1=30, y2=0, y3=71] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=31] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=31] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=31, x1=101, x2=1, y1=30, y2=0, y3=71] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=31, x1=101, x2=1, y1=30, y2=0, y3=71] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=31, x1=101, x2=1, y1=31, y2=0, y3=70] [L36] EXPR counter++ VAL [counter=32, counter++=31, x1=101, x2=1, y1=31, y2=0, y3=70] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=32] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=32] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=32, x1=101, x2=1, y1=31, y2=0, y3=70] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=32, x1=101, x2=1, y1=31, y2=0, y3=70] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=32, x1=101, x2=1, y1=32, y2=0, y3=69] [L36] EXPR counter++ VAL [counter=33, counter++=32, x1=101, x2=1, y1=32, y2=0, y3=69] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=33] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=33] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=33, x1=101, x2=1, y1=32, y2=0, y3=69] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=33, x1=101, x2=1, y1=32, y2=0, y3=69] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=33, x1=101, x2=1, y1=33, y2=0, y3=68] [L36] EXPR counter++ VAL [counter=34, counter++=33, x1=101, x2=1, y1=33, y2=0, y3=68] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=34] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=34] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=34, x1=101, x2=1, y1=33, y2=0, y3=68] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=34, x1=101, x2=1, y1=33, y2=0, y3=68] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=34, x1=101, x2=1, y1=34, y2=0, y3=67] [L36] EXPR counter++ VAL [counter=35, counter++=34, x1=101, x2=1, y1=34, y2=0, y3=67] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=35] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=35] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=35, x1=101, x2=1, y1=34, y2=0, y3=67] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=35, x1=101, x2=1, y1=34, y2=0, y3=67] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=35, x1=101, x2=1, y1=35, y2=0, y3=66] [L36] EXPR counter++ VAL [counter=36, counter++=35, x1=101, x2=1, y1=35, y2=0, y3=66] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=36] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=36] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=36, x1=101, x2=1, y1=35, y2=0, y3=66] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=36, x1=101, x2=1, y1=35, y2=0, y3=66] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=36, x1=101, x2=1, y1=36, y2=0, y3=65] [L36] EXPR counter++ VAL [counter=37, counter++=36, x1=101, x2=1, y1=36, y2=0, y3=65] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=37] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=37] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=37, x1=101, x2=1, y1=36, y2=0, y3=65] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=37, x1=101, x2=1, y1=36, y2=0, y3=65] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=37, x1=101, x2=1, y1=37, y2=0, y3=64] [L36] EXPR counter++ VAL [counter=38, counter++=37, x1=101, x2=1, y1=37, y2=0, y3=64] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=38] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=38] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=38, x1=101, x2=1, y1=37, y2=0, y3=64] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=38, x1=101, x2=1, y1=37, y2=0, y3=64] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=38, x1=101, x2=1, y1=38, y2=0, y3=63] [L36] EXPR counter++ VAL [counter=39, counter++=38, x1=101, x2=1, y1=38, y2=0, y3=63] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=39] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=39] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=39, x1=101, x2=1, y1=38, y2=0, y3=63] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=39, x1=101, x2=1, y1=38, y2=0, y3=63] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=39, x1=101, x2=1, y1=39, y2=0, y3=62] [L36] EXPR counter++ VAL [counter=40, counter++=39, x1=101, x2=1, y1=39, y2=0, y3=62] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=40] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=40] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=40, x1=101, x2=1, y1=39, y2=0, y3=62] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=40, x1=101, x2=1, y1=39, y2=0, y3=62] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=40, x1=101, x2=1, y1=40, y2=0, y3=61] [L36] EXPR counter++ VAL [counter=41, counter++=40, x1=101, x2=1, y1=40, y2=0, y3=61] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=41] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=41] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=41, x1=101, x2=1, y1=40, y2=0, y3=61] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=41, x1=101, x2=1, y1=40, y2=0, y3=61] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=41, x1=101, x2=1, y1=41, y2=0, y3=60] [L36] EXPR counter++ VAL [counter=42, counter++=41, x1=101, x2=1, y1=41, y2=0, y3=60] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=42] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=42] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=42, x1=101, x2=1, y1=41, y2=0, y3=60] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=42, x1=101, x2=1, y1=41, y2=0, y3=60] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=42, x1=101, x2=1, y1=42, y2=0, y3=59] [L36] EXPR counter++ VAL [counter=43, counter++=42, x1=101, x2=1, y1=42, y2=0, y3=59] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=43] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=43] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=43, x1=101, x2=1, y1=42, y2=0, y3=59] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=43, x1=101, x2=1, y1=42, y2=0, y3=59] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=43, x1=101, x2=1, y1=43, y2=0, y3=58] [L36] EXPR counter++ VAL [counter=44, counter++=43, x1=101, x2=1, y1=43, y2=0, y3=58] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=44] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=44] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=44, x1=101, x2=1, y1=43, y2=0, y3=58] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=44, x1=101, x2=1, y1=43, y2=0, y3=58] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=44, x1=101, x2=1, y1=44, y2=0, y3=57] [L36] EXPR counter++ VAL [counter=45, counter++=44, x1=101, x2=1, y1=44, y2=0, y3=57] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=45] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=45] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=45, x1=101, x2=1, y1=44, y2=0, y3=57] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=45, x1=101, x2=1, y1=44, y2=0, y3=57] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=45, x1=101, x2=1, y1=45, y2=0, y3=56] [L36] EXPR counter++ VAL [counter=46, counter++=45, x1=101, x2=1, y1=45, y2=0, y3=56] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=46] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=46] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=46, x1=101, x2=1, y1=45, y2=0, y3=56] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=46, x1=101, x2=1, y1=45, y2=0, y3=56] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=46, x1=101, x2=1, y1=46, y2=0, y3=55] [L36] EXPR counter++ VAL [counter=47, counter++=46, x1=101, x2=1, y1=46, y2=0, y3=55] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=47] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=47] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=47, x1=101, x2=1, y1=46, y2=0, y3=55] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=47, x1=101, x2=1, y1=46, y2=0, y3=55] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=47, x1=101, x2=1, y1=47, y2=0, y3=54] [L36] EXPR counter++ VAL [counter=48, counter++=47, x1=101, x2=1, y1=47, y2=0, y3=54] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=48] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=48] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=48, x1=101, x2=1, y1=47, y2=0, y3=54] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=48, x1=101, x2=1, y1=47, y2=0, y3=54] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=48, x1=101, x2=1, y1=48, y2=0, y3=53] [L36] EXPR counter++ VAL [counter=49, counter++=48, x1=101, x2=1, y1=48, y2=0, y3=53] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=49] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=49] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=49, x1=101, x2=1, y1=48, y2=0, y3=53] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=49, x1=101, x2=1, y1=48, y2=0, y3=53] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=49, x1=101, x2=1, y1=49, y2=0, y3=52] [L36] EXPR counter++ VAL [counter=50, counter++=49, x1=101, x2=1, y1=49, y2=0, y3=52] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=50] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=50] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=50, x1=101, x2=1, y1=49, y2=0, y3=52] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=50, x1=101, x2=1, y1=49, y2=0, y3=52] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=50, x1=101, x2=1, y1=50, y2=0, y3=51] [L36] EXPR counter++ VAL [counter=51, counter++=50, x1=101, x2=1, y1=50, y2=0, y3=51] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=51] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=51] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=51, x1=101, x2=1, y1=50, y2=0, y3=51] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=51, x1=101, x2=1, y1=50, y2=0, y3=51] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=51, x1=101, x2=1, y1=51, y2=0, y3=50] [L36] EXPR counter++ VAL [counter=52, counter++=51, x1=101, x2=1, y1=51, y2=0, y3=50] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=52] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=52] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=52, x1=101, x2=1, y1=51, y2=0, y3=50] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=52, x1=101, x2=1, y1=51, y2=0, y3=50] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=52, x1=101, x2=1, y1=52, y2=0, y3=49] [L36] EXPR counter++ VAL [counter=53, counter++=52, x1=101, x2=1, y1=52, y2=0, y3=49] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=53] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=53] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=53, x1=101, x2=1, y1=52, y2=0, y3=49] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=53, x1=101, x2=1, y1=52, y2=0, y3=49] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=53, x1=101, x2=1, y1=53, y2=0, y3=48] [L36] EXPR counter++ VAL [counter=54, counter++=53, x1=101, x2=1, y1=53, y2=0, y3=48] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=54] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=54] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=54, x1=101, x2=1, y1=53, y2=0, y3=48] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=54, x1=101, x2=1, y1=53, y2=0, y3=48] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=54, x1=101, x2=1, y1=54, y2=0, y3=47] [L36] EXPR counter++ VAL [counter=55, counter++=54, x1=101, x2=1, y1=54, y2=0, y3=47] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=55] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=55] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=55, x1=101, x2=1, y1=54, y2=0, y3=47] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=55, x1=101, x2=1, y1=54, y2=0, y3=47] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=55, x1=101, x2=1, y1=55, y2=0, y3=46] [L36] EXPR counter++ VAL [counter=56, counter++=55, x1=101, x2=1, y1=55, y2=0, y3=46] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=56] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=56] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=56, x1=101, x2=1, y1=55, y2=0, y3=46] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=56, x1=101, x2=1, y1=55, y2=0, y3=46] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=56, x1=101, x2=1, y1=56, y2=0, y3=45] [L36] EXPR counter++ VAL [counter=57, counter++=56, x1=101, x2=1, y1=56, y2=0, y3=45] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=57] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=57] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=57, x1=101, x2=1, y1=56, y2=0, y3=45] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=57, x1=101, x2=1, y1=56, y2=0, y3=45] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=57, x1=101, x2=1, y1=57, y2=0, y3=44] [L36] EXPR counter++ VAL [counter=58, counter++=57, x1=101, x2=1, y1=57, y2=0, y3=44] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=58] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=58] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=58, x1=101, x2=1, y1=57, y2=0, y3=44] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=58, x1=101, x2=1, y1=57, y2=0, y3=44] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=58, x1=101, x2=1, y1=58, y2=0, y3=43] [L36] EXPR counter++ VAL [counter=59, counter++=58, x1=101, x2=1, y1=58, y2=0, y3=43] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=59] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=59] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=59, x1=101, x2=1, y1=58, y2=0, y3=43] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=59, x1=101, x2=1, y1=58, y2=0, y3=43] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=59, x1=101, x2=1, y1=59, y2=0, y3=42] [L36] EXPR counter++ VAL [counter=60, counter++=59, x1=101, x2=1, y1=59, y2=0, y3=42] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=60] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=60] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=60, x1=101, x2=1, y1=59, y2=0, y3=42] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=60, x1=101, x2=1, y1=59, y2=0, y3=42] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=60, x1=101, x2=1, y1=60, y2=0, y3=41] [L36] EXPR counter++ VAL [counter=61, counter++=60, x1=101, x2=1, y1=60, y2=0, y3=41] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=61] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=61] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=61, x1=101, x2=1, y1=60, y2=0, y3=41] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=61, x1=101, x2=1, y1=60, y2=0, y3=41] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=61, x1=101, x2=1, y1=61, y2=0, y3=40] [L36] EXPR counter++ VAL [counter=62, counter++=61, x1=101, x2=1, y1=61, y2=0, y3=40] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=62] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=62] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=62, x1=101, x2=1, y1=61, y2=0, y3=40] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=62, x1=101, x2=1, y1=61, y2=0, y3=40] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=62, x1=101, x2=1, y1=62, y2=0, y3=39] [L36] EXPR counter++ VAL [counter=63, counter++=62, x1=101, x2=1, y1=62, y2=0, y3=39] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=63] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=63] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=63, x1=101, x2=1, y1=62, y2=0, y3=39] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=63, x1=101, x2=1, y1=62, y2=0, y3=39] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=63, x1=101, x2=1, y1=63, y2=0, y3=38] [L36] EXPR counter++ VAL [counter=64, counter++=63, x1=101, x2=1, y1=63, y2=0, y3=38] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=64] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=64] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=64, x1=101, x2=1, y1=63, y2=0, y3=38] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=64, x1=101, x2=1, y1=63, y2=0, y3=38] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=64, x1=101, x2=1, y1=64, y2=0, y3=37] [L36] EXPR counter++ VAL [counter=65, counter++=64, x1=101, x2=1, y1=64, y2=0, y3=37] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=65] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=65] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=65, x1=101, x2=1, y1=64, y2=0, y3=37] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=65, x1=101, x2=1, y1=64, y2=0, y3=37] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=65, x1=101, x2=1, y1=65, y2=0, y3=36] [L36] EXPR counter++ VAL [counter=66, counter++=65, x1=101, x2=1, y1=65, y2=0, y3=36] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=66] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=66] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=66, x1=101, x2=1, y1=65, y2=0, y3=36] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=66, x1=101, x2=1, y1=65, y2=0, y3=36] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=66, x1=101, x2=1, y1=66, y2=0, y3=35] [L36] EXPR counter++ VAL [counter=67, counter++=66, x1=101, x2=1, y1=66, y2=0, y3=35] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=67] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=67] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=67, x1=101, x2=1, y1=66, y2=0, y3=35] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=67, x1=101, x2=1, y1=66, y2=0, y3=35] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=67, x1=101, x2=1, y1=67, y2=0, y3=34] [L36] EXPR counter++ VAL [counter=68, counter++=67, x1=101, x2=1, y1=67, y2=0, y3=34] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=68] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=68] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=68, x1=101, x2=1, y1=67, y2=0, y3=34] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=68, x1=101, x2=1, y1=67, y2=0, y3=34] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=68, x1=101, x2=1, y1=68, y2=0, y3=33] [L36] EXPR counter++ VAL [counter=69, counter++=68, x1=101, x2=1, y1=68, y2=0, y3=33] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=69] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=69] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=69, x1=101, x2=1, y1=68, y2=0, y3=33] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=69, x1=101, x2=1, y1=68, y2=0, y3=33] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=69, x1=101, x2=1, y1=69, y2=0, y3=32] [L36] EXPR counter++ VAL [counter=70, counter++=69, x1=101, x2=1, y1=69, y2=0, y3=32] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=70] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=70] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=70, x1=101, x2=1, y1=69, y2=0, y3=32] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=70, x1=101, x2=1, y1=69, y2=0, y3=32] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=70, x1=101, x2=1, y1=70, y2=0, y3=31] [L36] EXPR counter++ VAL [counter=71, counter++=70, x1=101, x2=1, y1=70, y2=0, y3=31] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=71] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=71] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=71, x1=101, x2=1, y1=70, y2=0, y3=31] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=71, x1=101, x2=1, y1=70, y2=0, y3=31] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=71, x1=101, x2=1, y1=71, y2=0, y3=30] [L36] EXPR counter++ VAL [counter=72, counter++=71, x1=101, x2=1, y1=71, y2=0, y3=30] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=72] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=72] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=72, x1=101, x2=1, y1=71, y2=0, y3=30] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=72, x1=101, x2=1, y1=71, y2=0, y3=30] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=72, x1=101, x2=1, y1=72, y2=0, y3=29] [L36] EXPR counter++ VAL [counter=73, counter++=72, x1=101, x2=1, y1=72, y2=0, y3=29] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=73] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=73] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=73, x1=101, x2=1, y1=72, y2=0, y3=29] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=73, x1=101, x2=1, y1=72, y2=0, y3=29] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=73, x1=101, x2=1, y1=73, y2=0, y3=28] [L36] EXPR counter++ VAL [counter=74, counter++=73, x1=101, x2=1, y1=73, y2=0, y3=28] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=74] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=74] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=74, x1=101, x2=1, y1=73, y2=0, y3=28] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=74, x1=101, x2=1, y1=73, y2=0, y3=28] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=74, x1=101, x2=1, y1=74, y2=0, y3=27] [L36] EXPR counter++ VAL [counter=75, counter++=74, x1=101, x2=1, y1=74, y2=0, y3=27] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=75] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=75] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=75, x1=101, x2=1, y1=74, y2=0, y3=27] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=75, x1=101, x2=1, y1=74, y2=0, y3=27] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=75, x1=101, x2=1, y1=75, y2=0, y3=26] [L36] EXPR counter++ VAL [counter=76, counter++=75, x1=101, x2=1, y1=75, y2=0, y3=26] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=76] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=76] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=76, x1=101, x2=1, y1=75, y2=0, y3=26] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=76, x1=101, x2=1, y1=75, y2=0, y3=26] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=76, x1=101, x2=1, y1=76, y2=0, y3=25] [L36] EXPR counter++ VAL [counter=77, counter++=76, x1=101, x2=1, y1=76, y2=0, y3=25] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=77] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=77] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=77, x1=101, x2=1, y1=76, y2=0, y3=25] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=77, x1=101, x2=1, y1=76, y2=0, y3=25] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=77, x1=101, x2=1, y1=77, y2=0, y3=24] [L36] EXPR counter++ VAL [counter=78, counter++=77, x1=101, x2=1, y1=77, y2=0, y3=24] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=78] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=78] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=78, x1=101, x2=1, y1=77, y2=0, y3=24] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=78, x1=101, x2=1, y1=77, y2=0, y3=24] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=78, x1=101, x2=1, y1=78, y2=0, y3=23] [L36] EXPR counter++ VAL [counter=79, counter++=78, x1=101, x2=1, y1=78, y2=0, y3=23] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=79] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=79] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=79, x1=101, x2=1, y1=78, y2=0, y3=23] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=79, x1=101, x2=1, y1=78, y2=0, y3=23] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=79, x1=101, x2=1, y1=79, y2=0, y3=22] [L36] EXPR counter++ VAL [counter=80, counter++=79, x1=101, x2=1, y1=79, y2=0, y3=22] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=80] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=80] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=80, x1=101, x2=1, y1=79, y2=0, y3=22] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=80, x1=101, x2=1, y1=79, y2=0, y3=22] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=80, x1=101, x2=1, y1=80, y2=0, y3=21] [L36] EXPR counter++ VAL [counter=81, counter++=80, x1=101, x2=1, y1=80, y2=0, y3=21] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=81] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=81] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=81, x1=101, x2=1, y1=80, y2=0, y3=21] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=81, x1=101, x2=1, y1=80, y2=0, y3=21] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=81, x1=101, x2=1, y1=81, y2=0, y3=20] [L36] EXPR counter++ VAL [counter=82, counter++=81, x1=101, x2=1, y1=81, y2=0, y3=20] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=82] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=82] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=82, x1=101, x2=1, y1=81, y2=0, y3=20] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=82, x1=101, x2=1, y1=81, y2=0, y3=20] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=82, x1=101, x2=1, y1=82, y2=0, y3=19] [L36] EXPR counter++ VAL [counter=83, counter++=82, x1=101, x2=1, y1=82, y2=0, y3=19] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=83] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=83] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=83, x1=101, x2=1, y1=82, y2=0, y3=19] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=83, x1=101, x2=1, y1=82, y2=0, y3=19] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=83, x1=101, x2=1, y1=83, y2=0, y3=18] [L36] EXPR counter++ VAL [counter=84, counter++=83, x1=101, x2=1, y1=83, y2=0, y3=18] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=84] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=84] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=84, x1=101, x2=1, y1=83, y2=0, y3=18] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=84, x1=101, x2=1, y1=83, y2=0, y3=18] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=84, x1=101, x2=1, y1=84, y2=0, y3=17] [L36] EXPR counter++ VAL [counter=85, counter++=84, x1=101, x2=1, y1=84, y2=0, y3=17] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=85] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=85] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=85, x1=101, x2=1, y1=84, y2=0, y3=17] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=85, x1=101, x2=1, y1=84, y2=0, y3=17] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=85, x1=101, x2=1, y1=85, y2=0, y3=16] [L36] EXPR counter++ VAL [counter=86, counter++=85, x1=101, x2=1, y1=85, y2=0, y3=16] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=86] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=86] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=86, x1=101, x2=1, y1=85, y2=0, y3=16] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=86, x1=101, x2=1, y1=85, y2=0, y3=16] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=86, x1=101, x2=1, y1=86, y2=0, y3=15] [L36] EXPR counter++ VAL [counter=87, counter++=86, x1=101, x2=1, y1=86, y2=0, y3=15] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=87] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=87] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=87, x1=101, x2=1, y1=86, y2=0, y3=15] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=87, x1=101, x2=1, y1=86, y2=0, y3=15] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=87, x1=101, x2=1, y1=87, y2=0, y3=14] [L36] EXPR counter++ VAL [counter=88, counter++=87, x1=101, x2=1, y1=87, y2=0, y3=14] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=88] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=88] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=88, x1=101, x2=1, y1=87, y2=0, y3=14] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=88, x1=101, x2=1, y1=87, y2=0, y3=14] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=88, x1=101, x2=1, y1=88, y2=0, y3=13] [L36] EXPR counter++ VAL [counter=89, counter++=88, x1=101, x2=1, y1=88, y2=0, y3=13] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=89] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=89] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=89, x1=101, x2=1, y1=88, y2=0, y3=13] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=89, x1=101, x2=1, y1=88, y2=0, y3=13] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=89, x1=101, x2=1, y1=89, y2=0, y3=12] [L36] EXPR counter++ VAL [counter=90, counter++=89, x1=101, x2=1, y1=89, y2=0, y3=12] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=90] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=90] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=90, x1=101, x2=1, y1=89, y2=0, y3=12] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=90, x1=101, x2=1, y1=89, y2=0, y3=12] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=90, x1=101, x2=1, y1=90, y2=0, y3=11] [L36] EXPR counter++ VAL [counter=91, counter++=90, x1=101, x2=1, y1=90, y2=0, y3=11] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=91] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=91] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=91, x1=101, x2=1, y1=90, y2=0, y3=11] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=91, x1=101, x2=1, y1=90, y2=0, y3=11] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=91, x1=101, x2=1, y1=91, y2=0, y3=10] [L36] EXPR counter++ VAL [counter=92, counter++=91, x1=101, x2=1, y1=91, y2=0, y3=10] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=92] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=92] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=92, x1=101, x2=1, y1=91, y2=0, y3=10] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=92, x1=101, x2=1, y1=91, y2=0, y3=10] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=92, x1=101, x2=1, y1=92, y2=0, y3=9] [L36] EXPR counter++ VAL [counter=93, counter++=92, x1=101, x2=1, y1=92, y2=0, y3=9] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=93] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=93] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=93, x1=101, x2=1, y1=92, y2=0, y3=9] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=93, x1=101, x2=1, y1=92, y2=0, y3=9] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=93, x1=101, x2=1, y1=93, y2=0, y3=8] [L36] EXPR counter++ VAL [counter=94, counter++=93, x1=101, x2=1, y1=93, y2=0, y3=8] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=94] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=94] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=94, x1=101, x2=1, y1=93, y2=0, y3=8] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=94, x1=101, x2=1, y1=93, y2=0, y3=8] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=94, x1=101, x2=1, y1=94, y2=0, y3=7] [L36] EXPR counter++ VAL [counter=95, counter++=94, x1=101, x2=1, y1=94, y2=0, y3=7] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=95] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=95] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=95, x1=101, x2=1, y1=94, y2=0, y3=7] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=95, x1=101, x2=1, y1=94, y2=0, y3=7] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=95, x1=101, x2=1, y1=95, y2=0, y3=6] [L36] EXPR counter++ VAL [counter=96, counter++=95, x1=101, x2=1, y1=95, y2=0, y3=6] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=96] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=96] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=96, x1=101, x2=1, y1=95, y2=0, y3=6] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=96, x1=101, x2=1, y1=95, y2=0, y3=6] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=96, x1=101, x2=1, y1=96, y2=0, y3=5] [L36] EXPR counter++ VAL [counter=97, counter++=96, x1=101, x2=1, y1=96, y2=0, y3=5] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=97] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=97] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=97, x1=101, x2=1, y1=96, y2=0, y3=5] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=97, x1=101, x2=1, y1=96, y2=0, y3=5] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=97, x1=101, x2=1, y1=97, y2=0, y3=4] [L36] EXPR counter++ VAL [counter=98, counter++=97, x1=101, x2=1, y1=97, y2=0, y3=4] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=98] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=98] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=98, x1=101, x2=1, y1=97, y2=0, y3=4] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=98, x1=101, x2=1, y1=97, y2=0, y3=4] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=98, x1=101, x2=1, y1=98, y2=0, y3=3] [L36] EXPR counter++ VAL [counter=99, counter++=98, x1=101, x2=1, y1=98, y2=0, y3=3] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=99] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=99] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=99, x1=101, x2=1, y1=98, y2=0, y3=3] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=99, x1=101, x2=1, y1=98, y2=0, y3=3] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=99, x1=101, x2=1, y1=99, y2=0, y3=2] [L36] EXPR counter++ VAL [counter=100, counter++=99, x1=101, x2=1, y1=99, y2=0, y3=2] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=100] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=100] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=100, x1=101, x2=1, y1=99, y2=0, y3=2] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=100, x1=101, x2=1, y1=99, y2=0, y3=2] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=100, x1=101, x2=1, y1=100, y2=0, y3=1] [L36] EXPR counter++ VAL [counter=101, counter++=100, x1=101, x2=1, y1=100, y2=0, y3=1] [L36] COND FALSE !(counter++<100) [L50] CALL __VERIFIER_assert(y1*x2 + y2 == x1) VAL [\old(cond)=0, counter=101] [L16] COND TRUE !(cond) VAL [\old(cond)=0, cond=0, counter=101] [L18] reach_error() VAL [\old(cond)=0, cond=0, counter=101] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 25 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 47.2s, OverallIterations: 11, TraceHistogramMax: 101, PathProgramHistogramMax: 7, EmptinessCheckTime: 0.1s, AutomataDifference: 17.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3841 SdHoareTripleChecker+Valid, 3.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3839 mSDsluCounter, 3152 SdHoareTripleChecker+Invalid, 2.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2669 mSDsCounter, 961 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 2304 IncrementalHoareTripleChecker+Invalid, 3265 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 961 mSolverCounterUnsat, 483 mSDtfsCounter, 2304 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 3779 GetRequests, 3103 SyntacticMatches, 90 SemanticMatches, 586 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16647 ImplicationChecksByTransitivity, 25.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=916occurred in iteration=10, InterpolantAutomatonStates: 589, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 10 MinimizatonAttempts, 8 StatesRemovedByMinimization, 2 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.5s SsaConstructionTime, 2.6s SatisfiabilityAnalysisTime, 21.8s InterpolantComputationTime, 2725 NumberOfCodeBlocks, 2725 NumberOfCodeBlocksAsserted, 164 NumberOfCheckSat, 3503 ConstructedInterpolants, 0 QuantifiedInterpolants, 8883 SizeOfPredicates, 186 NumberOfNonLiveVariables, 4768 ConjunctsInSsa, 412 ConjunctsInUnsatCore, 17 InterpolantComputations, 3 PerfectInterpolantSequences, 23527/103872 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-11-16 11:32:32,043 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_084d4bcd-dfc9-4815-9a4f-8fefcd0aa6ca/bin/uautomizer-tPACEb0tL8/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE