./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-crafted/Arrays01-EquivalentConstantIndices-1.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-crafted/Arrays01-EquivalentConstantIndices-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash cad2c6f6e8ebe2adcd550e4a56b83be37e52f812ae33bfb645236c6925734dbf --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 19:36:58,121 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 19:36:58,123 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 19:36:58,167 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 19:36:58,168 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 19:36:58,169 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 19:36:58,170 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 19:36:58,172 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 19:36:58,173 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 19:36:58,174 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 19:36:58,175 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 19:36:58,177 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 19:36:58,177 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 19:36:58,178 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 19:36:58,184 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 19:36:58,186 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 19:36:58,187 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 19:36:58,193 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 19:36:58,196 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 19:36:58,205 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 19:36:58,208 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 19:36:58,210 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 19:36:58,214 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 19:36:58,215 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 19:36:58,220 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 19:36:58,221 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 19:36:58,221 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 19:36:58,222 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 19:36:58,222 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 19:36:58,223 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 19:36:58,224 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 19:36:58,224 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 19:36:58,225 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 19:36:58,226 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 19:36:58,227 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 19:36:58,227 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 19:36:58,228 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 19:36:58,228 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 19:36:58,229 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 19:36:58,230 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 19:36:58,234 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 19:36:58,236 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-18 19:36:58,276 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 19:36:58,276 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 19:36:58,277 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 19:36:58,277 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 19:36:58,278 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 19:36:58,279 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 19:36:58,279 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 19:36:58,279 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-18 19:36:58,279 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-18 19:36:58,280 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-18 19:36:58,281 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-18 19:36:58,281 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-18 19:36:58,281 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-18 19:36:58,281 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 19:36:58,282 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 19:36:58,282 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 19:36:58,282 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 19:36:58,282 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-18 19:36:58,283 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-18 19:36:58,283 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-18 19:36:58,283 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-18 19:36:58,283 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-18 19:36:58,284 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 19:36:58,284 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-18 19:36:58,284 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 19:36:58,284 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 19:36:58,285 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 19:36:58,285 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 19:36:58,286 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-18 19:36:58,286 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> cad2c6f6e8ebe2adcd550e4a56b83be37e52f812ae33bfb645236c6925734dbf [2022-11-18 19:36:58,603 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 19:36:58,642 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 19:36:58,645 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 19:36:58,647 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 19:36:58,647 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 19:36:58,649 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/termination-crafted/Arrays01-EquivalentConstantIndices-1.c [2022-11-18 19:36:58,718 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/data/96e9fd378/6c5886f4f6584dc985274b51f27602d8/FLAG4190d322a [2022-11-18 19:36:59,196 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 19:36:59,197 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/sv-benchmarks/c/termination-crafted/Arrays01-EquivalentConstantIndices-1.c [2022-11-18 19:36:59,202 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/data/96e9fd378/6c5886f4f6584dc985274b51f27602d8/FLAG4190d322a [2022-11-18 19:36:59,592 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/data/96e9fd378/6c5886f4f6584dc985274b51f27602d8 [2022-11-18 19:36:59,595 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 19:36:59,597 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 19:36:59,601 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 19:36:59,601 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 19:36:59,604 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 19:36:59,605 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,606 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@90e07ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59, skipping insertion in model container [2022-11-18 19:36:59,607 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,614 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 19:36:59,630 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 19:36:59,792 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 19:36:59,795 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 19:36:59,810 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 19:36:59,824 INFO L208 MainTranslator]: Completed translation [2022-11-18 19:36:59,824 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59 WrapperNode [2022-11-18 19:36:59,824 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 19:36:59,825 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 19:36:59,825 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 19:36:59,825 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 19:36:59,833 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,839 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,855 INFO L138 Inliner]: procedures = 8, calls = 9, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 32 [2022-11-18 19:36:59,855 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 19:36:59,856 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 19:36:59,856 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 19:36:59,856 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 19:36:59,863 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,863 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,864 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,864 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,868 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,872 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,872 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,873 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,883 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 19:36:59,886 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 19:36:59,886 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 19:36:59,887 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 19:36:59,888 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (1/1) ... [2022-11-18 19:36:59,893 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:36:59,903 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:36:59,921 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 19:36:59,950 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-18 19:36:59,974 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-18 19:36:59,974 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 19:36:59,975 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 19:36:59,975 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-18 19:36:59,975 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-18 19:36:59,975 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-18 19:37:00,036 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 19:37:00,038 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 19:37:00,136 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 19:37:00,142 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 19:37:00,143 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-18 19:37:00,145 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 07:37:00 BoogieIcfgContainer [2022-11-18 19:37:00,145 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 19:37:00,146 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-18 19:37:00,146 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-18 19:37:00,151 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-18 19:37:00,152 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 19:37:00,152 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 07:36:59" (1/3) ... [2022-11-18 19:37:00,153 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1f9ea952 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 07:37:00, skipping insertion in model container [2022-11-18 19:37:00,153 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 19:37:00,153 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 07:36:59" (2/3) ... [2022-11-18 19:37:00,154 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1f9ea952 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 07:37:00, skipping insertion in model container [2022-11-18 19:37:00,154 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 19:37:00,154 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 07:37:00" (3/3) ... [2022-11-18 19:37:00,155 INFO L332 chiAutomizerObserver]: Analyzing ICFG Arrays01-EquivalentConstantIndices-1.c [2022-11-18 19:37:00,208 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-18 19:37:00,208 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-18 19:37:00,209 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-18 19:37:00,209 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-18 19:37:00,209 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-18 19:37:00,209 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-18 19:37:00,209 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-18 19:37:00,209 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-18 19:37:00,214 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:00,230 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 19:37:00,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 19:37:00,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 19:37:00,236 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 19:37:00,236 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 19:37:00,237 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-18 19:37:00,237 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:00,238 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 19:37:00,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 19:37:00,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 19:37:00,238 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 19:37:00,239 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 19:37:00,247 INFO L748 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 7#L13-3true [2022-11-18 19:37:00,248 INFO L750 eck$LassoCheckResult]: Loop: 7#L13-3true assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 6#L13-2true main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 7#L13-3true [2022-11-18 19:37:00,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:00,254 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-11-18 19:37:00,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:00,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448502538] [2022-11-18 19:37:00,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:00,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:00,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:00,360 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 19:37:00,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:00,386 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 19:37:00,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:00,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2022-11-18 19:37:00,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:00,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795014080] [2022-11-18 19:37:00,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:00,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:00,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:00,402 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 19:37:00,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:00,411 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 19:37:00,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:00,416 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2022-11-18 19:37:00,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:00,417 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075924664] [2022-11-18 19:37:00,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:00,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:00,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:00,454 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 19:37:00,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:00,480 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 19:37:00,805 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 19:37:00,806 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 19:37:00,806 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 19:37:00,806 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 19:37:00,806 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 19:37:00,806 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:37:00,807 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 19:37:00,807 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 19:37:00,807 INFO L133 ssoRankerPreferences]: Filename of dumped script: Arrays01-EquivalentConstantIndices-1.c_Iteration1_Lasso [2022-11-18 19:37:00,807 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 19:37:00,807 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 19:37:00,849 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 19:37:00,909 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 19:37:01,084 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 19:37:01,087 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 19:37:01,091 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 19:37:01,094 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 19:37:01,101 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 19:37:01,263 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 19:37:01,267 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 19:37:01,269 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:37:01,270 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:01,275 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 19:37:01,278 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-18 19:37:01,280 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 19:37:01,293 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 19:37:01,293 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 19:37:01,293 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 19:37:01,293 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 19:37:01,302 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 19:37:01,304 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 19:37:01,323 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 19:37:01,328 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-18 19:37:01,328 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:37:01,328 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:01,332 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 19:37:01,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-18 19:37:01,339 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 19:37:01,352 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 19:37:01,353 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 19:37:01,353 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 19:37:01,353 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 19:37:01,357 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 19:37:01,357 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 19:37:01,386 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 19:37:01,396 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-18 19:37:01,397 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:37:01,397 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:01,401 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 19:37:01,412 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 19:37:01,425 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 19:37:01,425 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 19:37:01,425 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 19:37:01,426 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 19:37:01,429 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 19:37:01,429 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 19:37:01,436 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-18 19:37:01,451 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 19:37:01,457 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-18 19:37:01,457 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:37:01,457 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:01,459 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 19:37:01,472 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 19:37:01,477 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-18 19:37:01,484 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 19:37:01,484 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 19:37:01,485 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 19:37:01,485 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 19:37:01,493 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 19:37:01,494 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 19:37:01,514 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 19:37:01,519 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2022-11-18 19:37:01,519 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:37:01,519 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:01,520 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 19:37:01,548 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 19:37:01,561 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 19:37:01,561 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 19:37:01,561 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 19:37:01,561 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 19:37:01,562 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 19:37:01,562 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 19:37:01,563 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 19:37:01,567 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-18 19:37:01,576 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 19:37:01,585 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-18 19:37:01,585 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:37:01,585 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:01,586 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 19:37:01,595 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-18 19:37:01,596 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 19:37:01,606 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 19:37:01,606 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 19:37:01,606 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 19:37:01,607 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 19:37:01,607 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 19:37:01,610 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 19:37:01,610 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 19:37:01,626 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 19:37:01,636 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-11-18 19:37:01,636 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:37:01,636 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:01,638 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 19:37:01,652 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 19:37:01,652 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-18 19:37:01,665 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 19:37:01,665 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 19:37:01,665 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 19:37:01,665 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 19:37:01,678 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 19:37:01,679 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 19:37:01,699 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 19:37:01,748 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2022-11-18 19:37:01,749 INFO L444 ModelExtractionUtils]: 3 out of 13 variables were initially zero. Simplification set additionally 7 variables to zero. [2022-11-18 19:37:01,750 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 19:37:01,751 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:01,756 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 19:37:01,807 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 19:37:01,821 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-18 19:37:01,835 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 19:37:01,835 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 19:37:01,836 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#a~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = 2095*v_rep(select #length ULTIMATE.start_main_~#a~0#1.base)_1 - 8*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2022-11-18 19:37:01,840 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-18 19:37:01,851 INFO L156 tatePredicateManager]: 1 out of 1 supporting invariants were superfluous and have been removed [2022-11-18 19:37:01,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:01,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:01,912 INFO L263 TraceCheckSpWp]: Trace formula consists of 23 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 19:37:01,913 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 19:37:01,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:01,949 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-18 19:37:01,950 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 19:37:02,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:02,080 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-18 19:37:02,081 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:02,141 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 22 states and 31 transitions. Complement of second has 8 states. [2022-11-18 19:37:02,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 19:37:02,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:02,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 17 transitions. [2022-11-18 19:37:02,150 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 17 transitions. Stem has 2 letters. Loop has 2 letters. [2022-11-18 19:37:02,151 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 19:37:02,151 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 17 transitions. Stem has 4 letters. Loop has 2 letters. [2022-11-18 19:37:02,151 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 19:37:02,151 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 17 transitions. Stem has 2 letters. Loop has 4 letters. [2022-11-18 19:37:02,151 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 19:37:02,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 31 transitions. [2022-11-18 19:37:02,154 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:02,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 8 states and 10 transitions. [2022-11-18 19:37:02,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-11-18 19:37:02,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2022-11-18 19:37:02,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 10 transitions. [2022-11-18 19:37:02,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 19:37:02,160 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 10 transitions. [2022-11-18 19:37:02,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 10 transitions. [2022-11-18 19:37:02,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 7. [2022-11-18 19:37:02,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.2857142857142858) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:02,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 9 transitions. [2022-11-18 19:37:02,186 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7 states and 9 transitions. [2022-11-18 19:37:02,186 INFO L428 stractBuchiCegarLoop]: Abstraction has 7 states and 9 transitions. [2022-11-18 19:37:02,187 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-18 19:37:02,187 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 9 transitions. [2022-11-18 19:37:02,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:02,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 19:37:02,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 19:37:02,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2022-11-18 19:37:02,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 19:37:02,188 INFO L748 eck$LassoCheckResult]: Stem: 77#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 78#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 81#L13-3 assume !(main_~i~0#1 < 1048); 75#L17-2 [2022-11-18 19:37:02,188 INFO L750 eck$LassoCheckResult]: Loop: 75#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 76#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 75#L17-2 [2022-11-18 19:37:02,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:02,189 INFO L85 PathProgramCache]: Analyzing trace with hash 29861, now seen corresponding path program 1 times [2022-11-18 19:37:02,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:02,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405654493] [2022-11-18 19:37:02,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:02,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:02,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:02,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:02,240 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 19:37:02,240 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405654493] [2022-11-18 19:37:02,241 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405654493] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 19:37:02,241 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 19:37:02,241 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-18 19:37:02,241 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164123519] [2022-11-18 19:37:02,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 19:37:02,244 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 19:37:02,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:02,245 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 1 times [2022-11-18 19:37:02,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:02,245 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808606454] [2022-11-18 19:37:02,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:02,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:02,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:02,252 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 19:37:02,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:02,258 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 19:37:02,317 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2022-11-18 19:37:02,358 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 19:37:02,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 19:37:02,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 19:37:02,362 INFO L87 Difference]: Start difference. First operand 7 states and 9 transitions. cyclomatic complexity: 4 Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:02,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 19:37:02,381 INFO L93 Difference]: Finished difference Result 8 states and 9 transitions. [2022-11-18 19:37:02,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8 states and 9 transitions. [2022-11-18 19:37:02,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:02,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8 states to 8 states and 9 transitions. [2022-11-18 19:37:02,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-11-18 19:37:02,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-11-18 19:37:02,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 9 transitions. [2022-11-18 19:37:02,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 19:37:02,384 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 9 transitions. [2022-11-18 19:37:02,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 9 transitions. [2022-11-18 19:37:02,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 7. [2022-11-18 19:37:02,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:02,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 8 transitions. [2022-11-18 19:37:02,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2022-11-18 19:37:02,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 19:37:02,387 INFO L428 stractBuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2022-11-18 19:37:02,387 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-18 19:37:02,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 8 transitions. [2022-11-18 19:37:02,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:02,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 19:37:02,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 19:37:02,389 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-18 19:37:02,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 19:37:02,389 INFO L748 eck$LassoCheckResult]: Stem: 98#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 99#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 102#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 100#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 101#L13-3 assume !(main_~i~0#1 < 1048); 96#L17-2 [2022-11-18 19:37:02,389 INFO L750 eck$LassoCheckResult]: Loop: 96#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 97#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 96#L17-2 [2022-11-18 19:37:02,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:02,390 INFO L85 PathProgramCache]: Analyzing trace with hash 28698723, now seen corresponding path program 1 times [2022-11-18 19:37:02,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:02,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160628034] [2022-11-18 19:37:02,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:02,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:02,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:02,443 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:02,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 19:37:02,444 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160628034] [2022-11-18 19:37:02,444 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1160628034] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 19:37:02,444 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [458501674] [2022-11-18 19:37:02,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:02,445 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 19:37:02,445 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:02,446 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 19:37:02,452 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-18 19:37:02,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:02,501 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-18 19:37:02,502 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 19:37:02,515 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:02,515 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 19:37:02,537 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:02,537 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [458501674] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 19:37:02,538 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 19:37:02,538 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2022-11-18 19:37:02,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828524096] [2022-11-18 19:37:02,538 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 19:37:02,539 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 19:37:02,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:02,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 2 times [2022-11-18 19:37:02,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:02,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362461582] [2022-11-18 19:37:02,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:02,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:02,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:02,546 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 19:37:02,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:02,552 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 19:37:02,598 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 19:37:02,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-18 19:37:02,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-11-18 19:37:02,599 INFO L87 Difference]: Start difference. First operand 7 states and 8 transitions. cyclomatic complexity: 3 Second operand has 7 states, 6 states have (on average 2.0) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:02,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 19:37:02,630 INFO L93 Difference]: Finished difference Result 13 states and 14 transitions. [2022-11-18 19:37:02,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 14 transitions. [2022-11-18 19:37:02,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:02,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 13 states and 14 transitions. [2022-11-18 19:37:02,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-11-18 19:37:02,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-11-18 19:37:02,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 14 transitions. [2022-11-18 19:37:02,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 19:37:02,632 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13 states and 14 transitions. [2022-11-18 19:37:02,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 14 transitions. [2022-11-18 19:37:02,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2022-11-18 19:37:02,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.0769230769230769) internal successors, (14), 12 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:02,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 14 transitions. [2022-11-18 19:37:02,634 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13 states and 14 transitions. [2022-11-18 19:37:02,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-18 19:37:02,635 INFO L428 stractBuchiCegarLoop]: Abstraction has 13 states and 14 transitions. [2022-11-18 19:37:02,635 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-18 19:37:02,635 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 14 transitions. [2022-11-18 19:37:02,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:02,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 19:37:02,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 19:37:02,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1] [2022-11-18 19:37:02,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 19:37:02,637 INFO L748 eck$LassoCheckResult]: Stem: 152#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 153#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 156#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 154#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 155#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 157#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 162#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 161#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 160#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 159#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 158#L13-3 assume !(main_~i~0#1 < 1048); 150#L17-2 [2022-11-18 19:37:02,637 INFO L750 eck$LassoCheckResult]: Loop: 150#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 151#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 150#L17-2 [2022-11-18 19:37:02,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:02,638 INFO L85 PathProgramCache]: Analyzing trace with hash -1081477475, now seen corresponding path program 2 times [2022-11-18 19:37:02,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:02,638 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964436633] [2022-11-18 19:37:02,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:02,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:02,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:02,814 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:02,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 19:37:02,814 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964436633] [2022-11-18 19:37:02,815 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964436633] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 19:37:02,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [59698354] [2022-11-18 19:37:02,815 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 19:37:02,815 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 19:37:02,815 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:02,817 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 19:37:02,845 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-18 19:37:02,889 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 19:37:02,889 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 19:37:02,891 INFO L263 TraceCheckSpWp]: Trace formula consists of 68 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-18 19:37:02,892 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 19:37:02,938 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:02,939 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 19:37:03,028 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:03,029 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [59698354] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 19:37:03,029 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 19:37:03,029 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2022-11-18 19:37:03,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [575719150] [2022-11-18 19:37:03,029 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 19:37:03,031 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 19:37:03,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:03,031 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 3 times [2022-11-18 19:37:03,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:03,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399922899] [2022-11-18 19:37:03,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:03,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:03,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:03,045 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 19:37:03,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:03,063 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 19:37:03,113 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 19:37:03,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-11-18 19:37:03,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-11-18 19:37:03,116 INFO L87 Difference]: Start difference. First operand 13 states and 14 transitions. cyclomatic complexity: 3 Second operand has 13 states, 12 states have (on average 2.0) internal successors, (24), 13 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:03,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 19:37:03,186 INFO L93 Difference]: Finished difference Result 25 states and 26 transitions. [2022-11-18 19:37:03,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 26 transitions. [2022-11-18 19:37:03,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:03,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 25 states and 26 transitions. [2022-11-18 19:37:03,192 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-11-18 19:37:03,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-11-18 19:37:03,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 26 transitions. [2022-11-18 19:37:03,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 19:37:03,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 26 transitions. [2022-11-18 19:37:03,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 26 transitions. [2022-11-18 19:37:03,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2022-11-18 19:37:03,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.04) internal successors, (26), 24 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:03,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 26 transitions. [2022-11-18 19:37:03,201 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 26 transitions. [2022-11-18 19:37:03,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 19:37:03,202 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 26 transitions. [2022-11-18 19:37:03,202 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-18 19:37:03,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 26 transitions. [2022-11-18 19:37:03,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:03,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 19:37:03,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 19:37:03,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1] [2022-11-18 19:37:03,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 19:37:03,207 INFO L748 eck$LassoCheckResult]: Stem: 266#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 267#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 270#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 271#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 272#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 268#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 269#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 288#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 287#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 286#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 285#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 284#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 283#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 282#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 281#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 280#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 279#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 278#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 277#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 276#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 275#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 274#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 273#L13-3 assume !(main_~i~0#1 < 1048); 264#L17-2 [2022-11-18 19:37:03,207 INFO L750 eck$LassoCheckResult]: Loop: 264#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 265#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 264#L17-2 [2022-11-18 19:37:03,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:03,208 INFO L85 PathProgramCache]: Analyzing trace with hash 899905681, now seen corresponding path program 3 times [2022-11-18 19:37:03,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:03,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624035288] [2022-11-18 19:37:03,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:03,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:03,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:03,624 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:03,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 19:37:03,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624035288] [2022-11-18 19:37:03,625 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624035288] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 19:37:03,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2021963903] [2022-11-18 19:37:03,626 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 19:37:03,626 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 19:37:03,626 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:03,637 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 19:37:03,640 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-18 19:37:03,768 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-18 19:37:03,768 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 19:37:03,769 INFO L263 TraceCheckSpWp]: Trace formula consists of 134 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 19:37:03,771 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 19:37:03,850 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:03,850 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 19:37:04,145 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:04,147 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2021963903] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 19:37:04,147 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 19:37:04,147 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2022-11-18 19:37:04,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1344220966] [2022-11-18 19:37:04,147 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 19:37:04,148 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 19:37:04,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:04,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 4 times [2022-11-18 19:37:04,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:04,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616409780] [2022-11-18 19:37:04,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:04,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:04,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:04,156 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 19:37:04,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:04,166 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 19:37:04,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 19:37:04,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-11-18 19:37:04,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-11-18 19:37:04,213 INFO L87 Difference]: Start difference. First operand 25 states and 26 transitions. cyclomatic complexity: 3 Second operand has 25 states, 24 states have (on average 2.0) internal successors, (48), 25 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:04,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 19:37:04,325 INFO L93 Difference]: Finished difference Result 49 states and 50 transitions. [2022-11-18 19:37:04,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 50 transitions. [2022-11-18 19:37:04,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:04,327 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 49 states and 50 transitions. [2022-11-18 19:37:04,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-11-18 19:37:04,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-11-18 19:37:04,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 50 transitions. [2022-11-18 19:37:04,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 19:37:04,327 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49 states and 50 transitions. [2022-11-18 19:37:04,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 50 transitions. [2022-11-18 19:37:04,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2022-11-18 19:37:04,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.0204081632653061) internal successors, (50), 48 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:04,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 50 transitions. [2022-11-18 19:37:04,331 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49 states and 50 transitions. [2022-11-18 19:37:04,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-18 19:37:04,332 INFO L428 stractBuchiCegarLoop]: Abstraction has 49 states and 50 transitions. [2022-11-18 19:37:04,332 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-18 19:37:04,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 50 transitions. [2022-11-18 19:37:04,333 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:04,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 19:37:04,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 19:37:04,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1] [2022-11-18 19:37:04,335 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 19:37:04,335 INFO L748 eck$LassoCheckResult]: Stem: 500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 504#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 505#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 506#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 502#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 503#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 546#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 545#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 544#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 543#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 542#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 541#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 540#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 539#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 538#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 537#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 536#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 535#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 534#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 533#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 532#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 531#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 530#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 529#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 528#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 527#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 526#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 525#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 524#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 523#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 522#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 521#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 520#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 519#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 518#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 517#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 516#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 515#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 514#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 513#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 512#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 511#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 510#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 509#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 508#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 507#L13-3 assume !(main_~i~0#1 < 1048); 498#L17-2 [2022-11-18 19:37:04,335 INFO L750 eck$LassoCheckResult]: Loop: 498#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 499#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 498#L17-2 [2022-11-18 19:37:04,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:04,336 INFO L85 PathProgramCache]: Analyzing trace with hash -111832455, now seen corresponding path program 4 times [2022-11-18 19:37:04,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:04,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897814774] [2022-11-18 19:37:04,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:04,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:04,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:05,071 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:05,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 19:37:05,071 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897814774] [2022-11-18 19:37:05,071 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [897814774] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 19:37:05,072 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [709305473] [2022-11-18 19:37:05,072 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 19:37:05,072 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 19:37:05,072 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:05,078 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 19:37:05,098 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-18 19:37:05,196 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 19:37:05,196 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 19:37:05,199 INFO L263 TraceCheckSpWp]: Trace formula consists of 266 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-18 19:37:05,204 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 19:37:05,325 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:05,325 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 19:37:06,213 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:06,213 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [709305473] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 19:37:06,213 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 19:37:06,214 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2022-11-18 19:37:06,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108712738] [2022-11-18 19:37:06,214 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 19:37:06,217 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 19:37:06,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:06,218 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 5 times [2022-11-18 19:37:06,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:06,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881743367] [2022-11-18 19:37:06,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:06,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:06,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:06,224 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 19:37:06,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:06,230 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 19:37:06,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 19:37:06,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-18 19:37:06,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-11-18 19:37:06,277 INFO L87 Difference]: Start difference. First operand 49 states and 50 transitions. cyclomatic complexity: 3 Second operand has 49 states, 48 states have (on average 2.0) internal successors, (96), 49 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:06,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 19:37:06,494 INFO L93 Difference]: Finished difference Result 97 states and 98 transitions. [2022-11-18 19:37:06,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 98 transitions. [2022-11-18 19:37:06,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:06,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 98 transitions. [2022-11-18 19:37:06,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-11-18 19:37:06,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-11-18 19:37:06,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 98 transitions. [2022-11-18 19:37:06,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 19:37:06,498 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 98 transitions. [2022-11-18 19:37:06,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 98 transitions. [2022-11-18 19:37:06,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2022-11-18 19:37:06,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.0103092783505154) internal successors, (98), 96 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:06,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2022-11-18 19:37:06,504 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 98 transitions. [2022-11-18 19:37:06,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-11-18 19:37:06,505 INFO L428 stractBuchiCegarLoop]: Abstraction has 97 states and 98 transitions. [2022-11-18 19:37:06,505 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-18 19:37:06,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 98 transitions. [2022-11-18 19:37:06,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:06,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 19:37:06,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 19:37:06,508 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1] [2022-11-18 19:37:06,508 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 19:37:06,509 INFO L748 eck$LassoCheckResult]: Stem: 974#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 978#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 979#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 980#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 976#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 977#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1068#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1067#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1066#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1065#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1064#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1063#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1062#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1061#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1060#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1059#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1058#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1057#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1056#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1055#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1054#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1053#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1052#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1051#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1050#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1049#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1048#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1047#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1046#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1045#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1044#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1043#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1042#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1041#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1040#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1039#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1038#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1037#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1036#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1035#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1034#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1033#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1032#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1031#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1030#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1029#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1028#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1027#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1026#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1025#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1024#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1023#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1022#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1021#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1020#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1019#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1018#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1017#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1016#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1015#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1014#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1013#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1012#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1011#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1010#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1009#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1008#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1007#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1006#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1005#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1004#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1003#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1002#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1001#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1000#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 999#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 998#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 997#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 996#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 995#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 994#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 993#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 992#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 991#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 990#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 989#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 988#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 987#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 986#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 985#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 984#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 983#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 982#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 981#L13-3 assume !(main_~i~0#1 < 1048); 972#L17-2 [2022-11-18 19:37:06,509 INFO L750 eck$LassoCheckResult]: Loop: 972#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 973#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 972#L17-2 [2022-11-18 19:37:06,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:06,510 INFO L85 PathProgramCache]: Analyzing trace with hash -1497227703, now seen corresponding path program 5 times [2022-11-18 19:37:06,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:06,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369734077] [2022-11-18 19:37:06,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:06,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:06,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:08,987 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:08,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 19:37:08,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369734077] [2022-11-18 19:37:08,988 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369734077] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 19:37:08,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [846335168] [2022-11-18 19:37:08,988 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 19:37:08,988 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 19:37:08,989 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:08,992 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 19:37:09,014 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-18 19:37:13,620 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-11-18 19:37:13,620 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 19:37:13,630 INFO L263 TraceCheckSpWp]: Trace formula consists of 530 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-18 19:37:13,635 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 19:37:13,843 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:13,844 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 19:37:17,191 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:17,192 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [846335168] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 19:37:17,192 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 19:37:17,192 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2022-11-18 19:37:17,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940562023] [2022-11-18 19:37:17,192 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 19:37:17,193 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 19:37:17,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:17,193 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 6 times [2022-11-18 19:37:17,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:17,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423982014] [2022-11-18 19:37:17,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:17,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:17,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:17,202 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 19:37:17,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 19:37:17,207 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 19:37:17,250 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 19:37:17,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-11-18 19:37:17,254 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-11-18 19:37:17,254 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. cyclomatic complexity: 3 Second operand has 97 states, 96 states have (on average 2.0) internal successors, (192), 97 states have internal predecessors, (192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:17,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 19:37:17,662 INFO L93 Difference]: Finished difference Result 193 states and 194 transitions. [2022-11-18 19:37:17,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 194 transitions. [2022-11-18 19:37:17,668 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:17,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 193 states and 194 transitions. [2022-11-18 19:37:17,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-11-18 19:37:17,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-11-18 19:37:17,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 193 states and 194 transitions. [2022-11-18 19:37:17,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 19:37:17,682 INFO L218 hiAutomatonCegarLoop]: Abstraction has 193 states and 194 transitions. [2022-11-18 19:37:17,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states and 194 transitions. [2022-11-18 19:37:17,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 193. [2022-11-18 19:37:17,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193 states, 193 states have (on average 1.005181347150259) internal successors, (194), 192 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 19:37:17,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 194 transitions. [2022-11-18 19:37:17,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 193 states and 194 transitions. [2022-11-18 19:37:17,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-11-18 19:37:17,697 INFO L428 stractBuchiCegarLoop]: Abstraction has 193 states and 194 transitions. [2022-11-18 19:37:17,697 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-18 19:37:17,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193 states and 194 transitions. [2022-11-18 19:37:17,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 19:37:17,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 19:37:17,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 19:37:17,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1] [2022-11-18 19:37:17,709 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 19:37:17,710 INFO L748 eck$LassoCheckResult]: Stem: 1928#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1929#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 1932#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1933#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1934#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1930#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1931#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2118#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2117#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2116#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2115#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2114#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2113#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2112#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2111#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2110#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2109#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2108#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2107#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2106#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2105#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2104#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2103#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2102#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2101#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2100#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2099#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2098#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2097#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2096#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2095#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2094#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2093#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2092#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2091#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2090#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2089#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2088#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2087#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2086#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2085#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2084#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2083#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2082#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2081#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2080#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2079#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2078#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2077#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2076#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2075#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2074#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2073#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2072#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2071#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2070#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2069#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2068#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2067#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2066#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2065#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2064#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2063#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2062#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2061#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2060#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2059#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2058#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2057#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2056#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2055#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2054#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2053#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2052#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2051#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2050#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2049#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2048#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2047#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2046#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2045#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2044#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2043#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2042#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2041#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2040#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2039#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2038#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2037#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2036#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2035#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2034#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2033#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2032#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2031#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2030#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2029#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2028#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2027#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2026#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2025#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2024#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2023#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2022#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2021#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2020#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2019#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2018#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2017#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2016#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2015#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2014#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2013#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2012#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2011#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2010#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2009#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2008#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2007#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2006#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2005#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2004#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2003#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2002#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2001#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2000#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1999#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1998#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1997#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1996#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1995#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1994#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1993#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1992#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1991#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1990#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1989#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1988#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1987#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1986#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1985#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1984#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1983#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1982#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1981#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1980#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1979#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1978#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1977#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1976#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1975#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1974#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1973#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1972#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1971#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1970#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1969#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1968#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1967#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1966#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1965#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1964#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1963#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1962#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1961#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1960#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1959#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1958#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1957#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1956#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1955#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1954#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1953#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1952#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1951#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1950#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1949#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1948#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1947#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1946#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1945#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1944#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1943#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1942#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1941#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1940#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1939#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1938#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1937#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1936#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1935#L13-3 assume !(main_~i~0#1 < 1048); 1926#L17-2 [2022-11-18 19:37:17,714 INFO L750 eck$LassoCheckResult]: Loop: 1926#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 1927#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 1926#L17-2 [2022-11-18 19:37:17,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 19:37:17,715 INFO L85 PathProgramCache]: Analyzing trace with hash 2115802601, now seen corresponding path program 6 times [2022-11-18 19:37:17,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 19:37:17,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045457936] [2022-11-18 19:37:17,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 19:37:17,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 19:37:17,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 19:37:25,782 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 19:37:25,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 19:37:25,782 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045457936] [2022-11-18 19:37:25,783 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1045457936] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 19:37:25,783 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [492984634] [2022-11-18 19:37:25,783 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 19:37:25,783 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 19:37:25,783 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 19:37:25,784 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 19:37:25,787 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4f488ffc-6dbb-4e70-9375-b7005243d0d3/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process