./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength6.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength6.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ef2b56a2f4ebf2e6f7f4ededf8760f087ff726b08e36644d8dcb52a8d087cd1 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 21:02:49,389 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 21:02:49,392 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 21:02:49,420 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 21:02:49,420 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 21:02:49,421 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 21:02:49,423 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 21:02:49,425 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 21:02:49,427 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 21:02:49,428 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 21:02:49,429 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 21:02:49,430 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 21:02:49,431 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 21:02:49,432 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 21:02:49,433 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 21:02:49,435 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 21:02:49,436 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 21:02:49,437 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 21:02:49,439 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 21:02:49,441 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 21:02:49,443 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 21:02:49,444 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 21:02:49,446 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 21:02:49,447 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 21:02:49,451 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 21:02:49,452 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 21:02:49,452 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 21:02:49,453 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 21:02:49,454 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 21:02:49,455 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 21:02:49,455 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 21:02:49,456 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 21:02:49,457 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 21:02:49,458 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 21:02:49,459 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 21:02:49,460 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 21:02:49,460 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 21:02:49,461 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 21:02:49,461 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 21:02:49,462 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 21:02:49,463 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 21:02:49,464 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-18 21:02:49,488 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 21:02:49,489 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 21:02:49,489 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 21:02:49,489 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 21:02:49,490 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 21:02:49,491 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 21:02:49,491 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 21:02:49,491 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-18 21:02:49,491 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-18 21:02:49,492 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-18 21:02:49,492 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-18 21:02:49,492 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-18 21:02:49,492 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-18 21:02:49,493 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 21:02:49,493 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-18 21:02:49,493 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 21:02:49,493 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 21:02:49,494 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-18 21:02:49,494 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 21:02:49,494 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-18 21:02:49,494 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-18 21:02:49,495 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-18 21:02:49,495 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-18 21:02:49,495 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-18 21:02:49,495 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-18 21:02:49,495 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 21:02:49,496 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-18 21:02:49,496 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 21:02:49,496 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 21:02:49,496 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 21:02:49,497 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 21:02:49,498 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-18 21:02:49,498 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ef2b56a2f4ebf2e6f7f4ededf8760f087ff726b08e36644d8dcb52a8d087cd1 [2022-11-18 21:02:49,784 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 21:02:49,817 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 21:02:49,820 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 21:02:49,822 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 21:02:49,823 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 21:02:49,824 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength6.c [2022-11-18 21:02:49,900 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/data/c94748408/d66eb6fb997c43909eda0a2caf5eb176/FLAGa2334f335 [2022-11-18 21:02:50,374 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 21:02:50,374 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength6.c [2022-11-18 21:02:50,380 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/data/c94748408/d66eb6fb997c43909eda0a2caf5eb176/FLAGa2334f335 [2022-11-18 21:02:50,748 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/data/c94748408/d66eb6fb997c43909eda0a2caf5eb176 [2022-11-18 21:02:50,750 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 21:02:50,752 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 21:02:50,759 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 21:02:50,759 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 21:02:50,763 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 21:02:50,763 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:02:50" (1/1) ... [2022-11-18 21:02:50,765 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2245c646 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:50, skipping insertion in model container [2022-11-18 21:02:50,766 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:02:50" (1/1) ... [2022-11-18 21:02:50,774 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 21:02:50,788 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 21:02:50,985 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 21:02:50,995 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 21:02:51,009 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 21:02:51,022 INFO L208 MainTranslator]: Completed translation [2022-11-18 21:02:51,022 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51 WrapperNode [2022-11-18 21:02:51,022 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 21:02:51,023 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 21:02:51,024 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 21:02:51,024 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 21:02:51,031 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,037 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,055 INFO L138 Inliner]: procedures = 8, calls = 14, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 69 [2022-11-18 21:02:51,056 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 21:02:51,056 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 21:02:51,057 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 21:02:51,057 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 21:02:51,065 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,066 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,067 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,068 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,072 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,076 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,077 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,078 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,080 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 21:02:51,081 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 21:02:51,081 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 21:02:51,081 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 21:02:51,082 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (1/1) ... [2022-11-18 21:02:51,088 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:02:51,100 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:02:51,125 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:02:51,132 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-18 21:02:51,158 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-18 21:02:51,158 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 21:02:51,158 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 21:02:51,159 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-18 21:02:51,159 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-18 21:02:51,159 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-18 21:02:51,227 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 21:02:51,229 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 21:02:51,411 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 21:02:51,419 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 21:02:51,419 INFO L300 CfgBuilder]: Removed 3 assume(true) statements. [2022-11-18 21:02:51,421 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:02:51 BoogieIcfgContainer [2022-11-18 21:02:51,422 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 21:02:51,423 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-18 21:02:51,423 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-18 21:02:51,430 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-18 21:02:51,432 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 21:02:51,432 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 09:02:50" (1/3) ... [2022-11-18 21:02:51,434 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@536d285d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 09:02:51, skipping insertion in model container [2022-11-18 21:02:51,434 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 21:02:51,434 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:02:51" (2/3) ... [2022-11-18 21:02:51,435 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@536d285d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 09:02:51, skipping insertion in model container [2022-11-18 21:02:51,435 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 21:02:51,436 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:02:51" (3/3) ... [2022-11-18 21:02:51,437 INFO L332 chiAutomizerObserver]: Analyzing ICFG ArraysOfVariableLength6.c [2022-11-18 21:02:51,498 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-18 21:02:51,498 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-18 21:02:51,498 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-18 21:02:51,499 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-18 21:02:51,499 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-18 21:02:51,499 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-18 21:02:51,499 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-18 21:02:51,499 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-18 21:02:51,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:51,522 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2022-11-18 21:02:51,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:02:51,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:02:51,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 21:02:51,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-18 21:02:51,528 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-18 21:02:51,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:51,530 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2022-11-18 21:02:51,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:02:51,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:02:51,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 21:02:51,531 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-11-18 21:02:51,538 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 7#L25-3true [2022-11-18 21:02:51,539 INFO L750 eck$LassoCheckResult]: Loop: 7#L25-3true assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 6#L15-3true assume !(foo_~i~0#1 < foo_~size#1); 11#L15-4true foo_#res#1 := foo_~i~0#1; 12#L18true main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 13#L25-2true main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7#L25-3true [2022-11-18 21:02:51,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:51,545 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-11-18 21:02:51,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:51,555 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384587260] [2022-11-18 21:02:51,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:51,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:51,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:51,658 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:02:51,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:51,696 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:02:51,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:51,701 INFO L85 PathProgramCache]: Analyzing trace with hash 38364915, now seen corresponding path program 1 times [2022-11-18 21:02:51,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:51,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [764863030] [2022-11-18 21:02:51,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:51,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:51,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:02:51,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:51,930 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 21:02:51,930 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [764863030] [2022-11-18 21:02:51,931 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [764863030] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:02:51,931 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:02:51,931 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-18 21:02:51,932 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114048606] [2022-11-18 21:02:51,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:02:51,937 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-18 21:02:51,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 21:02:52,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:02:52,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:02:52,020 INFO L87 Difference]: Start difference. First operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:52,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:02:52,081 INFO L93 Difference]: Finished difference Result 19 states and 22 transitions. [2022-11-18 21:02:52,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 22 transitions. [2022-11-18 21:02:52,084 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11 [2022-11-18 21:02:52,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 14 states and 16 transitions. [2022-11-18 21:02:52,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-18 21:02:52,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-18 21:02:52,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 16 transitions. [2022-11-18 21:02:52,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 21:02:52,092 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 16 transitions. [2022-11-18 21:02:52,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 16 transitions. [2022-11-18 21:02:52,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 13. [2022-11-18 21:02:52,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.1538461538461537) internal successors, (15), 12 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:52,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 15 transitions. [2022-11-18 21:02:52,121 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13 states and 15 transitions. [2022-11-18 21:02:52,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:02:52,130 INFO L428 stractBuchiCegarLoop]: Abstraction has 13 states and 15 transitions. [2022-11-18 21:02:52,130 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-18 21:02:52,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 15 transitions. [2022-11-18 21:02:52,134 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-18 21:02:52,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:02:52,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:02:52,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 21:02:52,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:02:52,136 INFO L748 eck$LassoCheckResult]: Stem: 51#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 52#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 48#L25-3 [2022-11-18 21:02:52,136 INFO L750 eck$LassoCheckResult]: Loop: 48#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 54#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 55#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 57#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 45#L15-4 foo_#res#1 := foo_~i~0#1; 46#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 47#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 48#L25-3 [2022-11-18 21:02:52,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:52,140 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2022-11-18 21:02:52,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:52,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [883587289] [2022-11-18 21:02:52,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:52,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:52,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:52,172 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:02:52,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:52,190 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:02:52,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:52,192 INFO L85 PathProgramCache]: Analyzing trace with hash -1732759051, now seen corresponding path program 1 times [2022-11-18 21:02:52,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:52,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945815450] [2022-11-18 21:02:52,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:52,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:52,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:02:52,357 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:52,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 21:02:52,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945815450] [2022-11-18 21:02:52,358 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1945815450] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 21:02:52,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [873907157] [2022-11-18 21:02:52,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:52,359 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 21:02:52,359 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:02:52,363 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 21:02:52,382 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-18 21:02:52,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:02:52,452 INFO L263 TraceCheckSpWp]: Trace formula consists of 45 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:02:52,454 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:02:52,551 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:52,551 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:02:52,593 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:52,593 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [873907157] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:02:52,594 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 21:02:52,594 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 7 [2022-11-18 21:02:52,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1476597574] [2022-11-18 21:02:52,595 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 21:02:52,595 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-18 21:02:52,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 21:02:52,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-18 21:02:52,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=29, Unknown=0, NotChecked=0, Total=56 [2022-11-18 21:02:52,597 INFO L87 Difference]: Start difference. First operand 13 states and 15 transitions. cyclomatic complexity: 4 Second operand has 8 states, 8 states have (on average 1.875) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:52,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:02:52,634 INFO L93 Difference]: Finished difference Result 19 states and 21 transitions. [2022-11-18 21:02:52,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 21 transitions. [2022-11-18 21:02:52,635 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2022-11-18 21:02:52,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 19 states and 21 transitions. [2022-11-18 21:02:52,636 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-18 21:02:52,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-18 21:02:52,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19 states and 21 transitions. [2022-11-18 21:02:52,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 21:02:52,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19 states and 21 transitions. [2022-11-18 21:02:52,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states and 21 transitions. [2022-11-18 21:02:52,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2022-11-18 21:02:52,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.105263157894737) internal successors, (21), 18 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:52,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2022-11-18 21:02:52,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 21 transitions. [2022-11-18 21:02:52,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-18 21:02:52,641 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2022-11-18 21:02:52,641 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-18 21:02:52,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 21 transitions. [2022-11-18 21:02:52,642 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2022-11-18 21:02:52,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:02:52,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:02:52,643 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 21:02:52,643 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [4, 4, 1, 1, 1, 1, 1] [2022-11-18 21:02:52,643 INFO L748 eck$LassoCheckResult]: Stem: 128#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 129#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 127#L25-3 [2022-11-18 21:02:52,643 INFO L750 eck$LassoCheckResult]: Loop: 127#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 133#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 134#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 136#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 142#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 141#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 140#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 139#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 138#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 137#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 124#L15-4 foo_#res#1 := foo_~i~0#1; 125#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 126#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 127#L25-3 [2022-11-18 21:02:52,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:52,644 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 3 times [2022-11-18 21:02:52,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:52,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182838168] [2022-11-18 21:02:52,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:52,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:52,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:52,654 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:02:52,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:52,661 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:02:52,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:52,661 INFO L85 PathProgramCache]: Analyzing trace with hash -1316700165, now seen corresponding path program 2 times [2022-11-18 21:02:52,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:52,662 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19389052] [2022-11-18 21:02:52,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:52,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:52,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:02:52,973 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:52,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 21:02:52,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [19389052] [2022-11-18 21:02:52,977 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [19389052] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 21:02:52,978 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2053151110] [2022-11-18 21:02:52,978 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:02:52,979 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 21:02:52,979 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:02:52,982 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 21:02:53,003 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-18 21:02:53,050 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:02:53,051 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:02:53,052 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 21:02:53,053 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:02:53,172 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:53,173 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:02:53,352 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:53,352 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2053151110] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:02:53,352 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 21:02:53,352 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 16 [2022-11-18 21:02:53,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115692429] [2022-11-18 21:02:53,353 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 21:02:53,353 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-18 21:02:53,354 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 21:02:53,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-18 21:02:53,355 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=146, Unknown=0, NotChecked=0, Total=272 [2022-11-18 21:02:53,355 INFO L87 Difference]: Start difference. First operand 19 states and 21 transitions. cyclomatic complexity: 4 Second operand has 17 states, 17 states have (on average 1.9411764705882353) internal successors, (33), 16 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:53,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:02:53,424 INFO L93 Difference]: Finished difference Result 31 states and 33 transitions. [2022-11-18 21:02:53,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 33 transitions. [2022-11-18 21:02:53,425 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28 [2022-11-18 21:02:53,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 31 states and 33 transitions. [2022-11-18 21:02:53,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2022-11-18 21:02:53,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2022-11-18 21:02:53,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 33 transitions. [2022-11-18 21:02:53,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 21:02:53,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31 states and 33 transitions. [2022-11-18 21:02:53,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 33 transitions. [2022-11-18 21:02:53,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2022-11-18 21:02:53,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.064516129032258) internal successors, (33), 30 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:53,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2022-11-18 21:02:53,431 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 33 transitions. [2022-11-18 21:02:53,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 21:02:53,433 INFO L428 stractBuchiCegarLoop]: Abstraction has 31 states and 33 transitions. [2022-11-18 21:02:53,433 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-18 21:02:53,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 33 transitions. [2022-11-18 21:02:53,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28 [2022-11-18 21:02:53,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:02:53,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:02:53,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 21:02:53,437 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [10, 10, 1, 1, 1, 1, 1] [2022-11-18 21:02:53,437 INFO L748 eck$LassoCheckResult]: Stem: 270#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 271#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 269#L25-3 [2022-11-18 21:02:53,437 INFO L750 eck$LassoCheckResult]: Loop: 269#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 278#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 279#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 275#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 276#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 296#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 295#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 294#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 293#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 292#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 291#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 290#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 289#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 288#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 287#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 286#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 285#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 284#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 283#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 282#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 281#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 280#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 266#L15-4 foo_#res#1 := foo_~i~0#1; 267#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 268#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 269#L25-3 [2022-11-18 21:02:53,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:53,438 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 4 times [2022-11-18 21:02:53,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:53,439 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250680511] [2022-11-18 21:02:53,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:53,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:53,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:53,454 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:02:53,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:53,466 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:02:53,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:53,467 INFO L85 PathProgramCache]: Analyzing trace with hash 2131617415, now seen corresponding path program 3 times [2022-11-18 21:02:53,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:53,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100387635] [2022-11-18 21:02:53,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:53,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:53,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:02:53,984 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:53,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 21:02:53,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100387635] [2022-11-18 21:02:53,986 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100387635] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 21:02:53,986 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1085768303] [2022-11-18 21:02:53,986 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 21:02:53,987 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 21:02:53,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:02:54,021 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 21:02:54,055 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-18 21:02:54,161 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-18 21:02:54,162 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:02:54,164 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-18 21:02:54,166 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:02:54,539 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:54,539 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:02:54,982 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:54,983 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1085768303] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:02:54,983 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 21:02:54,983 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 34 [2022-11-18 21:02:54,983 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476686570] [2022-11-18 21:02:54,983 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 21:02:54,984 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-18 21:02:54,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 21:02:54,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-18 21:02:54,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=540, Invalid=650, Unknown=0, NotChecked=0, Total=1190 [2022-11-18 21:02:54,986 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. cyclomatic complexity: 4 Second operand has 35 states, 35 states have (on average 1.9714285714285715) internal successors, (69), 34 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:55,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:02:55,109 INFO L93 Difference]: Finished difference Result 55 states and 57 transitions. [2022-11-18 21:02:55,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 57 transitions. [2022-11-18 21:02:55,110 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52 [2022-11-18 21:02:55,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 55 states and 57 transitions. [2022-11-18 21:02:55,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55 [2022-11-18 21:02:55,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55 [2022-11-18 21:02:55,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 57 transitions. [2022-11-18 21:02:55,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 21:02:55,112 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55 states and 57 transitions. [2022-11-18 21:02:55,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 57 transitions. [2022-11-18 21:02:55,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2022-11-18 21:02:55,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.0363636363636364) internal successors, (57), 54 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:55,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 57 transitions. [2022-11-18 21:02:55,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 57 transitions. [2022-11-18 21:02:55,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-18 21:02:55,117 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 57 transitions. [2022-11-18 21:02:55,117 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-18 21:02:55,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 57 transitions. [2022-11-18 21:02:55,118 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52 [2022-11-18 21:02:55,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:02:55,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:02:55,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 21:02:55,119 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [22, 22, 1, 1, 1, 1, 1] [2022-11-18 21:02:55,119 INFO L748 eck$LassoCheckResult]: Stem: 538#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 539#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 537#L25-3 [2022-11-18 21:02:55,119 INFO L750 eck$LassoCheckResult]: Loop: 537#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 546#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 547#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 543#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 544#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 588#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 587#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 586#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 585#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 584#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 583#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 582#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 581#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 580#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 579#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 578#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 577#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 576#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 575#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 574#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 573#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 572#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 571#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 570#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 569#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 568#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 567#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 566#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 565#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 564#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 563#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 562#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 561#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 560#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 559#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 558#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 557#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 556#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 555#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 554#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 553#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 552#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 551#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 550#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 549#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 548#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 534#L15-4 foo_#res#1 := foo_~i~0#1; 535#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 536#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 537#L25-3 [2022-11-18 21:02:55,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:55,120 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 5 times [2022-11-18 21:02:55,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:55,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916914606] [2022-11-18 21:02:55,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:55,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:55,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:55,127 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:02:55,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:55,131 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:02:55,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:55,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1575559777, now seen corresponding path program 4 times [2022-11-18 21:02:55,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:55,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982026924] [2022-11-18 21:02:55,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:55,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:55,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:02:56,241 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:56,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 21:02:56,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982026924] [2022-11-18 21:02:56,242 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982026924] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 21:02:56,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [653001790] [2022-11-18 21:02:56,243 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 21:02:56,243 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 21:02:56,243 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:02:56,250 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 21:02:56,259 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-18 21:02:56,396 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 21:02:56,397 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:02:56,399 INFO L263 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-18 21:02:56,404 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:02:57,537 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:57,537 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:02:58,925 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:02:58,926 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [653001790] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:02:58,926 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 21:02:58,926 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 70 [2022-11-18 21:02:58,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093616826] [2022-11-18 21:02:58,927 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 21:02:58,927 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-18 21:02:58,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 21:02:58,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2022-11-18 21:02:58,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2050, Invalid=2920, Unknown=0, NotChecked=0, Total=4970 [2022-11-18 21:02:58,931 INFO L87 Difference]: Start difference. First operand 55 states and 57 transitions. cyclomatic complexity: 4 Second operand has 71 states, 71 states have (on average 1.9859154929577465) internal successors, (141), 70 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:59,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:02:59,133 INFO L93 Difference]: Finished difference Result 75 states and 77 transitions. [2022-11-18 21:02:59,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 77 transitions. [2022-11-18 21:02:59,135 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 72 [2022-11-18 21:02:59,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 75 states and 77 transitions. [2022-11-18 21:02:59,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2022-11-18 21:02:59,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2022-11-18 21:02:59,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 77 transitions. [2022-11-18 21:02:59,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 21:02:59,137 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75 states and 77 transitions. [2022-11-18 21:02:59,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 77 transitions. [2022-11-18 21:02:59,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2022-11-18 21:02:59,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.0266666666666666) internal successors, (77), 74 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:02:59,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 77 transitions. [2022-11-18 21:02:59,142 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 77 transitions. [2022-11-18 21:02:59,142 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2022-11-18 21:02:59,143 INFO L428 stractBuchiCegarLoop]: Abstraction has 75 states and 77 transitions. [2022-11-18 21:02:59,143 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-18 21:02:59,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 77 transitions. [2022-11-18 21:02:59,144 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 72 [2022-11-18 21:02:59,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:02:59,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:02:59,145 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 21:02:59,146 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [32, 32, 1, 1, 1, 1, 1] [2022-11-18 21:02:59,146 INFO L748 eck$LassoCheckResult]: Stem: 1030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1031#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 1028#L25-3 [2022-11-18 21:02:59,146 INFO L750 eck$LassoCheckResult]: Loop: 1028#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1038#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1039#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1035#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1036#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1100#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1099#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1098#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1097#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1096#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1095#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1094#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1093#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1092#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1091#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1090#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1089#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1088#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1087#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1086#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1085#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1084#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1083#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1082#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1081#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1080#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1079#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1078#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1077#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1076#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1075#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1074#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1073#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1072#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1071#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1070#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1069#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1068#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1067#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1066#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1065#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1064#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1063#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1062#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1061#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1060#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1059#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1058#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1057#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1056#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1055#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1054#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1053#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1052#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1051#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1050#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1049#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1048#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1047#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1046#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1045#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1044#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1043#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1042#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1041#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1040#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 1029#L15-4 foo_#res#1 := foo_~i~0#1; 1026#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1027#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1028#L25-3 [2022-11-18 21:02:59,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:59,147 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 6 times [2022-11-18 21:02:59,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:59,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443205216] [2022-11-18 21:02:59,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:59,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:59,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:59,153 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:02:59,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:59,157 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:02:59,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:59,158 INFO L85 PathProgramCache]: Analyzing trace with hash 776556339, now seen corresponding path program 5 times [2022-11-18 21:02:59,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:59,158 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328687059] [2022-11-18 21:02:59,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:59,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:59,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:59,231 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:02:59,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:59,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:02:59,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:02:59,311 INFO L85 PathProgramCache]: Analyzing trace with hash -378248015, now seen corresponding path program 1 times [2022-11-18 21:02:59,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:02:59,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726455718] [2022-11-18 21:02:59,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:02:59,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:02:59,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:59,373 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:02:59,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:02:59,427 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:05:53,854 WARN L233 SmtUtils]: Spent 2.91m on a formula simplification. DAG size of input: 507 DAG size of output: 317 (called from [L 278] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2022-11-18 21:05:53,943 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,944 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,945 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,946 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,948 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,949 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,950 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,951 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,953 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,954 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,955 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,956 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,957 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,959 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,960 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,961 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,963 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,964 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,965 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,966 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,968 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,969 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,970 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,971 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,973 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,974 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,975 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,976 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,978 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,979 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,980 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,981 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,983 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,984 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,985 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,986 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,988 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,989 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,990 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,992 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,993 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,994 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,996 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,997 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,998 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:53,999 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,001 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,002 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,003 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,005 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,006 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,007 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,012 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,013 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,014 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,016 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,017 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,018 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,019 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,021 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,022 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,024 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,025 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,026 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,028 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,029 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,031 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,033 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,034 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,036 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,037 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,039 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,040 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,042 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,043 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,045 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,046 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,047 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,049 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,050 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,052 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,053 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,055 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,056 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,058 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,059 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,060 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,062 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,063 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,065 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,066 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,067 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,069 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,070 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,072 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,074 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,075 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,077 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,087 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,089 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,090 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,092 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,093 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,094 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,096 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,097 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,098 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,099 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,101 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,102 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,103 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,105 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,107 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,111 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,112 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,113 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,115 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,116 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,117 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,118 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,120 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,121 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,122 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,123 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,125 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,127 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,129 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,130 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,132 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,133 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,134 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,135 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,137 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,138 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,139 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,141 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,142 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,143 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,144 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,146 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,147 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,148 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,150 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,151 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,152 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,153 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,154 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,156 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,157 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,158 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,159 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,161 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,162 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,163 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,164 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,166 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:05:54,944 INFO L217 Elim1Store]: Index analysis took 1004 ms [2022-11-18 21:05:55,013 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 496 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 367 treesize of output 429 [2022-11-18 21:05:56,079 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 21:05:56,079 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 21:05:56,079 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 21:05:56,080 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 21:05:56,080 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 21:05:56,080 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:56,080 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 21:05:56,080 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 21:05:56,080 INFO L133 ssoRankerPreferences]: Filename of dumped script: ArraysOfVariableLength6.c_Iteration6_Lasso [2022-11-18 21:05:56,080 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 21:05:56,081 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 21:05:56,111 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:56,120 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:56,122 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:56,124 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:56,127 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:59,149 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:59,152 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:59,155 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:59,157 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:59,160 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:59,162 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:05:59,660 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 21:05:59,665 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 21:05:59,667 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,667 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,668 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,670 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-18 21:05:59,671 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,682 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,682 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:05:59,683 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,683 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,683 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,685 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:05:59,685 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:05:59,693 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:05:59,696 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2022-11-18 21:05:59,696 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,696 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,697 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,701 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-18 21:05:59,702 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,712 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,713 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:05:59,713 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,713 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,713 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,713 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:05:59,714 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:05:59,715 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:05:59,728 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-11-18 21:05:59,729 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,729 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,730 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,735 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-18 21:05:59,736 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,746 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,746 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:05:59,746 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,746 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,746 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,747 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:05:59,747 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:05:59,749 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:05:59,755 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2022-11-18 21:05:59,756 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,756 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,757 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,758 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-18 21:05:59,760 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,770 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,770 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,770 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,771 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,789 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 21:05:59,789 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 21:05:59,793 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:05:59,799 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-11-18 21:05:59,800 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,800 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,801 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,802 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-18 21:05:59,803 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,813 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,813 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:05:59,814 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,814 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,814 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,815 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:05:59,815 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:05:59,816 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:05:59,819 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-11-18 21:05:59,820 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,820 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,821 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,822 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-18 21:05:59,823 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,833 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,833 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:05:59,834 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,834 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,834 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,834 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:05:59,834 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:05:59,836 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:05:59,843 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-18 21:05:59,844 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,844 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,845 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,846 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-11-18 21:05:59,847 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,857 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,857 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:05:59,857 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,857 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,858 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,858 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:05:59,858 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:05:59,868 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:05:59,871 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-11-18 21:05:59,871 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,871 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,873 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2022-11-18 21:05:59,880 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,890 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,890 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:05:59,890 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,891 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,891 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,895 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:05:59,895 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:05:59,919 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:05:59,922 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2022-11-18 21:05:59,922 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,923 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,924 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,931 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,932 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2022-11-18 21:05:59,943 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,943 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:05:59,943 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,943 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,943 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,944 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:05:59,944 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:05:59,953 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:05:59,962 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2022-11-18 21:05:59,962 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:05:59,962 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:05:59,963 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:05:59,976 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:05:59,988 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:05:59,988 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:05:59,988 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:05:59,988 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:05:59,989 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:05:59,989 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:05:59,989 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:05:59,991 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2022-11-18 21:06:00,006 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:00,015 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:00,015 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:00,016 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:00,017 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:00,021 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:00,033 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:00,033 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:06:00,033 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:00,033 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:00,033 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:00,034 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:06:00,034 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:06:00,036 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2022-11-18 21:06:00,046 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:00,055 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:00,055 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:00,055 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:00,056 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:00,078 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2022-11-18 21:06:00,078 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:00,092 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:00,093 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:06:00,093 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:00,093 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:00,093 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:00,094 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:06:00,095 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:06:00,104 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:00,113 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:00,114 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:00,115 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:00,118 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:00,130 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2022-11-18 21:06:00,131 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:00,141 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:00,141 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:06:00,141 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:00,141 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:00,141 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:00,142 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:06:00,142 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:06:00,143 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:00,151 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2022-11-18 21:06:00,151 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:00,151 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:00,152 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:00,156 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:00,159 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2022-11-18 21:06:00,167 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:00,167 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:06:00,167 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:00,167 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:00,167 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:00,168 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:06:00,168 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:06:00,169 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:00,172 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:00,172 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:00,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:00,173 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:00,176 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2022-11-18 21:06:00,177 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:00,187 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:00,187 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:06:00,187 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:00,187 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:00,187 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:00,187 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:06:00,188 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:06:00,189 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:00,197 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:00,197 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:00,197 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:00,198 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:00,200 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2022-11-18 21:06:00,201 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:00,211 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:00,211 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:06:00,211 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:00,211 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:00,211 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:00,212 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:06:00,212 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:06:00,213 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:00,227 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2022-11-18 21:06:00,227 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:00,227 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:00,228 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:00,230 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2022-11-18 21:06:00,231 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:00,240 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:00,241 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:06:00,241 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:00,241 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:00,241 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:00,241 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:06:00,241 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:06:00,243 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:00,247 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:00,247 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:00,247 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:00,248 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:00,259 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2022-11-18 21:06:00,260 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:00,270 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:00,271 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:00,271 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:00,271 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:00,276 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 21:06:00,277 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 21:06:00,302 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 21:06:00,329 INFO L443 ModelExtractionUtils]: Simplification made 8 calls to the SMT solver. [2022-11-18 21:06:00,329 INFO L444 ModelExtractionUtils]: 3 out of 13 variables were initially zero. Simplification set additionally 6 variables to zero. [2022-11-18 21:06:00,331 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:00,331 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:00,339 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:00,398 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2022-11-18 21:06:00,399 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 21:06:00,429 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 21:06:00,429 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 21:06:00,430 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~#b~0#1.offset, v_rep(select #length ULTIMATE.start_main_~#b~0#1.base)_1, ULTIMATE.start_main_~i~1#1) = -1*ULTIMATE.start_main_~#b~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~#b~0#1.base)_1 - 4*ULTIMATE.start_main_~i~1#1 Supporting invariants [] [2022-11-18 21:06:00,446 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2022-11-18 21:06:00,478 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2022-11-18 21:06:00,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:00,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:06:00,526 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 21:06:00,526 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:06:00,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:06:00,647 INFO L263 TraceCheckSpWp]: Trace formula consists of 386 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 21:06:00,653 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:06:01,161 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1024 trivial. 0 not checked. [2022-11-18 21:06:01,164 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-18 21:06:01,166 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 75 states and 77 transitions. cyclomatic complexity: 4 Second operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:06:01,221 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 75 states and 77 transitions. cyclomatic complexity: 4. Second operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 145 states and 151 transitions. Complement of second has 7 states. [2022-11-18 21:06:01,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 21:06:01,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:06:01,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 10 transitions. [2022-11-18 21:06:01,226 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 10 transitions. Stem has 2 letters. Loop has 69 letters. [2022-11-18 21:06:01,229 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:06:01,229 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 10 transitions. Stem has 71 letters. Loop has 69 letters. [2022-11-18 21:06:01,235 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:06:01,235 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 10 transitions. Stem has 2 letters. Loop has 138 letters. [2022-11-18 21:06:01,237 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:06:01,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 145 states and 151 transitions. [2022-11-18 21:06:01,246 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 21:06:01,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 145 states to 141 states and 146 transitions. [2022-11-18 21:06:01,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70 [2022-11-18 21:06:01,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72 [2022-11-18 21:06:01,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 141 states and 146 transitions. [2022-11-18 21:06:01,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 21:06:01,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 141 states and 146 transitions. [2022-11-18 21:06:01,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states and 146 transitions. [2022-11-18 21:06:01,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 78. [2022-11-18 21:06:01,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.064102564102564) internal successors, (83), 77 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:06:01,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 83 transitions. [2022-11-18 21:06:01,261 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78 states and 83 transitions. [2022-11-18 21:06:01,262 INFO L428 stractBuchiCegarLoop]: Abstraction has 78 states and 83 transitions. [2022-11-18 21:06:01,262 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-18 21:06:01,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 83 transitions. [2022-11-18 21:06:01,262 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 21:06:01,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:06:01,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:06:01,264 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2022-11-18 21:06:01,265 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 21:06:01,265 INFO L748 eck$LassoCheckResult]: Stem: 1502#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 1511#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1507#L15-3 [2022-11-18 21:06:01,265 INFO L750 eck$LassoCheckResult]: Loop: 1507#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1508#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1507#L15-3 [2022-11-18 21:06:01,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:01,266 INFO L85 PathProgramCache]: Analyzing trace with hash 29863, now seen corresponding path program 1 times [2022-11-18 21:06:01,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:06:01,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260294298] [2022-11-18 21:06:01,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:06:01,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:06:01,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:01,278 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:06:01,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:01,292 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:06:01,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:01,295 INFO L85 PathProgramCache]: Analyzing trace with hash 1539, now seen corresponding path program 1 times [2022-11-18 21:06:01,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:06:01,295 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075559291] [2022-11-18 21:06:01,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:06:01,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:06:01,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:01,304 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:06:01,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:01,308 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:06:01,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:01,311 INFO L85 PathProgramCache]: Analyzing trace with hash 28698921, now seen corresponding path program 1 times [2022-11-18 21:06:01,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:06:01,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358313370] [2022-11-18 21:06:01,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:06:01,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:06:01,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:01,321 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:06:01,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:01,335 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:06:01,540 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:01,705 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 21:06:01,706 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 21:06:01,706 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 21:06:01,706 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 21:06:01,706 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 21:06:01,706 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:01,706 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 21:06:01,706 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 21:06:01,706 INFO L133 ssoRankerPreferences]: Filename of dumped script: ArraysOfVariableLength6.c_Iteration7_Lasso [2022-11-18 21:06:01,706 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 21:06:01,706 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 21:06:01,710 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,713 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,920 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,923 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,926 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,930 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,932 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,936 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,939 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,942 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,945 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,948 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,950 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:01,953 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:06:02,324 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 21:06:02,325 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 21:06:02,325 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:02,325 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:02,332 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:02,334 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:02,346 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:02,346 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:02,346 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:02,347 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:02,348 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2022-11-18 21:06:02,349 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 21:06:02,349 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 21:06:02,359 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:02,369 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:02,370 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:02,370 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:02,371 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:02,375 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:02,388 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2022-11-18 21:06:02,388 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:02,388 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:06:02,389 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:02,389 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:02,389 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:02,389 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:06:02,389 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:06:02,406 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:02,415 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:02,415 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:02,415 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:02,416 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:02,424 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:02,437 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2022-11-18 21:06:02,438 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:02,438 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:02,438 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:02,438 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:02,441 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 21:06:02,442 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 21:06:02,462 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:02,471 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:02,472 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:02,472 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:02,473 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:02,478 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:02,492 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:02,492 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:02,492 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:02,492 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:02,495 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2022-11-18 21:06:02,498 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 21:06:02,498 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 21:06:02,518 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:06:02,522 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:02,522 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:02,522 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:02,523 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:02,531 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:06:02,544 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:06:02,544 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:06:02,544 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:06:02,544 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:06:02,547 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2022-11-18 21:06:02,558 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 21:06:02,559 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 21:06:02,580 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 21:06:02,625 INFO L443 ModelExtractionUtils]: Simplification made 14 calls to the SMT solver. [2022-11-18 21:06:02,625 INFO L444 ModelExtractionUtils]: 12 out of 31 variables were initially zero. Simplification set additionally 16 variables to zero. [2022-11-18 21:06:02,625 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:06:02,625 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:06:02,627 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:06:02,630 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 21:06:02,643 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2022-11-18 21:06:02,667 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 21:06:02,667 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 21:06:02,667 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_foo_~size#1, ULTIMATE.start_foo_~i~0#1) = 1*ULTIMATE.start_foo_~size#1 - 1*ULTIMATE.start_foo_~i~0#1 Supporting invariants [] [2022-11-18 21:06:02,676 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:02,692 INFO L156 tatePredicateManager]: 6 out of 6 supporting invariants were superfluous and have been removed [2022-11-18 21:06:02,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:02,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:06:02,719 INFO L263 TraceCheckSpWp]: Trace formula consists of 54 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 21:06:02,719 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:06:02,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:06:02,728 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 21:06:02,729 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:06:02,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:06:02,742 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-18 21:06:02,743 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 78 states and 83 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:06:02,766 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 78 states and 83 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 199 states and 210 transitions. Complement of second has 7 states. [2022-11-18 21:06:02,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 21:06:02,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:06:02,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 19 transitions. [2022-11-18 21:06:02,769 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 19 transitions. Stem has 3 letters. Loop has 2 letters. [2022-11-18 21:06:02,769 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:06:02,769 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 19 transitions. Stem has 5 letters. Loop has 2 letters. [2022-11-18 21:06:02,769 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:06:02,769 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 19 transitions. Stem has 3 letters. Loop has 4 letters. [2022-11-18 21:06:02,770 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:06:02,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 199 states and 210 transitions. [2022-11-18 21:06:02,771 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11 [2022-11-18 21:06:02,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 199 states to 155 states and 162 transitions. [2022-11-18 21:06:02,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-18 21:06:02,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-18 21:06:02,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155 states and 162 transitions. [2022-11-18 21:06:02,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 21:06:02,773 INFO L218 hiAutomatonCegarLoop]: Abstraction has 155 states and 162 transitions. [2022-11-18 21:06:02,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states and 162 transitions. [2022-11-18 21:06:02,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 78. [2022-11-18 21:06:02,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.0512820512820513) internal successors, (82), 77 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:06:02,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 82 transitions. [2022-11-18 21:06:02,778 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78 states and 82 transitions. [2022-11-18 21:06:02,778 INFO L428 stractBuchiCegarLoop]: Abstraction has 78 states and 82 transitions. [2022-11-18 21:06:02,778 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-18 21:06:02,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 82 transitions. [2022-11-18 21:06:02,779 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 21:06:02,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:06:02,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:06:02,779 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2022-11-18 21:06:02,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 21:06:02,780 INFO L748 eck$LassoCheckResult]: Stem: 1844#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 1850#L25-3 assume !(main_~i~1#1 % 4294967296 < 32); 1851#L25-4 main_~i~1#1 := 0; 1841#L29-3 [2022-11-18 21:06:02,780 INFO L750 eck$LassoCheckResult]: Loop: 1841#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 1842#L30 assume !(32 != main_#t~mem5#1);havoc main_#t~mem5#1; 1843#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1841#L29-3 [2022-11-18 21:06:02,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:02,781 INFO L85 PathProgramCache]: Analyzing trace with hash 925723, now seen corresponding path program 1 times [2022-11-18 21:06:02,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:06:02,781 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195808040] [2022-11-18 21:06:02,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:06:02,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:06:02,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:06:02,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:06:02,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 21:06:02,814 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195808040] [2022-11-18 21:06:02,815 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195808040] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:06:02,815 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:06:02,815 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 21:06:02,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [542517974] [2022-11-18 21:06:02,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:06:02,816 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 21:06:02,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:02,816 INFO L85 PathProgramCache]: Analyzing trace with hash 69737, now seen corresponding path program 1 times [2022-11-18 21:06:02,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:06:02,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443008457] [2022-11-18 21:06:02,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:06:02,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:06:02,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:02,820 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:06:02,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:02,823 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:06:02,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 21:06:02,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:06:02,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:06:02,872 INFO L87 Difference]: Start difference. First operand 78 states and 82 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:06:02,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:06:02,892 INFO L93 Difference]: Finished difference Result 149 states and 153 transitions. [2022-11-18 21:06:02,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 149 states and 153 transitions. [2022-11-18 21:06:02,893 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 21:06:02,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 149 states to 149 states and 153 transitions. [2022-11-18 21:06:02,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-18 21:06:02,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-11-18 21:06:02,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 149 states and 153 transitions. [2022-11-18 21:06:02,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 21:06:02,895 INFO L218 hiAutomatonCegarLoop]: Abstraction has 149 states and 153 transitions. [2022-11-18 21:06:02,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states and 153 transitions. [2022-11-18 21:06:02,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 78. [2022-11-18 21:06:02,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.0384615384615385) internal successors, (81), 77 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:06:02,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 81 transitions. [2022-11-18 21:06:02,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78 states and 81 transitions. [2022-11-18 21:06:02,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:06:02,900 INFO L428 stractBuchiCegarLoop]: Abstraction has 78 states and 81 transitions. [2022-11-18 21:06:02,900 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-18 21:06:02,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 81 transitions. [2022-11-18 21:06:02,900 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 21:06:02,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:06:02,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:06:02,902 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [32, 32, 2, 1, 1, 1, 1, 1, 1] [2022-11-18 21:06:02,902 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 21:06:02,903 INFO L748 eck$LassoCheckResult]: Stem: 2074#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2075#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 2083#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2084#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2086#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2081#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2082#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2147#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2146#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2145#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2144#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2143#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2142#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2141#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2140#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2139#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2138#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2137#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2136#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2135#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2134#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2133#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2132#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2131#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2130#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2129#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2128#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2127#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2126#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2125#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2124#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2123#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2122#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2121#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2120#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2119#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2118#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2117#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2116#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2115#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2114#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2113#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2112#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2111#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2110#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2109#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2108#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2107#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2106#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2105#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2104#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2103#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2102#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2101#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2100#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2099#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2098#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2097#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2096#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2095#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2094#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2093#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2092#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2091#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2090#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2089#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2088#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2087#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 2070#L15-4 foo_#res#1 := foo_~i~0#1; 2071#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2072#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2073#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2079#L15-3 [2022-11-18 21:06:02,903 INFO L750 eck$LassoCheckResult]: Loop: 2079#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2080#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2079#L15-3 [2022-11-18 21:06:02,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:02,903 INFO L85 PathProgramCache]: Analyzing trace with hash 1159213433, now seen corresponding path program 2 times [2022-11-18 21:06:02,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:06:02,904 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116652226] [2022-11-18 21:06:02,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:06:02,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:06:02,954 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2022-11-18 21:06:03,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:03,020 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:06:03,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:03,110 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:06:03,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:03,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1539, now seen corresponding path program 2 times [2022-11-18 21:06:03,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:06:03,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150757062] [2022-11-18 21:06:03,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:06:03,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:06:03,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:03,116 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:06:03,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:03,121 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:06:03,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:06:03,124 INFO L85 PathProgramCache]: Analyzing trace with hash 1607580027, now seen corresponding path program 3 times [2022-11-18 21:06:03,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:06:03,124 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [839524987] [2022-11-18 21:06:03,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:06:03,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:06:03,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:03,216 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:06:03,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:06:03,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:16:39,885 WARN L233 SmtUtils]: Spent 10.61m on a formula simplification. DAG size of input: 557 DAG size of output: 349 (called from [L 278] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2022-11-18 21:16:40,227 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 21:16:40,227 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 21:16:40,227 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 21:16:40,227 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 21:16:40,227 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 21:16:40,228 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:16:40,228 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 21:16:40,228 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 21:16:40,228 INFO L133 ssoRankerPreferences]: Filename of dumped script: ArraysOfVariableLength6.c_Iteration9_Lasso [2022-11-18 21:16:40,228 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 21:16:40,228 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 21:16:40,230 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,234 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,236 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,239 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,241 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,244 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,246 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,552 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,555 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,558 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,560 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,563 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 21:16:40,924 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 21:16:40,924 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 21:16:40,924 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:16:40,924 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:40,929 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:16:40,930 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2022-11-18 21:16:40,931 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:16:40,940 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:16:40,941 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:16:40,941 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:16:40,941 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:16:40,942 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 21:16:40,942 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 21:16:40,966 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:16:40,974 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2022-11-18 21:16:40,975 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:16:40,975 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:40,976 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:16:40,987 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:16:41,000 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:16:41,000 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:16:41,000 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:16:41,000 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:16:41,000 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:16:41,001 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:16:41,001 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:16:41,002 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2022-11-18 21:16:41,014 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:16:41,022 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2022-11-18 21:16:41,022 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:16:41,023 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:41,024 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:16:41,029 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:16:41,041 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:16:41,041 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:16:41,041 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:16:41,041 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:16:41,041 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:16:41,042 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:16:41,042 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:16:41,043 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2022-11-18 21:16:41,062 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:16:41,070 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2022-11-18 21:16:41,071 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:16:41,071 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:41,072 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:16:41,077 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:16:41,089 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:16:41,089 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:16:41,090 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:16:41,090 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:16:41,090 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:16:41,090 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:16:41,090 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:16:41,092 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2022-11-18 21:16:41,110 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:16:41,118 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2022-11-18 21:16:41,118 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:16:41,118 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:41,119 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:16:41,123 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:16:41,130 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2022-11-18 21:16:41,135 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:16:41,135 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:16:41,135 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:16:41,135 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:16:41,136 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:16:41,136 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:16:41,136 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:16:41,140 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:16:41,142 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2022-11-18 21:16:41,143 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:16:41,143 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:41,145 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:16:41,146 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2022-11-18 21:16:41,147 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:16:41,157 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:16:41,157 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 21:16:41,158 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:16:41,158 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:16:41,158 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:16:41,158 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 21:16:41,158 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 21:16:41,159 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 21:16:41,161 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2022-11-18 21:16:41,162 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:16:41,162 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:41,163 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:16:41,165 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2022-11-18 21:16:41,166 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 21:16:41,176 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 21:16:41,176 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 21:16:41,176 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 21:16:41,176 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 21:16:41,191 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 21:16:41,192 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 21:16:41,211 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 21:16:41,245 INFO L443 ModelExtractionUtils]: Simplification made 16 calls to the SMT solver. [2022-11-18 21:16:41,245 INFO L444 ModelExtractionUtils]: 7 out of 31 variables were initially zero. Simplification set additionally 18 variables to zero. [2022-11-18 21:16:41,245 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 21:16:41,245 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:41,250 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 21:16:41,256 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 21:16:41,266 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2022-11-18 21:16:41,268 INFO L438 nArgumentSynthesizer]: Removed 1 redundant supporting invariants from a total of 2. [2022-11-18 21:16:41,268 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 21:16:41,269 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_foo_~i~0#1, ULTIMATE.start_foo_~b#1.offset) = -2*ULTIMATE.start_foo_~i~0#1 - 2*ULTIMATE.start_foo_~b#1.offset + 63 Supporting invariants [-1*v_rep(select #length ULTIMATE.start_main_~#mask~0#1.base)_3 + 32 >= 0] [2022-11-18 21:16:41,271 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2022-11-18 21:16:41,298 INFO L156 tatePredicateManager]: 5 out of 7 supporting invariants were superfluous and have been removed [2022-11-18 21:16:41,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:16:41,420 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Forceful destruction successful, exit code 0 [2022-11-18 21:16:41,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:41,458 INFO L263 TraceCheckSpWp]: Trace formula consists of 438 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-18 21:16:41,461 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:16:41,489 INFO L321 Elim1Store]: treesize reduction 11, result has 45.0 percent of original size [2022-11-18 21:16:41,489 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 9 treesize of output 15 [2022-11-18 21:16:41,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:41,809 INFO L263 TraceCheckSpWp]: Trace formula consists of 16 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-18 21:16:41,810 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:16:41,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:16:41,841 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.2 stem predicates 2 loop predicates [2022-11-18 21:16:41,841 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 78 states and 81 transitions. cyclomatic complexity: 6 Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:41,900 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 78 states and 81 transitions. cyclomatic complexity: 6. Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 191 states and 199 transitions. Complement of second has 8 states. [2022-11-18 21:16:41,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 2 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 21:16:41,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:41,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 14 transitions. [2022-11-18 21:16:41,904 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 14 transitions. Stem has 72 letters. Loop has 2 letters. [2022-11-18 21:16:41,904 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:16:41,904 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2022-11-18 21:16:41,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:16:42,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:42,028 INFO L263 TraceCheckSpWp]: Trace formula consists of 438 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-18 21:16:42,031 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:16:42,058 INFO L321 Elim1Store]: treesize reduction 11, result has 45.0 percent of original size [2022-11-18 21:16:42,058 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 9 treesize of output 15 [2022-11-18 21:16:42,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:42,395 INFO L263 TraceCheckSpWp]: Trace formula consists of 16 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-18 21:16:42,395 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:16:42,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:16:42,431 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.2 stem predicates 2 loop predicates [2022-11-18 21:16:42,432 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 78 states and 81 transitions. cyclomatic complexity: 6 Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:42,502 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 78 states and 81 transitions. cyclomatic complexity: 6. Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 191 states and 199 transitions. Complement of second has 8 states. [2022-11-18 21:16:42,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 2 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 21:16:42,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:42,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 14 transitions. [2022-11-18 21:16:42,504 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 14 transitions. Stem has 72 letters. Loop has 2 letters. [2022-11-18 21:16:42,504 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:16:42,504 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2022-11-18 21:16:42,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:16:42,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:42,632 INFO L263 TraceCheckSpWp]: Trace formula consists of 438 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-18 21:16:42,634 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:16:42,656 INFO L321 Elim1Store]: treesize reduction 11, result has 45.0 percent of original size [2022-11-18 21:16:42,656 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 9 treesize of output 15 [2022-11-18 21:16:42,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:42,960 INFO L263 TraceCheckSpWp]: Trace formula consists of 16 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-18 21:16:42,961 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:16:42,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:16:42,991 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.2 stem predicates 2 loop predicates [2022-11-18 21:16:42,991 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 78 states and 81 transitions. cyclomatic complexity: 6 Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:43,060 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 78 states and 81 transitions. cyclomatic complexity: 6. Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 120 states and 126 transitions. Complement of second has 7 states. [2022-11-18 21:16:43,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 2 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 21:16:43,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:43,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 26 transitions. [2022-11-18 21:16:43,061 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 26 transitions. Stem has 72 letters. Loop has 2 letters. [2022-11-18 21:16:43,062 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:16:43,062 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 26 transitions. Stem has 74 letters. Loop has 2 letters. [2022-11-18 21:16:43,062 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:16:43,062 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 26 transitions. Stem has 72 letters. Loop has 4 letters. [2022-11-18 21:16:43,062 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 21:16:43,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120 states and 126 transitions. [2022-11-18 21:16:43,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 21:16:43,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120 states to 76 states and 78 transitions. [2022-11-18 21:16:43,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-18 21:16:43,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-11-18 21:16:43,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 78 transitions. [2022-11-18 21:16:43,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 21:16:43,069 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76 states and 78 transitions. [2022-11-18 21:16:43,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 78 transitions. [2022-11-18 21:16:43,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 76. [2022-11-18 21:16:43,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.0263157894736843) internal successors, (78), 75 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:43,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 78 transitions. [2022-11-18 21:16:43,078 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 78 transitions. [2022-11-18 21:16:43,079 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 78 transitions. [2022-11-18 21:16:43,079 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-18 21:16:43,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 78 transitions. [2022-11-18 21:16:43,080 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 21:16:43,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:16:43,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:16:43,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:16:43,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 21:16:43,082 INFO L748 eck$LassoCheckResult]: Stem: 3406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 3411#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3412#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3414#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3409#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3410#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3475#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3474#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3473#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3472#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3471#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3470#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3469#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3468#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3467#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3466#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3465#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3464#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3463#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3462#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3461#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3460#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3459#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3458#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3457#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3456#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3455#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3454#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3453#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3452#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3451#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3450#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3449#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3448#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3447#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3446#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3445#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3444#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3443#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3442#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3441#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3440#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3439#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3438#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3437#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3436#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3435#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3434#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3433#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3432#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3431#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3430#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3429#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3428#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3427#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3426#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3425#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3424#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3423#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3422#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3421#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3420#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3419#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3418#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3417#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3416#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3415#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 3400#L15-4 foo_#res#1 := foo_~i~0#1; 3401#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3402#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3403#L25-3 assume !(main_~i~1#1 % 4294967296 < 32); 3413#L25-4 main_~i~1#1 := 0; 3404#L29-3 [2022-11-18 21:16:43,083 INFO L750 eck$LassoCheckResult]: Loop: 3404#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 3405#L30 assume !(32 != main_#t~mem5#1);havoc main_#t~mem5#1; 3408#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3404#L29-3 [2022-11-18 21:16:43,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:16:43,083 INFO L85 PathProgramCache]: Analyzing trace with hash 1575878025, now seen corresponding path program 1 times [2022-11-18 21:16:43,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:16:43,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461582137] [2022-11-18 21:16:43,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:16:43,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:16:43,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:43,320 INFO L134 CoverageAnalysis]: Checked inductivity of 1025 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1024 trivial. 0 not checked. [2022-11-18 21:16:43,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 21:16:43,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461582137] [2022-11-18 21:16:43,320 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [461582137] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 21:16:43,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [752583909] [2022-11-18 21:16:43,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:16:43,321 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 21:16:43,321 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:43,322 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 21:16:43,350 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-11-18 21:16:43,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:43,478 INFO L263 TraceCheckSpWp]: Trace formula consists of 422 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-18 21:16:43,480 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:16:43,641 INFO L134 CoverageAnalysis]: Checked inductivity of 1025 backedges. 0 proven. 95 refuted. 0 times theorem prover too weak. 930 trivial. 0 not checked. [2022-11-18 21:16:43,642 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:16:43,866 INFO L134 CoverageAnalysis]: Checked inductivity of 1025 backedges. 93 proven. 2 refuted. 0 times theorem prover too weak. 930 trivial. 0 not checked. [2022-11-18 21:16:43,866 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [752583909] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:16:43,867 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 21:16:43,867 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 6] total 11 [2022-11-18 21:16:43,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [718880315] [2022-11-18 21:16:43,867 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 21:16:43,868 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 21:16:43,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:16:43,869 INFO L85 PathProgramCache]: Analyzing trace with hash 69737, now seen corresponding path program 2 times [2022-11-18 21:16:43,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:16:43,869 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175829186] [2022-11-18 21:16:43,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:16:43,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:16:43,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:16:43,874 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:16:43,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:16:43,877 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:16:43,931 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 21:16:43,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-18 21:16:43,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=63, Unknown=0, NotChecked=0, Total=110 [2022-11-18 21:16:43,932 INFO L87 Difference]: Start difference. First operand 76 states and 78 transitions. cyclomatic complexity: 4 Second operand has 11 states, 11 states have (on average 2.6363636363636362) internal successors, (29), 11 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:44,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:16:44,078 INFO L93 Difference]: Finished difference Result 293 states and 298 transitions. [2022-11-18 21:16:44,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 293 states and 298 transitions. [2022-11-18 21:16:44,080 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 21:16:44,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 293 states to 293 states and 298 transitions. [2022-11-18 21:16:44,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-18 21:16:44,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-18 21:16:44,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 293 states and 298 transitions. [2022-11-18 21:16:44,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 21:16:44,084 INFO L218 hiAutomatonCegarLoop]: Abstraction has 293 states and 298 transitions. [2022-11-18 21:16:44,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293 states and 298 transitions. [2022-11-18 21:16:44,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293 to 283. [2022-11-18 21:16:44,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 283 states, 283 states have (on average 1.017667844522968) internal successors, (288), 282 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:44,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 283 states to 283 states and 288 transitions. [2022-11-18 21:16:44,092 INFO L240 hiAutomatonCegarLoop]: Abstraction has 283 states and 288 transitions. [2022-11-18 21:16:44,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-18 21:16:44,093 INFO L428 stractBuchiCegarLoop]: Abstraction has 283 states and 288 transitions. [2022-11-18 21:16:44,093 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-18 21:16:44,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 283 states and 288 transitions. [2022-11-18 21:16:44,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 21:16:44,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:16:44,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:16:44,100 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [128, 128, 4, 4, 4, 4, 4, 1, 1, 1, 1] [2022-11-18 21:16:44,100 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 21:16:44,101 INFO L748 eck$LassoCheckResult]: Stem: 4225#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4226#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 4229#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4230#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4499#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4498#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4496#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4494#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4492#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4490#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4488#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4486#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4484#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4482#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4480#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4478#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4476#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4474#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4472#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4470#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4468#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4466#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4464#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4462#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4460#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4458#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4456#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4454#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4452#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4450#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4448#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4446#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4444#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4442#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4440#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4438#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4436#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4434#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4432#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4430#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4428#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4426#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4424#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4422#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4420#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4418#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4416#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4414#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4412#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4410#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4408#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4406#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4404#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4402#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4400#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4398#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4396#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4394#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4392#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4390#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4388#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4386#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4384#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4382#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4380#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4378#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4375#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4374#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 4217#L15-4 foo_#res#1 := foo_~i~0#1; 4218#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4372#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4231#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4227#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4228#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4233#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4497#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4495#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4493#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4491#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4489#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4487#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4485#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4483#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4481#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4479#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4477#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4475#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4473#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4471#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4469#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4467#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4465#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4463#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4461#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4459#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4457#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4455#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4453#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4451#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4449#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4447#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4445#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4443#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4441#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4439#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4437#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4435#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4433#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4431#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4429#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4427#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4425#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4423#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4421#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4419#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4417#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4415#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4413#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4411#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4409#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4407#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4405#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4403#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4401#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4399#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4397#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4395#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4393#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4391#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4389#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4387#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4385#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4383#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4381#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4379#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4377#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4376#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 4373#L15-4 foo_#res#1 := foo_~i~0#1; 4219#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4220#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4221#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4371#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4370#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4369#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4368#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4367#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4366#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4365#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4364#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4363#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4362#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4361#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4360#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4359#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4358#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4357#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4356#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4355#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4354#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4353#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4352#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4351#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4350#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4349#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4348#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4347#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4346#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4345#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4344#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4343#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4342#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4341#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4340#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4339#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4338#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4337#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4336#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4335#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4334#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4333#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4332#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4331#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4330#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4329#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4328#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4327#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4326#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4325#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4324#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4323#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4322#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4321#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4320#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4319#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4318#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4317#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4316#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4315#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4314#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4313#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4312#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4311#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4310#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4309#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4308#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4307#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 4306#L15-4 foo_#res#1 := foo_~i~0#1; 4305#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4304#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4303#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4235#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4302#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4301#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4300#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4299#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4298#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4297#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4296#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4295#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4294#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4293#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4292#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4291#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4290#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4289#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4288#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4287#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4286#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4285#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4284#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4283#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4282#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4281#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4280#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4279#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4278#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4277#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4276#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4275#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4274#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4273#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4272#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4271#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4270#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4269#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4268#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4267#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4266#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4265#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4264#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4263#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4262#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4261#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4260#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4259#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4258#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4257#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4256#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4255#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4254#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4253#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4252#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4251#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4250#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4249#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4248#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4247#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4246#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4245#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4244#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4243#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4242#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4241#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4240#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4239#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 4238#L15-4 foo_#res#1 := foo_~i~0#1; 4237#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4236#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4234#L25-3 assume !(main_~i~1#1 % 4294967296 < 32); 4232#L25-4 main_~i~1#1 := 0; 4222#L29-3 [2022-11-18 21:16:44,101 INFO L750 eck$LassoCheckResult]: Loop: 4222#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 4223#L30 assume !(32 != main_#t~mem5#1);havoc main_#t~mem5#1; 4224#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4222#L29-3 [2022-11-18 21:16:44,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:16:44,102 INFO L85 PathProgramCache]: Analyzing trace with hash 951220635, now seen corresponding path program 2 times [2022-11-18 21:16:44,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:16:44,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808732563] [2022-11-18 21:16:44,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:16:44,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:16:44,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:45,451 INFO L134 CoverageAnalysis]: Checked inductivity of 16802 backedges. 0 proven. 12706 refuted. 0 times theorem prover too weak. 4096 trivial. 0 not checked. [2022-11-18 21:16:45,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 21:16:45,451 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808732563] [2022-11-18 21:16:45,451 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1808732563] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 21:16:45,451 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1132234408] [2022-11-18 21:16:45,452 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:16:45,452 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 21:16:45,452 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:45,453 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 21:16:45,478 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-11-18 21:16:45,878 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:16:45,878 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:16:45,888 INFO L263 TraceCheckSpWp]: Trace formula consists of 1574 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-18 21:16:45,894 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:16:46,912 INFO L134 CoverageAnalysis]: Checked inductivity of 16802 backedges. 0 proven. 12974 refuted. 0 times theorem prover too weak. 3828 trivial. 0 not checked. [2022-11-18 21:16:46,913 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:16:47,884 INFO L134 CoverageAnalysis]: Checked inductivity of 16802 backedges. 252 proven. 12722 refuted. 0 times theorem prover too weak. 3828 trivial. 0 not checked. [2022-11-18 21:16:47,884 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1132234408] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:16:47,884 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 21:16:47,885 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 12] total 23 [2022-11-18 21:16:47,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980528196] [2022-11-18 21:16:47,885 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 21:16:47,886 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 21:16:47,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:16:47,886 INFO L85 PathProgramCache]: Analyzing trace with hash 69737, now seen corresponding path program 3 times [2022-11-18 21:16:47,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:16:47,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769972885] [2022-11-18 21:16:47,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:16:47,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:16:47,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:16:47,891 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 21:16:47,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 21:16:47,894 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 21:16:47,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 21:16:47,944 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-18 21:16:47,944 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=173, Invalid=333, Unknown=0, NotChecked=0, Total=506 [2022-11-18 21:16:47,944 INFO L87 Difference]: Start difference. First operand 283 states and 288 transitions. cyclomatic complexity: 10 Second operand has 23 states, 23 states have (on average 3.608695652173913) internal successors, (83), 23 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:48,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:16:48,827 INFO L93 Difference]: Finished difference Result 725 states and 736 transitions. [2022-11-18 21:16:48,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 725 states and 736 transitions. [2022-11-18 21:16:48,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 21:16:48,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 725 states to 725 states and 736 transitions. [2022-11-18 21:16:48,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2022-11-18 21:16:48,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2022-11-18 21:16:48,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 725 states and 736 transitions. [2022-11-18 21:16:48,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 21:16:48,837 INFO L218 hiAutomatonCegarLoop]: Abstraction has 725 states and 736 transitions. [2022-11-18 21:16:48,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 725 states and 736 transitions. [2022-11-18 21:16:48,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 725 to 697. [2022-11-18 21:16:48,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 697 states, 697 states have (on average 1.0157819225251077) internal successors, (708), 696 states have internal predecessors, (708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:16:48,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 697 states to 697 states and 708 transitions. [2022-11-18 21:16:48,851 INFO L240 hiAutomatonCegarLoop]: Abstraction has 697 states and 708 transitions. [2022-11-18 21:16:48,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 21:16:48,852 INFO L428 stractBuchiCegarLoop]: Abstraction has 697 states and 708 transitions. [2022-11-18 21:16:48,852 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-18 21:16:48,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 697 states and 708 transitions. [2022-11-18 21:16:48,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 21:16:48,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 21:16:48,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 21:16:48,875 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [320, 320, 10, 10, 10, 10, 10, 1, 1, 1, 1] [2022-11-18 21:16:48,875 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 21:16:48,876 INFO L748 eck$LassoCheckResult]: Stem: 6939#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6940#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 6946#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 6944#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6945#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6949#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7627#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7625#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7623#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7621#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7619#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7617#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7615#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7613#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7611#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7609#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7607#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7605#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7603#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7601#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7599#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7597#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7595#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7593#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7591#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7589#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7587#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7585#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7583#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7581#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7579#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7577#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7575#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7573#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7571#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7569#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7567#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7565#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7563#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7561#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7559#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7557#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7555#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7553#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7551#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7549#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7547#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7545#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7543#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7541#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7539#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7537#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7535#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7533#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7531#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7529#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7527#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7525#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7523#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7521#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7519#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7517#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7515#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7513#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7511#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7509#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7507#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7506#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 6933#L15-4 foo_#res#1 := foo_~i~0#1; 6934#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 6937#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6938#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 6947#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7629#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7628#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7626#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7624#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7622#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7620#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7618#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7616#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7614#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7612#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7610#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7608#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7606#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7604#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7602#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7600#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7598#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7596#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7594#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7592#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7590#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7588#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7586#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7584#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7582#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7580#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7578#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7576#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7574#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7572#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7570#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7568#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7566#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7564#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7562#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7560#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7558#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7556#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7554#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7552#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7550#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7548#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7546#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7544#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7542#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7540#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7538#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7536#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7534#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7532#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7530#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7528#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7526#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7524#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7522#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7520#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7518#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7516#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7514#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7512#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7510#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7508#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7505#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7504#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 7503#L15-4 foo_#res#1 := foo_~i~0#1; 6935#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 6936#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7502#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7501#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7500#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7499#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7498#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7497#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7496#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7495#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7494#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7493#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7492#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7491#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7490#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7489#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7488#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7487#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7486#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7485#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7484#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7483#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7482#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7481#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7480#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7479#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7478#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7477#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7476#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7475#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7474#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7473#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7472#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7471#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7470#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7469#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7468#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7467#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7466#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7465#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7464#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7463#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7462#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7461#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7460#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7459#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7458#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7457#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7456#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7455#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7454#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7453#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7452#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7451#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7450#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7449#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7448#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7447#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7446#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7445#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7444#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7443#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7442#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7441#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7440#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7439#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7438#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7437#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 7436#L15-4 foo_#res#1 := foo_~i~0#1; 7435#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7434#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7433#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7432#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7431#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7430#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7429#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7428#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7427#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7426#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7425#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7424#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7423#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7422#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7421#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7420#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7419#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7418#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7417#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7416#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7415#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7414#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7413#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7412#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7411#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7410#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7409#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7408#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7407#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7406#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7405#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7404#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7403#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7402#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7401#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7400#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7399#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7398#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7397#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7396#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7395#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7394#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7393#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7392#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7391#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7390#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7389#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7388#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7387#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7386#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7385#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7384#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7383#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7382#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7381#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7380#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7379#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7378#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7377#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7376#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7375#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7374#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7373#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7372#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7371#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7370#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7369#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7368#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 7367#L15-4 foo_#res#1 := foo_~i~0#1; 7366#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7365#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7364#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7363#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7362#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7361#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7360#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7359#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7358#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7357#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7356#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7355#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7354#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7353#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7352#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7351#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7350#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7349#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7348#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7347#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7346#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7345#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7344#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7343#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7342#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7341#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7340#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7339#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7338#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7337#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7336#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7335#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7334#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7333#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7332#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7331#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7330#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7329#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7328#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7327#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7326#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7325#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7324#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7323#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7322#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7321#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7320#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7319#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7318#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7317#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7316#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7315#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7314#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7313#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7312#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7311#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7310#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7309#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7308#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7307#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7306#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7305#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7304#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7303#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7302#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7301#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7300#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7299#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 7298#L15-4 foo_#res#1 := foo_~i~0#1; 7297#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7296#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7295#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7294#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7293#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7292#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7291#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7290#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7289#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7288#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7287#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7286#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7285#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7284#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7283#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7282#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7281#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7280#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7279#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7278#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7277#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7276#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7275#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7274#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7273#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7272#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7271#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7270#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7269#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7268#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7267#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7266#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7265#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7264#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7263#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7262#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7261#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7260#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7259#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7258#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7257#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7256#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7255#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7254#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7253#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7252#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7251#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7250#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7249#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7248#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7247#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7246#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7245#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7244#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7243#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7242#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7241#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7240#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7239#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7238#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7237#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7236#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7235#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7234#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7233#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7232#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7231#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7230#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 7229#L15-4 foo_#res#1 := foo_~i~0#1; 7228#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7227#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7226#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7225#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7224#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7223#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7222#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7221#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7220#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7219#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7218#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7217#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7216#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7215#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7214#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7213#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7212#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7211#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7210#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7209#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7208#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7207#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7206#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7205#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7204#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7203#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7202#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7201#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7200#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7199#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7198#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7197#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7196#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7195#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7194#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7193#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7192#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7191#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7190#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7189#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7188#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7187#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7186#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7185#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7184#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7183#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7182#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7181#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7180#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7179#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7178#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7177#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7176#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7175#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7174#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7173#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7172#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7171#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7170#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7169#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7168#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7167#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7166#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7165#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7164#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7163#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7162#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7161#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 7160#L15-4 foo_#res#1 := foo_~i~0#1; 7159#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7158#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7157#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7156#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7155#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7154#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7153#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7152#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7151#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7150#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7149#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7148#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7147#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7146#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7145#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7144#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7143#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7142#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7141#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7140#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7139#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7138#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7137#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7136#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7135#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7134#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7133#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7132#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7131#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7130#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7129#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7128#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7127#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7126#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7125#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7124#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7123#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7122#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7121#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7120#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7119#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7118#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7117#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7116#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7115#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7114#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7113#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7112#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7111#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7110#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7109#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7108#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7107#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7106#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7105#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7104#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7103#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7102#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7101#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7100#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7099#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7098#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7097#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7096#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7095#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7094#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7093#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7092#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 7091#L15-4 foo_#res#1 := foo_~i~0#1; 7090#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7089#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7088#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7087#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7086#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7085#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7084#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7083#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7082#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7081#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7080#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7079#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7078#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7077#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7076#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7075#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7074#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7073#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7072#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7071#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7070#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7069#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7068#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7067#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7066#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7065#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7064#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7063#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7062#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7061#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7060#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7059#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7058#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7057#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7056#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7055#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7054#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7053#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7052#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7051#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7050#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7049#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7048#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7047#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7046#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7045#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7044#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7043#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7042#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7041#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7040#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7039#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7038#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7037#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7036#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7035#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7034#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7033#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7032#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7031#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7030#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7029#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7028#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7027#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7026#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7025#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7024#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7023#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 7022#L15-4 foo_#res#1 := foo_~i~0#1; 7021#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7020#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7019#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 6951#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7018#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7017#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7016#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7015#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7014#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7013#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7012#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7011#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7010#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7009#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7008#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7007#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7006#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7005#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7004#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7003#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7002#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7001#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7000#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6999#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6998#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6997#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6996#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6995#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6994#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6993#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6992#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6991#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6990#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6989#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6988#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6987#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6986#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6985#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6984#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6983#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6982#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6981#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6980#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6979#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6978#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6977#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6976#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6975#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6974#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6973#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6972#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6971#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6970#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6969#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6968#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6967#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6966#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6965#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6964#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6963#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6962#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6961#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6960#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6959#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6958#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6957#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6956#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6955#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 6954#L15-4 foo_#res#1 := foo_~i~0#1; 6953#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 6952#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6950#L25-3 assume !(main_~i~1#1 % 4294967296 < 32); 6948#L25-4 main_~i~1#1 := 0; 6941#L29-3 [2022-11-18 21:16:48,878 INFO L750 eck$LassoCheckResult]: Loop: 6941#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 6942#L30 assume !(32 != main_#t~mem5#1);havoc main_#t~mem5#1; 6943#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6941#L29-3 [2022-11-18 21:16:48,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:16:48,879 INFO L85 PathProgramCache]: Analyzing trace with hash -223676453, now seen corresponding path program 3 times [2022-11-18 21:16:48,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 21:16:48,879 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918047737] [2022-11-18 21:16:48,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:16:48,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 21:16:49,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:16:53,005 INFO L134 CoverageAnalysis]: Checked inductivity of 105515 backedges. 0 proven. 95275 refuted. 0 times theorem prover too weak. 10240 trivial. 0 not checked. [2022-11-18 21:16:53,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 21:16:53,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [918047737] [2022-11-18 21:16:53,006 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [918047737] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 21:16:53,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [103672564] [2022-11-18 21:16:53,007 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 21:16:53,007 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 21:16:53,007 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:16:53,014 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 21:16:53,034 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_30a8eb2a-c33d-4e51-9522-3407988480d6/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process